CMOS Image Sensors and Plasma Processes: How PMD Nitride Charging Acts on the Dark Current
<p>(<b>a</b>) Illustration of the configurations of active and dark reference pixel. (<b>b</b>) Mean dark current for active pixel of the matrix and dark reference pixel processed with “strip A” process.</p> "> Figure 2
<p>(<b>a</b>) Mean dark current for active pixel of the matrix, processed with the two cavity strip processes used in this study. (<b>b</b>) “Strip A” is a high-density oxygen plasma created in the cavity etch reactor and “Strip B” is created in a dedicated stripping tool with a remote plasma.</p> "> Figure 3
<p>Schematic representation of the pixel cross section is shown for (<b>a</b>) the standard process, with one (<b>b</b>) two (<b>c</b>) or three (<b>d</b>) layers of SiCN left above the pixel and under the cavity. (<b>e</b>) Mean dark current for active pixel of the matrix with varying number of SiCN layers between the photodiode and the cavity and processed with “strip A”. (<b>f</b>) Partial wafer mapping of the mean dark current of pixel with zero SiCN layer and strip A process.</p> "> Figure 4
<p>Mean dark current for active pixel of the matrix and dark reference pixel processed with “strip A”. (<b>a</b>) Comparison of four pixel versions, the reference pixel with deep trench isolation (DTI) as pixel isolation, the other with implant as pixel isolation, one without STI and one with a larger tranfer gate. The degradation of dark current is the same for all the versions. The pixel layouts are illustrated in (<b>b</b>).</p> "> Figure 5
<p>Illustration of the plasma induced degradation mechanism: (<b>a</b>) SiCN layers allow to block the ultraviolet (UV) radiation. (<b>b</b>) Without any absorption layers on the optical path, the plasma UV associated with the electric field at the wafer surface can lead to charge generation into the dielectrics, and interface states degradation.</p> "> Figure 6
<p>Experimental procedure to study the impact of plasma “strip A” on the dielectric stack. (<b>a</b>) Oxide-nitride-oxide of pre-metal dielectric layers. (<b>b</b>) Kelvin probe measurement setup. (<b>c</b>) Corona method to deposit charge at the wafer surface.</p> "> Figure 7
<p>Potential (<span class="html-italic">V<sub>CPD</sub></span>) of the different dielectric stacks as deposited and after plasma exposure.</p> "> Figure 8
<p>Wafer mapping of <span class="html-italic">V<sub>CPD</sub></span> value for sample 3 with the 500 nm oxide layer. (<b>a</b>) before plasma (<b>b</b>) after plasma exposure.</p> "> Figure 9
<p>Wafer mapping of <span class="html-italic">V<sub>CPD</sub></span> value for sample 4 with the thin oxide + nitride layers. (<b>a</b>) Before plasma (<b>b</b>) after plasma exposure.</p> "> Figure 10
<p>Principle of the silicon surface barrier measurement: (<b>a</b>) band diagram in the dark of the oxide + nitride + oxide stack, illustrated with positive charges in the nitride layer <span class="html-italic">Qf</span> and few negative charge <span class="html-italic">Qs</span> at the top oxide surface. As <span class="html-italic">Qf</span> >> <span class="html-italic">Qs</span>, the silicon is depleted and a positive <span class="html-italic">V<sub>sb</sub></span> appears; (<b>b</b>) the same band diagram under the light, <span class="html-italic">V<sub>sb</sub></span> is now zero due to the photogeneration of electrons and holes in the silicon.</p> "> Figure 11
<p>(<b>a</b>) Mapping of the surface barrier potential, <span class="html-italic">V<sub>sb</sub></span>, measured on sample 5 with oxide + nitride + oxide layers. (<b>b</b>) Correlation between the surface barrier potential and the <span class="html-italic">V<sub>CPD</sub></span>.</p> "> Figure 12
<p>(<b>a</b>) Mapping of the total charges measured on sample 4 with oxide + nitride layers. Charges are positive in the center of the wafer and negative at the edge. (<b>b</b>) Correlation between the total charge <span class="html-italic">Qtot</span> and the <span class="html-italic">V<sub>CPD</sub></span>.</p> "> Figure 13
<p>(<b>a</b>) Mapping of the photoluminescence intensity measured on sample 4. (<b>b</b>) Correlation between the photoluminescence intensity and the silicon surface barrier potential.</p> "> Figure 14
<p>Minimum of the interface states density D<sub>IT</sub>, extrapolated during Qtot measurement on sample 4. Mean value on the wafer.</p> "> Figure 15
<p>Representation of positive and negative charges creation in the nitride layer of the pixel under plasma exposure.</p> "> Figure 16
<p>Total charge and mean dark current as a function of the radial coordinate (0 = center of the wafer).</p> "> Figure 17
<p>TCAD simulation of the photodiode without (<b>a</b>) and with (<b>b</b>) fixed positive charge in the nitride. The white line shows the depletion region. (<b>c</b>) Illustration of the depleted interface under the spacer, which is the transition area between the accumulation under the transfer gate, and a possible inverted interface above the photodiode.</p> ">
Abstract
:1. Introduction
2. Dark Current Degradation by Plasma Strip Process
2.1. Experimental
2.2. Pixel Dark Current Results
2.3. Degradation Mechanism Hypothesis
3. Study of the Plasma Impact on the Pixel Dielectric Properties
3.1. Experimental Set-Up
3.2. Pre-Metal Dielectrics (PMD) Properties Measurement
3.2.1. Surface Potential Voltage Evolution
3.2.2. Silicon Surface Barrier Potential Evolution
3.2.3. Total Charge Measurement
3.2.4. Silicon Photo Luminescence Signal
3.2.5. Interface States Density Measurement
4. Discussion
4.1. Interaction Plasma versus Dielectrics
4.2. Relation between the PMD Dielectrics Properties and the Pixel Dark Current
- First, the p+ pinning implant in the pinned photodiode, which was not present on the COCOS characterization wafers, usually accumulates on the surface and moves the depletion edge deeper into the silicon. But the strong positive charges above the Si surface will move it to depletion, or move the depletion edge closer to the surface. This means that the same positive electric field causing an inversion at the silicon interface on the COCOS wafer may cause a silicon depletion touching the interface on the wafer with the CMOS image sensors. Even if the silicon depletion does not reach the interface, it can be close enough to the surface so that the diffusion length of carriers is longer than the distance from surface to depletion edge as reported in [14]. This strongly enhances the minority carrier diffusion and increases the electron generation from the interface.
- Finally, even if the interface above the photodiode is inverted, there is always a lateral frontier region close to the photodiode periphery where the inversion will change to depletion, before reaching the accumulation: either close to the STI interface, or under the spacer of the transfer gate. This is illustrated on the pixel TCAD cross section of the Figure 17b,c. Moreover, high electric fields are created by the negative voltage applied on the transfer gate: this can also enhance the dark current generated in the spacer interface area.
4.3. Ways to Prevent Plasma Damage on CMOS Image Sensor
5. Conclusions
Author Contributions
Funding
Acknowledgments
Conflicts of Interest
References
- Tokashiki, K.; Bai, K.H.; Baek, K.H.; Kim, Y.; Min, G.; Kang, C.; Cho, H.; Moon, J. Study of plasma charging-induced white pixel defect increase in CMOS active pixel sensor. Thin Solid Film. 2007, 515, 4864–4868. [Google Scholar] [CrossRef]
- Carrère, J.-P.; Oddou, J.P.; Place, S.; Richard, C.; Benoit, D.; Jenny, C.; Gatefait, M.; Aumont, C.; Tournier, A.; Roy, F. New mechanism of plasma induced damage on CMOS image sensor: Analysis and process optimization. Solid State Electron. 2011, 65–66, 51–56. [Google Scholar]
- Wilson, M. COCOS (corona oxide characterization of semiconductor) non-contact metrology for gate dielectrics. AIP Conf. Proc. 2001, 550, 220–225. [Google Scholar]
- Cheung, K.P.; Chang, C.P. Plasma-Charging Damage: A Physical Model. J. Appl. Phys. 1994, 75, 4415. [Google Scholar] [CrossRef]
- Sacchettini, Y.; Carrère, J.-P.; Goiffon, V.; Magnan, P. Plasma Antenna Charging in CMOS Image Sensors. In Proceedings of the 2019 IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA, 31 March–4 April 2019. [Google Scholar]
- Sinha, H.; Lauer, J.L.; Antonelli, G.A.; Nishi, Y.; Shohet, J.L. Charging response of back-end-of-the-line barrier dielectrics to VUV radiation. Thin Solid Film. 2012, 520, 5300–5303. [Google Scholar] [CrossRef]
- Powell, R.J.; Derbenwick, G.F. Vacuum ultraviolet radiation effects in SiO2(Vacuum UV irradiation of silicon dioxide, discussing positive charging for photon energies above threshold for electron-hole pair creation). IEEE Trans. Nucl. Sci. 1971, 18, 99–105. [Google Scholar] [CrossRef]
- Cismaru, C.; Shohet, J.L. In situ electrical characterization of dielectric thin films directly exposed to plasma vacuum-ultraviolet radiation. J. Appl. Phys. 2000, 88, 1742–1746. [Google Scholar] [CrossRef]
- Trupke, T.; Bardos, R.A. Photoluminescence imaging of silicon wafers. Appl. Phys. Lett. 2006, 89, 044107. [Google Scholar] [CrossRef]
- Haug, H.; Olibet, S.; Nordseth, Ø.; Marstein, E.S. Modulating the field-effect passivation at the SiO2/c-Si interface: Analysis and verification of the photoluminescence imaging under applied bias method. J. Appl. Phys. 2013, 114, 174502. [Google Scholar] [CrossRef] [Green Version]
- Sharma, V.; Tracy, C.; Schroder, D.; Flores, M.; Dauksher, B.; Bowden, S. Study and manipulation of charges present in silicon nitride films. In Proceedings of the 2013 IEEE 39th Photovoltaic Specialists Conference (PVSC), Tampa, FL, USA, 16–21 June 2013; pp. 1288–1293. [Google Scholar]
- Takahashi, Y.; Ohnishil, K.; Fujimakil, T.; Yoshikawaz, M. Radiation-induced trapped charge in metal-nitride-oxide-semiconductor structure. IEEE Trans. Nucl. Sci. 1999, 46, 1578–1585. [Google Scholar] [CrossRef]
- Shockley, W.; Read, W.T. Statistics of the Recombination of Holes and Electrons. Phys. Rev. 1952, 87, 835–842. [Google Scholar] [CrossRef]
- Teranishi, N. Effect and Limitation of Pinned Photodiode. IEEE Trans. Electron Devices 2016, 63, 10–15. [Google Scholar] [CrossRef]
- Regolini, J.L.; Benoit, D.; Morin, P. Passivation issues in active pixel CMOS image sensors. Microelectron. Reliab. 2007, 47, 739–742. [Google Scholar] [CrossRef]
- Carrère, J.-P.; Place, S.; Oddou, J.-P.; Benoit, D.; Roy, F. CMOS Image Sensor: Process impact on Dark current. In Proceedings of the 2014 IEEE International Reliability Physics Symposium (IRPS), Waikoloa, HI, USA, 1–5 June 2014. [Google Scholar]
Sample Number | Dielectric Stack |
---|---|
1 | Thin Bottom Oxide: about 10–50 nm |
2 | Anti-Reflective Nitride 50 nm |
3 | Top Oxide 500 nm |
4 | Bottom oxide + Nitride 50 nm |
5 | Oxide + Nitride + Oxide |
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Sacchettini, Y.; Carrère, J.-P.; Duru, R.; Oddou, J.-P.; Goiffon, V.; Magnan, P. CMOS Image Sensors and Plasma Processes: How PMD Nitride Charging Acts on the Dark Current. Sensors 2019, 19, 5534. https://doi.org/10.3390/s19245534
Sacchettini Y, Carrère J-P, Duru R, Oddou J-P, Goiffon V, Magnan P. CMOS Image Sensors and Plasma Processes: How PMD Nitride Charging Acts on the Dark Current. Sensors. 2019; 19(24):5534. https://doi.org/10.3390/s19245534
Chicago/Turabian StyleSacchettini, Yolène, Jean-Pierre Carrère, Romain Duru, Jean-Pierre Oddou, Vincent Goiffon, and Pierre Magnan. 2019. "CMOS Image Sensors and Plasma Processes: How PMD Nitride Charging Acts on the Dark Current" Sensors 19, no. 24: 5534. https://doi.org/10.3390/s19245534