Design of Microfabricated Inductors L. Daniel C. R. Sullivan S. R. Sanders From IEEE Transactions on Power Electronics, vol. 14, no. 4, pp. 709– 723. c °1999 IEEE. Personal use of this material is permitted. However, permission to reprint or republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 14, NO. 4, JULY 1999 709 Design of Microfabricated Inductors Luca Daniel, Student Member, IEEE, Charles R. Sullivan, Member, IEEE, and Seth R. Sanders, Member, IEEE Abstract— Possible configurations for microfabricated inductors are considered. Inductance can be set by adjusting permeability through control of anisotropy of a permalloy core or via a patterned quasi-distributed gap. A design methodology based on a simple model is proposed. A more accurate model and a numerical optimization are also developed. Design examples for 5- and 10-MHz buck converters and 2.5-MHz resonant converter applications are presented. Index Terms—Anisotropy, application, automatic design, buck converter, code, coil fabrication process, computer program, control of permeability, design, design example, design methodology, distributed gap, eddy currents, efficiency, end turns, fabrication process, hard-baked photoresist, high-frequency power inductors, hysteresis losses, inductance adjustment, inductor geometries, inductors, loss analysis, magnetic thin films, microfabricated inductors, microfabricated inductors design, multilayer core, multiturn windings, numerical simulation, optimization, permalloy, planar inductors, power density, quasi-distributed gap, resonant converter, secondary effects, SEM pictures. I. INTRODUCTION ECENT advances in microfabrication of transformers, using thin-film magnetic materials, show much promise for miniaturization of power converters [1]–[10]. Microfabrication techniques can produce fine patterning and thin films, which are advantageous for the control of eddy-current losses. This allows the use of magnetic metal alloys at frequencies in the range of 2–20 MHz. These materials can have high usable flux density and low-hysteresis loss [8]. Although some inductors have been built using similar techniques [11]–[20], many have not been designed for power applications. Through design and optimization specifically for these applications, higher efficiencies and power densities can be achieved. In this paper, various geometries and fabrication methods for inductors are considered. Design calculations and optimizations for one configuration are developed. Specific results for example designs are presented. R II. INDUCTOR CONFIGURATIONS AND GEOMETRIES The designer of a magnetic component with a magnetic core, fabricated by deposition of metal or other films on a substrate, faces a basic choice between depositing two layers of magnetic material with a conductor in between, or depositing two layers Manuscript received October 20, 1997; revised September 9, 1998. This work was supported by grants from the National Semiconductor Corporation and the University of California Micro Program. Recommended by Associate Editor, J. Sarjeant. The authors are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 USA (e-mail: dluca@eecs.berkeley.edu; sanders@eecs.berkeley.edu; Charles.R.Sullivan@Dartmouth.EDU). Publisher Item Identifier S 0885-8993(99)05569-6. Fig. 1. Cross section of a planar inductor. The low-permeability material acts as a distributed gap. The resulting field distribution controls ac conduction losses in multiturn planar windings. of conductor with a magnetic core in between. A device that uses two layers of conductor requires low resistance via contacts, and does not allow optimal use of an anisotropic magnetic material. As discussed in more detail in [8] and [21], a configuration using two layers of magnetic material above and below a conductor is preferred for these reasons, and because it generally allows higher power density. This geometry has been applied in [9] and [20]. A high-frequency inductor with substantial ac current requires careful design to avoid high-ac conduction losses. When a material with appropriate permeability is not available, highpermeability materials are generally used, and most designs will require increasing the overall reluctance of the magnetic path by introducing a gap. An air gap can adversely affect the field distribution, causing eddy currents, particularly with planar conductors and multiturn windings. A series of fine gaps could be used to form a “quasidistributed gap” to approximate a low-permeability material [8], [22], [23]. However, the scale of patterning that would be required for a typical design, on the order of a few microns, is difficult to achieve with a multilayer core [9]. Discrete gaps would be more easily placed at the “magnetic vias” where the top and bottom core materials connect. This leads to a large vertical field in the winding space, and problems with ac losses in the conductor. Turns that are wide compared to a skin depth, especially in multiturn designs, become problematic. Designs that use single narrow turns, such as in the “meander coil,” are preferred [9], [17], [24]. Perhaps the most elegant solution to the gap problem is the use of a low-permeability magnetic material to act as a distributed gap across the top and the bottom of the conductors, as shown in Fig. 1. In this case, the field lines are nearly horizontal in the winding space, and the ac resistance effects are determined by the height of the conductor, not its width. Additionally, the number of turns does not affect ac resistance as long as the turns accumulate horizontally, rather than vertically [8], [25]. If the permeability required for a distributed gap is achievable, the distributed gap design 0885–8993/99$10.00  1999 IEEE 710 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 14, NO. 4, JULY 1999 (a) Fig. 4. Copper coils are electroplated over the laminated core. A mold is not needed. The coils in this SEM are 40 m thick, and the spacing between turns is 40 m. (b) Fig. 2. (a) Schematic and (b) top views of a planar inductor approximating the design in Fig. 1. Fig. 5. Core laminations are sputtered over bumps of hard-baked photoresist which are 60 m thick and allow complete closure of the magnetic path. Fig. 3. SEM of a microfabricated planar inductor approximating the design in Fig. 1. is preferred. A way to control permeability in anisotropic permalloy is presented in Section III. An approximation of the distributed gap design can be fabricated as shown in Figs. 2 and 3 using a process similar to that presented in [9] and [10], but with a modified coil fabrication process. In [9] and [10], a photoresist mold is used to insulate the turns. But the thickness obtainable with such a mold is limited in practice. For thicker coils, the following process could instead be used. A thin layer of chrome (7 nm) and a seed layer of copper (200 nm) are evaporated over a 5- m layer of insulation photoresist. The copper seed layer is patterned, but the chrome layer is not patterned. The coil is then deposited by electroplating in a copper sulfate solution. The copper does not grow over the unpatterned chrome layer and a mold is not necessary. Schematic sections of the electroplated turns are shown in Figs. 14 and 15. Finally, the chrome layer can be removed with a sputter-etch process. Figs. 3 and 4 show the coil over the lower part of the core after the plating and the sputter-etching process. The magnetic path could be closed by a lid applied on the top and built on a second silicon wafer [10]. The core laminations can be sputtered over bumps of hard-baked photoresist (Fig. 5). Such bumps allow complete closure of the magnetic path when the lid is applied. Finite-element simulations [26] of the distributed gap geometry in Fig. 2 have been used to predict the value of the loss for a design example at the operating frequency MHz (see Fig. 6). From the simulation, the ac resistance factor for a 5-MHz sinusoidal waveform, assuming a lossless core, . From a one-dimensional (1-D) analysis as in was would have been expected. Section IV, a factor of The difference can be explained by the reluctance of the side DANIEL et al.: DESIGN OF MICROFABRICATED INDUCTORS 711 Fig. 6. Finite-element simulation of the ungapped configuration. The dimensions are the same as in Figs. 3 and 4, which are approximately those in the example design presented in Table I. The ac resistance factor at 5 MHz from the simulation is Fr = 1:8. Fig. 8. Hard-axis permeability controlled by a dc magnetic field applied in the easy-axis direction: r = 4300 at zero-field applied, r = 370 with 788 A/m applied, and r = 230 with 1800 A/m applied. Fig. 7. Simulation of the example design with three gaps on the upper lid core. Each gap is 12 m wide. The ac resistance factor at 5 MHz from the simulation is Fr = 1:8. portions of the core, which are of low-permeability material in the simulation, unlike those in Fig. 1. For the same device a quasi-distributed gap configuration could also be attempted by the creation of several gaps along the upper part of the core. A finite-element simulation (Fig. 7) of a device with three gaps, positioned over each of the three turns of our design example, gives an ac resistance factor , which promises performance close to that of the ungapped design. III. CONTROL OF PERMEABILITY A given permeability may be achieved in several different ways. A particular material or alloy may be selected to meet the requirements of a given design. Since this might require a new magnetic material deposition process for each design, a more practical approach would be to develop processes for a limited set of materials giving a range of permeabilities, and then to adapt a design to match one of the available materials. A single material in which the permeability could be varied during deposition or by other means would be even better. Anisotropic materials such as permalloy (NiFe alloy) allow the possibility of controlling permeability through the application of a dc magnetic field in the easy-axis direction, while the inductor operates with the main flux path in the hardaxis direction. The applied field acts to increase the anisotropy energy, decreasing the permeability while maintaining the lowhysteresis loss and high-saturation flux density characteristics of the material. Using an applied field of 1800 A/m, control of permeability down to one eighteenth of the zero-field permeability has been demonstrated, as shown in Fig. 8. This has been proposed as a way to make devices with variable inductance, controlled by the applied field [11]. By applying a fixed field strength with a permanent magnet, it is possible, in principle, to use this as a method to set the permeability at the desired value for a given design. IV. DESIGN BASED ON A SIMPLIFIED MODEL A design methodology is presented for a distributed or quasi-distributed gap inductor, as in Fig. 2, to be used in a power converter circuit. A pulsewidth modulation (PWM) buck converter [27] is chosen as an illustrative example, but the calculations could be adapted for other converter topologies as shown in Appendix III. The optimization, detailed in Appendix I, follows a procedure similar to that developed for a transformer design in [8]. A. Definition of the Simplified Model In a first analysis the end turns, the lateral width needed to close the core, and the lateral separation between turns have been neglected (see Fig. 2). A more accurate model will be presented in Section V to account for the effects of these “nonactive” spaces. First, the losses and power handling per unit area are calculated. Appendix I-A contains details on these. The field in the window area is assumed horizontal. The ac losses in the windings can then be estimated by a 1-D analysis [28] and depend only on the ratio between the height of the conductor and the skin depth , even for multiple turns. This is described by an ac resistance factor . We calculate a Fourier representation for the current waveform, and we estimate the factors for every significant harmonic as in [29]. If anisotropic NiFe alloy is used for the magnetic core, the main flux path can be chosen along the nonhysteretic hardaxis direction [8]. To control the eddy-current loss, a laminated core is deposited as a multilayer film. Such loss is estimated for each layer and for each significant harmonic of the flux 712 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 14, NO. 4, JULY 1999 density waveform and added together. For this estimation, the flux density is assumed parallel to the layers. B. Core Optimization Based on the Simplified Model Design specifications referring to the buck-converter application can be chosen as: input voltage , output voltage , dc, peak-to-peak ripple output current , and switching frequency . The optimization calculations are reported in Appendix I-B. The resulting tradeoff between power density and efficiency is shown here. According to (9) in Appendix I-A, the power loss in the winding can be reduced by an increase in height of the conductor . The improvement, however, is negligible for conductors thicker than two skin depths. For this first-order analysis, could be chosen as about one to two skin depths. Consideration of the neglected “nonactive” areas allows a more accurate optimization of as shown in Section V. The power loss in the core, according to (11) in Appendix I-A, can be made almost negligible by an increasing number of laminations . Consideration of the fabrication costs would be needed to optimize . We assume here a given number of laminations. The height of the core can then be adjusted for maximum power density as shown in [8], yielding (e.g., for this buck-converter application) the expression Fig. 9. Power density versus power loss percentage for a fixed number of laminations = 12. Logarithmic scales are used for both axes. Parameters in Table I have been assumed. End turns and the other “nonactive” areas have been neglected. N This produces a favorable field configuration, and avoids introducing the inductance constraint in the optimization process. The effective permeability required to produce the desired inductance for the optimized design is calculated in Appendix I-C and is reported here (2) (1) is the “active” device area, and are the where respective resistivities of the core and of the conductor, is the duty cycle of the converter, is a factor accounting for the ac loss in the windings as defined in (9) of Appendix I-A, is a factor accounting for the harmonic loss in the core as defined by (11) in Appendix I-A, and is the first Fourier coefficient of the current waveform as defined by (6) in Appendix I-A. Variable is one half the peak-to-peak value of the ac flux density. For an optimized design, the peak of the total flux density should be close to (or at) the saturation level [8]. Hence, we choose such that . Expression (1) for the maximum power density as a function of the given efficiency is plotted in Fig. 9. Parameters in Table I have been assumed as an example. In designs optimized as described above, the power loss is distributed between core and winding such that . This relation, derived in Appendix I-B, holds in general for all optimized designs of planar inductors and transformers with the configuration in Fig. 2 as long as hysteresis losses are neglected, core laminations are thin compared to a skin depth and their number is decided a priori, end turns and “nonactive” spaces are neglected, and inductance requirements are met by adjusting permeability. C. Inductance Adjustment One way to satisfy the inductance requirement is by adjusting the permeability of the core as described in Section III. is the current density per unit width of conwhere ductor at the efficiency [Appendix I-C, eq. (23)]. For an optimal design, choosing the efficiency completely specifies the permeability . As an example, assuming the parameters in Table I and neglecting end-turn and the other “nonactive” spaces, designs in the range % % are possible for values of relative permeability in the range , as shown in Fig. 10. Practical designs generally require, for a given efficiency, higher permeabilities than those shown in Fig. 10. This is because the spaces to close the core and to insulate the turns, neglected in this analysis, increase the length of the magnetic path (see Fig. 2). V. DESIGN BASED ON A MORE ACCURATE MODEL In this section, a model and a numerical optimization are developed to account also for end turns and “nonactive” spaces needed to insulate turns and close the core (see and in Figs. 2 and 15). A. Height of the Conductor and Number of Turns The analysis and design optimization presented in Section IV cannot be used to determine the optimal height of conductor and the number of turns . As is increased up to two skin depths, both ac and dc resistances decrease. Beyond this point, the improvement in ac resistance is small. With sufficient thickness, the dc loss can be made negligible in relation to ac loss. For higher values of there will not DANIEL et al.: DESIGN OF MICROFABRICATED INDUCTORS 713 TABLE I INDUCTOR EXAMPLE DESIGN FOR A 5-MHz ZERO-VOLTAGE-SWITCHING BUCK CONVERTER [27], [31]. THE UPPER PART OF THE TABLE CONTAINS THE INPUT PARAMETERS FOR THE DESIGN, AND THE LOWER PART CONTAINS THE OUTPUTS (REFER TO FIGS. 2, 15, AND 16) Fig. 10. Permeability versus power loss percentage for optimal designs at a = 12. Logarithmic scales are used for both given number of laminations axes. Parameters in Table I have been assumed. End turns and “nonactive” spaces have been neglected. N is a trade off between reducing resistance conductor height with a thicker conductor, or minimizing area by reducing and with a thinner conductor. In a first-order analysis as shown in Section IV, the number of turns does not affect the performance of the device. If we consider end turns and “nonactive” spaces, when is too small much space is used to laterally close the core. When is too large, much space is wasted in the end turns. An optimal value exists between these two extremes. B. Refining of the Model be significant advantages because only the dc losses, which are already negligible, will be reduced. When “nonactive” spaces are also taken into account, as increases, the lateral width required to separate the turns required to close the core, assuming and the lateral width fixed slopes, will eventually become substantial (Fig. 15). This effectively reduces the power density. Thus, the selection of Unitless factors refine the model capturing the effects of the spaces and as well as the effects of the end turns. The formulas for the simplified model presented in Appendix I-A are modified only by multiplicative coefficients as shown in detail in Appendix II. The power loss in the end turns is captured by the factor such that . The factor is defined such that , where is the length of the core (Fig. 2) and is the total length of the device including end turns. The quantity represents half of the total width (Fig. 2) and is given by the expression , where is the number of turns, is the width of each turn, and accounts for the nonactive width needed to close the core and to insulate the turns. For some designs, where is much larger than the height , these factors are close to unity, reducing the model to that presented in Section IV. However, for other designs, consideration of the factors , , and may be necessary to achieve an optimal design. For example, for low-output-current designs, the areas needed to close the core and to separate the turns become significant compared to the active area occupied by the conductor. In these cases, the simplified model does not describe the device accurately, and optimization based on the complete model is necessary. Moreover, the same argument shows that low-current designs generally have lower power density than higher current ones. 714 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 14, NO. 4, JULY 1999 If an efficiency of 94% is chosen for the design, a throughput power density of 10.6 W/cm is calculated. The three main parameters characterizing this design as found by the program are: core height m, number of turns , and conductor height m. All the other parameters of the device can be calculated from these three using [Appendix II, eqs. (50)–(58), (60), (61), and (64)]. Table I collects all the specifications and parameters of this design. (a) VI. POSSIBLE IMPROVEMENTS (b) (c) OF THE DESIGN One of the main parameters is the specified switching frequency of the converter. When the frequency is increased, the flux carrying requirement decreases. The device can then be made much smaller, while thinner core layers control the increase of the eddy-current losses. An optimization has been performed using a higher switching frequency: MHz. The upper bound of 16 m to the height of the core has also been removed. Fig. 12 shows the “power density versus efficiency” curve resulting from this optimization. A complete design is reported as an example in Table II where an efficiency of 94% allows a power density of 25.3 W/cm . The design methodology presented in this paper can also be applied to other topologies of converters. As an example, a design procedure is detailed in Appendix III for designs of inductors to be used in resonant converters. An example design for a 2.5-MHz resonant converter is presented in Table III. VII. CONCLUSIONS (d) Fig. 11. Maximum power density and required permeability versus efficiency at f = 5 MHz. Specifications and technology parameters have been assumed from the example design in Table I. The number of laminations is fixed N = 12. The optimal number of turns n, heights of the conductor hc , and core hs are also shown. In this example, hs has been limited to a maximum of 16 m. C. Optimization Based on the More Accurate Model The problem of finding the optimal power density for a given efficiency can be summarized and formulated mathematically, as presented in Appendix II-B, by a system of 8 equations [(48)–(55)] with 11 unknowns. Thus, the problem has three degrees of freedom that can be used to maximize the throughput power density for a given efficiency. A convenient choice of the three variables for the optimization is given by the height of the core , height of the conductor , and number of turns . A Matlab program has been developed to implement this optimization numerically [30]. As an example, assuming the specifications and the material data in Table I, we obtain from the program the curve in Fig. 11. The height of the core in this specific example has been limited for practical reasons to values not higher then 16 m. A methodology for the design of microfabricated planar inductors to be used in power conversion circuits has been presented. Availability of low-permeability magnetic materials is desirable for high-performance designs. Permeability of anisotropic materials such as permalloy can be controlled applying a dc magnetic field in the easy-axis direction. A design tradeoff between power density and efficiency exists and a method to calculate it and plot it is given. An example design for a 5-MHz buck converter shows that a power density of 10.6 W/cm is theoretically possible with an efficiency of 94%. If the frequency is increased to 10 MHz, a power density of 25.3 W/cm is calculated for the same efficiency. The design methodology can be applied to other converter topologies. As an example, the design of an inductor for a resonant converter has been developed. APPENDIX I SIMPLIFIED MODEL ANALYSIS AND OPTIMIZATION A. Definition of the Model and Loss Analysis The meaning of the terminology can be found in Tables I or II and in Figs. 2, 15, and 16. The end turns, the space to insulate the conductors and space to close the core , will be neglected in this analysis. Given these assumptions, the “active” area is (3) The current waveform is assumed triangular as in Fig. 13. DANIEL et al.: DESIGN OF MICROFABRICATED INDUCTORS 715 TABLE II INDUCTOR EXAMPLE DESIGN FOR A 10-MHz BUCK CONVERTER. THE UPPER PART OF THE TABLE CONTAINS THE INPUT PARAMETERS FOR THE DESIGN, AND THE LOWER PART CONTAINS THE OUTPUTS (REFER TO FIGS. 2, 15, AND 16) (a) (b) (c) (d) Fig. 12. Maximum power density and required permeability versus ef= 10 MHz. ficiency when the switching frequency is increased to Specifications and technology parameters have been assumed from the example design in Table II. The number of laminations is fixed = 12. The optimal number of turns , heights of the conductor c , and core s are also shown. f n h N h We represent such waveform using a Fourier series (4) where is the amplitude of the th harmonic The power loss in the winding is estimated using (5) (7) , introducing which we refer to the dc component the ripple factor, and the Fourier coefficients Assuming a horizontal field in the winding area, the ac resistance factors can be estimated as in [28] and [29] (6) to approximate We neglect harmonics higher then the band-limited waveform of an actual converter. (8) 716 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 14, NO. 4, JULY 1999 TABLE III PARAMETERS OF EXAMPLE DESIGN FOR A RESONANT INDUCTOR. REFER TO FIGS. 2, 15, AND 16. THE UPPER PART OF THE TABLE CONTAINS THE INPUT PARAMETERS FOR THE DESIGN, AND THE LOWER PART CONTAINS THE OUTPUTS the value can be assumed. For quasi-distributed gap designs as in Fig. 7, we use the value . Using (3), (5), and (7), the power loss in the winding per unit area is (9) is the dc current density per unit width of where is the total conductor and ac factor defined such that . To control eddy-current loss in the core, we divide the total height into laminations. The thickness of each lamination is smaller than two skin depths. In this case, and frequency for a sinusoidal flux density of amplitude , the loss in one lamination due to eddy currents can be approximated as in [32] (10) the same waveform and Assuming for the flux density Fourier representation of the current in (4) and assuming the thickness of each lamination is smaller than two skin depths for each considered harmonic, the eddy-current loss in the core per unit area is (11) is the amplitude of the th harmonic, is half of the flux density ripple, are the same coefficients defined by (6) used for the current waveform, and is a factor accounting for the loss in the core due to the harmonic contributions. If anisotropic material is used, as shown in Section III, the hysteresis losses in the hard-axis direction can be made negligible, and (11) is the total core loss per unit area. The throughput power for a buck converter is where Fig. 13. Assumed inductor current waveform. (12) where is the ratio between the conductor thickness and the skin depth at the th harmonic. Parameter is the “Dowell” effective number of conductor layers [28]. For distributed gap designs as in Figs. 1 and 6, has been expressed as a function where the output voltage of the ripple of the flux linkage and as a function of the off time , where DANIEL et al.: DESIGN OF MICROFABRICATED INDUCTORS 717 is the duty cycle. Using these expressions the throughput power density is (13) C. Estimation of the Permeability Required to Produce the Desired Inductance The current density efficiency substituting for using the optimal value can be calculated for any in (17), and B. Optimization Based on Simplified Model An efficiency objective is fixed and the throughput power density is optimized, as in [8]. The efficiency constraint, , is imposed by (14) Substituting the expressions from the previous analysis (23) For a closed-core structure, with low reluctance via connections, such as the high-permeability materials in Fig. 1, this current density produces a field which can be calculated using Ampere’s law (24) (15) yielding (25) To facilitate calculations, this can be rewritten as (16) where , , and . We solve (16) for by choosing the largest root for largest power density (17) . Using (13) and (17), the power where density can now be expressed as a function of the variable The field gives a flux density (26) should be chosen in order to have the This flux density maximum value of the flux density correspond to the saturation level [8] (27) The desired flux density level is then (18) (28) Theoretically, one optimizes for the best height of the core , but in practice calculations are easier if is calculated first. Setting to zero the derivative with respect to of the expression above, the optimal value is found. Using this value, the maximum power density is is the ripple of the current. where To attain such a level, the permeability should be adjusted to (19) APPENDIX II MORE ACCURATE PROBLEM FORMULATION AND OPTIMIZATION The core loss per unit area is (29) A. Definition of the More Accurate Model (20) The winding loss per unit area is (21) In the optimal design, the losses will then be divided between core and winding such that (22) The analysis refers to the configuration in Figs. 2 and 14–16. Several factors have been neglected in the simplified model presented in Appendix I-A: the width to insulate adjacent turns, the width required to close the core laterally, and the space occupied by the end turns and their effects on the total dc resistance of the windings. These factors will be included, refining the simplified model by means of multiplicative unitless factors. The width to insulate adjacent turns is calculated using (30) where is a constant dependent on the process. We assume that for small conductor heights ( m), a hard-baked 718 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 14, NO. 4, JULY 1999 Fig. 14. Schematic section of the turns after the electroplating process without a mold. Compare with the SEM in Fig. 4. Fig. 16. Top view of the inductor end turns. The total dc resistance, including the end turns, can be estimated by the expression (32) Fig. 15. where the th turn (Fig. 16) Schematic section of the inductor. photoresist mold is used to insulate the turns. Due to the photolithographic process, the minimum width of the mold is approximately proportional to its height. For larger conductor heights, a mold is not likely to be practical. In this case, a process as described in Section II can be used. A copper “seed” layer for an electroplating process is created over a thin chrome layer. During the electroplating process, the copper does not grow on the unpatterned chrome. Anyway, we observed that the copper extends laterally from its seed layer by the same amount of the final conductor height as shown in Fig. 14. The space to separate the turns can still be assumed proportional to their height. We use for the “no-mold process” a value larger than the one used for the “mold process.” The turn width and the separation width are the equivalent widths for rectangular section conductors with the same area of those shown in Figs. 14 and 15. The space includes the space to close laterally the core, the width needed for the upper core to contact with the lower core, and the width required by a lamination etching process (see Figs. 15 and 16) is the radius of (33) where is a unitless factor accounting for the additional resistance of the end turns. The total length of the device, including the end turns, can be estimated by the expression (34) . The total width of the which defines the unitless factor device, including the space to insulate adjacent turns, and the space to close the core laterally can be approximated by the expression (31) (35) As presented in Section II and in [10], the magnetic path is closed by a core processed on another silicon substrate. Hardbaked photoresist bumps produce the needed slope to allow the upper core on the “lid wafer” to contact the lower core on the “coil wafer.” The total height of the bumps is given by the height of the conductor plus the height to separate and insulate vertically the two cores from the coils. For a quasi-distributed gap design might be chosen larger than the minimum value needed to insulate the coils from the core. This can allow a favorable configuration of the field seen by the conductors [22] (Fig. 7). The width required by the lamination etching process is approximately proportional to the height of the core . The symbol is used to indicate the slope of the etched NiFe core. . which defines the unitless factor The total area occupied by the device can now be easily expressed as a function of these factors (36) where represents the “active” area as defined in the simplified model presented in Appendix I-A. The width of the core is times larger than in the simplified model, as the lateral width has been included. The power loss in the core due to eddy currents scales linearly with the width of the core. Hence (37) DANIEL et al.: DESIGN OF MICROFABRICATED INDUCTORS 719 is the core loss neglecting “nonactive” spaces where as given by (11) in Appendix I-A. Thus, the total power loss per unit area is B. Optimization Problem The problem of finding the maximum power density for a given efficiency can be summarized and formulated mathematically as follows: (38) (47) As shown in (33), the end turns increase the resistance by a . An approximation for the total power loss in the factor windings can then be written as given the equality constraints defined explicitly or implicitly by (8), (9), (30), (31), (33), (35), (44), and (46) which we collect here (39) The power loss in the winding per unit area is Finally, the increase of the area by a factor the throughput power density (48) (40) (49) decreases (50) (51) (41) (52) (53) (54) The equation that determines the efficiency (14) in Appendix I-A can now be refined as (42) Simplifying and rearranging the terms we obtain (43) , , and are the power where throughput and the power loss components per unit area calculated from the simplified model, respectively. The equation above shows an example of how the factors and can easily refine the equations of the simplified model to capture the effects of the neglected items. Substituting (9), (11), and (13), from Appendix I-A the equation can be expanded to (44) The throughput power density to be maximized is (45) Finally, the specification on the flux capability requirement adds to the problem the equation (46) (55) We choose as specifications for the problem, the following five parameters referred to the converter behavior: the frequency , the input and output voltages and , and the dc and “peak-to-peak” current output and . Directly from the specifications, we calculate the current ripple , the duty cycle , the “peakto-peak” flux linkage ripple , the conductor skin depth at each significant harmonic : , the Fourier coefficients and the harmonic core loss . factor The problem as written above, presents 8 equations and 11 unknowns: , , , , , , , , , , and . Hence, three independent unknowns can be used to maximize the throughput power density. C. Optimization Procedure A convenient parameterization is represented by the three unknowns ( , , ). We calculate the throughput power 720 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 14, NO. 4, JULY 1999 density as a function of only these three variables using the following steps. • Calculate , , , , , , and using (34), (49), and (53)–(55) in Appendix II-B and (16) in Appendix I-B. • Calculate the quantities (56) (57) (58) defined such that and . Substituting such quantities, (49) and (52) in (48), we obtain the quadratic equation Fig. 17. Power density for a given efficiency  = 94% and a fixed number of laminations N = 12. The number of turns is also fixed n = 3. Specifications and technology parameters have been assumed from the example design in Table I. (59) • Calculate the current density given by the larger solution of (59) for larger power density (60) • Finally, the throughput power density using (47) is (61) We summarize our optimization procedure with the following steps implemented in our Matlab program [30]. For the meaning of the symbols, refer to Table I. 1) Read specs . 2) Read technology parameters . 3) Calculate . 4) Fix the number of laminations. 5) Fix the efficiency. 6) Using a numerical function optimizer, find the optimal for max power density . A three-dimensional (3-D) plot of the throughput power density as a function of two of the three main parameters and can be obtained if the third one is fixed (Fig. 17). Such a plot shows a well-defined maximum. Fig. 18 shows such maxima for different number of turns . The largest value of power density in Fig. 18 corresponds to the optimal design. The entire optimization presented so far can be repeated for different values of the efficiency in order to obtain the fundamental curve in Fig. 11 showing the maximum throughput power density achievable at any chosen efficiency. Fig. 11 shows also the values of the three parameters , , and needed to achieve the optimal design. In that example, has been limited to a maximum of 16 m. Fig. 18. The power density maximized with respect to hc and hs is here shown for different number of turns n. Specifications and technology parameters have been assumed from the example design in Table I. The efficiency is chosen  = 94%, and the number of turns is fixed N = 12. D. Permeability Calculations for the More Accurate Model The permeability required to produce the desired inductance can be calculated following the procedure in Appendix I-C. The magnetic field produced in the core by the current density [Appendix III-C, eq. (60)] is (62) which gives a flux density (63) The permeability should then be selected so that (64) It can be observed that with respect to the simplified model a times higher is required when also “nonacpermeability tive” spaces are included in the calculations. DANIEL et al.: DESIGN OF MICROFABRICATED INDUCTORS 721 APPENDIX III INDUCTOR DESIGN FOR A RESONANT CONVERTER The design methodology can be applied to inductors used in other circuit topologies. As an example an optimization procedure is presented for an inductor to be used in a resonant converter. The frequency , the desired inductance , and the rms value of the current are assumed as specification parameters. The resulting trade off existing between quality factor and power density is shown. The analysis refers to the same model described in Appendix II-A and the configuration in Fig. 2. The resistance of the windings at the operative frequency, including the end turns, can be estimated by the expression (a) (65) The power loss in a laminated core for a sinusoidal flux density is given by (b) (66) The total power loss in the core, assuming negligible hysteresis loss, can be modeled by the equivalent resistance (67) The value of the quality factor resistance (c) is determined by the total (68) The peak flux is set to saturation level imposing (69) where is the current peak. The inductance requirement, similarly to Appendix II-D, is satisfied by adjusting the permeability of the core such that (d) Fig. 19. Maximum power density and required permeability versus quality factor. Specifications and technology parameters have been assumed from the example design in Table III. The height of conductor hc , height of the core hs , and number of turns n are also shown. In this example, hs has been limited to values not larger then 16 m. (70) Finally, the goal is maximizing the power density. We use as a parameter for the power handling of the device the “volt–ampere” product , where is the rms voltage. The objective of the optimization procedure is then Power Area (71) A. Optimization Problem for the Resonant Inductor The problem of finding the maximum power density for can be summarized and formulated a given quality factor mathematically as follows: (72) given (73) (74) and the five equations in Appendix II-B defining the unknowns , , , , and . Other unknowns are , , , , and . The problem presents seven equations and ten unknowns. Hence, three independent unknowns can be used to maximize the power density. B. Optimization Procedure for the Resonant Inductor As in Appendix III-C, a convenient choice for the optimization problem defined above is represented by the three 722 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 14, NO. 4, JULY 1999 unknowns ( , , and ). Given these three variables the power density can be calculated in the following ways. • and are first evaluated using (30) and (31) in Appendix II-A. • Using the saturation equation (74), we can calculate (75) • Rearranging the quality factor equation (73), we see a quadratic form , where (76) (77) (78) and using the smaller solution for larger • Solving for power density (79) • and can then be easily calculated using (34) and (35) in Appendix II. • Finally, the area (36) and the power density (71) can be evaluated. We summarize the design procedure used in our Matlab program [30] with the following steps. Refer to Table III for the meaning of the symbols. 1) Read specs . 2) Read technology parameters . 3) Fix the number of laminations. 4) Fix the quality factor. 5) Using a numerical function optimizer, find the optimal for max power density . As an example, we used the specifications and the material data in Table III, obtaining the curves in Fig. 19. Once a point on the tradeoff curve “power-density versus quality factor” is specified, the physical parameters for the fabrication are derived using (30), (31), and (75)–(79). An example design for is shown in Table III. REFERENCES [1] K. Yamasawa, K. Maruyama, I. Hirohama, and P. Biringer, “Highfrequency operation of a planar-type microtransformer and its application to multilayered switching regulators,” IEEE Trans. Magn., vol. 26, pp. 1204–1209, May 1990. [2] K. Yamaguchi, E. Sugawara, O. Nakajima, and H. Matsuki, “Load characteristics of a spiral coil type thin film microtransformer,” IEEE Trans. Magn., vol. 29, no. 6, pp. 3207–3209, 1993. [3] K. Yamaguchi, S. Ohnuma, T. Imagawa, J. Toriu, H. Matsuki, and K. Murakami, “Characteristics of a thin film microtransformer with spiral coils,” IEEE Trans. Magn., vol. 29, no. 5, pp. 2232–2237, 1993. [4] T. Yachi, M. Mino, A. Tago, and K. Yanagisawa, “A new planar microtransformer for use in micro-switching-converters,” in 22nd Annu. Power Electronics Specialists Conf., June 1991, pp. 1003–1010. , “A new planar microtransformer for use in micro-switching[5] converters,” IEEE Trans. Magn., vol. 28, no. 4, pp. 1969–1973, 1992. [6] M. Mino, T. Yachi, A. Tago, K. Yanagisawa, and K. Sakakibara, “Microtransformer with monolithically integrated rectifier diodes for micro-switching converters,” in 24th Annu. Power Electronics Specialists Conf., June 1993, pp. 503–508. [7] M. Mino, T. Yachi, K. Yanagisawa, A. Tago, and K. Tsukamoto, “Switching converter using thin film microtransformer with monolithically-integrated rectifier diodes,” in 26th Annu. Power Electronics Specialists Conf., June 1995, pp. 665–670. [8] C. R. Sullivan and S. R. Sanders, “Design of microfabricated transformers and inductors for high-frequency power conversion,” IEEE Trans. Power Electron., vol. 11, no. 2, pp. 228–238, 1996. , “Microfabrication process for high-frequency power-conversion [9] transformers,” in 26th Annu. Power Electronics Specialists Conf., June 1995, pp. 658–664. , “Measured performance of a high-power-density microfabri[10] cated transformer in a dc–dc converter,” in 27th Annu. Power Electronics Specialists Conf., June 1996. [11] N. Saleh, “Variable microelectronic inductor,” IEEE Trans. Comp., Hybrids, Manufact. Technol., vol. CHMT-1, no. 1, 1978. [12] R. F. Soohoo,P “Magnetic thin film inductors for integrated circuit applications,” IEEE Trans. Magn., vol. MAG-15, pp. 1803–1805, Nov. 1979. [13] K. Kawabe, H. Koyama, and K. Shirae, “Planar inductor,” IEEE Trans. Magn., vol. MAG-20, pp. 1804–1806, Sept. 1984. [14] O. Oshiro, H. Tsujimoto, and K. Shirae, “A novel miniature planar inductor,” IEEE Trans. Magn., vol. MAG-23, pp. 3759–3761, Sept. 1987. [15] M. Yamaguchi, M. Matsumoto, H. Ohzeki, and K. I. Arai, “Fabrication and basic characteristics of dry-etched micro inductors,” IEEE Trans. Magn., vol. 26, no. 5, 1990. [16] M. Yamaguchi, S. Arakawa, H. Ohzeki, Y. Hayashi, and K. I. Arai, “Characteristics and analysis for a thin film inductor with closed magnetic circuit structure,” IEEE Trans. Magn., vol. 28, no. 5, 1992. [17] M. Yamaguchi, S. Arakawa, S. Yabukami, K. I. Arai, F. Kumagai, and S. Kikuchi, “Estimation of the in-situ permeabilities in thin-film inductors,” IEEE Trans. Magn., vol. 29, no. 5, 1993. [18] C. H. Ahn, Y. J. Kim, and M. G. Allen, “A fully integrated micromachined toroidal inductor with a nickel-iron magnetic core (the switched dc/dc boost converter application),” in 7th Annu. Int. Conf. Solid-State Sensors and Actuators, 1993, pp. 70–73. [19] C. H. Ahn and M. G. Allen, “A comparison of two micromachined inductors (bar- and meander-type) for fully integrated boost dc/dc power converters,” IEEE Trans. Power Electron., vol. 11, pp. 239–245, Mar. 1996. [20] M. Mino, K. Tsukamoto, K. Yanagisawa, A. Tago, and T. Yachi, “A compact buck-converter using a thin-film inductor,” in 11th Annu. Applied Power Electronics Conf. Exposition, Mar. 1996, pp. 422–426. [21] C. R. Sullivan and S. R. Sanders, “Microfabrication of transformers and inductors for high frequency power conversion,” in 24th Annu. Power Electronics Specialists Conf., June 1993, pp. 33–40. [22] J. Hu and C. R. Sullivan, “The quasidistributed gap technique for planar inductors: Design guidelines,” in IEEE Industry Applications Soc. Annu. Meeting, Oct. 1997. [23] U. Kirchenberger, M. Marx, and D. Schroder, “A contribution to the design optimization of resonant inductors in high power resonant converters,” in 1992 IEEE Industry Applications Society Annu. Meeting, Oct. 1992, vol. 1, pp. 994–1001. [24] I. Sasada, T. Yamaguchi, and K. Harada, “Methods for loss reduction in planar inductors,” in 23rd Annu. Power Electronics Specialists Conf., June 1992, pp. 1409–1415. [25] W. M. Chew and P. D. Evans, “High frequency inductor design concepts,” in 22nd Annu. Power Electronics Specialists Conf., June 1991, pp. 673–678. [26] Maxwell EM 2D Field Simulator Manual, Ansoft Corp., Pittsburgh, PA. [27] W. Lau and S. Sanders, “An integrated controller for a high frequency buck converter,” in 28th Annu. Power Electronics Specialists Conf., July 1997. [28] P. Dowell, “Effects of eddy currents in transformer windings,” Proc. Inst. Elect. Eng., vol. 113, pp. 1387–1394, Aug. 1966. [29] J. G. Bresil and W. G. Hurley, “Derivation of optimum winding thickness for duty cycle modulated current waveshapes,” in 28th Annu. Power Electronics Specialists Conf., July 1997. [30] L. Daniel, M.I.D. Microfabricated Inductors Designer, 1996. Available: DANIEL et al.: DESIGN OF MICROFABRICATED INDUCTORS http://www-cad.EECS.Berkeley.EDU/HomePages/dluca/mid.html. [31] A. J. Stratakos, S. R. Sanders, and R. W. Brodersen, “A low-voltage CMOS dc–dc converter for a portable battery-operated system,” in 25th Annu. Power Electronics Specialists Conf., June 1994, pp. 619–626. [32] E. C. Snelling, Soft Ferrites, Properties and Applications, 2nd ed. London, U.K.: Butterworth, 1988. Luca Daniel (S’98) was born in Pederobba, Italy, in 1971. He received the Laurea degree (summa cum laude) in electronic engineering from the Universita’ degli Studi di Padova, Padova, Italy, in 1996. He is currently working towards the Ph.D. degree in electrical engineering and computer sciences at the University of California, Berkeley. His research interests are in thin-film magnetics and, more recently, in simulation and design methodology for electromagnetic compatibility. In 1998, he was at the ULSI Research Laboratory, Hewlett-Packard Company, Palo Alto, CA, working on simulation of electromagnetic interference from IC packages. Charles R. Sullivan (S’93–M’96) was born in Princeton, NJ, in 1964. He received the B.S. degree in electrical engineering from Princeton University, Princeton, in 1987 and the Ph.D. degree in electrical engineering and computer sciences from the University of California, Berkeley, in 1996. From 1987 to 1990, he was with Lutron Electronics, Coopersburg, PA, developing a highfrequency dimming ballast for compact fluorescent lamps. He is presently an Assistant Professor at the Thayer School of Engineering, Dartmouth College, Hanover, NH. He has published technical papers on topics including thin-film magnetics for high-frequency power conversion, dc–dc converter topologies, energy and environmental issues, and modeling, analysis, and control of electric machines. 723 Seth R. Sanders (M’87) received the B.S. degree in electrical engineering and physics in 1981 and the M.S. and Ph.D. degrees in electrical engineering in 1985 and 1989, respectively, all from the Massachusetts Institute of Technology (MIT), Cambridge. He was a Design Engineer at the Honeywell Test Instruments Division, Denver, CO, from 1981 to 1983. He is presently an Associate Professor in the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley. During the 1992–1993 academic year, he was on industrial leave with National Semiconductor, Santa Clara, CA. His research interests are in power electronics, variable-speed drive systems, simulation, and nonlinear circuit and system theory as related to the power electronics field. Dr. Sanders is the recipient of the 1993 NFS Young Investigator Award and presently serves as Chair of the IEEE Technical Committee on Computers in Power Electronics.