-
PEARSON
Education
'"
:»
z
PIC MICROCONTROLLER
AND EMBEDDED SYSTEMS
Using Assembly and C for PIC18
Muhammad Ali Mazidi
Rolin D. McKinlay
Danny Causey
PEARSON
Prentice
Hall
Pearson Education International
If you purchased this book within the United States or Canada you should be aware that it has been
wrongfully imported without the approval of the Publisher or the Author.
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This book was set in Times Roman by M. Mazidi, Rolin McKinlay and Danny Causey. It was printed and bound by Courier Kendallville, Inc. The cover was printed by Coral Graphic Services, Inc.
Copyright © 2008 by Pearson Education, Inc., Upper Saddle River, New Jersey 07458. Pearson
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Hall
10 9 8 7 6 5 4 3 2 1
ISBN 0-13-600902-6
Trademark Information and Acknowledgments
Certain materials contained herein are reprinted with the permission of Microchip
Technology Incorporated. No further reprints or reproductions may be made of said
materials without Microchip Technology Inc.'s prior written consent.
Accuron®, dsPIC®, KEELOQ®, microID®, MPLAB®. PIC®, PICmicro®, PICSTART®, PICkit 2®, PowerSmart®, PRO MATE®, rfPIC® and SmartShunt®, the
Microchip name and logo, and the KEELOQ logo are trademarks or registered trademarks of Microchip Technology, Inc., in the United States and other countries.
All the figures, tables, and instructions related to the PIC family of microcontrollers
used in this textbook belong to Microchip Technology, Inc. They are reproduced with
the permission of Microchip Technology, Inc.
Instruction mnemonics and clock cycles listed in Appendix A are copyrighted by
Microchip Technology, Inc. They are reproduced with the permission of Microchip
Technology, Inc.
The PICl8 data sheets listed in Appendix H are copyrighted by Microchip Technology,
Inc. They are reproduced with the permission of Microchip Technology, Inc.
iii
Regard man as a mine rich in gems of
inestimable value. Education can, alone, cause it
to reveal its treasures, and enable mankind to
benefit therefrom.
Baha'u'liah
iv
BRIEF CONTENTS
CHAPTERS
0:
I:
2:
3:
4:
5:
6:
7:
8:
9:
10:
11 :
12:
13:
14:
15:
16:
17:
Introduction to Computing
The PIC Microcontrollers: History and Features
PIC Architecture & Assembly Language Programming
Branch, Call, and Time Delay Loop
PIC I/O Port Programming
Arithmetic, Logic Instructions, and Programs
Bank Switching, Table Processing, Macros, and Modules
PIC Programming in C
PICI8F Hardware Connection and ROM Loaders
PIC18 Timer Programming in Assembly and C
PIC18 Serial Port Programming in Assembly and C
Interrupt Programming in Assembly and C
LCD and Keyboard Interfacing
ADC, DAC, and Sensor Interfacing
Using Flash and EEPROM Memories for Data Storage
CCP and ECCP Programming
SPI Protocol and DS 1306 RTC Interfacing
Motor Control: Relay, PWM, DC, and Stepper Motors
23
39
97
129
155
193
251
299
335
387
423
473
499
529
569
603
635
APPENDICES
A:
B:
C:
D:
E:
F:
G:
H:
PICI8 Instructions: Format and Description
Basics of Wire Wrapping
IC Technology and System Design Issues
Flowcharts and Pseudocode
PICI8 Primer for x86 and 8051 Programmers
ASCII Codes
Assemblers, Development Resources, and Suppliers
Data Sheets
673
721
725
745
750
752
754
756
v
CONTENTS
CHAPTER 0: INTRODUCTION TO COMPUTING
SECTION 0.1: NUMBERING AND CODING SYSTEMS
SECTION 0.2: DIGITAL PRIMER
SECTION 0.3: INSIDE THE COMPUTER
CHAPTER 1: THE PIC MICROCONTROLLERS: HISTORY AND
FEATURES
SECTION I.l: MICROCONTROLLERS AND EMBEDDED
PROCESSORS
SECTION 1.2: OVERVIEW OF THE PIC18 FAMILY
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
PROGRAMMING
SECTION 2.1: THE WREG REGISTER IN THE PIC
SECTION 2.2: THE PIC FILE REGISTER
SECTION 2.3: USING INSTRUCTIONS WITH THE
DEFAULT ACCESS BANK
SECTION 2.4: PIC STATUS REGISTER
SECTION 2.5: PIC DATA FORMAT AND DIRECTIVES
SECTION 2.6: INTRODUCTION TO PIC ASSEMBLY
PROGRAMMING
SECTION 2.7: ASSEMBLING AND LINKING A PIC
PROGRAM
SECTION 2.8: THE PROGRAM COUNTER AND
PROGRAM ROM SPACE IN THE PIC
SECTION 2.9: RISC ARCHITECTURE IN THE PIC
SECTION 2.10: VIEWING REGISTER AND MEMORY
WITH MPLAB SIMULATOR
1
2
9
13
23
24
28
39
40
43
48
57
61
67
70
73
84
87
CHAPTER 3: BRANCH, CALL, AND TIME DELAY LOOP
SECTION 3.1: BRANCH INSTRUCTIONS AND LOOPING
SECTION 3.2: CALL INSTRUCTIONS AND STACK
SECTION 3.3: PIC18 TIME DELAY AND INSTRUCTION
PIPELINE
97
98
110
CHAPTER 4: PIC I/O PORT PROGRAMMING
SECTION 4.1: I/O PORT PROGRAMMING IN PIC18
SECTION 4.2: I/O BIT MANIPULATION PROGRAMMING
129
130
143
vi
117
CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND
PROGRAMS
SECTION 5.1: ARITHMETIC INSTRUCTIONS
SECTION 5.2: SIGNED NUMBER CONCEPTS AND
ARITHMETIC OPERATIONS
SECTION 5.3: LOGIC AND COMPARE INSTRUCTIONS
SECTION 5.4: ROTATE INSTRUCTION AND DATA
SERIALIZATION
SECTION 5.5: BCD AND ASCII CONVERSION
155
156
166
171
179
184
CHAPTER 6: BANK SWITCHING, TABLE PROCESSING,
MACROS, AND MODULES
SECTION 6.1: IMMEDIATE AND DIRECT ADDRESSING
MODES
SECTION 6.2: REGISTER INDIRECT ADDRESSING MODE
SECTION 6.3: LOOK-UP TABLE AND TABLE PROCESSING
SECTION 6.4: BIT-ADDRESSABILITY OF DATA RAM
SECTION 6.5: BANK SWITCHING IN THE PICI8
SECTION 6.6: CHECK SUM AND ASCII SUBROUTINES
SECTION 6.7: MACROS AND MODULES
194
199
205
214
219
227
234
CHAPTER 7: PIC PROGRAMMING IN C
SECTION 7.1: DATA TYPES AND TIME DELAYS IN C
SECTION 7.2: I/O PROGRAMMING IN C
SECTION 7.3: LOGIC OPERATIONS IN C
SECTION 7.5: DATA SERIALIZATION IN C
SECTION 7.6: PROGRAM ROM ALLOCATION IN CI8
SECTION 7.7: DATA RAM ALLOCATION IN C18
251
252
259
267
277
280
286
193
CHAPTER 8: PIC18F HARDWARE CONNECTION AND
ROM LOADERS
SECTION 8.1: PIC18F458/452 PIN CONNECTION
SECTION 8.2: PIC18 CONFIGURATION REGISTERS
SECTION 8.3: EXPLAINING THE INTEL HEX FILE
FOR PIC18
SECTION 8.4: PICI8 TRAINER DESIGN AND
LOADING
323
CHAPTER 9: PIC18
AND C
SECTION 9.1:
SECTION 9.2:
SECTION 9.3:
SECTION 9.4:
335
336
355
362
373
299
300
304
316
TIMER PROGRAMMING IN ASSEMBLY
PROGRAMMING TIMERS 0 AND 1
COUNTER PROGRAMMING
PROGRAMMING TIMERS 0 AND 1 IN C
PROGRAMMING TIMERS 2 AND 3
vii
CHAPTER 10: PIC18 SERIAL PORT PROGRAMMING IN
ASSEMBLY AND C
SECTION 10.1: BASICS OF SERIAL COMMUNICATION
SECTION 10.2: PICI8 CONNECTION TO RS232
SECTION 10.3: PICI8 SERIAL PORT PROGRAMMING
IN ASSEMBLY
SECTION 10.4: PICI8 SERIAL PORT PROGRAMMING
IN C
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY
AND C
SECTION 11.1: PICI8 INTERRUPTS
SECTION 11.2: PROGRAMMING TIMER INTERRUPTS
SECTION 11.3: PROGRAMMING EXTERNAL HARDWARE
INTERRUPTS
SECTION 11.4: PROGRAMMING THE SERIAL
COMMUNICATION INTERRUPTS
SECTION 11.5: PORTB-CHANGE INTERRUPT
SECTION 11.6: INTERRUPT PRIORITY IN THE PICI8
387
388
395
397
414
423
424
429
439
445
449
454
CHAPTER 12: LCD AND KEYBOARD INTERFACING
SECTION 12.1: LCD INTERFACING
SECTION 12.2: KEYBOARD INTERFACING
473
474
487
CHAPTER 13: ADC, DAC, AND SENSOR INTERFACING
SECTION 13.1: ADC CHARACTERISTICS
SECTION 13.2: ADC PROGRAMMING IN THE PICI8
SECTION 13.3: DAC INTERFACING
SECTION 13.4: SENSOR INTERFACING AND SIGNAL
CONDITIONING
499
500
505
516
CHAPTER 14: USING FLASH AND EEPROM MEMORIES
FOR DATA STORAGE
SECTION 14.1: SEMICONDUCTOR MEMORY
SECTION 14.2: ERASING AND WRITING TO FLASH
IN THE PICI8F
SECTION 14.3: READING AND WRITING TO DATA
EEPROM IN THE PICI8
CHAPTER 15: CCP AND ECCP PROGRAMMING
SECTION 15.1: STANDARD AND ENHANCED CCP
MODULES
SECTION 15.2: COMPARE MODE PROGRAMMING
SECTION 15.3: CAPTURE MODE PROGRAMMING
SECTION 15.4: PWM PROGRAMMING
SECTION 15.5: ECCP PROGRAMMING
viii
521
529
530
539
555
569
570
573
579
586
592
CHAPTER 16: SPI PROTOCOL AND DS1306 RTC
INTERFACING
SECTION 16.1: SPI BUS PROTOCOL
SECTION 16.2: DS1306 RTC INTERFACING AND
PROGRAMMING
SECTION 16.3: DS1306 RTC PROGRAMMING IN C
SECTION 16.4: ALARM AND INTERRUPT FEATURES
OF THE DS1306
603
604
608
619
622
CHAPTER 17: MOTOR CONTROL: RELAY, PWM, DC,
AND STEPPER MOTORS
SECTION 17.1: RELAYS AND OPTOISOLATORS
SECTION 17.2: STEPPER MOTOR INTERFACING
SECTION 17.3: DC MOTOR INTERFACING AND PWM
SECTION 17.4: PWM MOTOR CONTROL WITH CCP
SECTION 17.5: DC MOTOR CONTROL WITH ECCP
635
636
642
651
663
665
APPENDIX A: PICI8 INSTRUCTIONS: FORMAT AND
DESCRIPTION
673
APPENDIX B: BASICS OF WIRE WRAPPING
721
APPENDIX C: IC TECHNOLOGY AND SYSTEM DESIGN ISSUES
725
APPENDIX D: FLOWCHARTS AND PSEUDOCODE
745
APPENDIX E: PICI8 PRIMER FOR x86 AND 8051 PROGRAMMERS
750
APPENDIX F: ASCII CODES
752
APPENDIX G: ASSEMBLERS, DEVELOPMENT RESOURCES,
AND SUPPLIERS
754
APPENDIX H: DATA SHEETS
756
INDEX
807
ix
INTRODUCTION
Products using microprocessors generally fall into two categories. The first
category uses high-performance microprocessors such as the Pentium in applications where system performance is critical. We have an entire book dedicated to
this topic, The 80x86 IBM PC and Compatible Computers, Volumes I and II, from
Prentice Hall. In the second category of applications, performance is secondary;
issues of cost, space, power, and rapid development are more critical than raw processing power. The microprocessor for this category is often called a microcontroller.
This book is for the second category of applications. The PIC 18 is a widely used microcontroller. There are many reasons for this, including the existence
of massive support in both software and hardware by Microchip Technology. This
book is intended for use in college-level courses teaching microcontrollers and
embedded systems. It not only establishes a foundation of Assembly language
programming, but also provides a comprehensive treatment of PIC 18 interfacing
for engineering students. From this background, the design and interfacing of
microcontroller-based embedded systems can be explored. This book can also be
used by practicing technicians, hardware engineers, computer scientists, and hobbyists. It is an ideal source for those building stand-alone projects, or projects in
which data is collected and fed into a PC for distribution on a network.
Prerequisites
Readers should have had an introductory digital course. Knowledge of
Assembly language would be helpful but is not necessary. Although the book is
written for those with no background in Assembly language programming, students with prior Assembly language experience will be able to gain a mastery of
PICI8 architecture very rapidly and start on their projects right away. For the
PICI8 C programming sections of the book, a basic knowledge ofC programming
is required. We use the PICI8 C compiler from Microchip Technology throughout
the book. The PIC 18 C compiler is compatible with MPLAB and is available for
free from the Microchip website (www.microchip.com). We encourage you to use
the MPLAB to simulate and run the programs in this book.
Overview
A systematic, step-by-step approach is used to cover various aspects of
PICI8 C and Assembly language programming and interfacing. Many examples
and sample programs are given to clarify the concepts and provide students with
an opportunity to learn by doing. Review questions are provided at the end of each
section to reinforce the main points of the section.
Chapter 0 covers number systems (binary, decimal, and hex), and provides
an introduction to basic logic gates and computer terminology. This is designed
especially for students, such as mechanical engineering students who have not
taken a digital logic course or those who need to refresh their memory on these
topics.
Chapter I discusses the history of the PIC 18 and features of other PIC
family members such as the PIC 16. It also provides a list of various members of
x
the PICIS family.
Chapter 2 discusses the internal architecture of the PIC IS and explains the
use of a PIC IS assembler to create ready-to-run programs. It also explores the
stack and the flag register.
In Chapter 3 the topics of loop, jump, and call instructions are discussed,
with many programming examples.
Chapter 4 is dedicated to the discussion of 110 ports. This allows students
who are working on a project to start experimenting with PICIS 1/0 interfacing
and start the project as soon as possible.
Chapter 5 is dedicated to arithmetic, logic instructions, and programs.
Chapter 6 covers the PIC IS addressing modes and explains how to access
the data stored in the code space of the PIC IS, as well as how to do bank switchmg.
The C programming of the PIC IS is covered in Chapter 7. We use the
PICIS C compiler from Microchip Technology for this and other C programs of
the PIC IS family throughout the book. The PIC IS C compiler is compatible with
MPLAB and is available for free from the www.microchip.com website.
In Chapter S we discuss the hardware connection of the PIC IS chip.
Chapter 9 describes the PIC IS timers and how to use them as event counters.
Chapter 10 is dedicated to serial data communication ofthe PICIS and its
interfacing to the RS232. It also shows PIC IS communication with COM ports of
the xS6 IBM PC and compatible computers.
Chapter II provides a detailed discussion of PIC IS interrupts with many
examples on how to write interrupt handler programs.
Chapter 12 shows PICIS interfacing with real-world devices such as LCDs
and keyboards.
Chapter 13 shows PIC IS interfacing with real-world devices such as DAC
chips, ADC chips, and sensors.
In Chapter 14 we cover how to use PICIS Flash and EEPROM memories
for data storage.
Chapter IS covers the CCP and ECCP modules inside the PICIS and shows
how they are used.
Chapter 16 shows how to connect and program the DS 1306 real-time clock
chip using the SPI bus protocol.
Finally, Chapter 17 shows basic interfacing to relays, optoisolators, and
motors.
The appendices have been designed to provide all reference material
required for the topics covered in the book. Appendix A describes each PIC IS
instruction in detail, with examples. Appendix B describes basics of wire wrapping. Appendix C covers IC technology and logic families, as well as PIC IS 110
port interfacing and fan-out. Make sure you study this before connecting the
PIC IS to an external device. In Appendix D, the use of flowcharts and psuedocode
is explored. Appendix E is for students familiar with xS6 and S051 architectures
who need to make a rapid transition to PICIS architecture. Appendix F provides
the table of ASCII characters. Appendix G lists resources for assembler shareware,
and electronics parts. Appendix H contains data sheets for the PICIS chip.
xi
Lab Manual
The lab manual covers some very basic labs and can be found at the
www.MicroDigitalEd.com website. The more advanced and rigorous lab assignments are left up to the instructors depending on the course objectives, class level,
and whether the course is graduate or undergraduate. The support materials for this
and other books by the authors can be found on this website, too.
Solutions Manual/PowerPoint® Slides
The end-of-chapter problems cover some very basic concepts. The more
challenging and rigorous homework assignments are left up to the instructors
depending on the course objectives, class level, and whether the course is graduate or undergraduate. The solutions manual was produced with the help of Mr.
Rasti and Prof. Faramarz Mortezae. The solutions manual and PowerPoint®
slides for the drawings are available online for instructors only.
Online Instructor Resources
To access supplementary materials online, instructors need to request an
instructor access code. Go to www.prenhall.com.click the Instructor Resource
Center link, and then click Register Today for an instructor access code. Within
48 hours after registering you will receive a confirming e-mail including an
instructor access code. Once you have received your code, go to the site and log
on for full instructions on downloading the materials you wish to use.
Acknowledgments
This book is the result of the dedication and encouragement of many individuals. Our sincere and heartfelt appreciation goes to all of them.
First, we would like to thank Mr. Javad Rasti of Esfahan University. His
detailed and thorough reading of the chapters resulted in finding and fixing some
of the errors before the book was published. Many of the drawings and tables in
this book were recreated from PICl8 data sheets by Pedram Mazidi. Numerous
professors, professional engineers, and students found errors or made suggestions
in improving this book. We would like to thank all of them sincerely for their
enthusiasm and support. They are Javad Rasti (Esfahan University), Vahid
Mokhtari (BIHE), Mohammadi Abdar (Azad University), Clyde Knight, Sam
Waterman, and Faramarz Mortezaei (all from DeVry University), Frank Fortman,
David Goodman, and Maryam Mohseni. Their encouragement meant a great deal
to us in writing this book.
xii
Thanks to the reviewers of this edition:
Shujen Chen, DeVry University - Tinley Park;
Lawrence Lam, DeVry University - Federal Way;
Vahid Mokhtari, BIHE University;
Faramarz Mortezaie, DeVry University - Fremont;
Sepehr Naimi, BIHE University;
Javad Rasti, Esfahan University; and
Chao-Yin Wang, DeVry University - North Brunswick.
Finally, we would like to thank the people at Prentice Hall, in particular our
editor Jeff Riley, who continues to support and encourage our writing, and our production editor Rex Davidson, who made the book a reality. We were lucky to get
the best copy editors in the world, Janice Mazidi and Bret Workman. Thank you
both for your fantastic job, as usual
We enjoyed writing this book, and hope you enjoy reading it and using it
for your courses and projects. Please let us know if you have any suggestions or
find any errors.
Assemblers/Compiler
The MPLAB and PICl8 C compilers can be downloaded from the following website:
http://www.microchip.com
xiii
ABOUT THE AUTHORS
Muhammad Ali Mazidi went to Tabriz University and holds Master's
degrees from both Southern Methodist University and the University of Texas at
Dallas. He is currently a.b.d. on his Ph.D. in the Electrical Engineering
Department of Southern Methodist University. He is co-author of some widely
used textbooks, including The 80x86 IBM PC and Compatible Computers and
The 8051 Microcontroller and Embedded Systems, also available from Prentice
Hall. He teaches microprocessor-based system design at DeVry University in
Dallas, Texas. He is the founder of MicroDigitalEd.com.
Rolin McKinlay has a BSEET from DeVry University. He is co-author of
The 8051 Microcontroller and Embedded Systems. He is working on his Master's
degree and PE license in the state of Texas. He is currently self-employed as a senior embedded engineer and hardware designer, and is a partner in
MicroDigitalEd.com.
Danny Causey is a U.S. Army veteran having served in Germany and Iraq.
He graduated from the CET department of DeVry University. His areas of interest
include networking, game development, and microcontroller and FPGA embedded
system design. He is a partner in MicroDigitalEd.com.
The authors can be contacted at the following e-mail addresses if you have
any comments or suggestions, or if you find any errors.
mdebooks@yahoo.com
mmazidi@microdigitaled.com
rmckinlay@microdigitaled.com
dcausey@microdigitaled.com
xiv
This book is dedicated
to the memory of Mr. N. Akhtar-Khavari and Mr. Z. Mahrami
for their dedication to the cause of world peace.
- Muhammad Ali Mazidi
To Tony and Jim for their friendship and faith in me over the years.
- Rolin D. McKinlay
I dedicate my part to my brother John, who reached out to me even though we
lived in different homes. The experience that was given provided me the
inspiration to look for something more in life.
- Danny Causey
xv
CHAPTER 0
INTRODUCTION TO
COMPUTING
OBJECTIVES
Upon completion of this chapter, you will be able to:
»
»
»
»
»
»
»
»
»
»
»
»
»
»
Convert any number from base 2, base 10, or base 16 to any of the
other two bases
Add and subtract hex numbers
Add binary numbers
Represent any binary number in 2's complement
Represent an alphanumeric string in ASCII code
Describe the logical operations AND, OR, NOT, XOR, NAND, and NOR
Use logic gates to diagram simple circuits
Explain the difference between a bit, a nibble, a byte, and a word
Give precise mathematical definitions of the terms kilobyte, megabyte,
gigabyte, and terabyte
Explain the difference between RAM and ROM and describe their use
Describe the purpose of the major components of a computer system
List the three types of buses found in computers and describe the
purpose of each type of bus
Describe the role of the CPU in computer systems
List the major components of the CPU and describe the purpose of each
1
To understand the software and hardware of a microcontroller-based system, one must first master some very basic concepts underlying computer design.
In this chapter (which in the tradition of digital computers is called Chapter 0), the
fundamentals of numbering and coding systems are presented. After an introduction to logic gates, an overview of the workings inside the computer is given.
Finally, in the last section we give a brief history of CPU architecture. Although
some readers may have an adequate background in many of the topics ofthis chapter, it is recommended that the material be scanned, however briefly.
SECTION 0.1: NUMBERING AND CODING SYSTEMS
Whereas human beings use base 10 (decimaT) arithmetic, computers use
the base 2 (binary) system. In this section we explain how to convert from the decimal system to the binary system, and vice versa. The convenient representation of
binary numbers, called hexadecimal, also is covered. Finally, the binary format of
the alphanumeric code, called ASCII, is explored.
Decimal and binary number systems
Although there has been speculation that the origin of the base 10 system
is the fact that human beings have 10 fingers, there is absolutely no speculation
about the reason behind the use of the binary system in computers. The binary system is used in computers because I and 0 represent the two voltage levels of on
and off. Whereas in base 10 there are 10 distinct symbols, 0, 1,2, ... , 9, in base 2
there are only two, 0 and 1, with which to generate numbers. Base 10 contains digits 0 through 9; binary contains digits 0 and 1 only. These two binary digits, 0 and
1, are commonly referred to as bits.
Converting from decimal to binary
One method of converting from decimal to binary is to divide the decimal
number by 2 repeatedly, keeping track of the remainders. This process continues
until the quotient becomes zero. The remainders are then written in reverse order
to obtain the binary number. This is demonstrated in Example 0-1.
Example 0-1
Convert 25 10 to binary.
Solution:
25/2
12/2
6/2
3/2
1/2
=
1
=
0
1
=
=
=
Therefore, 25 10
2
Remainder
Quotient
12
6
3
1
=
11001 2,
1
LSB (least significant bit)
o
o
MSB (most significant bit)
Converting from binary to decimal
740683 10
To convert from binary to decimal, it is
important to understand the concept of weight
associated with each digit position. First, as an
analogy, recall the weight of numbers in the base
10 system, as shown in the diagram. By the same
token, each digit position of a number in base 2
has a weight associated with it:
3 x 10°
8 x 10 1
6 x 10 2
a x 10 3
4 x 10 4
7 x 105
3
80
600
0000
40000
=
700000
740683
Decimal
Binary
=
1
=
a
1
00
100
0000
10000
100000
110101
110101 2 =
1 x
a x
1 x
a x
1 x
1 x
20
21
22
23
24
25
=
=
=
=
=
1 xl
a X2
1 X4
a X8
1 x 16
1 x 32
4
=
a
16
32
53
=
=
Knowing the weight of each bit in a binary number makes it simple to add
them together to get its decimal equivalent, as shown in Example 0-2.
Example 0-2
Convert 11001 2 to decimal.
Solution:
Weight:
Digits:
Sum:
16
I
16 +
8
I
8+
4
0
0+
I
I
I = 25 10
2
0
0+
Knowing the weight associated with each binary bit position allows one to
convert a decimal number to binary directly instead of going through the process
of repeated division. This is shown in Example 0-3.
Example 0-3
Use the concept of weight to convert 3910 to binary.
Solution:
Weight:
32
I
32+
Therefore, 3910 = 100111 2.
16
0
0+
8
0
0+
4
I
4+
CHAPTER 0; INTRODUCTION TO COMPUTING
2
I
2+
I
I
1=39
3
Hexadecimal system
Table 0-1: Base 16
Number System
Base 16, or the hexadecimal system as it is called in
computer literature, is used as a convenient representation Decimal
of binary numbers. For example, it is much easier for a 0
human being to represent a string of Os and 1s such as 1
100010010110 as its hexadecimal equivalent of 896H. The 2
binary system has 2 digits, 0 and 1. The base 10 system has 3
10 digits, 0 through 9. The hexadecimal (base 16) system 4
has 16 digits. In base 16, the first 10 digits, 0 to 9, are the 5
same as in decimal, and for the remaining six digits, the let- 6
ters A, B, C, D, E, and F are used. Table 0-1 shows the 7
equivalent binary, decimal, and hexadecimal representa- 8
9
tions for 0 to 15.
10
Converting between binary and hex
11
To represent a binary number as its equivalent hexa- 12
decimal number, start from the right and group 4 bits at a 13
time, replacing each 4-bit binary number with its hex equiv- 14
alent shown in Table 0-1. To convert from hex to binary, 15
each hex digit is replaced with its 4-bit binary equivalent.
See Examples 0-4 and 0-5.
Binary
0000
0001
0010
0011
0100
0101
OllO
0111
1000
1001
1010
lOll
1100
1101
1110
III I
Example 0-4
Represent binary 100111110 10 I in hex.
Solution:
First the number is grouped into sets of 4 bits: 1001 1111 0101.
Then each group of 4 bits is replaced with its hex equivalent:
1001 III 1 0101
9
F
5
Therefore, 100111110101 2 = 9F5 hexadecimal.
Example 0-5
Convert hex 29B to binary.
Solution:
2
9
B
0010 1001 1011
Dropping the leading zeros gives 1010011011.
=
.
.
Convertmg from deCimal to hex
Converting from decimal to hex could be approached in two ways:
1. Convert to binary first and then convert to hex. Example 0-6 shows this
method of converting decimal to hex.
2. Convert directly from decimal to hex by repeated division, keeping track of the
remainders. Experimenting with this method is left to the reader.
4
Hex
0
I
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Example 0-6
(a) Convert 45 10 to hex.
32
I
lQ
£
1
I
1
0
1
I
0
1
32
I
16
1
First, convert to binary.
32 + 8 + 4 + 1 = 45
45 10 =00101101 2 = 2D hex
(b) Convert 629 10 to hex.
ill
I
256
0
128
0
64
1
£
1
I
1
0
1
0
1
629 10 = (512 + 64 + 32 + 16 + 4 + 1) = 0010 0111 0101 2 = 275 hex
(c) Convert 171410 to hex.
1024 512
1
1
256
0
128
1
64
0
32
16
1
1
£
o
1
o
I
1
o
1
171410 = (1024 + 512 + 128 + 32 + 16 + 2) = 0110 lOll 00102 = 6B2 hex
Converting from hex to decimal
Conversion from hex to decimal can also be approached in two ways:
I. Convert from hex to binary and then to decimal. Example 0-7 demonstrates
this method of converting from hex to decimal.
2. Convert directly from hex to decimal by summing the weight of all digits.
Example 0-7
Convert the following hexadecimal numbers to decimal.
(a) 6B2 16 = 0110 1011 0010 2
1024 512
256
128
I
101
64
0
32
16
1
1
£
o
1
o
I
I
1
o
1024 + 512 + 128 + 32 + 16 + 2 = 171410
(b) 9F2D 16 = 1001 111100101101 2
32768 16384 8192 4096 2048 1024 512 256 128 64 32 lQ £ 1 I 1
1
001111100101101
32768 + 4096 + 2048 + 1024 + 512 + 256 + 32 + 8 + 4 + 1 = 40,749 10
CHAPTER 0: INTRODUCTION TO COMPUTING
5
Table 0-2: Counting in Bases
Counting in bases 10, 2, and 16
Decimal Binary
o
00000
00001
2
00010
3
00011
4
00100
5
00101
6
00110
7
00111
8
01000
9
01001
10
01010
II
01011
12
01100
13
01101
14
01110
15
01111
16
10000
10001
17
18
10010
19
10011
20
10100
21
10101
22
10110
23
10111
24
11000
25
11001
26
11010
27
11 OIl
28
11100
29
11101
30
11110
31
11111
To show the relationship between all
three bases, in Table 0-2 we show the sequence
of numbers from 0 to 31 in decimal, along with
Hex
o
2
the equiva- Table 0-3: Binary Addition
lent binary
and
hex ;,;A;.,+~B;...._C~a;;.;rr;ay_"""";S~u;;;;m=~
0
0
numbers. 0+0
0
I
Notice In 0+ I
1
+
0
0
1
each base
0
that when 1 + 1
one more IS
added
to
the highest digit, that digit becomes zero and a
1 is carried to the next-highest digit position.
For example, in decimal, 9 + 1 = 0 with a carry
to the next-highest position. In binary, 1 + 1 =
owith a carry; similarly, in hex, F + 1 = 0 with
a carry.
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
lA
1B
lC
1D
IE
IF
Addition of binary and hex numbers
The addition of binary numbers is a
very straightforward process. Table 0-3 shows
the addition of two bits. The discussion of subtraction of binary numbers is bypassed since all
computers use the addition process to implement subtraction. Although computers have
adder circuitry, there is no separate circuitry for
subtractors. Instead, adders are used in conjunction with 2:S complement circuitry to perform subtraction. In other words, to implement
"x - y", the computer takes the 2 's complement
of y and adds it to x. The concept of 2 's complement is reviewed next. Example 0-8 shows
the addition of binary numbers.
Example 0-8
Add the following binary numbers. Check against their decimal equivalents.
Solution:
Binary
+
6
1101
1001
10110
Decimal
13
.....2
22
2's complement
To get the 2's complement of a binary number, invert all the bits and then
add I to the result. Inverting the bits is simply a matter of changing all Os to I sand
Is to Os. This is called the 1 s complement. See Example 0-9.
Example 0-9
Take the 2's complement of 100 III 0 I.
Solution:
10011101
01100010
+
binary number
I's complement
I
01100011
2's complement
Addition and subtraction of hex numbers
In studying issues related to software and hardware of computers, it is
often necessary to add or subtract hex numbers. Mastery of these techniques is
essential. Hex addition and subtraction are discussed separately below.
Addition of hex numbers
This section describes the process of adding hex numbers. Starting with the
least significant digits, the digits are added together. If the result is less than 16,
write that digit as the sum for that position. If it is greater than 16, subtract 16 from
it to get the digit and carry I to the next digit. The best way to explain this is by
example, as shown in Example 0-10.
Example 0-10
Perform hex addition: 2309 + 94BE.
Solution:
+
2309
94BE
B897
LSD: 9 + 14 = 23
1 + 13 + 11 = 25
23 - 16 = 7 with a carry
25 - 16 = 9 with a carry
1+3~4=8
MSO: 2 +9
=
B
Subtraction of hex numbers
In subtracting two hex numbers, if the second digit is greater than the first,
borrow 16 from the preceding digit. See Example 0-11.
ASCII code
The discussion so far has revolved around the representation of number
systems. Because all information in the computer must be represented by Os and
I s, binary patterns must be assigned to letters and other characters. In the 1960s a
standard representation called ASCII (American Standard Code for Information
Interchange) was established. The ASCII (pronounced "ask-E") code assigns bina-
CHAPTER 0: INTRODUCTION TO COMPUTING
7
ry patterns for numbers 0 to 9, all the let- Hex Symbol
Hex Symbol
ters of the English alphabet, both upper- 41
A
61
a
case (capital) and lowercase, and many 42
B
62
b
43
C
63
c
control codes and punctuation marks.
D
64
d
The great advantage ofthis system is that 44
it is used by most computers, so that
y
79
y
information can be shared among corn- 59
5A
Z
7A
z
puters. The ASCII system uses a total of
7 bits to represent each code. For examFigure 0-1. Selected ASCII Codes
pie, 100 000 I is assigned to the uppercase letter "A" and 110 000 I is for the
lowercase "a". Often, a zero is placed in the most-significant bit position to make
it an 8-bit code. Figure 0-1 shows selected ASCII codes. A complete list of ASCII
codes is given in Appendix F. The use of ASCII is not only standard for keyboards
used in the United States and many other countries but also provides a standard for
printing and displaying characters by output devices such as printers and monitors.
Notice that the pattern of ASCII codes was designed to allow for easy
manipulation of ASCII data. For example, digits 0 through 9 are represented by
ASCII codes 30 through 39. This enables a program to easily convert ASCII to
decimal by masking off the "3" in the upper nibble. Also notice that there is a relationship between the uppercase and lowercase letters. The uppercase letters are
represented by ASCII codes 41 through 5A while lowercase letters are represented by codes 61 through 7A. Looking at the binary code, the only bit that is different between the uppercase "A" and lowercase "a" is bit 5. Therefore, conversion
between uppercase and lowercase is as simple as changing bit 5 of the ASCII code.
Example 0-11
Perform hex subtraction: 59F - 2B8.
Solution:
-
59F
2B8
2E7
LSD: 8 from 15 = 7
11 from 25 (9 + 16) = 14 (E)
2 from 4 (5 - I) = 2
Review Questions
1. Why do computers use the binary number system instead of the decimal system?
2. Convert 3410 to binary and hex.
3. Convert 110101 2 to hex and decimal.
4. Perform binary addition: 101100 + 1O\.
5. Convert 1011002 to its 2's complement representation.
6. Add 36BH + F6H.
7. Subtract 36BH - F6H.
8. Write "80x86 CPUs" in its ASCII code (in hex form).
8
SECTION 0.2: DIGITAL PRIMER
This section gives an overview of digital logic and design. First, we cover
binary logic operations, then we show gates that perfonn these functions. Next,
logic gates are put together to fonn simple digital circuits. Finally, we cover some
logic devices commonly found in microcontroller interfacing.
Binary logic
Sf-
As mentioned earlier, computers use the
binary number system because the two voltage levels can be represented as the two digits 0 and I.
Signals in digital electronics have two distinct voltage levels. For example, a system may define 0 V as
logic 0 and +5 V as logic I. Figure 0-2 shows this
system with the built-in tolerances for variations in
the voltage. A valid digital signal in this example
should be within either of the two shaded areas.
4
Logic I
3f-
If01-
Logic 0
Figure 0-2. Binary Signals
Logic gates
Binary logic gates are simple circuits that
take one or more input signals and send out one output signal. Several of these gates are defined below.
Logical AND Function
In!!uts
Output
XY
00
XANDY
0
0
0
1
AND gate
oI
The AND gate takes two or more inputs and
perfonns a logic AND on them. See the truth table
and diagram of the AND gate. Notice that if both
inputs to the AND gate are 1, the output will be 1.
Any other combination of inputs will give a 0 output.
The example shows two inputs, x and y. Multiple
outputs are also possible for logic gates. In the case
of AND, if all inputs are 1, the output is I. If any
input is 0, the output is O.
I0
11
OR gate
The OR logic function will output a I if one
or more inputs is 1. If all inputs are 0, then and only
then will the output be O.
yX ~ XAND Y
~
Logical OR Function
In!!uts
Out!!ut
XY
00
o1
10
11
XORY
0
1
1
~=f)-XORY
Tri-state buffer
Buffer
A buffer gate does not change the logic level
of the input. It is used to isolate or amplify the sigx -----l>-y
nal.
Control --.J
CHAPTER 0: INTRODUCTION TO COMPUTING
9
Inverter
The inverter, also called NOT, outputs the
value opposite to that input to the gate. That is, a I
input will give a 0 output, while a 0 input will give a
I output.
Logical Inverter
Input
Output
x
NOT X
I
o
o
XORgate
The XOR gate perfonns an exclusive-OR
operation on the inputs. Exclusive-OR produces a I
output if one (but only one) input is I. If both
operands are 0, the output is O. Likewise, if both
operands are I, the output is also O. Notice from the
XOR truth table, that whenever the two inputs are
the same, the output is O. This function can be used
to compare two bits to see if they are the same.
NAND and NOR gates
The NAND gate functions like an AND gate
with an inverter on the output. It produces a 0 output
when all inputs are I; otherwise, it produces a I output. The NOR gate functions like an OR gate with an
inverter on the output. It produces a I if all inputs are
0; otherwise, it produces a o. NAND and NOR gates
are used extensively in digital design because they
are easy and inexpensive to fabricate. Any circuit
that can be designed with AND, OR, XOR, and
INVERTER gates can be implemented using only
NAND and NOR gates. A simple example of this is
given below. Notice in NAND, that if any input is 0,
the output is I. Notice in NOR, that if any input is I,
the output is o.
I
x --{>o---- NOT X
Logical XOR Function
Inputs
Output
XY
XXORY
0
I
00
oI
I0
II
I
0
Logical NAND Function
Inputs
XY
00
Output
XNANDY
I
I
I
oI
I0
I I
o
~ =::[)O-X NAND Y
Logic design using gates
Next we will show a simple logic design to
add two binary digits. If we add two binary digits
there are four possible outcomes:
Carry Sum
0+0=
0+1=
1+0=
I+I=
10
0
0
0
I
0
I
I
0
Logical NOR Function
Inputs
Output
XY
00
XNORY
I
01
0
100
I I
~
=::L»---
0
X NOR Y
Notice that when we add 1 + 1 we get 0 with a carry to the next higher
place. We will need to detennine the sum and the carry for this design. Notice that
the sum column above matches the output for the XOR function, and that the carry
column matches the output for the AND function. Figure 0-3(a) shows a simple
adder implemented with XOR and AND gates. Figure 0-3(b) shows the same logic
circuit implemented with AND and OR gates and inverters.
x
y
x
y--'--j
)---Sum
}---Sum
X-.,.--i
Y
L--L)--- Carry
X---i
)-------Carry
y--j
(b) Half-Adder Using AND, OR, Inverters
(a) Half-Adder Using XOR and AND
Figure 0-3. Two Implementations of a Half-Adder
Figure 0-4 shows a block diaX
Sum
gram of a half-adder. Two half-adders
can be combined to fonn an adder that
Halfcan add three input digits. This is called
Adder
a full-adder. Figure 0-5 shows the logic
y
Carry
out
diagram of a full-adder, along with a
block diagram that masks the details of
the circuit. Figure 0-6 shows a 3-bit F·
0-4 Bl k D·
f H If. Add
er
.
h
full dd
.gure . oe mgram 0 a a add er usmg tree
-a ers.
x
y
X
Sum
y
Half- Carry
Adder
Sum
- C out
C in
HalfAdder Carry
C in
Final Sum
Figure 0-5. Full-Adder Built From a Half-Adder
CHAPTER 0: INTRODUCTION TO COMPUTING
11
Decoders
Another example of the application
of logic gates is the decoder. Decoders are
widely used for address decoding in computer design. Figure 0-7 shows decoders for
9 (1001 binary) and 5 (0101) using inverters and AND gates.
Flip-flops
XO
YO
FullAdder
X1
FullAdder
I------SO
Carry
1-------S1
A widely used component in digital Y1
Carry
systems is the flip-flop. Frequently, flipflops are used to store data. Figure 0-8
shows the logic diagram, block diagram,
and truth table for a flip-flop.
X2
1------S2
The D flip-flop is widely used to
Fulllatch data. Notice from the truth table that a Y2
Adder Carry
1------S3
D-FF grabs the data at the input as the clock
is activated. A D-FF holds the data as long
as the power is on.
LF-i-g-ur-e-0-_-6-.3---B-it-A-dd-e-r-U-s-i-ng-T-h-re-e-F-u-'-'----'
Adders
LSB
LSB
---{>o(a) Address decoder for 9 (binary 1001)
The output of the AND gate will be 1
ifand only if the input is binary 1001.
(b) Address decoder for 5 (binary 010 1)
The output of the AND gate will be 1
ifand only if the input is binary 0101.
Figure 0-7. Address Decoders
D
Q
Q
Figure 0-8. D Flip-Flops
12
Q
"1"1-
Clk
elk
(a) Circuit diagram
D
elk
No
Q -(b) Block diagram
D
x
0
I
x = don't care
(c) Truth table
0
I
Review Questions
I. The logical operation _ _ gives a I output when all inputs are I.
2. The logical operation _ _ gives a I output when one or more of its inputs is
I.
3. The logical operation _ _ is often used to compare two inputs to determine
whether they have the same value.
4. A _ _ gate does not change the logic level of the input.
5. Name a common use for flip-flops.
6. An address
is used to identifY a predetermined binary address.
SECTION 0.3: INSIDE THE COMPUTER
In this section we provide an introduction to the organization and internal
working of computers. The model used is generic, but the concepts discussed are
applicable to all computers, including the IBM PC, PS/2, and compatibles. Before
embarking on this subject, it will be helpful to review definitions of some of the
most widely used terminology in computer literature, such as K, mega, giga, byte,
ROM, RAM, and so on.
Some important terminology
One of the most important features of a computer is how much memory it
has. Next we review terms used to describe amounts of memory in IBM PCs and
compatibles. Recall from the discussion
Bit
o
above that a bit is a binary digit that can Nibble
0000
have the value 0 or 1. A byte is defined as Byte
0000 0000
8 bits. A nibble is half a byte, or 4 bits. A Word 0000 0000
0000 0000
word is two bytes, or 16 bits. The display is
intended to show the relative size of these
units. Of course, they could all be composed of any combination of zeros and ones.
A kilobyte is 2 10 bytes, which is 1024 bytes. The abbreviation K is often
used to represent kilobytes. For example, some floppy disks hold 356K of data. A
megabyte, or meg as some call it, is 220 bytes. That is a little over I million bytes;
it is exactly 1,048,576 bytes. Moving rapidly up the scale in size, a gigabyte is 230
bytes (over I billion), and a terabyte is 240 bytes (over I trillion). As an example
of how some of these terms are used, suppose that a given computer has 16
megabytes of memory. That would be 16 x 220 , or 24 x 220 , which is 224.
Therefore 16 megabytes is 224 bytes.
Two types of memory commonly used in microcomputers are RAM, which
stands for "random access memory" (sometimes called read/write memory), and
ROM, which stands for "read-only memory." RAM is used by the computer for
temporary storage of programs that it is running. That data is lost when the computer is turned off. For this reason, RAM is sometimes called volatile memory.
ROM contains programs and information essential to operation of the computer.
The information in ROM is permanent, cannot be changed by the user, and is not
lost when the power is turned off. Therefore, it is called nonvolatile memory.
CHAPTER 0: INTRODUCTION TO COMPUTING
13
Internal organization of computers
The internal working of every computer can be broken down into three
parts: CPU (central processing unit), memory, and IIO (input/output) devices (see
Figure 0-9). The function of the CPU is to execute (process) information stored in
memory. The function of I/O devices such as the keyboard and video monitor is to
provide a means of communicating with the CPU. The CPU is connected to memory and I/O through strips of wire called a bus. The bus inside a computer carries
information from place to place just as a street bus carries people from place to
place. In every computer there are three types of buses: address bus, data bus, and
control bus.
For a device (memory or I/O) to be recognized by the CPU, it must be
assigned an address. The address assigned to a given device must be unique; no
two devices are allowed to have the same address. The CPU puts the address (in
binary, of course) on the address bus, and the decoding circuitry finds the device.
Then the CPU uses the data bus either to get data from that device or to send data
to it. The control buses are used to provide read or write signals to the device to
indicate if the CPU is asking for information or sending information. Of the three
buses, the address bus and data bus determine the capability of a given CPU.
Address Bus
I
I
Memory
Peripherals
(RAM, ROM)
(monitor,
printer, etc.)
I
I
CPU
Data Bus
Figure 0-9. Inside the Computer
More about the data bus
Because data buses are used to carry information in and out of a CPU, the
more data buses available, the better the CPU. If one thinks of data buses as highway lanes, it is clear that more lanes provide a better pathway between the CPU
and its external devices (such as printers, RAM, ROM, etc.; see Figure 0-10). By
the same token, that increase in the number of lanes increases the cost of construction. More data buses mean a more expensive CPU and computer. The average size of data buses in CPUs varies between 8 and 64. Early personal computers such as Apple 2 used an 8-bit data bus, while supercomputers such as Cray use
a 64-bit data bus. Data buses are bidirectional, because the CPU must use them
either to receive or to send data. The processing power of a computer is related to
the size of its buses, because an 8-bit bus can send out I byte a time, but a 16-bit
bus can send out 2 bytes at a time, which is twice as fast.
14
More about the address bus
Because the address bus is used to identify the devices and memory connected to the CPU, the more address buses available, the larger the number of
devices that can be addressed. In other words, the number of address buses for a
CPU determines the number of locations with which it can communicate. The
number oflocations is always equal to 2\ where x is the number of address lines,
regardless of the size of the data bus. For example, a CPU with 16 address lines
can provide a total of 65,536 (2 16) or 64K of addressable memory. Each location
can have a maximum of I byte of data. This is because all general-purpose microprocessor CPUs are what is called byte addressable. As another example, the IBM
PC AT uses a CPU with 24 address lines and 16 data lines. Thus, the total accessible memory is 16 megabytes (224 = 16 megabytes). In this example there would
be 224 locations, and because each location is one byte, there would be 16
megabytes of memory. The address bus is a unidirectional bus, which means that
the CPU uses the address bus only to send out addresses. To summarize: The total
number of memory locations addressable by a given CPU is always equal to 2x
where x is the number of address bits, regardless of the size of the data bus.
, ,
Address Bus
•
RAM
•
ROM
Printer
Disk
•
Monitor
•
Keyboard
CPU
Data Bus
Read/write
Control Bus
FIgure 0-10. Internal Orgamzatton of a Computer
CPU and its relation to RAM and ROM
For the CPU to process information, the data must be stored in RAM or
ROM. The function of ROM in computers is to provide information that is fixed
and permanent. This is information such as tables for character patterns to be displayed on the video monitor, or programs that are essential to the working of the
computer, such as programs for testing and finding the total amount of RAM
installed on the system, or for displaying information on the video monitor. In contrast, RAM stores temporary information that can change with time, such as various versions of the operating system and application packages such as word processing or tax calculation packages. These programs are loaded from the hard
drive into RAM to be processed by the CPU. The CPU cannot get the information
CHAPTER 0: INTRODUCTION TO COMPUTING
15
from the disk directly because the disk is too slow. In other words, the CPU first
seeks the information to be processed from RAM (or ROM). Only if the data is not
there does the CPU seek it from a mass storage device such as a disk, and then it
transfers the information to RAM. For this reason, RAM and ROM are sometimes
referred to as primary memory and disks are called secondary memory.
Figure 0-11 shows a block diagram of the internal organization of the PC.
I
I Program Counter I
I
Flags
IInstruction Register I
I-I-I--
ALU
I
Instruction
decoder, timing,
and control
I
f---
Internal
buses
Register A
Register B
Register C
Register D
Figure 0-11. Internal Block Diagram of a CPU
Inside CPUs
A program stored in memory provides instructions to the CPU to perform
an action. The action can simply be adding data such as payroll data or controlling
a machine such as a robot. The function of the CPU is to fetch these instructions
from memory and execute them. To perform the actions of fetch and execute, all
CPUs are equipped with resources such as the following:
I. Foremost among the resources at the disposal of the CPU are a number of registers. The CPU uses registers to store information temporarily. The information could be two values to be processed, or the address of the value needed to
be fetched from memory. Registers inside the CPU can be 8-bit, 16-bit, 32-bit,
or even 64-bit registers, depending on the CPU. In general, the more and bigger the registers, the better the CPU. The disadvantage of more and bigger registers is the increased cost of such a CPU.
2. The CPU also has what is called the ALU (arithmetic/logic unit). The ALU section ofthe CPU is responsible for performing arithmetic functions such as add,
subtract, multiply, and divide, and logic functions such as AND, OR, and NOT.
16
n
o
[
3. Every CPU has what is called a program counter. The function of the program
counter is to point to the address of the next instruction to be executed. As each
instruction is executed, the program counter is incremented to point to the
address of the next instruction to be executed. The contents of the program
counter are placed on the address bus to find and fetch the desired instruction.
In the IBM PC, the program counter is a register called IP, or the instruction
pointer.
4. The function of the instruction decoder is to interpret the instruction fetched
into the CPU. One can think of the instruction decoder as a kind of dictionary,
storing the meaning of each instruction and what steps the CPU should take
upon receiving a given instruction. Just as a dictionary requires more pages the
more words it defines, a CPU capable of understanding more instructions
requires more transistors to design.
Internal working of computers
To demonstrate some of the concepts discussed above, a step-by-step
analysis of the process a CPU would go through to add three numbers is given
next. Assume that an imaginary CPU has registers called A, B, C, and D. It has an
8-bit data bus and a 16-bit address bus. Therefore, the CPU can access memory
from addresses 0000 to FFFFH (for a total of 10000H locations). The action to be
performed by the CPU is to put hexadecimal value 21 into register A, and then add
to register A values 42H and 12H. Assume that the code for the CPU to move a
value to register A is 10 II 0000 (BOH) and the code for adding a value to register
A is 0000 01 00 (04H). The necessary steps and code to perform them are as follows.
Action
Code
Data
Move value 2lH into register A
Add value 42H to register A
Add value l2H to register A
BOH
04H
04H
21H
42H
12H
If the program to perform the actions listed above is stored in memory
locations starting at 1400H, the following would represent the contents for each
memory address location:
Memory address
1400
1401
1402
1403
1404
1405
1406
Contents of memory address
(80) code for moving a value to register A
(21)value to be moved
(04)code for adding a value to register A
(42)value to be added
(04) code for adding a value to register A
(12)value to be added
(F4) code for halt
The actions performed by the CPU to run the program above would be as
follows:
1. The CPU's program counter can have a value between 0000 and FFFFH. The
program counter must be set to the value 1400H, indicating the address of the
CHAPTER 0: INTRODUCTION TO COMPUTING
17
2.
3.
4.
5.
6.
first instruction code to be executed. After the program counter has been
loaded with the address of the first instruction, the CPU is ready to execute.
The CPU puts l400H on the address bus and sends it out. The memory circuitry finds the location while the CPU activates the READ signal, indicating
to memory that it wants the byte at location l400H. This causes the contents
of memory location 1400H, which is BO, to be put on the data bus and brought
into the CPU.
The CPU decodes the instruction BO with the help of its instruction decoder
dictionary. When it finds the definition for that instruction it knows it must
bring into register A of the CPU the byte in the next memory location.
Therefore, it commands its controller circuitry to do exactly that. When it
brings in value 21 H from memory location 1401, it makes sure that the doors
of all registers are closed except register A. Therefore, when value 21 H comes
into the CPU it will go directly into register A. After completing one instruction, the program counter points to the address of the next instruction to be executed, which in this case is 1402H. Address 1402 is sent out on the address bus
to fetch the next instruction.
From memory location 1402H the CPU fetches code 04H. After decoding, the
CPU knows that it must add the byte sitting at the next address (1403) to the
contents of register A. After the CPU brings the value (in this case, 42H) into
register A, it provides the contents of register A along with this value to the
ALU to perform the addition. It then takes the result of the addition from the
ALU's output and puts it in register A. Meanwhile the program counter
becomes 1404, the address of the next instruction.
Address 1404H is put on the address bus and the code is fetched into the CPU,
decoded, and executed. This code again is adding a value to register A. The
program counter is updated to 1406H.
Finally, the contents of address 1406 are fetched in and executed. This HALT
instruction tells the CPU to stop incrementing the program counter and asking
for the next instruction. Without the HALT, the CPU would continue updating
the program counter and fetching instructions.
Now suppose that address 1403H contained value 04 instead of 42H. How
would the CPU distinguish between data 04 to be added and code 04? Remember
that code 04 for this CPU means "move the next value into register A". Therefore,
the CPU will not try to decode the next value. It simply moves the contents of the
following memory location into register A, regardless of its value.
Review Questions
1.
2.
3.
4.
5.
6.
7.
18
How many bytes is 24 kilobytes?
What does "RAM" stand for? How is it used in computer systems?
What does "ROM" stand for? How is it used in computer systems?
Why is RAM called volatile memory?
List the three major components of a computer system.
What does "CPU" stand for? Explain its function in a computer.
List the three types of buses found in computer systems and state briefly the
purpose of each type of bus.
8. State which of the following is unidirectional and which is bidirectional:
(a) data bus (b) address bus
9. If an address bus for a given computer has 16 lines, what is the maximum
amount of memory it can access?
10. What does "ALU" stand for? What is its purpose?
II. How are registers used in computer systems?
12. What is the purpose of the program counter?
13. What is the purpose of the instruction decoder?
SUMMARY
The binary number system represents all numbers with a combination of
the two binary digits, 0 and 1. The use of binary systems is necessary in digital
computers because only two states can be represented: on or off. Any binary number can be coded directly into its hexadecimal equivalent for the convenience of
humans. Converting from binary/hex to decimal, and vice versa, is a straightforward process that becomes easy with practice. The ASCII code is a binary code
used to represent alphanumeric data internally in the computer. It is frequently
used in peripheral devices for input and/or output.
The logic gates AND, OR, and inverter are the basic building blocks of
simple circuits. NAND, NOR, and XOR gates are also used to implement circuit
design. Diagrams of half-adders and full-adders were given as examples of the use
of logic gates for circuit design. Decoders are used to detect certain addresses.
Flip-flops are used to latch in data until other circuits are ready for it.
The major components of any computer system are the CPU, memory, and
110 devices. "Memory" refers to temporary or permanent storage of data. In most
systems, memory can be accessed as bytes or words. The terms kilobyte,
megabyte, gigabyte, and terabyte are used to refer to large numbers of bytes. There
are two main types of memory in computer systems: RAM and ROM. RAM (random access memory) is used for temporary storage of programs and data. ROM
(read-only memory) is used for permanent storage of programs and data that the
computer system must have in order to function. All components of the computer
system are under the control of the CPU. Peripheral devices such as 110 (input/output) devices allow the CPU to communicate with humans or other computer systems. There are three types of buses in computers: address, control, and data.
Control buses are used by the CPU to direct other devices. The address bus is used
by the CPU to locate a device or a memory location. Data buses are used to send
information back and forth between the CPU and other devices.
Finally, this chapter gave an overview of digital logic.
CHAPTER 0: INTRODUCTION TO COMPUTING
19
PROBLEMS
SECTION 0.1: NUMBERlNG AND CODlNG SYSTEMS
1. Convert the following decimal numbers to binary:
(b) 123 (c) 63 (d) 128 (e) 1000
(a) 12
2. Convert the following binary numbers to decimal:
(a) 100100
(b) 1000001 (c) 11101 (d) 1010 (e) 00100010
3. Convert the values in Problem 2 to hexadecimal.
4. Convert the following hex numbers to binary and decimal:
(a) 2B9H (b) F44H (c) 912H (d) 2BH (e) FFFFH
5. Convert the values in Problem 1 to hex.
6. Find the 2's complement of the following binary numbers:
(a) 1001010 (b) 111001 (c) 10000010 (d) 111110001
7. Add the following hex values:
(a) 2CH + 3FH (b) F34H + 5D6H
(c) 20000H + 12FFH
(d) FFFFH + 2222H
8. Perform hex subtraction for the following:
(a) 24FH - 129H (b) FE9H - 5CCH
(c) 2FFFFH - FFFFFH
(d) 9FF25H - 4DD99H
9. Show the ASCII codes for numbers 0, 1,2, 3, ... ,9 in both hex and binary.
10. Show the ASCII code (in hex) for the following string:
"U.S.A. is a country" CR,LF
"in North America" CR,LF
(CR is carriage return, LF is line feed)
SECTION 0.2: DIGITAL PRIMER
II.
12.
13.
14.
15.
16.
17.
18.
19.
20.
Draw a 3-input OR gate using a 2-input OR gate.
Show the truth table for a 3-input OR gate.
Draw a 3-inputAND gate using a 2-inputAND gate.
Show the truth table for a 3-input AND gate.
Design a 3-input XOR gate with a 2-input XOR gate. Show the truth table for
a 3-input XOR.
List the truth table for a 3-input NAND.
List the truth table for a 3-input NOR.
Show the decoder for binary 1100.
Show the decoder for binary 11011.
List the truth table for a D-FF.
SECTION 0.3: INSIDE THE COMPUTER
21. Answer the following:
(a) How many nibbles are 16 bits?
(b) How many bytes are 32 bits?
(c) If a word is defined as 16 bits, how many words is a 64-bit data item?
(d) What is the exact value (in decimal) of 1 meg?
20
(e)
(f)
(g)
(h)
How many K is I meg?
What is the exact value (in decimal) of I gigabyte?
How many K is I gigabyte?
How many meg is I gigabyte?
(i) If a given computer has a total of 8 megabytes of memory, how many
bytes (in decimal) is this? How many kilobytes is this?
22. A given mass storage device such as a hard disk can store 2 gigabytes of information. Assuming that each page of text has 25 rows and each row has 80
columns of ASCII characters (each character = I byte), approximately how
many pages of information can this disk store?
23. In a given byte-addressable computer, memory locations 10000H to 9FFFFH
are available for user programs. The first location is 10000H and the last location is 9FFFFH. Calculate the following:
(a) The total number of bytes available (in decimal)
(b) The total number of kilobytes (in decimal)
24. A given computer has a 32-bit data bus. What is the largest number that can be
carried into the CPU at a time?
25. Below are listed several computers with their data bus widths. For each computer, list the maximum value that can be brought into the CPU at a time (in
both hex and decimal).
(a) Apple 2 with an 8-bit data bus
(b) IBM PS/2 with a 16-bit data bus
(c) IBM PS/2 model 80 with a 32-bit data bus
(d) Cray supercomputer with a li4-hit data hus
26. Find the total amount of memory, in the units requested, for each of the following CPUs, given the size ofthe address buses:
(a) l6-bit address bus (in K)
(b) 24-bit address bus (in megs)
(c) 32-bit address bus (in megabytes and gigabytes)
(d) 48-bit address bus (in megabytes, gigabytes, and terabytes)
27. Regarding the data bus and address bus, which is unidirectional and which is
bidirectional?
28. Which register of the CPU holds the address of the instruction to be fetched?
29. Which section of the CPU is responsible for performing addition?
30. List the three bus types present in every CPU.
CHAPTER 0: INTRODUCTION TO COMPUTING
21
ANSWERS TO REVIEW QUESTIONS
SECTION 0.1: NUMBERING AND CODING SYSTEMS
1.
2.
Computers use the binary system because each bit can have one of two voltage levels: on and
off.
3410 = 1000102 = 22 16
3.
4.
5.
6.
7.
8.
110101 2 = 35 16 = 5310
1110001
010100
461
275
3830 78 38 36 20 43 50 55 73
SECTION 0.2: DIGITAL PRIMER
1.
2.
3.
4.
5.
6.
AND
OR
XOR
Buffer
Storing data
Decoder
SECTION 0.3: INSIDE THE COMPUTER
3.
24,576
Random access memory; it is used for temporary storage of programs that the CPU is running, such as the operating system, word processing programs, etc.
Read-only memory; it is used for permanent programs such as those that control the keyboard,
4.
5.
6.
The contents of RAM are lost when the computer is powered off.
The CPU, memory, and 1/0 devices
Central processing unit; it can be considered the "brain" of the computer; it executes the pro-
7.
The address bus carries the location (address) needed by the CPU; the data bus carries information in and out of the CPU; the control bus is used by the CPU to send signals controlling
110 devices.
(a) bidirectional (b) unidirectional
64K, or 65,536 bytes
Arithmeticllogic unit; it performs all arithmetic and logic operations.
They are used for temporary storage of information.
It holds the address of the next instruction to be executed.
It tells the CPU what steps to perform for each instruction.
1.
2.
etc.
grams and controls all other devices in the computer.
8.
9.
10.
II.
12.
13.
22
CHAPTER!
THE PIC
MICROCONTROLLERS:
HISTORY AND
FEATURES
OBJECTIVES
Upon completion of this chapter, you will be able to:
»
»
»
»
»
»
»
Compare and contrast microprocessors and microcontroUers
Describe the advantages of microcontrollers for some applications
Explain the concept of embedded systems
Discuss criteria for considering a microcontroller
Explain the variations of speed, packaging, memory, and
cost per unit and how these affect choosing a microcontroller
Compare and contrast the various members of the PIC family
Compare the PIC with microcontrollers offered by other manufacturers
23
This chapter begins with a discussion of the role and importance of microcontrollers in everyday life. In Section l.l we also discuss criteria to consider in
choosing a microcontroller, as well as the use of microcontrollers in the embedded
market. Section 1.2 covers various members of the PIC 18 family and their features. In addition, we provide a brief discussion of alternatives to the PIC chip such
as the 8051, AVR, and 68HCII microcontrollers.
SECTION 1.1: MICROCONTROLLERS AND EMBEDDED
PROCESSORS
In this section we discuss the need for microcontrollers and contrast them
with general-purpose microprocessors such as the Pentium and other x86 microprocessors. We also look at the role of microcontrollers in the embedded market.
In addition, we provide some criteria on how to choose a microcontroller.
Microcontroller versus general-purpose microprocessor
What is the difference between a microprocessor and microcontroller? By
microprocessor is meant the general-purpose microprocessors such as Intel's x86
family (8086, 80286, 80386, 80486, and the Pentium) or Motorola's PowerPC
family. These microprocessors contain no RAM, no ROM, and no 1/0 ports on the
chip itself. For this reason, they are commonly referred to as general-purpose
microprocessors See Figure I-I
Data bus
CPU
GeneralPurpose
Microprocessor
I
I
I
I
I
RAM
ROM
I/O
Port
Timer
Serial
COM
Port
I
I
I
I
CPU
1/0
RAM
ROM
Timer
Serial
COM
Port
I
Address bus
(a) General-Purpose Microprocessor System
(b) Microcontroller
FIgure 1-1. MIcroprocessor System Contrasted WIth Mlcrocontroller System
A system designer using a general-purpose microprocessor such as the
Pentium or the PowerPC must add RAM, ROM, I/O ports, and timers externally
to make them functional. Although the addition of external RAM, ROM, and I/O
ports makes these systems bulkier and much more expensive, they have the advantage of versatility, enabling the designer to decide on the amount of RAM, ROM,
and 1/0 ports needed to fit the task at hand. This is not the case with microcontrollers. A microcontroller has a CPU (a microprocessor) in addition to a fixed
amount of RAM, ROM, I/O ports, and a timer all on a single chip. In other words,
the processor, RAM, ROM, 1/0 ports, and timer are all embedded together on one
chip; therefore, the designer cannot add any external memory, 1/0, or timer to it.
The fixed amount of on-chip ROM, RAM, and number of 1/0 ports in microcontrollers makes them ideal for many applications in which cost and space are critical. In many applications, for example a TV remote control, there is no need for
24
Home
Appliances
Intercom
Telephones
Security systems
Garage door openers
Answering machines
Fax machines
Home computers
TVs
Cable TV tuner
VCR
Camcorder
Remote controls
Video games
Cellular phones
Musical instruments
Sewing machines
Lighting control
Paging
Camera
Pinball machines
Toys
Exercise equipment
Office
Telephones
Computers
Security systems
Fax machine
Microwave
Copier
Laser printer
Color printer
Paging
Auto
Trip computer
Engine control
Air bag
ABS
Instrumentation
Security system
Transmission control
Entertainment
Climate control
Cellular phone
Keyless entry
Table 1-1: Some
Embedded Products
Using Microcontrollers
the computing power of a 486 or even an 8086 microprocessor. In
many applications, the space used, the power consumed, and the
price per unit are much more critical considerations than the computing power. These applications most often require some lIO
operations to read signals and turn on and off certain bits. For this
reason some call these processors IBP, "itty-bitty processors."
(See "Good Things in Small Packages Are Generating Big
Product Opportunities" by Rick Grehan, BYTE magazine,
September 1994 (http://www.byte.com) for an excellent discussion of microcontrollers.)
It is interesting to note that some microcontroller manufacturers have gone as far as integrating an ADC (analog-to-digital converter) and other peripherals into the microcontroller.
Microcontrollers for embedded systems
In the literature discussing microprocessors, we often see
the term embedded system. Microprocessors and microcontrollers
are widely used in embedded system products. An embedded
product is controlled by its own internal microprocessor (or
microcontroller) as opposed to an external controller. Typically, in
an embedded system, the microcontroller's ROM is burned with
a purpose for specific functions needed for the system. A printer
is an example of an embedded system because the processor
inside it performs one task only; namely, getting the data and
printing it. Contrast this with a Pentium-based PC (or any x86
IBM-compatible PC), which can be used for any number of applications such as word processor, print-server, bank teller terminal,
video game player, network server, or Internet terminal. A PC can
also load and run software for a variety of applications. Of course,
the reason a PC can perform myriad tasks is that it has RAM
memory and an operating system that loads the application software into RAM and lets the CPU run it. In an embedded system,
typically only one application software is burned into ROM. An
x86 PC contains or is connected to various embedded products
such as the keyboard, printer, modem, disk controller, sound card,
CD-ROM driver, mouse, and so on. Each one of these peripherals
has a microcontroller inside it that performs only one task. For
example, inside every mouse a microcontroller performs the task
of finding the mouse's position and sending it to the Pc. Table 1-1
lists some embedded products.
x86 PC embedded applications
Although microcontrollers are the preferred choice for
many embedded systems, sometimes a microcontroller is inadequate for the task. For this reason, in recent years many manufacturers of general-purpose microprocessors such as Intel, Freescale
Semiconductor (formerly Motorola), and AMD (Advanced Micro
CHAPTER 1: THE PIC MICROCONTROLLERS: HISTORY AND FEATURES
25
Devices, Inc.) have targeted their microprocessor for the high end of the embedded market. Intel and AMD push their x86 processors for both the embedded and
desktop PC markets. In the early 1990s, Apple computer began using the PowerPC
microprocessors (604, 603, 620, etc.) in place of the 680xO for the Macintosh. The
PowerPC microprocessor is a joint venture between IBM and Motorola, and is targeted for the high end ofthe embedded market as well as the PC market. It must
be noted that when a company targets a general-purpose microprocessor for the
embedded market it optimizes the processor used for embedded systems. For this
reason these processors are often called high-end embedded processors. Another
chip widely used in the high end of the embedded system design is the ARM
microprocessor. Very often the terms embedded processor and microcontroller are
used interchangeably.
One of the most critical needs of an embedded system is to decrease power
consumption and space. This can be achieved by integrating more functions into
the CPU chip. All the embedded processors based on the x86 and PowerPC 6xx
have low power consumption in addition to some forms of 1/0, COM port, and
ROM, all on a single chip. In high-performance embedded processors, the trend is
to integrate more and more functions on the CPU chip and let the designer decide
which features to use. This trend is invading PC system design as well. Normally,
in designing the PC motherboard we need a CPU plus a chipset containing 1/0, a
cache controller, a flash ROM containing BIOS, and finally a secondary cache
memory. New designs are emerging in industry. For example, many companies
have a chip that contains the entire CPU and all the supporting logic and memory,
except for DRAM. In other words, we have the entire computer on a single chip.
Currently, because of Linux, MS-DOS, and Windows standardization,
many embedded systems use x86 PCs. In many cases, using x86 PCs for the highend embedded applications not only saves money but also shortens development
time because a vast library of software already exists for the Linux, DOS, and
Windows platforms. The fact that Windows and Linux are widel y used and
well-understood platforms means that developing a Windows-based or Linuxbased embedded product reduces the cost and shortens the development time considerably.
Choosing a microcontroller
There are five major 8-bit microcontrollers. They are: Freescale
Semiconductor's (formerly Motorola) 68HC08/68HCll, Intel's 8051, Atmel's
AVR, Zilog's Z8, and PIC from Microchip Technology. Each ofthe above microcontrollers has a unique instruction set and register set; therefore, they are not
compatible with each other. Programs written for one will not run on the others.
There are also 16-bit and 32-bit microcontrollers made by various chip makers.
With all these different microcontrollers, what criteria do designers consider in
choosing one? Three criteria in choosing microcontrollers are as follows: (1)
meeting the computing needs of the task at hand efficiently and cost effectively;
(2) availability of software and hardware development tools such as compilers,
assemblers, debuggers, and emulators; and (3) wide availability and reliable
sources of the microcontroller. Next, we elaborate on each of the above criteria.
26
Criteria for choosing a microcontroller
I. The first and foremost criterion in choosing a microcontroller is that it must
meet the task at hand efficiently and cost effectively. In analyzing the needs of
a microcontroller-based project, we must first see whether an 8-bit, 16-bit, or
32-bit microcontroller can best handle the computing needs of the task most
effectively. Among other considerations in this category are:
(a) Speed. What is the highest speed that the microcontroller supports?
(b) Packaging. Does it come in a 40-pin DIP (dual inline package) or a QFP
(quad flat package), or some other packaging format? This is important in
terms of space, assembling, and prototyping the end product.
(c) Power consumption. This is especially critical for battery-powered products.
(d) The amount of RAM and ROM on the chip.
(e) The number of I/O pins and the timer on the chip.
(0 Ease of upgrade to higher-performance or lower-power-consumption verSIOns.
(g) Cost per unit. This is important in terms of the final cost of the product in
which a microcontroller is used. For example, some microcontrollers cost
50 cents per unit when purchased 100,000 units at a time.
2. The second criterion in choosing a microcontroller is how easy it is to develop products around it. Key considerations include the availability of an assembler, debugger, a code-efficient C language compiler, emulator, technical support, and both in-house and outside expertise. In many cases, third-party vendor (i.e., a supplier other than the chip manufacturer) support for the chip is as
good as, if not better than, support from the chip manufacturer.
3. The third criterion in choosing a microcontroller is its ready availability in
needed quantities both now and in the future. For some designers this is even
more important than the first two criteria. Currently, ofthe leading 8-bit microcontrollers, the 8051 family has the largest number of diversified (multiple
source) suppliers. (Supplier means a producer besides the originator of the
microcontroller.) In the case of the 8051, which was originated by Intel, several companies also currently produce (or have produced in the past) the 8051.
Note that Freescale Semiconductor (Motorola), Atmel, Zilog, and
Microchip Technology have all dedicated massive resources to ensure wide and
timely availability of their products because their products are stable, mature, and
single sourced. In recent years, companies have begun to sell Field-Programmable
Gate Array (FPGA) and Application-Specific Integrated Circuit (ASIC) libraries
for the different microcontrollers.
Mechatronics and microcontrollers
The microcontroller is playing a major role in an emerging field called
mechatronics. Here is an excellent summary of what the field of mechatronics is
all about, taken from the web site of Newcastle University (http://mechatronics2004.newcastle.edu.auimech2004), which holds a major conference every year
on this subject:
"Many technical processes and products in the area of mechanical and
CHAPTER 1: THE PIC MICROCONTROLLERS: HISTORY AND FEATURES
27
electrical engineering show an increasing integration of mechanics with electronics and information processing. This integration is between the components (hardware) and the information-driven functions (software), resulting in integrated systems called mechatronic systems.
The development of mechatronic systems involves finding an optimal balance between the basic mechanical structure, sensor and actuator implementation,
automatic digital information processing and overall control, and this synergy
results in innovative solutions. The practice of mechatronics requires multidisciplinary expertise across a range of disciplines, such as: mechanical engineering,
electronics, information technology, and decision making theories."
Review Questions
I. True or false. Microcontrollers are normally less expensive than microprocessors.
2. When comparing a system board based on a microcontroller and a generalpurpose microprocessor, which one is cheaper?
3. A microcontroller normally has which of the following devices on-chip?
(a) RAM
(b) ROM
(c) I/O
(d) all of the above
4. A general-purpose microprocessor normally needs which of the following
devices to be attached to it?
(d) all of the above
(a) RAM
(b) ROM
(c) 110
5. An embedded system is also called a dedicated system. Why?
6. What does the term embedded system mean?
7. Why does having multiple sources of a given product matter?
SECTION 1.2: OVERVIEW OF THE PIC18 FAMILY
In this section, we first look at the PIC family of micro controllers and then
examine the PICI8 family in more detail.
A brief history of the PIC microcontroller
In 1989, Microchip Technology Corporation introduced an 8-bit microcontroller called the PIC, which stands for Peripheral Interface Controller. This
microcontroller had small amounts of data RAM, a few hundred bytes of on-chip
ROM for the program, one timer, and a few pins for I/O ports, all on a single chip
with only 8 pins. (See Figure 1-2.) It is amazing that a company that began with
such a humble product became one of the leading suppliers of 8-bit microcontrollers in less than a decade. At the time of this writing, Microchip is the numberone supplier of 8-bit microcontrollers in the world. Since the introduction of the
PIC16xxx, they have introduced an array of 8-bit microcontrollers too numerous
to list here. They include the PIC families of 10xxx, 12xxx, 14xxx, 16xxx, 17xxx,
and 18xxx. They are all 8-bit processors, meaning that the CPU can work on only
8 bits of data at a time. Data larger than 8 bits has to be broken into 8-bit pieces to
be processed by the CPU. One of the problems with the PIC family is that they are
not all 100% upwardly compatible in terms of software when going from one family to another family. For example, while the 12xxx/16xxx have 12-bit and l4-bit
wide instructions, the PIC 18xxx instruction is 16 bits wide with many new instruc28
tions. To run programs written for the PIC 12xxx on a PIC 18, we must recompile
the program and possibly change some register locations before loading it into the
PIC 18. At the time of this writing, the PIC 18xxx family has the highest performance of all the families of 8-bit PIC microcontrollers. The fact that PIC 18xxx is
available in 18- to 80-pin packages makes it an ideal choice for new designs
because it allows an easy migration to more powerful versions of the chip without
losing software compatibility. At this time, no 8-pin version of the PIC 18xxx
exists, and that is the main reason to choose other family members of the
I Oxxx-16xxx if your design calls for a small package. Because this book is about
the PICI8 family, we describe some of the main features of this family and refer
the reader to the Microchip web site for other families of PIC IOxxx-16xxx. For
those who have mastered the PICI8 family, understanding the other families is
very easy and straightforward. The following is a brief description of the PIC 18
senes.
PIC18 features
The PICI8 has a RISC architecture that comes with some standard features
such as on-chip program (code) ROM, data RAM, data EEPROM, timers, ADC,
and USART and I/O ports. See Figure 1-2. Although the size of the program ROM,
data RAM, data EEPROM, and I/O ports varies among the family members, they
all have peripherals such as timers, ADC, and USART. See Figures 1-3 and 1-4.
Due to the importance of these peripherals, we have dedicated an entire chapter to
each one of them. The details of the RAMIROM memory and I/O features of the
PIC 18 are given in the next few chapters.
STACK
PROGRAM
ROM
...
Program
Bus
..._ _~..
Interrupt
Control
Logic
PC
CPU
RAM
EEPROM
Ports
Other
Peripherals
Data
Bus
I I
OSC
Timers
~II~
,1,1,1,1,1,1,1,1,
1/0
PINS
Figure 1-2. Simplified View of a PIC MicrocontroIIer
CHAPTER 1: THE PIC MICROCONTROLLERS: HISTORY AND FEATURES
29
r
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01==~2~0=l
Address Latch
Program Memory
IpCLATU PCLATH
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PCU PCH
pel
(up to 2M Bytes)
Data Latch
r ram aun ar
131 L';:St"k 1
~~
AI"
__
41"
12
I
I
1,21'"
I
P
BSR
k1
l FSRO
I
'-
Address<12>
~
~
RAO
1
rrl> L'--'---'----'-JO-.---<f>~~ ~
(up 10 4k
address reach )
Address Latch
inc/dec logic
---,
PORTA
I
Data 8us<8>
-.....
L .:::::..
d l'"
I
b,"ko, FI
RAS
RA6
H
PORTS
~
~
I
1
L-_L-
I
PORTe
RBO/INTO
RBI/INn
R62/1NT2
~~~7.4>
FSRI
F==========d
,~-
16
TABLELATCH
1
~~
1
~j,~8
I
Instruction
I
OSC2ICLKDUT
OSCll~CLKIN
Tl0S1
~. ~ +.1
II
-<7
T10Sa
I
I
4X PLl
Precision
Bandgap
Reference
Dorod,
Ij,~::,
l
RCO
RC1
- ill
ROMLATCH
!
'---_ _----' -1
ll======;c========d
1
"
1
Instruction
Register I
~
~
RC7
PORTO
ROO
RD1
RD2
RD3
RD.
RDS
RD'
RD7
~
1
'P-,-.-,-,.-,,-'
~
I
12
I
Decode &
Control
Timing
Generation
FS.R2
1
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brownr-out
Reset
1
PORTE
4t
1
T,,----r
'----,
8
=r----,
rX1 M
t
: m
1
1
REO
RE1
RE2
L-_---'
1
1
MClR VDD. VSS
1
1
1
1
PORTx
1
1
~
,-
1
------
I TimerO I
- ----
-
ITim,,1 I
IT,;:;r
---
L
I~'i' 1-
- :{;j AID c'""""I
Ii=====;r====~:=======ii~
11'====iF===="II'=;;F=='-'=d'Jl.:1
_~
.~
~
~
vI
Icep, I
IE,h,"oed I I
CCP's
Peripheral Modules (Note 1)
M,"'"
Synchronous
II Add""''''1 I I
USART
CAN
USB
I
__
Other
Peripherals
--,...J
1
I
Senal Port
_I
Note 1: Many of the general purpose 1/0 pins are multiplexed with one or more peripheral module functions. The
multiplexing combinations are device dependent.
Figure 1-3. PIC18 Block Diagram
30
,-
PORTA
8
13
EPROM
RAO
RA1
I
Program Counter
I
Registers
Up to
8 Level Slack
(13-bit)
8kx 14
I
RA3
RA'
RA5
File
Memory
Uplo
Program
Bus
RA2
RAM
Program
368 x 8
14~
PORTS
{1
V
RAM A.rdd"r~=
RBO/INT
R81
RB2
RB3
RB'
RB5
RB'
RB7
Instruction reg
Direct Addr
7
PORTe
RCO
RC1
RC2
RC3
RC,
RC5
RC,
RC7
Power-up
Timer
Oscillator
Start-up Timer
Instruction
Decode &
Power-on
Control
Timer
Generation
OSC2/CLKOU
I
Watchdog
Timing
OSC1/CLKIN
PORTO
Reset
ROO
RD1
RD2
RD3
RD'
RD5
RD,
RD7
Wreg
Brown-out
Reset (2)
Internal
RC clock (2)
PORTE
MCLR
,-
-
:I
-
TimerO
CCPs
REO
RE1
RE2
RE3
RE'
RE5
RE,
RE7
VDD, VSS
--
I I
I I
Timer1
Comparators
I I
Timer2
I I
Synchronous
Serial Port
I I
I I
AID
PORTF
RFO
USARTs
RF1
RF2
RF3
RF4
Other
Modules
Voltage
Reference
I I
Parallel
Slave Port
I I
LCD Driveffi
RFS
RFS
RFl
I
PORTG
RGO
RG1
RG2
RG3
RG,
RG5
RG,
RG7
Data EEPROM
I I
Up to
256 x 8
Peripheral Modules (Note 3)
L
_____
_
L
General Purpose 110
(Note 3)
__
_
Note 1: The high order bits of the Direct Address for the RAM are from the STATUS register .
2: Not all devices have this feature, please refer to device data sheet.
3: Many of the general purpose 1/0 pins are multiplexed with one or more peripheral module functions.
The multiplexing combinations are device dependent.
Figure 1-4. PIC16 Block Diagram
CHAPTER 1: THE PIC MICROCONTROLLERS: HISTORY AND FEATURES
31
PIC microcontro/ler program ROM
In microcontrollers, the ROM is used to store programs and for that reason
it is called program or code ROM. Although the PICl8 has 2M (megabytes) of
program (code) ROM space, not all family members come with that much ROM
installed. The program ROM size can vary from 4K to 128K at the time of this
writing, depending on the family member. The PICl8 program ROM is available
in different memory types, such as flash, OTP, and masked, all of which have different part numbers. A discussion of the various types of ROM is given in Chapter
14, if you need to refresh your memory on these important memory technologies.
Note that although different flavors of the PICl8 exist in terms of speed and
amount of on-chip RAM/ROM, they are all compatible with each other as far as
the instructions are concerned. This means that if you write your program for one,
it will run on any of them regardless of the chip number. Next, we discuss briefly
the program ROM type for the PIC 18 family.
PIC microcontro/ler with UV-EPROM
Some of the PIC rnicrocontrollers use UV-EPROM, for on-chip program
ROM. To use these kinds of chips for development requires access to a PROM
burner, as well as a UV-EPROM eraser to erase the contents of ROM. The window
on the UV-EPROM chip allows the UV light to erase the ROM. The problem with
the UV-EPROM is that it takes around 20 minutes to erase the chip before it can
be programmed again. This has led Microchip to introduce a flash version of the
PIC family. At this time flash is replacing the UV-EPROM altogether. Table 1-2
shows some members of the PICl8 family.
PIC18Fxxx with flash
Many PICl8 chips have on-chip program ROM in the form of flash memory. The flash version uses the letter F in the part number to indicate that the onchip ROM is flash. PIC18F458 is an example ofPICl8 with flash ROM. The flash
version is ideal for fast development because flash memory can be erased in seconds compared to the 20 minutes or more needed for the UV-EPROM version. For
this reason, the PICI8F has been used in place of the UV-EPROM to eliminate
the waiting time needed to erase the chip, thereby speeding up the development
time. To use the PIC 18F to develop a microcontroller-based system requires a
ROM burner that supports flash memory; however, a ROM eraser is not needed,
because flash is an EEPROM (electrically erasable PROM). Notice that in flash
memory, you must erase the entire contents of ROM in order to program it again.
This erasing of flash is done by the ROM programmer itself, and so a separate
eraser is not needed. We can also program the PICl8F via the PICkit 2 from
MicroChip using the USB port of an IBM Pc.
OTP version of the PIC
OTP (one-time-programmable) versions of the PIC are also available from
Microchip. PIC 16C432 chip uses OTP for program ROM. Contrast the
PIC16C432 and PIC18F252. The letter C indicates the OTP ROM, while the letter F is for the flash. The flash version is typically used for product development.
When a product is designed and absolutely finalized, the OTP version of the PIC
32
is used for mass production because it is cheaper than flash in terms of price per
unit. The problem with the OTP is that you cannot reprogram it if you want to
modify your program.
Masked version of PIC
Microchip Corporation provides a service in which you can send in your
program and they will burn the program into the PIC chip during the fabrication
process of the chip. This chip is commonly referred to as masked PIC, which is
one of the stages oflC fabrication. Masked PIC is the cheapest of all types, if the
unit numbers are high enough. This is because there is a minimum order for the
masked version of the PIC microcontrollers.
PIC microcontrol/er data RAM and EEPROM
While ROM is used to store program (code), the RAM space is for data
storage. The PICI 8 has a maximum of 4096 bytes (4K) of data RAM space. Not
all of the family members come with that much RAM. The data RAM size for the
PIC 18 varies from 256 bytes to 4096 bytes. As we will see in the next chapter, the
data RAM space has two components: General-Purpose RAM (GPR) and Special
Function Registers (SFRs). Because the SFRs are fixed and every microcontroIIer
must have them, it is the GPR's size that varies from chip to chip. For this reason,
the Microchip web site gives only the GPR size. The RAM GPR space is used for
read/write scratch pad and data manipulation and is divided into banks of 256
bytes each, as we will see in Chapter 6. The GPR size given for the PICI8 is
always a multiple of 256 bytes. In some of the PICI 8 family members, we also
have a smalI amount of EEPROM to store critical data that does not need to be
changed very often. While every PIC 18 must have some data RAM for scratch
pad, the EEPROM is optional, so not all versions of the PIC 18 come with EEPROM. EEPROM is used mainly for storage of critical data, as we will see in
Chapter 14.
Table 1-2: Some Members of the PIC1S Family (http://www.microchip.com)
PartNum
PICI8FI220
PICI8F2420
PICI8F2220
PICI8F452
PICI8F4520
PIC18F458
PICI8F4580
PICI8F8722
Code
ROM
4K (flash2
16K (flash2
4K (flash2
32K (flash2
32K (flash}
32K (flash}
32K (flash}
128K (flash}
Data
RAM
256
768
512
1536
1536
1536
1536
3936
Data
1/0 pins
EEPROM ~ins
256
16
0
25
256
25
256
34
256
36
256
34
256
36
1024
70
ADC Timers
10-bit
IO-bit
10-bit
10-bit
10-bit
10-bit
IO-bit
10-bit
4
4
4
4
4
4
4
5
Pin numbers
& Package
18 DIP
28 DIP
28 DIP
40 DIP
40 DIP
40 DIP
40 DIP
80 TQFP
Notes:
I. All ROM, RAM, and EEPROM memories are in bytes.
2. Data RAM (General-Purpose RAM) is the amount of RAM available for data manipulation (scratch
pad) in addition to the Special Function Registers (SFRs) space.
3. All the above chips have USART for serial data transfer.
CHAPTER 1: THE PIC MICROCONTROLLERS: HISTORY AND FEATURES
33
PIC microcontrol/er liD pins
The PIC 18 can have from 16 to 72 pins dedicated for 110. The number of
1/0 pins depends on the number of pins in the package itself. The number of pins
for the PICI8 package goes from 18 to 80 at this time. In the case of the 18-pin
PIC18F1220. we have 16 pins for 1/0, while in the case of the 80-pin PICI8F8722,
we can use up to 72 pins for 1/0. We will study 1/0 pins and programming in
Chapter 4.
PIC microcontrol/er peripherals
All the members of the PICI8 family come with ADC (analog-to-digital
converter), timers, and USART (Universal Synchronous Asynchronous Receiver
Transmitter) as standard peripherals. As we will see in Chapter 13, the ADC is 10bit and the number of ADC channels in each PIC chip varies from 5 to 16, depending on the number of pins in the package. The PIC 18 can have up to 4 timers
besides the watchdog timer. We will examine timers in Chapter 9. The USART
peripheral allows us to connect the PIC 18-based system to serial ports such as the
COM port of the IBM PC, as we will see in Chapter 10. Many of the PICI8 family members come with the PC and CAN bus as well.
PIC trainer
In Chapter 8, we discuss the design of the PIC 18F458 trainer extensively.
This trainer is programmed using the PICkit 2. The MDEPIC trainer is also compatible with other 40-pin devices from Microchip.
Other Microcontrollers
There are many other popular 8-bit microcontrollers besides the PIC chip.
Among them are the 8051, 68HCII,AVR, and Z8. Besides Intel, a number of other
companies make the 8051 family, as seen in Table 1-4. TheAVR is made by Atmel
Corp. Freescale (Motorola) makes the 68HC II and many of its variations. Zilog
produces the Z8 microcontroller. To contrast the PIC I 8 family with the 8051152
chip, examine Table 1-3. For a comprehensive treatment of the 8051 microcontroller, see "The 8051 Microcontroller and Embedded Systems" by Mazidi, et. al.
Table 1-3: Comparison of 8051 and PIC18 Family (40-pin package)
Feature
Program ROM (maximum space)
Data RAM (maximum space)
Timers
1/0 pins
Serial port
34
8051152
64K
256 bytes
3
32
I
PIC18xxx
2M
4K
4
33
Table 1-4: Some of the Companies that Produce Widely Used 8-bit Microcontrollers
Company
Microchip
Intel
Atmel
Philips/Signetics
Zilog
Dallas Semi/Maxim
Freescale Semi
Web Site
http://www.microchip.com
http://www.intel.comldesignimcs51
http://www.atmel.com
http://www.semiconductors.philips.com
http://www.zilog.com
http://www.maxim-ic.com
http://www.freescale.com
Architecture
PIC 16xxxll8xxx
8051
AVR and 8051
8051
Z8 andZ80
8051
68HC 11I68HC08
See http://www.microcontroller.com for a complete list.
See the following web sites for PIC microcontrollers and PIC Trainer:
http://www.microchip.com
http://www.MicroDigitaIEd.com
Review Questions
1. Name three features of the PlCl8xxx.
2. What is the main difference between the PICI8Fxxx and PIC I 8Cxxx microcontrollers?
3. Give the size of RAM in each of the following:
(a) PIC18F2420
(b) PICI8F4520
4. Give the size of the on-chip program ROM in each of the following:
(a) PICI8F2420
(b) PICI8F4520
5. The PICl8 is a(n)
-bit microprocessor.
SUMMARY
This chapter discussed the role and importance of microcontrollers in
everyday life. Microprocessors and microcontrollers were contrasted and compared. We discussed the use of microcontrollers in the embedded market. We also
discussed criteria to consider in choosing a microcontroller such as speed, memory, I/O, packaging, and cost per unit. The second section of this chapter described
various families of the PIC, such as the PIC 18 and PIC 16, and their features. In
addition, we discussed various members of the PIC 18 family such as the
PIC 18F252 and PIC 18F458.
CHAPTER 1: THE PIC MICROCONTROLLERS: HISTORY AND FEATURES
35
PROBLEMS
SECTION 1.1: MICROCONTROLLERSAND EMBEDDED PROCESSORS
I.
2.
3.
4.
5.
True or False. A general-purpose microprocessor has on-chip ROM.
True or False. Generally, a microcontroller has on-chip ROM.
True or False. A microcontroller has on-chip 1/0 ports.
True or False. A microcontroller has a fixed amount of RAM on the chip.
What components are usually put together with the microcontroller onto a single chip?
6. Intel's Pentium chips used in Windows PCs need external
and
chips to store data and code.
7. List three embedded products attached to a PC.
8. Why would someone want to use an x86 as an embedded processor?
9. Give the name and the manufacturer of some of the most widely used 8-bit
microcontrollers.
10. In Question 9, which one has the most manufacture sources?
II. In a battery-based embedded product, what is the most important factor in
choosing a microcontroller?
12. In an embedded controller with on-chip ROM, why does the size of the ROM
matter?
13. In choosing a microcontroller, how important is it to have multiple sources for
that chip?
14. What does the term "third-party support" mean?
15. Suppose that a microcontroller architecture has both 8-bit and 16-bit versions.
Which of the following statements is true?
(a) The 8-bit software will run on the 16-bit system.
(b) The 16-bit software will run on the 8-bit system.
SECTION 1.2: OVERVIEW OF THE PICI8 FAMILY
16. The PICI8F458 has _ _ bytes of on-chip program ROM.
17. The PIC I 8F2420 has _ _ bytes of on-chip data RAM.
18. The PICI8F452 has __ on-chip timer(s).
19. The PIC 18F458 has __ bytes of on-chip data RAM.
20. Check the Microchip web site to see if we have a ROMless version of the
PIC 18. Give the part number if there is one.
21. The PICI8F458 has __ pins for lIO.
22. The PIC 18Fxxx has circuitry to support _ _ serial ports.
23. The PICI8F458 on-chip program ROM is of type _ __
24. The PICI6C432 on-chip program ROM is of type _ _.
25. The PICI8F452 on-chip program ROM is of type _ _.
26. The PICI8F8772 on-chip program ROM is of type _ _ .
27. Give the amount of program ROM and data RAM for the following chips:
(a) PIC I 8F2420 (b) PICI8F458
(c) PIC I 8F8772
28. Of the PICI8 family, which memory type is the most cost effective if you are
using a million of them in an embedded product?
36
29. What are the main differences between the PIC 18F2420 and PIC18F2220?
30. The PIC 18F458/4580 has
bytes of data EEPROM.
ANSWERS TO REVIEW QUESTIONS
SECTION 1.1: MICROCONTROLLERS AND EMBEDDED PROCESSORS
1.
True
2,
3.
A microcontroller-based system
(d)
4.
5.
(d)
It is dedicated because it is dedicated to doing one type of job.
6.
Embedded system means that the application and processor are combined into a single system.
Having multiple sources for a given part means you are not hostage to one supplier. More
7.
importantly, competition among suppliers brings about lower cost for that product.
SECTION 1.2: OVERVIEW OF THE PICI8 FAMILY
I.
2.
3.
4.
5.
4K of RAM space, 2M of on-chip ROM space, and a large number of 110 pins.
C is OTP while F is the flash ROM.
The PICI8F2420 has 768 bytes of RAM and the PICI8F4520 has 1536 bytes.
(a) 16K
(b) 32K
8
CHAPTER 1: THE PIC MICROCONTROLLERS: HISTORY AND FEATURES
37
CHAPTER 2
PIC ARCHITECTURE &
ASSEMBLY LANGUAGE
PROGRAMMING
OBJECTIVES
Upon completion of this chapter, you will be able to:
»
»
»
»
»
»
»
»
»
»
»
»
»
»
»
Examine the data RAM file register of the PIC microcontroller
Manipulate data using the WREG and MOVE instructions
Perform simple operations such as ADD and MOVE using the file
register and access bank in the PIC microcontroller
Explain the purpose ofthe status register
Discuss data RAM memory space allocation in the PIC microcontroller
List SFRs (special function registers) of the PIC microcontroller
Code simple PIC Assembly language instructions
Describe PIC data types and directives
Assemble and run a PIC program using MPLAB
Describe the sequence of events that occur upon PIC power-up
Examine programs in PIC ROM code
Explain the PIC ROM memory map
Detail the execution of PIC Assembly language instructions
Understand the RISC and Harvard architectures of the PIC
microcontroller
Examine the PIC's registers and data RAM using the MPLAB simulator
39
CPU s use many registers to store data temporarily. To program in
Assembly language, we must understand the registers and architecture of a given
CPU and the role they play in processing data. In Section 2.1 we look at the
WREG register of the PIC. We demonstrate the use of one of the most widely used
registers of the PIC with simple instructions such as MOVE and ADD. Allocation
of RAM memory inside the PIC and the access bank of the PIC 18 are discussed in
Section 2.2. Programming the access bank is examined in Section 2.3. In Section
2.4 we discuss the status register's flag bits and how they are affected by arithmetic instructions. In Section 2.5 we look at some widely used Assembly language
directives, pseudocode, and data types related to the PIC. In Section 2.6 we examine Assembly language and machine language programming and define terms such
as mnemonics, opcode, operand, and so on. The process of assembling and creating a ready-to-run program for the PIC is discussed in Section 2.7. Step-by-step
execution of a PIC program and the role of the program counter are examined in
Section 2.8. The merits of RISC architecture are examined in Section 2.9.
Assembling and running of the PIC programs with MPLAB are discussed in
Section 2.10. In that section we also examine the registers and memory of the PIC
using the MPLAB simulator.
SECTION 2.1: THE WREG REGISTER IN THE PIC
PIC microcontrollers have many registers for arithmetic and logic operations. Among them is the WREG register. Because there are a large number of registers inside the PIC, we will concentrate on the widely used register WREG in this
section. General-purpose registers are covered in the next section, as well as special function registers. In this section we examine the WREG register of the PIC
and show its use with the simple instructions MOVE and ADD.
WREG register
In the CPU, registers are used to store information temporarily. That information could be a byte of data to be processed, or an address pointing to the data
to be fetched. The vast majority of PIC registers are 8-bit registers. In the PIC there
is only one data type: 8-bit. The 8 bits of a register are shown in the diagram below.
These range from the MSB (most-significant bit) 07 to the LSB (least-significant
bit) DO. With an 8-bit data type, any data larger than 8 bits must be broken into
8-bit chunks before it is processed.
07
06
05
04
03
02
01
DO
The 8-bit WREG register is the most widely used register in the PIC microcontroller. WREG stands for working register, as there is only one. The WREG
register is the same as the accumulator in other microprocessors. The WREG register is used for all arithmetic and logic instructions. To understand the use of the
WREG register, we will show it in the context of two simple instructions: MOVE
and ADD.
40
MOVLW instruction
Simply stated, the MOVLW instruction moves 8-bit data into the WREG
register. It has the following format:
MOVLW K
iffiove literal value K into WREG
K is an 8-bit value that can range from 0-255 in decimal, or OO-FF in hex.
The L stands for literal, which means, literally, a number must be used. In other
words, if we see the word literal in any instruction, we are dealing with an actual
value that must be provided right there with the instruction. This is similar to the
immediate value we see in other microprocessors. Notice that in MOVLW, the letter L (literal) comes first and then the letter W (WREG), which means "move a literal value to WREG," the destination. The following instruction loads the WREG
register with a literal value of 25H (i.e., 25 in hex).
MOVLW 2SH
;move value 2SH into WREG (WREG
=
2SH)
The following instruction loads the WREG register with value 87H (87 in
hex).
MOVLW 87H
;load 87H into WREG (WREG
=
87H)
The following instruction loads the WREG register with value 15H (15 in
hex and 21 in decimal).
MOVLW ISH
;load ISH into WREG (WREG
IsH)
ADDLW instruction
The ADDLW instruction has the following format:
ADDLW K
;ADD literal value K to WREG
The ADD instruction tells the CPU to add the literal value K to register
WREG and put the result back in the WREG register. Notice that in ADDLW, first
comes the letter L (literal) and then the letter W (WREG), which means "add a literal value to WREG," the destination. To add two numbers such as 25H and 34H,
one can do the following:
MOVLW 25H
ADDLW 34H
;load 2SH into WREG
;add value 34 to W(W = W + 34H)
Executing the above lines results in WREG = 59H (25H + 34H
=
59H)
Figure 2-1 shows the literal value and WREG being fed to the PIC ALU.
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
41
8-BIT LITERAL (FROM
INSTRUCTION WORD)
8-BITWIDE
WREG REGISTER
CARRY BIT
\
ALU
/
N,
STATUS
REGISTER
OV, Z, DC, C FLAGS
8-BITWIDE
FIgure 2-1. PIC WREG and ALU Usmg LIteral Value
The following program will add values 12H, 16H, 31H, and 43H:
MOVLW
ADDLW
ADDLW
ADDLW
l2H
l6H
llH
43H
;load value l2H
;add 16 to WREG
;add 11 to WREG
;add 43 to WREG
into WREG (WREG
(WREG
28H)
(WREG
39H)
(WREG
7CH)
=
12H)
When programming the WREG register of the PIC microcontroller with a
literal value, the following points should be noted:
I. Values can be loaded directly into the WREG register. There is no need for a
preceding pound sign or dollar sign to indicate that a value is an immediate
value as is the case with some other microcontrollers.
2. If values 0 to F are moved into an 8-bit register such as WREG, the rest of the
bits are assumed to be all zeros. For example, in "MOVLW 5H" the result will
be WREG = 05H; that is, WREG = 00000101 in binary.
3. Moving a value larger than 255 (FF in hex) into the WREG register will truncate the upper byte and cause a warning in the ,err file,
MOVLW 7F2H ;ILLEGAL 7F2H > 8 bits (FFH) , becomes F2H
MOVLW 456H ;ILLEGAL 456H > FFH, becomes 56H
MOVLW 60A5H ;ILLEGAL but becomes A5H
42
Review Questions
I. Write instructions to move value 34 H into the WREG register.
2. Write instructions to add the values l6H and CDH. Place the result in the
WREG register.
3. True or false. No value can be moved directly into the WREG register.
4. What is the largest hex value that can be moved into an 8-bit register? What is
the decimal equivalent of that hex value?
5. The vast majority of registers in the PIC are _ _-bit.
SECTION 2.2: THE PIC FILE REGISTER
The PIC microcontroller has many other registers in addition to the WREG
register. They are called data memory space to distinguish them from program
(code) memory space. The data memory space in PIC is a read/write (static RAM)
memory. In the PIC microcontroller literature, the data memory is also called the
file register. In this section, we examine the various locations of file register data
RAM in the PIC family and discuss their usage with simple instructions such as
ADD and MOVE.
File register (data RAM) space allocation in PIC
The file register is read/write memory used by the CPU for data storage,
scratch pad, and registers for internal use and functions. As with WREG, we can
perform arithmetic and logic operations on many locations of the file register data
RAM. The PIC microcontrollers' file register size ranges from 32 bytes to several
thousand bytes depending on the chip. Even within the same family, the size ofthe
file register data RAM varies from chip to chip. Notice that the file register data
RAM has a byte-size width, just like WREG The file register data RAM in PIC is
divided into two sections: (a) Special Function Registers (SFR), and (b) GeneralPurpose Registers (GPR). The general-purpose register section is also referred to
as General-Purpose RAM (GP RAM). We examine each section separately.
SFRs (Special Function Registers)
The Special Function Registers (SFRs) are dedicated to specific functions
such as ALU status, timers, serial communication, I/O ports, ADC, and so on. The
function of each SFR is fixed by the CPU designer at the time of design because
it is used for control of the microcontroller or peripheral. The PIC SFRs are 8-bit
registers. The number oflocations in the file register set aside for SFR depends on
the pin numbers and peripheral functions supported by that chip. That number can
vary from chip to chip even among members of the same family. Some have as few
as 7 (8-pin PICl2C508 with no on-chip analog-to-digital converter) and some
have over a hundred (40-pin PICl8F458 with on-chip analog-to digital converter).
For example, the more timers we have in a PIC chip, the more SFR registers we
will have. We will study and use many SFRs in future chapters.
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
43
GPR (General-Purpose Registers or RAM)
The general-purpose registers are a group of RAM locations in the file register that are used for data storage and scratch pad. Each location is 8 bits wide and
can be used to store any data we want as long as it is 8-bit. Again, the number of
RAM locations in the file register that are set aside for general-purpose registers
can vary from chip to chip, even among members of the same family. In the PIC
controllers, the space that is not allocated to the SFRs typically is used for general-purpose registers. That means in a PIC chip with a thousand-byte file register,
no more than 100 bytes are used for SFRs and the rest are used for general-purpose registers. A larger GPR size means more difficulties in managing these registers if you use Assembly language programming. In today's high-performance
microcontroller, however, with over a thousand bytes of GPR, the job of managing them is handled by the C compilers. Indeed, the C compilers are the very reason we need a large GPR since it makes it easier for C compilers to store parameters and perform their jobs much faster. See Table 2-1 for a comparison of file registers among various PIC chips. Also see Figure 2-2.
Table 2-1: File Register Size for PIC Chips
File Register
SFR
(Bytes)
=
(Bytes) +
PICI2F508 32
7
PICI6F84
80
12
PICI8FI220 512
256
PIC18F452
1792
256
PICI8F2220 768
256
PICI8F458
1792
256
PICI8F8722 4096
158
Available space for GPR
(Bytes)
25
68
256
1536
512
1536
3938
Extracted from http://www.microchip.com
GP RAM vs. EEPROM in PIC chips
Note that there are two RAM columns in the chip information section of
the Microchip web site. One refers to the general-purpose registers' (GP RAM)
size, and the other is the EEPROM size. GP RAM (which constitutes most of the
file register) must not be confused with the EEPROM data memory. The GPRs are
used by the CPU for internal data storage, whereas the EEPROMs are considered
as an add-on memory that one can also add externally to the chip. In other words,
while many PTC chips have zero bytes of EEPROM data memory, it is impossible
for a microcontroller to have zero size for the file register. The EEPROM memory of PIC chips is covered in Chapter 14.
The Microchip website provides the data RAM size, which is
the same as GPR size.
44
PIC12F508
PIC16F84
OOh
OOh
SFR
07h
08h
"I-- GP
PIC18F8722
OOOh
SFR
,. ...
OSh
OCh
.. ...
RAM
.....
GP ,. i-'
RAM
GP
RAM
.. ...
1Fh
F7Fh
4Fh
F80h
SFR
FFFh
Figure 2-2. File Registers of PIC12, PIC16, and PIC18
a-bit
a-bit
0000 h
0000 h
0001 h
0002 h
~-
GPRAM
~
- f-
-
4096-128 '"'
3968 bytes.
Not all
~
members
have this
-
Va,;ous PIC18
members have
different amount
}
amount
F7Fh
FBOh
SFR
Region
(128 bytes)
FFDh
}
FFEh
FFFh
a
b) File register
allocation between
GP RAM and SFR
See Chapter 6 for more
on how to access the
entire 4096 of the file
register
a-bit
a-bit
GPRAM
OOOh
128
07Fh
Bank 1
Access
Bank 14
Bank 15
chips have
this section
FFFh
a) Maximum space of
file register (data
RAM) in PIC18F
(4096 byte)
Bank
All PIC18F
Access
Bank
Bank
Sog 0
GPRAM
Sog 1
SFR
FBOh
--SFR.....
c) Data memory map
FFFh
d) Access Bank
Figure 2-3. File Register for PIC18 Family
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
45
File register and access bank in the PIC18
The file register of the PICI8 family can have a maximum of 4096 (4K)
bytes. With 4096 bytes, the file register has addresses of OOO-FFFH. The file register in the PICI8 is divided into 256-byte banks. Therefore, we can have up to a
maximum of 16 banks (16 x 256 = 4096). Although not all members ofthe PIC 18
family have that many banks, every PICI8 family member has at least one bank
for the file register. This bank is called the access bank and is the default bank
when we power up the PIC 18 chip. To simplify the discussion of how to use the
file register in the PIC family, we focus on this single bank that is found in every
member of the PICI8 family. You can examine the file registers in other PIC families such as PIC 12 and PIC 16 at the Microchip website. In this book we concentrate on the PICI8 series with their large file register, although the insight gained
in the process can be applied to the PICI6 and PICl2 series.
Examine the access bank for the PICI8 in Figure 2-3. The 256-byte access
bank is divided into two equal sections of 128 bytes. These 128-byte sections are
given to the general-purpose registers and special function registers. The 128 bytes
from locations OOH to 7FH are set aside for general-purpose registers and are used
for read/write storage, or what is normally called a scratch pad. These 128 locations of RAM are widely used for storing data and parameters by PIC 18 programmers and C compilers. Each location of this 128-byte RAM of general-purpose
registers can be accessed directly by its address. We will use these locations in
future chapters to store data brought into the CPU via 110 and serial ports. We will
also use them to define counters for time delay in Chapter 3. The other 128 bytes
of the access bank is used for SFRs. It has addresses of F80H to FFFH, as shown
in Figure 2-4. One might wonder why the memory space of the SFRs and GPRs in
the access bank is not contiguous. The reason is to allow the RAM space between
080H and F7FH to be used for the general-purpose registers by various members
of the PIC 18 if they implement a larger data RAM size for the file register. A file
register of more than 256 bytes will necessitate bank switching. Bank switching is
a method used to access all the banks of the file register for PIC 18 family members that have more than the minimum access bank. PICI8 members with a file
register of more than 256 bytes will be discussed in more detail in Chapter 6 when
we discuss bank switching.
Notice that the 1/0 port SFRs, PORTA, PORTB, PORTC, PORTD,
and associated registers are among the most widely used SFRs in PIC. See
Chapter 4 for additional information on the special function registers.
46
F80h
PORTA
FAOh
PIE2
FCOh
----
FEOh
BSR
F8lh
PORTB
FAlh
PIR2
FClh
ADCONl
FElh
FSR1L
F82h
PORTC
FA2h
IPR2
FC2h
ADCONO
FE2h
FSR1H
F83h
PORTO
FA3h
FC3h
ADRESL
FE3h
PLUSWl
F84h
PORTE
FA4h
-------
FC4h
ADRESH
FE4h
PREINCl
F8Sh
----
FASh
SSPCON2
FE5h POSTOECl
F86h
----
--
FC5h
FA6h
FC6h
SSPCONl
FE6h POSTINCl
F87h
----
FA7h
--
FC7h
SSPSTAT
FE7h
INDFl
F88h
----
FA8h
-
FC8h
SSPADD
FE8h
WREG
FC9h
SSPBUF
FE9h
FSROL
FCAh
T2CON
FEAh
FSROH
F89h
LATA
FA9h
F8Ah
LATB
FAAh
--
F8Bh
LATC
FABh
RCSTA
FCBh
PR2
FEBh
PLUSWD
F8Ch
LATO
FACh
TXSTA
FCCh
TMR2
FECh
PREINCO
F8Dh
LATE
FADh
TXREG
FCDh
T1CON
FEDh POSTOECO
F8Eh
-------
FAEh
RCREG
FCEh
TMR1L
FEEh POSTINCO
FAFh
SPBRG
FCFh
TMR1H
FEFh
INDFO
FBOh
----
FDOh
RCON
FFOh
INTCON3
F9lh
-------
FBlh
T3CON
FDlh
WDTCON
FFlh
INTCON2
F92h
TRISA
FB2h
TMR3L
FD2h
LVDCON
FF2h
INTCON
F93h
TRISB
FB3h
TMR3H
FD3h
OSCCON
FF3h
PRODL
F94h
TRISC
FB4h
----
FD4h
----
FF4h
PRODH
F9Sh
TRISD
FBSh
FD5h
TOCON
FF5h
TABLAT
F96h
TRISE
FB6h
FD6h
TMROL
FF6h
TBLPTRL
F97h
-------------------
FB7h
FD7h
TMROH
FF7h
TBLPTRH
FD8h
STATUS
FF8h
TBLPTRU
FB9h
----------------
FD9h
FSR2L
FF9h
PCL
FBAh
CCP2CON
FDAh
FSR2H
FFAh
PCLATH
FBBh
CCPR2L
FDBh
PLUSW2
FBCh
CCPR2H
FDCh
F9Dh
PIEl
FBDh
CCP1CON
F9Eh
PIRl
FBEh
F9Fh
IPRl
FBFh
F8Fh
F90h
F98h
F99h
F9Ah
F9Bh
F9Ch
FB8h
··
FFBh
PCLATU
PREINC2
FDDh POSTOEC2 •
FFCh
STKPTR
FFDh
TOSL
CCPR1L
FDEh POSTINC2
FFEh
TOSH
CCPR1H
FDFh
FFFh
TOSU
INDF2
·
·
* - These are not physical registers.
Figure 2-4_ Special Function Registers of the PICIS Family_
Review Questions
I. True or false. Data space in PIC is SRAM memory, whereas program (code)
space is of the ROM type.
2. The general-purpose RAM and SFRs together are calledo-:--..,.---:_
3. True or false. The larger the file register, the more difficult it is to manage.
4. True or false. The more file register space that is assigned to the SFRs, the less
is available for the GP RAM.
5. The SFR registers in PIC are _ _-bit.
6. The file register space in PIC 18 is divided into _ _-byte banks.
7. The file register space in PIC 18 can be a maximum of
bytes.
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
47
SECTION 2.3: USING INSTRUCTIONS WITH THE DEFAULT
ACCESS BANK
The instructions we have used so far are the literal (constant) value of K
and the WREG register. They also used the WREG register as their destination. We
saw simple examples of using MOVLW and ADDLW earlier in Section 2.1. The
PIC allows direct access to other locations in the file register for ALU and other
operations. In this section we show the instructions using various locations of the
file register. This is one of the most important sections in the book for mastering
the topic of PIC Assembly language programming.
MOVWF instruction
As we discussed in the last section, the access bank of the file register is
the default bank upon powering up the PIC 18. The term file register must be
emphasized because the instructions have the letter F in their mnemonics. In
instructions such as MOVWF, the F stands for a location in the file register, while
W means WREG The MOVWF instruction tells the CPU to move (in reality,
copy) the source register of WREG to a destination in the file register (F). After
this instruction is executed, the location in the file register will have the same value
as register WREG The location in the file register can be one of the SFRs or a
location in the general purpose registers region. For example, the "MOVWF
PORTA" instruction will move the contents ofWREG into the SFR register called
PORTA. The following program first loads the WREG register with value 55H,
then moves this value around to various SFRs of ports B, C, and D:
MOVLW
MOVWF
MOVWF
MOVWF
55H
PORTB
PORTC
PORTD
;WREG ~ 55H
;copy WREG to Port B (Port B
;copy WREG to Port C (Port C
;copy WREG to Port D (Port D
55H)
55H)
55H)
PORTB, PORTC, and PORTD are part of the special function registers in
the file register, as was shown in Figure 2-4. They can be connected to the 110 pins
of the PIC microcontroller as we will see in Chapter 4. We can also move (copy)
the contents of WREG into any location in the general-purpose registers (RAM)
region of the file registers. The following program will put 99H into locations 0-4
of the GPR region in the file register:
MOVLW
MOVWF
MOVWF
MOVWF
MOVWF
MOVWF
99H
OH
IH
2H
3H
4H
;WREG
99H
imove (copy)
imove (copy)
WREG contents to location Oh
WREG contents to location Ih
The chart indicates the contents of addresses 0-4
after execution of the code.
48
Address
000
001
002
003
004
Data
99
99
99
99
99
Example 2-1
State the contents of file register RAM locations after the following program:
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
99H
I2H
8SH
I3H
3FH
I4H
63H
ISH
I2H
I6H
iload WREG with value 99H
;load WREG with value 8SH
iload WREG with value 3FH
iload WREG with value 63H
; load WREG with value I2H
Solution:
After the execution of MOVWF I2H
After the execution of MOVWF 13H
After the execution of MOVWF I4H
After the execution of MOVWF I5H
And so on, as shown in the chart.
fileReg
fileReg
fileReg
fileReg
RAM
RAM
RAM
RAM
location
location
location
location
12H has
13H has
14H has
ISH has
Address
012
013
014
015
016
value
value
value
value
99H;
85H;
3FH;
63H;
Data
99
85
3F
63
12
Notice that you cannot move literal (immediate) values directly into
the general-purpose RAM locations in the PICI8. They must be moved there
viaWREG
More instructions involving the WREG and the access
bank
There is a group of logic and arithmetic instructions that involve both the
WREG and a location in the file register. The ADDWF instruction is one of them.
The ADDWF instruction adds together the contents of WREG and a file register
location. The file register location can be one of the SFRs or a general-purpose
register. The destination for the result can be the WREG or the file register. The
following format indicates the destination:
ADDWF fiIeReg, D
where fileReg is the file register location and D indicates the destination bit. The
D bit can be 0 or 1. IfD = 0, it means that the destination is WREG. IfD = 1, then
the result will be placed in the file register.
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
49
The following will first put value 22H into GP RAM locations 5, 6, and 7,
then add them together and put the result in WREG:
MOVLW
MOVWF
MOVWF
MOVWF
ADDWF
ADDWF
ADDWF
22H
;WREG = 22H
5H
; move (copy) WREG contents
6H
; move (copy) WREG contents
7H
; move (copy) WREG contents
5H, 0 ;add W and loc 5, result
6H, 0 ;add W and loc 6, result
7H, 0 ;add W and loc 7, result
to location 5H
to location 6H
to location 7H
in WREG (W
44H)
in WREG (W
66H)
in WREG (W
BBH)
Address
Data
Address
Data
005
006
007
22
22
22
005
006
007
22
22
22
GPR after the execution up to
GPR after the execution up to
"MOVWF 7H"
"ADDWF 7H,
WREG=22H
WREG= 88H
0"
Now look at the same program where the result is put into file register location 7:
MOVLW
MOVWF
MOVWF
MOVWF
ADDWF
ADDWF
ADDWF
50
22H
5H
6H
7H
5, 0
6, 0
7, 1
;WREG = 22H
iffiove (copy) WREG contents to location 5H
imove (copy) WREG contents to location 6H
jffiOVe
(copy) WREG contents to location 7H
;add W and loc 5, result in WREG (W = 44H)
;add W and loc 6, result in WREG (W = 66H)
;add W and loc 7, result in location 7H
inOW location 7 has BBH and WREG = 66H
Address
Data
Address
Data
005
006
007
22
22
22
005
006
007
22
22
88
GP RAM after the execution up to
GP RAM after the execution up to
"MOVWF 7H"
"ADDWF 7H,
WREG = 22H
WREG = 66H
1"
To make things less confusing as far as the D bit is concerned, the PIC
assembler allows us to use the letters W or F instead of 0 or I to indicate the destination. Look at the following two formats:
ADDWF fileReg,
ADDWF fileReg,
W
f
;add WREG and fileReg.
;add WREG and fileReg
;fileReg = the result
WREG
the result
This format is much easier and will help us to avoid confusion about the
destination. Look at the rewrite of the last program with the new format for the
ADDWF instruction:
MOVLW
MOVWF
MOVWF
MOVWF
ADDWF
ADDWF
ADDWF
22H
5H
6H
7H
5H,W
6H,W
7H,F
;WREG
=
22H
(copy) WREG contents to location 5H
iffiove (copy) WREG contents to location 6H
iffiove (copy) WREG contents to location 7H
;add W and loc 5, result in WREG (W = 44H)
; add W and loc 6, result in WREG (W = 66H)
;add W and loc 7, result in location 7
inow location 7 has 88H and WREG = 66H
i ffiove
The above concept is important and must be understood since there are a
large number of instructions with this format. Compare Examples 2-2 and 2-3.
Example 2-2
State the contents of file register RAM locations 12H and WREG after the following
program:
MOVLW
MOVWF
MOVLW
ADDWF
ADDWF
ADDWF
ADDWF
iffiove o WREG to clear it (WREG = 0)
i ffiove WREG to location 12 to clear i t
0
12H
22H
12H, F
12H, F
12H, F
12H, F
;load WREG with value
;add WREG to loc 12H,
iadd WREG to loc 12H,
; add WREG to loc 12H,
; add WREG to loc 12H,
22H
loc
loc
loc
loc
sum
sum
sum
sum
12
12
12
12
Solution:
The program clears both the WREG and RAM location 12H in the file register.
Then it loads WREG with value 22H. From then on, it adds the WREG register and
location 12 together and saves the result in location 12H. It does that four times. {\,t the
end, location 12H ofGP RAM has the value of88H (4 x 22H = 88H) and WREG = 22H.
After each "ADDWF 12, F" instruction
Address
OIl
012
013
Data
WREG
22H
=
22
Address
011
012
013
WREG
=
Data
44
22H
Address
Oil
012
013
WREG
=
Data
66
22H
Address
Oil
012
013
Data
WREG
22H
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
=
88
51
Example 2-3
Rewrite the last example to place the sum in WREG as you add the file register locations and the WREG register.
MOVLW
MOVWF
MOVLW
ADDWF
ADDWF
ADDWF
ADDWF
iffiove o WREG to clear it (WREG = 0)
; move WREG to location 12 to clear it
;load WREG with value 22H
;add WREG and loc 12H. WREG = sum
; add WREG and loc 12H, WREG = sum
;add WREG and loc 12H. WREG = sum
;add WREG and loc 12H, WREG = sum
0
12H
22H
W
12H. W
12H. W
12H. W
12H,
Solution:
The program adds WREG and location 12H together and saves the result in WREG
each time. At the end, location 12H has a value of22H and WREG = 88H
(4 x 22H = 88H).
After each "ADDWF 12, W" instruction:
Address
011
012
013
Data
Address
011
012
013
22
WREG = 22H
WREG
Data
Address
011
012
013
22
=
44H
Data
Address
011
012
013
22
WREG = 66H
8·BIT LITERAL (FROM
INSTRUCTION WORD)
Data
22
WREG = BBH
I
8-BITWIDE
000
8-BITWIDE
REGISTER VALUE
--l
WREG REGISTER
-
I
MUX
\
ALU
8-BITWIDE
,
I.
/
I
REGISTER
FILE
CARRY
I
N, OV, Z, DC, C
STATUS
REGISTER
I
SPECIAL
FUNCTION
REGISTER
AND
GENERAL
PURPOSE
RAM
o BIT, OR FROM
INSTRUCTION
FFF
FIgure 2-5. WREG, fileReg, and ALU
52
III
PIC18
Now examine the instructions in Tables 2-2 and 2-3. The instructions in
Table 2-2 operate on both WREG and a file register location and then give you the
option of placing the result in WREG or a file register location. The instructions
in Table 2-3, however, operate on the file register only and then give you the option
of placing the result in WREG or a file register location.
Table 2-2: ALU Instructions Using Botb WREG and fileReg
Instruction
ADDWF
ADDWFC
ANDWF
IORWF
SUBFWB
SUBWF
SUBWFB
XORWF
fileReg,
fileReg,
fileReg,
fileReg,
fileReg,
fileReg,
fileReg,
fileReg,
d
d
d
d
d
d
d
d
ADD WREG and fileReg
ADD WREG and fileReg with Carry
AND WREG with fileReg
OR WREG with fileReg
Subtract fileReg from WREG with borrow
Subtract WREG from fileReg
Subtract WREG from fileReg with borrow
Exclusive-OR WREG with fileReg
Note: The d bit selects the destination for the operation. If d = w; the result is
stored in WREG (d = 0). If d = F; the result is stored in the fileReg (d =
1). The default is F. That means "ADDWF myf i le" is the same as "ADDWF
myfile, F."
See Chapter 5 for examples of the instructions in Table 2-2.
Table 2-3: File Register Instructions Using fileReg or WREG as Destination
Instruction
COMF
DECF
DECFSZ
DECFSNZ
INCF
INCFSZ
INCSNZ
MOVF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SWAPF
BTG
fileReg,
fileReg,
fileReg,
fileReg,
fileReg,
fileReg,
fileReg,
fileReg,
fileReg,
fileReg,
fileReg,
fileReg,
fileReg,
fileReg,
fileReg,
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
Complement fileReg
Decrement fileReg
Decrement fileReg and skip if zero
Decrement fileReg and skip if not zero
Increment fileReg
Increment fileReg and skip if zero
Increment fileReg and skip if not zero
Move fileReg
Negative fileReg
Rotate left fileReg through carry
Rotate left fileReg (No carry)
Rotate right fileReg through carry
Rotate right fileReg (No carry)
Swap nibbles in fileReg
Bit Toggle fileReg
Note: The d bit selects the destination for the operation. If d = w; the result is
stored in the WREG (d = 0). If d = F; the result is stored in the fileReg (d
= 1). The default is F. That means "DECF myf ile" is the same as "DECF
myfile I F."
Chapters 3 through 6 will show how to use the instructions in Table 2-3.
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
53
COMF instruction
The "COMF fileReg, d" instruction complements (inverts) the contents of fileReg and places the result in WREG or fileReg. This is an example of
what is called Read - Modify - Write and we will see more of this in future chapters. In the following program, we put 55H into WREG and then send it to SFR
location of Port B. Then the content of Port B is complemented, which becomes
AA in hex. The 01010101 (55H) is inverted and becomes 10101010 (AAH).
MOVLW 55H
MOVWF PORTB
COMF PORTB, F
;WREG = 55h
;Move WREG to Port B SFR (PB = 55h)
;complement Port B (PB = AAh)
Examine Example 2-4.
Example 2-4
Write a simple program to toggle the SFR of PORT B continuously forever.
Solution:
B1
MOVLW
MOVWF
COMF
GOTO
55H
PORTB
PORTB, F
B1
;WREG = 55h
;move WREG to Port B SFR (PB = 55h)
jcomplement Port B and place it in Port B
;repeat forever (See Chapter 3 for GOTO)
DECF instruction
The "DECF fileReg, d" instruction decrements (subtracts one from)
the contents of fileReg and places the result in WREG or fileReg. In the following
program, we put the value 3 into fileReg location Ox20. Then the value in location
Ox20 is decremented and placed in fileReg.
MOVLW
MOVWF
DECF
DECF
DECF
3
20H
Ox20, F
Ox20, F
Ox20, F
;WREG = 3
iffiove WREG to loc 20H (loc 20H
;loc 20H has 2
;loc 20H has 1
;loc 20H has 0 and WREG = 3
3)
Now, contrast the above code with the following:
MOVLW
MOVWF
DECF
DECF
DECF
3
20H
Ox20, W
Ox20, W
Ox20, W
;WREG = 3
iffiove WREG to loc 20H
;loc 20H has 3 (WREG
iloc 20H has 3 (WREG
;loc 20H has 3 (WREG
(loc 20H
2)
2)
2)
The above concept will be used in loops in the next chapter.
S4
3)
MOVF instruction
The MOVF mnemonic is intended to perform MOVFW. It has the following format:
MOVF
fileReg, D
If D = 0, it copies the content of fileReg to WREG. If D = 1, the content of
fileReg is copied to itself. While typically we use the MOVF instruction to bring
data into WREG from 1/0 pins, we sometimes use it to copy fileReg to itself for
the purpose of testing fileReg contents. Examine the difference between the
MOVWF and MOVF instructions. We used the MOVWF instruction earlier to
move data to SFRs such as Port B. We also saw how it is widely used to load fixed
(literal) data into the RAM locations of the file register because there is no way we
can load data into the file register directly. In contrast, the MOVF instruction is
widely used to bring data from 110 ports such as Port B into the CPU. We also use
the MOVF instruction to bring data into WREG from any SFRs or from any location in the GP RAM in order to perform arithmetic and operations on them.
Examine Examples 2-5 and 2-6. Note that the only time we use the "MOVF
f i leReg, F" instruction to copy data from fileReg to itself is when we want to
affect the flag bits of the status register. The status register bits are discussed in the
next section, and Chapter 3 shows how to use them.
Example 2-5
Write a program to get data from the SFRs of Port B and send it to the SFRs of PORT
C continuously.
Solution:
AGAIN MOVF PORTB, W
MOVWF PORTC
GOTO AGAIN
;bring data from PortB into WREG
;send it to Port C
ikeep doing it forever
In Example 2-5 we use GOTO to repeat an action indefinitely. We will
study looping in Chapter 3. The details of 1/0 ports are discussed in Chapter 4.
Example 2-6
Write a program to get data from the SFRs of Port B. Add the value 5 to it and send it
to the SFRs of Port C.
Solution:
MOVF
PORTB,W
ADDLW 05H
MOVWF PORTC
;bring data from Port B into WREG
;add 5 to WREG
;copy WREG to Port C
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
55
MOVFF instruction
The MOVFF instruction copies data from one location in fileReg to another location in fileReg. The fileReg location for source and destination can be any
of the 4096 locations in the data RAM space of the PICI8. The MOVFF instruction allows us to move data within the 4K space of the data RAM without going
through the WREG register. (See Figure 2-6.) Compare Examples 2-5 and 2-7.
BEFORE MOVFF
COMMAND
000 h
AFTER MOVFF
COMMAND
000 h
SOURCE
ADDRESS
VALUE
.. ....
~I--
????
FFF h
VALUE
......
DESTINATION
ADDRESS
~
i-'
VALUE
......
FFF h
Figure 2-6. Moving Data Directly Among the fiJeReg Locations
Example 2-7
Write a program to get data from the SFRs of Port B and send it to the SFRs of PORT
C continuously using MOVFF. Compare this to Example 2-5 and explain the difference.
Solution:
AGAIN MOVFF PORTB, PORTC
GOTO AGAIN
;copy data from Port B to Port C
ikeep doing it forever
In Example 2-5 we have:
AGAIN MOVF PORTB, W
MOVWF PORTC
GOTO AGAIN
;bring data from Port B into WREG
isend it to Port C
ikeep doing it forever
Using MOBVFF we simply copy data from one location to another location. But
when we use WREG we can perform arithmetic and logic operations on data before it
is moved.
56
Review Questions
I. True or false. The access bank is 256 bytes divided evenly between GPRs and
SFRs.
2. Write instructions to add the values 16H and CDH. Place the result in location
o of the file register.
3. True or false. No value can be moved directly into general-purpose RAM.
4. What is the largest hex value that can be moved into a location in the file register? What is the decimal equivalent of the hex value?
5. "ADDWF PORTB, w" puts the result in _ _ .
SECTION 2.4: PIC STATUS REGISTER
Like all other microprocessors, the PIC has a flag register to indicate arithmetic conditions such as the carry bit. The flag register in the PIC is called the status register. In this section, we discuss various bits of this register and provide
some examples of how it is altered. Chapters 3 and 5 show how the flag bits of the
status register are used.
PIC18 status register
The status register is an 8-bit register. It is also referred to as the flag register. Although the status register is 8 bits wide, only 5 bits of it are used by the
PIC 18. The three unused bits are unimplemented and read as O. The five flags are
called conditional flags, meaning that they indicate some conditions that result
after an instruction is executed. These five flags are C (carry), DC (digital carry),
Z (zero), OV (overflow), and N (negative). See Figure 2-7 for the bits of the status register. Each of the conditional flags can be used to perform a conditional
branch (jump), as we will see in Chapter 3.
07
x
I
X
X
I
N
I OV
00
Z
OC
C
I
C - Carry flag
OC - Oigital Carry flag
Z - Zero flag
OV - Overflow flag
N - Negative flag
X - 05, 06, and 07 are not implemented,
and reserved for future use.
Figure 2-7. Bits of Status Register
The following is a brief explanation of the flag bits of the status register.
The impact of instructions on this register is then discussed.
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
57
C, the carry flag
This flag is set whenever there is a carry out from the D7 bit. This flag bit
is affected after an 8-bit addition or subtraction. Chapter 5 shows how the carry
flag is used.
DC, the digital carry flag
If there is a carry from D3 to D4 during an ADD or SUB operation, this bit
is set; otherwise, it is cleared. This flag bit is used by instructions that perform
BCD (binary coded decimal) arithmetic. In some microprocessors this is called
the AC flag (Auxiliary Carry flag). See Chapter 5 for more information.
Z, the zero flag
The zero flag reflects the result of an arithmetic or logic operation. If the
result is zero, then Z = I. Therefore, Z = 0 if the result is not zero. See Chapter 3
to see how we use the Z flag for looping.
OV, the overflow flag
This flag is set whenever the result of a signed number operation is too
large, causing the high-order bit to overflow into the sign bit. In general, the carry
flag is used to detect errors in unsigned arithmetic operations while the overflow
flag is used to detect errors in signed arithmetic operations. The OV and N flag
bits are used for the signed number arithmetic operations and are discussed in
Chapter 5.
N, the negative flag
Binary representation of signed numbers uses D7 as the sign bit. The negative flag reflects the result of an arithmetic operation. If the D7 bit of the result is
zero, then N = 0 and the result is positive. If the D7 bit is one, then N = I and the
result is negative. The negative and OV flag bits are used for the signed number
arithmetic operations and are discussed in Chapter 5.
ADDLW instruction and the status register
Next we examine the impact of the ADDLW instruction on the flag bits C,
DC, and Z of the status register. Some examples should clarify their meanings.
Although all the flag bits C, Z, DC, Ov, and N are affected by the ADDLW instruction, we will focus on flags C, DC, and Z for now. The other flag bits are discussed
in Chapter 5, because they relate only to signed number operations. Examine
Examples 2-8 through 2-10 to see the impact of the ADD instruction on selected
flag bits.
Not all instructions affect the flags
Some instructions affect all the five flag bits C, DC, Z, OV, and N (e.g.,
ADDWL). But some instructions affect no flag bits at all. The move instructions
are in this category (except MOVF). And some instructions affect only the Z or N
flag bits, or both. The logic instructions are in this category (e.g., ANDWL).
58
Example 2-8
Show the status of the C, DC, and Z flags after the addition of 38H and 2FH in the
following instructions:
MOVLW 3SH
ADDLW 2FH
;add 2FH to WREG
Solution:
38H
+2FH
67H
0011 1000
0010 1111
01100111
WREG=67H
C = 0 because there is no carry beyond the D7 bit.
DC = 1 because there is a carry from the D3 to the D4 bit.
Z = 0 because the WREG has a value other than 0 after the addition.
Example 2-9
Show the status of the C, DC, and Z flags after the addition of 9CH and 64H in the
following instructions:
MOVLW 9CH
ADDLW 64H
;add 64H to WREG
Solution:
9CH
+ 64H
100H
1001 1100
01100100
0000 0000
WREG = 00
C = 1 because there is a carry beyond the D7 bit.
DC = 1 because there is a carry from the D3 to the D4 bit.
Z = 1 because the WREG has a value 0 in it after the addition.
Example 2-10
Show the status of the C, DC, and Z flags after the addition of 88H and 93H in the
following instructions:
MOVLW SSH
ADDLW 93H
;add 93H to WREG
Solution:
88H
+93H
llBH
10001000
1001 0011
0001 1011
WREG = lBH
C = 1 because there is a carry beyond the D7 bit.
DC = 0 because there is no carry from the D3 to the D4 bit.
Z = 0 because the WREG has a value other than 0 after the addition.
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
59
Table 2-4 shows the instructions and the flag bits affected by them.
Appendix A provides a complete list of all the instructions and their associated flag
bits.
Table 2-4: Instructions That Affect Flag Bits
Instruction
C
ADDLW
X
ADDWF
X
ADDWFC
X
ANDLW
ANDWF
CLRF
COMF
DAW
X
DECF
X
INCF
X
IORLW
IORWF
MOVF
X
NEGF
RLCF
X
RLNCF
RRCF
X
RRNCF
X
SUBFWB
X
SUBLW
SUBWF
X
SUBWFB
X
XORLW
XORWF
Note: X can be 0 or 1.
DC
z
X
X
X
X
X
X
OV
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
N
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
See Chapter 5 for how to use these instructions.
Flag bits and decision making
Because status flags are also
called conditional flags, there are instructions that will make a conditional jump
(branch) based on the status of the flag
bits. Table 2-5 provides the list. Chapter 3
will discuss the conditional branch
instructions and how they are used.
60
Table 2-5: PIC18 Branch (Jump)
Instructions Using Flag Bits
Instruction
Action
BC
BNC
BZ
BNZ
BN
BNC
BOV
BNOV
Branch
Branch
Branch
Branch
Branch
Branch
Branch
Branch
if C ~ 1
if C ~ 0
if Z = 1
if Z ~ 0
ifN = 1
ifN ~ 0
if OV = 1
if OV ~ 0
Review Questions
I. The flag register in the PIC is called the _ _ __
2. What is the size of the flag register in the PIC?
3. Which bits of the status register are unused?
4. Find the C, Z, and DC flag bits for the following code:
MOVLW 9FH
ADDLW 61H
5. Find the C, Z, and DC flag bits for the following code:
MOVLW 82H
ADDLW 22H
6. Find the C, Z, and DC flag bits for the following code:
MOVLW 67H
ADDLW 99H
SECTION 2.5: PIC DATA FORMAT AND DIRECTIVES
In this section we look at some widely used data formats and directives
supported by the PIC assembler.
PIC data type
The PIC microcontroller has only one data type. It is 8 bits, and the size of
each register is also 8 bits. It is the job of the programmer to break down data larger than 8 bits (00 to FFH, or 0 to 255 in decimal) to be processed by the CPU. For
examples of how to process data larger than 8 bits, see Chapter 5. The data types
used by the PIC can be positive or negative. A discussion of signed numbers is
given in Chapter 5 also. The bit-addressable data is discussed in Chapters 4 and 6.
Data format representation
There are four ways to represent a byte of data in the PIC assembler. The
numbers can be in hex, binary, decimal, or ASCII formats. The following are
examples of how each work.
Hex numbers
There are four ways to show hex numbers:
I. We can use h (or H) right after the number like this: MOVLW 99H
2. Put Ox (or OX) in front of the number like this: MOVLW Ox99
3. Put nothing in front or back of the number like this: MOVLW 99
4. Put h in front of the number, but with single quotes around the number like
this: MOVLW h' 99'
We use all four of these methods in this book, because many application
notes out there use one of them and we need to get used to them. Notice that some
PIC assemblers might give you a warning (but no error) when you use 99H
because the assembler already knows that data is in hex and there is no need to
remind it. We do that simply to remind ourselves (and it is a good reminder) when
we do coding in Assembly.
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
61
Here are a few lines of code that use the hex format:
MOVLW
ADDLW
ADDLW
ADDLW
ADDLW
25
Oxll
12H
;WREG
i
WREG
H'2A'
;WREG
;WREG
2CH
i
WREG
25H
25H
36H
48H
72H
+
+
+
+
llH
12H
2AH
2CH
36H
48H
72H
9EH
The following are invalid:
MOVLW ESH
ADDLW C6
invalid,
; invalid,
i
it must be MOVLW OE5H
i t must be ADDLW OC6
Notice in the last two instructions that if the value starts with the hex digits A-F, then it must be preceded with a zero. However, the following is valid:
MOVLW OF
;va1id, WREG
=
OFH (or 00001111 in binary)
Binary numbers
There is only one way to represent binary numbers in a PIC assembler. It
is as follows:
MOVLW B'10011001'
;WREG
=
10011001 or 99 in hex
The lowercase b will also work. Note that' is the single quote key, which
is on the same key as the double quote". This is different from other assemblers
such as the 8051 and x86. Here are some examples of how to use it:
MOVLW B'00100101'
ADDLW B'00010001'
;WREG
;WREG
2SH
25H + llH
36H
Decimal numbers
There are two ways to represent decimal numbers in a PIC assembler. One
way is as follows:
MOVLW D'12'
;WREG
=
00001100 or OC in hex
The lowercase d will work also. This is different from other assemblers
such as the 8051 and x86. In those assemblers, to indicate decimal numbers we
simply use the decimal (e.g., 12) and nothing before or after it, while in the PIC
assembler, 12 is the default for hex numbers. Here are some examples of how to
use it:
MOVLW D r 37'
iWREG
ADDLW D'17'
;WREG
25H (37 in decimal is 25 in hex)
37 + 17 = 54 where 54 in dec is 36H
The other way to represent decimal numbers is to use". value" as seen in
some application notes for PIC microcontrollers. This is shown as follows:
MOVLW .12
62
;WREG
=
00001100
=
OCH
=
12
ASCII character
To represent ASCII data in a PIC assembler we use the letter A as follows:
MOVLW A'2'
;WREG = 00110010 or 32 in hex (See Appendix F)
Lowercase 'a' will work as well. Again, this is different from other assemblers such as the 8051 and x86. In those assemblers, single quotes are used for single ASCII characters and double quotes are used for a string. Here are some more
examples:
MOVLW A'gI
iWREG
ADDLW A'l'
;WREG = 39H + 31H = 70H
; (31 hex is for ASCII '1')
;WREG = 39H another way for ASCII
MOVLW '9'
=
39H,
which is hex number for ASCII
'9'
To define ASCII strings (more than one character), we use the DB (define
byte) directive. We will see DB usage in Chapter 6.
Assembler directives
While instructions tell the CPU what to do, directives (also called pseudoinstructions) give directions to the assembler. For example, the MOVLW and
ADDLW instructions are commands to the CPU, but EQU, ORG, and END are
directives to the assembler. The following sections present some more widely used
directives of the PIC and how they are used.
EQU (equate)
This is used to define a constant value or a fixed address. The EQU directive does not set aside storage for a data item, but associates a constant number
with a data or an address label so that when the label appears in the program, its
constant will be substituted for the label. The following uses EQU for the counter
constant, and then the constant is used to load the WREG register:
COUNT EQU
MOVLW
Ox25
COUNT ;WREG
=
25H
When executing the above instruction "MOVLW COUNT", the register
WREG will be loaded with the value 25H. What is the advantage of using EQU?
Assume that a constant (a fixed value) is used throughout the program, and the
programmer wants to change its value everywhere. By the use of EQU, the programmer can change it once and the assembler will change all of its occurrences
throughout the program, rather than search the entire program trying to find every
occurrence.
SET
This directive is used to define a constant value or a fixed address. In this
regard, the SET and EQU directives are identical. The only difference is the value
assigned by the SET directive may be reassigned later.
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
63
Using EQU for fixed data assignment
To get more practice using EQU to assign fixed data, examine the following:
DATAl
DATA2
DATA3
DATA4
DATA5
EQU
EQU
EQU
EQU
EQU
; in hexadecimal
39
;hex data is
Ox39
; another way
39H
ianother way
HI 39'
; another way
h l 39'
; another way
DATA6 EQU
DATA7 EQU
,-in binary
b'00110101'
B' 00110101'
DATAB EQU
DATA9 EQU
D'28
d' 28
DATAl 0 EQU
DATA11 EQU
DATA12 EQU
A'2 '
ibinary
the
for
for
for
for
default
hex
hex (redundant)
hex
hex
(35 in hex)
ibinary (35 in hex)
lin decimal
r
idecimal numbers
r
isecond way for decimal
(lC in hex)
; in ASCII
a'2'
'2 '
;ASCII characters
; another way for ASCII char
; another way for ASCII char
We use DB to allocate code ROM memory locations for fixed data such as
ASCII strings. See Chapter 6 for more examples.
Using EQU for SFR address assignment
EQU is also widely used to assign SFR addresses. Examine the following
code:
COUNTER EQU OxOO
PORTB EQU OxFF6
MOVLW COUNTER
MOVWF PORTB
INCF PORTB, F
INCF PORTB, F
INCF PORTE, F
icounter value 00
iSFR Port B address
;WREG
OOH
;Fort B now has 00 too
; Port B has 01
iincrement Port B (Port B
02)
;increment Port B (Port B
03)
The above is for the PIC 18 family. If you use a different PIC controller
such as PICI6F, where Port B is a different address, then change the EQU address
for Port Band re-assemble the program and run it.
COUNTER EQU OxOO
PORTB EQU Ox07
MOVLW COUNTER
MOVWF PORTB
INCF PORTB, F
INCF PORTB, F
INCF PORTB, F
and so on
64
;counter value 00
;Port B addr in PIC16F
;WREG
OOH
iPort B now has 00 too
;Fort B has 01
; Port B has 02
; Port B has 03
Using EQU for RAM address assignment
Another common usage of EQU is for the address assignment of the
general-purpose region of the file register. Examine the following rewrite of an
earlier example using EQU:
MYREG EQU Ox12
;assign RAM loc to MYREG
MOVLW
MOVWF
MOVLW
ADDWF
ADDWF
ADDWF
ADDWW
;clear WREG (WREG = 0)
;clear MYREG (lac 12H has 0)
i WREG = 22H
WREG + MYREG
; MYREG
WREG + MYREG
; MYREG
WREG + MYREG
; MYREG
iMYREG
WREG + MYREG
0
MYREG
22H
MYREG, F
MYREG, F
MYREG, F
MYREG, F
This is especially helpful when the address needs to be changed in order to
use a different PIC chip for a given project. It is much easier to refer to a name
than a number when accessing RAM address locations.
The following program will move value 9 into RAM locations 0-4, then
add them together and place the sum in location IOH:
MYVAL
RO
Rl
R2
R3
R4
SUM
MOVLW
MOVWF
MOVWF
MOVWF
MOVWF
MOVWF
MOVLW
ADDWF
ADDWF
ADDWF
ADDWF
ADDWF
MOVWF
EQU
EQU
EQU
EQU
EQU
EQU
EQU
9
0
1
2
3
4
lOH
MYVAL
RO
Rl
R2
R3
R4
0
RO,
Rl,
R2,
R3,
R4,
W
W
W
W
W
;MYVAL = 9
;assign RAM addresses to RO
ito Rl
;WREG
; RAM
; RAM
; RAM
; RAM
; RAM
;WREG
;WREG
;WREG
i
WREG
;WREG
;WREG
=
9
lac
lac
lac
lac
lac
0 has 9
1 has 9
2 has 9
3 has 9
4 has 9
0
RO
Rl
R2
R3
R4
+
+
+
+
+
WREG
WREG
WREG
WREG
WREG
SUM
ORG (origin)
The ORG directive is used to indicate the beginning of the address. It can
be used for both code and data. The number that comes after ORG must be in hex.
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
65
END directive
Another important pseudocode is the END directive. This indicates to the
assembler the end ofthe source (asm) file. The END directive is the last line of the
PIC program, meaning that anything after the END directive in the source code is
ignored by the assembler.
LIST directive
Unlike ORG and END, which are used by all assemblers, the LIST directive is unique to the PIC assembler. It indicates to the assembler the specific PIC
chip for which the program should be assembled. It is used as follows:
LIST P=18F458
The above tells the PIC assembler to assemble the program specifically for
the PIC 18F458 microcontroller. We use LIST to state the target chip.
#include directive
The #include directive tells the PIC assembler to use the libraries associated with the specific chip for which we are compiling the program.
_config directive
The _ config directive tells the assembler the configuration bits for the targeted PIC chip. It is important to use the correct _ config directive, because incorrect use may make the chip unusable. The configuration bits are read during
power-up of the PIC device and are stored at location 300000H. Microchip has
defined the _ config directive symbols to ease the configuration. These symbols are
located in the .INC file for the device that is being used. See Chapter 8.
radix directive
We can use the radix directive to indicate whether the numbering system is
hexadecimal or decimal. The default is hex if we do not use the radix directive. If
we use "radix dec", the default representation will change to decimal and any
unformatted number will be interpreted as decimal rather than hex, as seen before.
Rules for labels in Assembly language
By choosing label names that are meaningful, a programmer can make a
program much easier to read and maintain. There are several rules that names must
follow. First, each label name must be unique. The names used for labels in
Assembly language programming consist of alphabetic letters in both upper and
lower case, the digits 0 through 9, and the special characters question mark (?),
period (.), at (@), underline U, and dollar sign ($). The first character of the label
must be an alphabetic character. In other words, it cannot be a number. Every
assembler has some reserved words that must not be used as labels in the program.
Foremost among the reserved words are the mnemonics for the instructions. For
example, "MOVWL" and "ADDWL" are reserved because they are instruction
mnemonics. In addition to the mnemonics there are some other reserved words.
Check your assembler for the list of reserved words.
66
Review Questions
1. Give three ways for hex data representation in the PIC assembler.
2. Show how to represent decimal 99 in formats of (a) hex, (b) decimal, and (c)
binary in the PIC assembler.
3. What is the advantage in using the EQU directive to define a constant value?
4. Show the hex number value used by the following directives:
(a) ASC_DATA EQU A'4' (b) MY_DATA EQU B'00011111'
5. Give the value in WREG for the following:
MYCOUNT
EQU 15
MOVLW
MYCOUNT
6. Give the value in fileReg Ox20 for the following:
MYCOUNT
EQU Ox95
MYREG
EQU Ox20
MOVLW
MYCOUNT
MOVWF
MYREG
7. Give the value in fileReg Ox63 for the following:
MYDATA
EQU D'12'
MYREG
EQU Ox63
FACTOR
EQU Ox10
MOVLW
MYDATA
ADDLW
FACTOR
MOVWF
MYREG
SECTlON 26: INTRODUCTION TO PIC ASSEMBLY PROGRAMMING
In this section we discuss Assembly language format and define some
widely used terminology associated with Assembly language programming.
While the CPU can work only in binary, it can do so at a very high speed.
It is quite tedious and slow for humans, however, to deal with Os and I s in order
to program the computer. A program that consists of Os and 1s is called machine
language. In the early days of the computer, programmers coded programs in
machine language. Although the hexadecimal system was used as a more efficient
way to represent binary numbers, the process of working in machine code was still
cumbersome for humans. Eventually, Assembly languages were developed, which
provided mnemonics for the machine code instructions, plus other features that
made programming faster and less prone to error. The term mnemonic is frequently used in computer science and engineering literature to refer to codes and abbreviations that are relatively easy to remember. Assembly language programs must
be translated into machine code by a program called an assembler. Assembly language is referred to as a low-level language because it deals directly with the internal structure of the CPU. To program in Assembly language, the programmer must
know all the registers of the CPU and the size of each, as wen as other details.
Today, one can use many different programming languages, such as
BASIC, Pascal, C, C++, Java, and numerous others. These languages are caned
high-level languages because the programmer does not have to be concerned with
the internal details of the CPU. Whereas an assembler is used to translate an
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
67
Assembly language program into machine code (sometimes also called object
code or opcode for operation code), high-level languages are translated into
machine code by a program called a compiler. For instance, to write a program in
C, one must use a C compiler to translate the program into machine language. Next
we look at PIC Assembly language format.
Structure of Assembly language
An Assembly language program consists of, among other things, a series
of lines of Assembly language instructions. An Assembly language instruction
consists of a mnemonic, optionally followed by one or two operands. The
operands are the data items being manipulated, and the mnemonics are the commands to the CPU, telling it what to do with those items.
An Assembly language program (see Program 2-1) is a series of statements, or lines, which are either Assembly language instructions such as ADDLW
and MOVWF, or statements called directives. While instructions tell the CPU
what to do, directives (also called pseudo-instructions) give directions to the
assembler. For example, in Program 2-1 while the MOVWF and ADDLW instructions are commands to the CPU, ORG and END are directives to the assembler.
The directive ORG tells the assembler to place the opcode at memory location 0
while END indicates the end of the source code to the assembler. In other words,
one directive is for the start of the program and the other for the end of the program.
An Assembly language instruction consists of four fields:
[label]
mnemonic
[operands]
[; comment]
Brackets indicate that a field is optional and not all lines have them.
Brackets should not be typed in. Regarding the above format, the following points
should be noted:
I. The label field allows the program to refer to a line of code by name. The label
field cannot exceed a certain number of characters. Check your assembler for
the rule.
2. The Assembly language mnemonic (instruction) and operand(s) fields together perform the real work of the program and accomplish the tasks for which
the program was written. In Assembly language statements such as
MOVLW 55H
ADDLW 67H
ADDLW and MOVLW are the mnemonics that produce opcodes; the "55H"
and "67H" are the operands. Instead of a mnemonic and an operand, these two
fields could contain assembler pseudo-instructions, or directives. Remember
that directives do not generate any machine code (opcode) and are used only
by the assembler, as opposed to instructions that are translated into machine
68
code (opcode) for the CPU to execute. In Program 2-1 the commands ORG
(origin) and END are examples of directives. More of these pseudo-instructions are discussed in future chapters.
3. The comment field begins with a semicolon comment indicator ";". Comments
may be at the end of a line or on a line by themselves. The assembler ignores
comments, but they are indispensable to programmers. Although comments
are optional, it is recommended that they be used to describe the program in a
way that makes it easier for someone else to read and understand.
4. Notice the label "HERE" in the label field in Program 2-1. In the GOTO the
PIC is told to stay in this loop indefinitely. If your system has a monitor program you do not need this line and it should be deleted from your program. In
Section 2.7 we will see how to create a ready-to-run program.
;PIC Assembly Language Program To Add Some Data.
jstore SUM in fileReg location 10H.
SUM
HERE
EQU
10H
ORG
OH
MOVLW 25H
ADDLW Ox34
ADDLW 11H
ADDLW D118 1
ADDLW lCH
ADDLW B' 00000110'
MOVWF SUM
GOTO HERE
END
; RAM
lac 10H for SUM
istart at address 0
;WREG = 25
i add 34H to WREG
;add llH to WREG
W + 12H = 7CH
;W
;W = W + lCH = 98H
;W = W + 6 = 9EH
isave the SUM in lac 10H
jstay here forever
i end of asm source file
Program 2-1: Sample of an Assembly Language Program
Review Questions
I. What is the purpose of pseudo-instructions?
2.
are translated by the assembler into machine code, whereas
_ _ _,--:-_ _ _ _ are not.
3. True or false. Assembly language is a high-level language.
4. Which of the following instructions produces opcode? List all that do.
(a) MOVLW 25H (b)ADDLW 12 (c) ORG 2000H (d) GO TO HERE
5. Pseudo-instructions are also called _ _ _ __
6. True or false. Assembler directives are not used by the CPU itself. They are
simply a guide to the assembler.
7. In Question 4, which one is an assembler directive?
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
69
SECTION 2.7: ASSEMBLING AND LINKING A PIC PROGRAM
Now that the basic form of an Assembly language program has been given,
the next question is: How it is created, assembled, and made ready to run? The
steps to create an executable Assembly language program (Figure 2-8) are outlined
as follows:
I. First we use a text editor to type in a program similar to Program 2-1. In the
case of the PIC microcontrollers, we use the MPLAB IDE, which has a text
editor, assembler, linker, simulator, and much more all in one software package. It is an excellent development software that supports all the PIC chips and
is free. Many editors or word processors are also available that can be used to
create or edit the program. Some widely used editors are the MS-DOS EDIT,
and Notepad in Windows, which comes with all Microsoft operating systems.
Notice that the editor must be able to produce an ASCII file. For assemblers,
the file names follow the usual DOS conventions, but the source file has the
extension "asm". The "asm" extension for the source file is used by an assembler in the next step.
2. The "asm" source file containing the program code created in step I is fed to
the PIC assembler. The assembler converts the instructions into machine code.
The assembler will produce an object file and an error file. The extension for
EDITOR
PROGRAM
myfile.asm
ASSEMBLER
PROGRAM
I
myfile.err
.Iib additional
library files
myfile.out
myfile.o
LINKER
PROGRAM
myfile.cod
myfile.hex
DOWNLOAD
TO PIC'sROM
Figure 2-8. Steps to Create a Program
70
-
.0 additional
object files
.lkr linker
script file
myfile.map
myfile.lst
the object file is "0". The extension for the error file, which contains any syntax errors and their line numbers, is "err". The error file can be viewed with
any text editor.
3. Assemblers require a third step called linking. The link program takes one or
more object files and produces a hex file, a list file, a map file, an intermediate object file, and a debug file. The hex file has the extension "hex", the list
file extension is "1st", the map file extension is "map", the intermediate object
file extension is "out", and the debug file extension is "cod". After a successfullink, the hex file is ready to be burned into the PIC's program ROM and is
downloaded into the PIC Trainers. See Chapter 8 for more details.
The MPLAB IDE, a Windows-based program, combines steps 2 and 3 into
one step after the program has been typed.
More about asm, err, and object files
The asm file is also called the source file and must have the "asm" extension. As mentioned earlier, this file is created with a text editor such as MS-DOS
EDIT or Windows Notepad. Many assemblers come with a text editor. The assembler converts the asm file's Assembly language instructions into machine language
and provides the 0 (object) file. The PIC assembler produces the object and error
files. The object file as mentioned earlier, has an "0" as it extension. In modular
programming, we use the linker to link many object files together to create a
ready-to-burn hex file as we will see in Chapter 6. But before we can link a program to create a ready-to-run program, we must make sure that it is error free. The
PIC assembler provides us the error file with the extension of "err" and this is the
file we examine to see the nature of syntax errors. The linker will not link the program until all the syntax errors are fixed. We can print the error file or use Notepad
to examine the nature of the errors. Then we go back to the asm file and correct all
the errors before we assemble it again. A sample of an error file is shown on the
next page.
;PIC Assembly Language Program To Add Some Data.
istore sum in fileReg location lOH.
SUM
HERE
EQU
10H
; RAM
loe 10H for sum
ORG
OH
istart at address 0
MOVLW 25H
;WREG = 25
ADDLW Ox34
;add 34H to WREG
ADDLW 11H
;add 11H to WREG
ADDLW D'18'
;W
W + 12H = 7CH
ADDLW lCH
;W = W + lCH = 98H
ADDLW B' 00000110' ;W = W + 6 = 9EH
MOVWF SUM
isave the sum in loe 10H
GOTO HERE
;stay here forever
END
iend of asm source file
Program 2-1: Sample of a PIC Assembly Source Code (asm file)
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
71
Warning [207] C:\MDEPIC\EXAMPLE
Warning [207] C:\MDEPIC\EXAMPLE
Error [122]
C:\MDEPIC\EXAMPLE
Warning [207] C:\MDEPIC\EXAMPLE
Error [122]
C:\MDEPIC\EXAMPLE
Warning [203] C:\MDEPIC\EXAMPLE
Warning [207] C:\MDEPIC\EXAMPLE
Error [108]
C:\MDEPIC\EXAMPLE
Error [116]
C:\MDEPIC\EXAMPLE
ent in second pass (AGAIN)
2-l.ASM
2-1.ASM
2-1.ASM
2-1.ASM
2-l.ASM
2-1.ASM
2-1.ASM
2-1.ASM
2-1.ASM
6
13
13
17
17
20
21
21
29
Found label after column 1.
Found label after column 1.
(R4)
(movIe)
Illegal opcode (d)
Found label after column 1. (DEC)
Illegal opcode (COUNT)
Found opcode in column 1. (movwf)
Found label after column 1. (addl)
Illegal character (0)
Address label duplicated or differ-
Program 2-1: Sample of a PIC Error (err file)
"1st" and "map" files
The 1st (list) and map files are very useful to the programmer. The list
shows the binary and source code. The map file shows the memory layout of used
and unused memory locations. These files can be accessed by an editor such as
Notepad and displayed on the monitor, or sent to the printer to get a hard copy. The
programmer uses the list and map files to ensure correct system design.
LOC
OBJECT CODE LINE SOURCE TEXT
00000010
000000
000000
000002
000004
000006
000008
OOOOOA
OOOOOC
OOOOOE
OE25
OF34
OF11
OF12
OF1C
OF06
6E10
EF07 FOOO
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
VALUE
jPIC Asm Language Program To Add Some Data
istore SUM in fileReg location lOH
SUM EQU 10H
;RAM lac 10H for Sum
ORG OH
MOVLW 25H
ADDLW Ox34
ADDLW 11H
ADDLW D'18'
ADDLW 1CH
ADDLW B' 00000110'
MOVWF SUM
HERE GOTO HERE
END
jstart at address 0
WREG = 25
;add 34H to WREG
jadd 11H to WREG
;W
W + 12H = 7CH
;W = W + 1CH = 98H
;W = W + 6 = 9EH
jsave the SUM in lac 10H
jstay here forever
jend of asm source file
i
Program 2-1: List File
Review Questions
1. True or false. The MPLAB, MS-DOS Edit, and Windows Notepad text editors
all produce an ASCII file.
2. True or false. The extension for the source file is "asm".
3. Which of the following files can be produced by the text editor?
(a) myprog.asm (b) myprog.o (c) myprog.hex (d) myprog.lst (e) myprog.err
4. Which of the following files is produced by an assembler?
(a) myprog.asm (b) myprog.o (c) myprog.hex (d) myprog.lst (e) myprog.err
5. Which of the following files lists syntax errors?
(a) myprog.asm (b) myprog.o (c) myprog.hex (d) myprog.lst (e) myprog.err
72
SECTION 2.8: THE PROGRAM COUNTER AND PROGRAM
ROM SPACE IN THE PIC
In this section we discuss the role of the program counter (PC) in executing a program and show how the code is fetched from ROM and executed. We will
also discuss the program (code) ROM space for various PIC family members.
Finally, we examine the Harvard architecture of the PIC 18.
Program counter in the PIC
Another important register in the PIC microcontroller is the PC (program
counter). The program counter is used by the CPU to point to the address of the
next instruction to be executed. As the CPU fetches the opcode from the program
ROM, the program counter is incremented automatically to point to the next
instruction. The wider the program counter, more the memory locations a CPU can
access. That means that a 14-bit program counter can access a maximum of 16K
(214 = 16K) of code from addresses 0000-3FFFH. The PIC family 16F has 14-bit
program counters, while the program counter in PICI2F is 12-bit. In the case ofa
16-bit program counter, the code space is 64K (2 16 = 64K), which occupies the
OOOO-FFFFH address range. The 8051 microcontrollers have a 16-bit program
counter. The program counter in the PIC 18 family is 21-bit. This means that the
PIC 18 family can access program addresses 000000 to I FFFFFH, a total of 2M of
code. However, not all members ofthe PIC 18 family have the entire 2M (221 = 2M)
of on-chip ROM installed. See Table 2-6. The 14-bit program counter in the
PICI6C family had imposed the maximum code size of 16K. To overcome this
major limitation, PIC designers had to introduce the tedious job of page switching
in the later members of the PIC 16 family. They learned their lessons and solved
the problem for the PIC 18 family by expanding the program counter to 21-bit for
that family. See Figure 2-9. The 2M code space is plenty of space for many years
to come. The data in Table 2-6 is from the Microchip web site.
ROM memory map in the PIC18 family
As we just saw, some family members have only a few K of on-chip ROM
(PICI8F2220) and some, such as the PIC18F6680, have 64K of ROM. PICI8F458
has 32K of on-chip ROM. The point to remember is that no member of the PIC
family can access more than 2M of opcode because the program counter in the PIC
is 21 bits wide (000000 to I FFFFF address range). It must be noted that while the
first location of program ROM inside the PIC has the address of 000000, the last
location can be different depending on the size of the ROM on the chip. (See
Figure 2-10.) Among the
PIC 18 family members, the
PICI8F2220 has 4K of onpcu
0
PCH
PCl
chip ROM. This 4K ROM
.. II
a-bit ------........-- 8-bit
8-bit -----+memory
has
memory
21-bit PC (Program Counter)
addresses of 00000 to
OOOFFFH. Therefore, the
first location of on-chip
.
Figure 2-9. Program Counter In PICl8
11+1
-I
I
I
I
I
.
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
73
ROM of this PIC has an address of 000000 and the last location has the address of
OFFFH. Look at Example 2-11 to see how this is computed.
Table 2-6: PIC18 On-chip ROM Size and Address Space
On-Chip Code ROM
Code Address Range
(Bytes)
(Hex)
PIC I 8F2220
4K
OOOOO-OOFFF
PICI8F2410
16K
00000-03FFF
PICI8F458
32K
00000-07FFF
PICI8F6680
64K
OOOOO-OFFFF
PIC I 8F8722
128K
00000-1 FFFF
Example 2-11
Find the ROM memory address of each of the following PIC chips:
(a) PIC I 8F2220 with 4 KB
(b) PICI8F2410 with 16 KB
(c) PICI8F458 with 32 KB
Solution:
(a) With 4K of on-chip ROM memory space, we have 4096 bytes (4 x 1024 = 4096).
This maps to address locations of 0000 to OFFFH. Notice that 0 is always the first
location.
(b) With 16K of on-chip ROM memory space, we have 16,384 bytes (16 x 1024 =
16,384),which gives 0000-3FFFH.
(c) With 32K we have 32,768 bytes (32 x 1024 = 32,768). Converting 32,768 to hex,
we get 8000H; therefore, the memory space is 0000 to 7FFFH.
byte
II
byte
..
000000
II
..
..
000000
byte
..
000000
OOOFFF ' - - - - - - '
PIC18F2220
003FFF
PIC18F241O
007FFF
PICI8F458
Figure 2-10. PIC18 On-Chip Program (code) ROM Address Range
74
Where the PIC wakes up when it is powered up
One question that we must
~ 8-bit wide ~
ask about any microcontroller (or
microprocessor) is: At what
DDDDDDh
RESET VECTOR
address does the CPU wake up
when power is applied? Each
HIGH PRIORITY
DDDDD8h INTERRUPT
VECTOR
microprocessor is different. In the
case of the PIC family, that is, all
LOW PRIORITY
DDDD18h INTERRUPT
members regardless of the family
VECTOR
and variation, the microcontroller
wakes up at memory address 0000
when it is powered up. By powerON-CHIP PROGRAM
MEMORY
ing up we mean applying Vee to
the RESET pin as discussed in
Chapter S. In other words, when
the PIC is powered up, the PC (program counter) has the value of
00000 in it. This means that it
EXTERNAU
UNIMPLEMENTED
expects the first opcode to be
PROGRAM MEMORY
stored at ROM address OOOOOH.
(READ AS '0' IN
For this reason, in the PIC system,
MICROCONTROLLER
MODE)
the first opcode must be burned
into memory location OOOOOH of
program ROM because this is
1FFFFFh
where it looks for the first instruction when it is booted. We achieve Figure 2-11. PIC1S Program ROM Space
this by using the ORO statement in
the source program as shown earlier. Next we discuss the step-by-step action of the
program counter in fetching and executing a sample program.
Placing code in program ROM
To get a better understanding of the role of the program counter in fetching and executing a program, we examine the action of the program counter as
each instruction is fetched and executed. First, we examine once more the list file
of the sample program and show how the code is placed in the ROM of PIC chip.
As we can see, the opcode and operand for each instruction are listed on the left
side of the list file.
After the program is burned into ROM of a PIC family member such as
PICISF452 or PICISF45S, the opcode and operand are placed in ROM memory
locations starting at 0000 as shown in the Program 2-1 list file.
The list shows that address 0000 contains OE, which is the opcode for moving a value into WREG, and address 0001 contains the operand (in this case 25H)
to be moved to WREG. Therefore, the instruction "MOVLW 2 5H" has a machine
code of "OE25", where OE is the opcode and 25 is the operand. Similarly, the
machine code "OF34" is located in memory locations 0002 and 0003 and represents the opcode and the operand for the instruction "ADDLW 34H". In the same
way, machine code "OF 11 " is located in memory locations 0004 and 0005 and repCHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
75
resents the opcode and the operand for the instruction "ADDLW 11". The memory location 0006 has the opcode of OF, which is the opcode for the instruction
"MOVLW" and memory location 0007 has the content 12, which is the operand for
the decimal 18 in the ADDLW D ' 18' instruction. The opcode for instruction
"ADDLW 1CH" is located at address 0008 and the operand 1CH at address 0009.
The memory locations OOOA and OOOOB have the opcode and operand for the
ADDLW B' 00000110' instruction. The opcode for instruction "MOVWF SUM"
is located at address OOOOC and its address of IOH at address OOOOD. The opcode
for "GOTO HERE" and its target address are located in locations OOOOE, F, 10, and
II. While all the instructions in this program are 2-byte instructions, the GOTO
instruction is a 4-byte instruction. The reasons are explained at the end of this section.
LOC
OBJECT CODE LINE SOURCE TEXT
00000010
000000
000000
000002
000004
000006
000008
OOOOOA
OOOOOC
OOOOOE
OE25
OF34
OF11
OF12
OF1C
OF06
6E10
EF07 FOOD
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
VALUE
;PIC Asm Language Program To Add Some Data
istore sum in fileReg location lOH
SUM EQU 10H
iRAM lac lOH for sum
ORG OH
MOVLW 25H
ADDLW Ox34
ADDLW 11H
ADDLW D'18 1
ADDLW 1CH
ADDLW B' 00000110'
MOVWF SUM
HERE GOTO HERE
END
istart at address 0
;WREG = 25
;add 34H to WREG
; add 11H to WREG
;W
W + 12H = 7CH
;W = W + 1CH = 98H
;W = W + 6 = 9EH
jsave the sum in lac lOH
jstay here forever
iend of asm source file
Program 2-1: List File
ROM Address
00000
00002
00004
00006
00008
OOOOA
OOOOC
OOOOE
76
Machine Language
OE25
OF34
OF11
OF12
OFlC
OF06
6E10
EF07 FOOO
Assembly Language
MOVLW 25H
ADDLW 34
ADDLW llH
ADDLW D' 18'
ADDLW 1CH
ADDLW B'00000110'
MOVWF SUM
HERE GOTO HERE
Executing a program byte by byte
Assuming that the above program is burned into the ROM of a PIC 18 chip,
the following is a step-by-step description of the action of the PIC upon applying
power to it:
I. When the PIC is powered up, the PC (program countProgram 2-1: ROM
er) has 00000 and starts to fetch the first opcode from
Contents
location 00000 of the program ROM. In the case of
the above program the first opcode is OE, which is the Address
Code
code for moving an operand to WREG. Upon execut- 000000
OE
ing the opcode, the CPU places the value of 25 in 000001
25
WREG. Now one instruction is finished. Then the 000002
OF
program counter is incremented to point to 00002 000003
34
(PC = 00002), which contains opcode OF, the opcode 000004
OF
for the instruction "ADDLW 34H".
000005
11
2. Upon executing the opcode OF, the value 34H is 000006
OF
added to WREG. Then the program counter is incre- 000007
12
mented to 0004.
000008
OF
3. ROM location 0004 has the opcode for instruction 000009
IC
"ADDLW IlH". This instruction is executed and now OOOOOA
OF
PC = 0006.
000008
06
4. This process goes on until all the instructions up to OOOOOC
6E
"MOVWF SUM" are fetched and executed. Notice that
OOOOOD
10
all the above instructions are 2-byte instructions; that OOOOOE
07
is, each one takes two memory locations.
OOOOOF
EF
5. Now PC = OOOE points to the next instruction, which 000010
00
is "GOTO HERE". This is a 4-byte instruction. It 000011
FO
takes ROM addresses of OE, OF, 10, and II. After the 000012
execution of this instruction, PC = OOOOE. This keeps
the program in an infinite loop. If your PIC Trainer
has a monitor program you do not have to use the GOTO instruction, and the
program will go back to the monitor program. The fact that the program counter points at the next instruction to be executed explains why some microprocessors (notably the x86) call the program counter the instruction pointer.
ROM width in the PIC18
A microprocessor's memory that holds code is byte-addressable and under
the control of the program counter, as we have seen so far in this section. That
means that each location of the address space holds only one byte. If we have 16
address lines, it will give us 2 16 locations, which is 64K of memory space with an
address map of OOOO--FFFFH. CPUs with 8-bit data will fetch one byte at a time.
This was the case in the first IBM PC and Apple computers. To bring in more
information (code or data) into the CPU we can increase the width of the data bus
to 16 bits. That is what IBM did to the PC AT in 1984. To increase performance
even further, Intel Corporation increased the data bus width to 32 bits for the 386
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
77
and 64 bits for the Pentium. In a sense, the data bus is like traffic lanes on the highway where each lane is 8 bits wide. The more lanes, the more information we can
bring into the CPU for processing. For the PICI8, the internal data bus between
the code ROM and the CPU is 16 bits, as shown in Figure 2-12. Therefore, the 64K
ROM space is shown as 32K x 16 using a 16-bit word data size. The same rule
applies to the entire program address space of PIC 18, which is 2M, organized as
1M x 16. The widening of the data path between the program ROM and the CPU
is another way in which the PIC designers increased the processing power of the
PIC 18 family. Another reason to make the code ROM 16 bits wide is to match it
with the instruction width of the PIC 18 because the vast majority of the instructions are 2-byte instructions. This way, the CPU brings in an instruction from
ROM everytime it makes a trip to the program ROM. That will make instruction
fetch a single cycle, as we will see in the next chapter when instruction timing is
discussed.
+--2·Byte_
I·Byte
OOOOOOh
.
Byte
0OOOOOh
000002h
000004h
16·bit
~
Organized as
•
~i-'
• i-'
•
Ao CODE
Ao
PIC
CPU
1FFFFDh
1FFFFEh
1FFFFFh
B·blt
Low
Byte
000001 h
000003 h
000005 h
000001h
000002h
.~
High
ROM
>
~
Aj9 0 15
A19
D15
lFFFFB h
lFFFFDh
lFFFFFh
1FFFFAh
1FFFFCh
1FFFFEh
Do
<
16·blt Wide ROM
Figure 2-12, Program ROM Width for the PIe18
The PICI8 designers have made all instructions either 2-byte or 4-byte;
there are no I-byte or 3-byte instructions, as is the case with the x86 and 8051
chips. This is part of the RlSC architectural philosophy, which we will study in the
next section. It must be noted that not all the program ROMs in the PIC microcontrollers have 16-bit width. The PIC 16 ROM width is 14-bit, while the PIC 12
has a 12-bit width. It must also be noted that the data memory SRAM for the file
register in the PTC microcontroller is 8-bit, and just like program ROM, it is byte
addressable.
78
Do
WORD
ADDRESS
HIGH
LOW
BYTE
BYTE
OOOOOOh
0OOOO2h
0OOOO4h
0OOOO6h
0OOOO8h
OOOOOAh
OOOOOCh
OOOOOEh
0OOO10h
OEh
OFh
OFh
OFh
OFh
OFh
6Eh
EFh
OFh
25h
34h
11h
12h
1Ch
06h
10h
07h
OOh
Figure 2-13. PIC18 Program ROM Contents for Program 2-1 List File
Little endian vs. big endian war
Examine the placing of the code in the PICI8 ROM, shown in Figure 2-13.
The low byte goes to the low memory location and the high byte goes to the high
memory address. This convention is called little endian to contrast it with big endian. The origin ofthe terms big endian and little endian is from a Gulliver's Travels
story about how an egg should be opened: from the big end or the little end. In the
big endian method, the high byte goes to the low address, whereas in the little
endian method, the high byte goes to the high address and the low byte to the low
address. All Intel microprocessors and many microcomputers, notably the Digital
VAX, use the little endian convention. Freescale (Motorola) microprocessors (used
in the Macintosh), along with some mainframes, use big endian. The difference
might seem as trivial as whether to break an egg from the big end or the little end,
but it is a nuisance in converting software from one camp to be run on a computer of the other camp. Some microprocessors, such as the PowerPC from
IBMlFreescale (Motorola), let the software designer choose little endian or big
endian convention.
Harvard architecture in the PIC
Every microprocessor must have memory space to store program (code)
and data. As we have seen so far, the PIC is no exception with its code ROM space
and data RAM (file register) space. While code provides instructions to the CPU,
the data provides the information to be processed. The CPU uses buses (wire
traces) to access the code ROM and data RAM memory spaces. The early computers used the same bus for accessing both the code and data. Such an architecture is commonly referred to as von Neumann (Princeton) architecture. That
means for von Neumann computers, the process of accessing the code or data
could cause them to get in each other's way and slow down the processing speed
of the CPU, because each had to wait for the other to finish fetching. To speed up
the process of program execution, some CPUs use what is called Harvard architecture. In Harvard architecture, we have separate buses for the code and data
memory. That means that we need four sets of buses: (I) a set of data buses for
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
79
carrying data into and out of the CPU, (2) a set of address buses for accessing the
data, (3) a set of data buses for carrying code into the CPU, and (4) an address bus
for accessing the code. See Figure 2-14. This is easy to implement inside an IC
chip such as a microcontroller where both ROM code and data RAM are internal
(on-chip) and distances are on the micron and millimeter scale. But to implement
Harvard architecture for systems such as x86 IBM PC-type computers is very
expensive because the RAM and ROM that hold code and data are external to the
CPU. Separate wire traces for data and code on the motherboard will make the
board large and expensive. For example, for a Pentium microprocessor with a 64bit data bus and a 32-bit address bus we will need about 100 wire traces on the
mother board if it is von Neumann architecture (96 for address and data, plus a few
others for control signals of read and write and so on). But the number of wire
traces will double to 200 if we use Harvard architecture. Harvard architecture will
also necessitate a large number of pins coming out of the microprocessor itself. For
this reason you do not see Harvard architecture implemented in the world of PCs
and workstations. This is also the reason that microcontrollers such as PIC use
Harvard architecture internally, but they still use von Neumann architecture if they
need external memory for code and data space. The von Neumann architecture was
developed at Princeton University, while the Harvard architecture was the work of
Harvard University.
An
>
A"
von Neumann Architecture
CPU
CODE
MEMORY
DATA
MEMORY
Do
<
0,
>
......... __ ...... __ ... __ ... _--_ ...... _--------------------------------------------------------S·bit
DATA RAM
(file reg)
Harvard Architecture
16-bit
An
Up to 4kbyte
(4kxS)
A"
0,
Do
An
An
CPU
<
.
A"
>
0,
.
FIgure 2-14. von Neumann vs. Harvard ArchItecture
80
>
CODE
ROM
Up to 2Mbyte
(IMxI6)
A"
Do
<
An
A"
015
<
Do
015
Do
Instruction size of the PIC18
Recall that PIC 18 program memory is byte-addressable, and the instructions are either 2-byte or 4-byte. Almost all the instructions in the PIC 18 are 2-byte
instructions. The exceptions are MOVFF, GOTO, and a few others. Next we
explore the instruction size and formation for a few of the instructions we have
used in this chapter. This should give you some insights into the instructions of the
PICI8.
MOVLW instruction formation
The MOVLW is a 2-byte (l6-bit) instruction. Of the 16 bits, the first 8 bits
are set aside for the opcode and the other 8 bits are used for the literal value of 00
to FFH. This is shown below.
10000 11110 1 kkkk 1 kkkk
o
S
k S
I
FF
ADDLW instruction formation
The ADDLW is a 2-byte (l6-bit) instruction. Of the 16 bits, the first 8 bits
are set aside for the ope ode and the other 8 bits are used for the literal value of 00
to FFH. This is shown below.
10000 11111 1 kkkk 1 kkkk 1
o
S
k
S
FF
MOVWF instruction formation
The MOVWF is a 2-byte (16-bit) instruction. Of the 16 bits, the first 8 bits
are set aside for the opcode and the other 8 bits are used for the location of the file
register in the data RAM. The LSB bit of the opcode is designated by the letter a
to signify the access from the access bank or the other bank in the 4096 location.
If a = 0, the fileReg is in the access bank. If a = 1, then we have to use bank switching, which is covered in Chapter 6. This is shown below.
101101111al ffff
o s
f
S
ffff
FF
=
a 0 : access bank is used.
a = 1 : access bank is specified by the BSR register.
See Chapter 6.
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
81
MOVFF instruction formation
The MOVFF is a 4-byte (32-bit) instruction. Of the 32 bits, the first 16 bits
are set aside for the opcode and the address of the source fileReg and the other 16
bits are used for the opcode and the address of the destination. This is shown
below.
1100 ssss ssss ssss
1111 dddd dddd dddd
o
o
::5
ts ::5 FFF
::5
td ::5 FFF
Source (ts)
Destination (td)
Notice that for both the source and destination parts of the instruction, 12
bits are used for the file register address of the PIC18. The 12 bits cover the entire
range of the addresses OOO-FFFH for the file register, which has 4096 bytes (4K)
of data RAM space. That means that MOVFF can move the contents of any location in the file register to any other location directly. This is done without going
through the WREG, as we saw in Section 2.3.
GOTO instruction formation
The GOTO is a 4-byte (32-bit) instruction. Of the 32 bits, only 12 bits are
set aside for the opcode and the rest (20 bits) are used for the target address of the
GOTO. This is shown below.
1110 1111 k7 kkk
1111 k'9 kkk kkkk
o
::5
k
::5
kkkko
kkkks
FFFFF
However, the 20-bit address gives us only I M of address space and the
PICI8 has 2M of ROM space. This is solved by making the least-significant bit
(LSB) of the GOTO instruction 0, as shown below.
.1010101
PCU
8 bit
k'9
..
.. .
k1s1 k'4
PCH
8-bit
~
.
k71 k6
21-bit Program Counter
PCl
8-bit
~
kola
..
I
Setting the LSB of the target address to zero will make sure that the target
address is an even address. As we saw in the last section, that is exactly what we
want because all the instructions are either 2-byte or 4-byte. This should also avoid
landing at the middle of an instruction.
82
Coming from other microprocessors to the PIC18
If you have a background in programming other microprocessors/microcontrollers, making the transition from these devices to the PIC 18 can be easier if
we remember some facts about the PICI8. They are:
I. The access bank section of the register of the PIC 18 with its address range of
00-7FH can be viewed as large a number of registers, except they do not have
names like other processors. We can assign any register names we want, however, as long as we are not using any of the reserved names used by SFRs,
WREG, and so on. Here is an example if we are used to the 8051 or some other
RISC processor:
RO
RI
R2
R3
EQU
EQU
EQU
EQU
o
I
2
3
Or look at the following for the x86:
BL
BH
CL
CH
DL
DH
EQU
EQU
EQU
EQU
EQU
EQU
0
I
2
4
5
6
In both of the above we can use any fileReg address of 00-7FH.
2. WREG is exactly like the accumulator in other microprocessors. It must be
involved in all the arithmetic and logic operations.
3. To move data to locations in the file register or SFR, we must first move it to
WREG. As was shown, we use the MOVLW instruction first to load the value
into the WREG and then use MOVWF to move it to a desired location in the
fileReg. In other words, no value can be moved directly to SFR or fileReg.
Review Questions
I. In the PIC 18, the program counter is
bits wide.
2. True or false. Every member of the PIC 18 family, regardless of the program
ROM size, wakes up at memory OOOOH when it is powered up.
3. At what ROM location do we store the first opcode of a PICI8 program?
4. The instruction "MOVLW 44H" is a _ _-byte instruction.
5. What is the ROM address space for the PIC18F458?
6. The instruction "GOTO 1 abe 1" is a _ _-byte instrnction.
7. True or false. All the instructions in the PIC 18 are 2- or 4-byte instructions.
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
83
SECTION 2.9: RISC ARCHITECTURE IN THE PIC
There are three ways available to microprocessor designers to increase the
processing power of the CPU:
I. Increase the clock frequency of the chip. One drawback of this method is that
the higher the frequency, the more power and heat dissipation. Power and heat
dissipation is especially a problem for hand-held devices.
2. Use Harvard architecture by increasing the number of buses to bring more
information (code and data) into the CPU to be processed. While in the case of
x86 and other general purpose microprocessors this architecture is very expensive and unrealistic, in today's microcontrollers this is not a problem. As we
saw in the last section, the PIC 18 has Harvard architecture.
3. Change the internal architecture of the CPU and use what is called RISC architecture.
Microchip used all three methods to increase the processing power of the
PICI8 microcontrollers. In this section we discuss the merits ofRISC architecture
and examine how the PIC 18 microcontrollers have adapted it.
RISC architecture
In the early 1980s, a controversy broke out in the computer design community, but unlike most controversies, it did not go away. Since the 1960s, in all
mainframes and minicomputers, designers put as many instructions as they could
think of into the CPU. Some of these instructions performed complex tasks. An
example is adding data memory locations and storing the sum into memory.
Naturally, microprocessor designers followed the lead of minicomputer and mainframe designers. Because these microprocessors used such a large number of
instructions and many of them performed highly complex activities, they came to
be known as CISC (complex instruction set computer). According to several studies in the I 970s, many of these complex instructions etched into the brain of the
CPU were never used by programmers and compilers. The huge cost of implementing a large number of instructions (some of them complex) into the microprocessor, plus the fact that a good portion of the transistors on the chip are used
by the instruction decoder, made some designers think of simplifying and reducing the number of instructions. As this concept developed, the resulting processors
came to be known as RISC (reduced instruction set computer).
Features of RISC
The following are some of the features of RISC as implemented by the
PIC 18 microcontroller.
Feature 1
RISC processors have a fixed instruction size. In a CISC microcontroller
such as the 8051, instructions can be 1,2, or even 3 bytes. For example, look at
84
the following instructions in the 8051:
CLR C
;Clear Carry flag
,a I-byte instruction
ADD Accumulator, #mybyte
;a 2-byte instruction
LJMP target_address
;a 3-byte instruction
This variable instruction size makes the task of the instruction decoder very
difficult because the size of the incoming instruction is never known. In a RISC
architecture, the size of all instructions is fixed. Therefore, the CPU can decode the
instructions quickly. This is like a bricklayer working with bricks of the same size
as opposed to using bricks of variable sizes. Of course, it is much more efficient
to use bricks of the same size. In the last section we saw how the PIC 18 uses 2byte instructions with very few 4-byte instructions.
Feature 2
One of the major characteristics of RISC architecture is a large number of
registers. All RISC architectures have at least 32 registers. Of these 32 registers,
only a few are assigned to a dedicated function. One advantage of a large number
of registers is that it avoids the need for a large stack to store parameters. Although
a stack can be implemented on a RISC processor, it is not as essential as in CISC
because so many registers are available. In the PIC microcontrollers the use of a
256-byte bank for the file register satisfies this RISC feature. The stack for the
PIC 18 is covered in the next chapter.
Feature 3
RISC processors have a small instruction set. RISC processors have only
the basic instructions such as ADD, SUB, MUL, LOAD, STORE, AND, OR,
EXOR, CALL, JUMP, and so on. The limited number of instructions is one of the
criticisms leveled at the RISC processor because it makes the job of Assembly language programmers much more tedious and difficult compared to CISC Assembly
language programming. This is one reason that RISC is used more commonly in
high-level language environments such as the C programming language rather
than Assembly language environments. It is interesting to note that some defenders of CISC have called it "complete instruction set computer" instead of "complex instruction set computer" because it has a complete set of every kind of
instruction. How many of these instructions are used and how often is another matter. The limited number of instructions in RISC leads to programs that are large.
Although these programs can use more memory, this is not a problem because
memory is cheap. Before the advent of semiconductor memory in the 1960s, however, CISC designers had to pack as much action as possible into a single instruction to get the maximum bang for their buck. In the PIC 16 we have around 35
instructions, while the PICI8 has 75 instructions. We will examine more of the
instruction set for the PIC 18 in future chapters.
Feature 4
At this point, one might ask, with all the difficulties associated with RISC
programming, what is the gain? The most important characteristic of the RISC
processor is that more than 95% of instructions are executed with only one clock
cycle, in contrast to CISC instructions. Even some of the 5% of the RISC instrucCHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
85
tions that are executed with two clock cycles can be executed with one clock cycle
by juggling instructions around (code scheduling). Code scheduling is most often
the job of the compiler. We will examine the instruction cycle time and pipelining
of the PICI8 in Chapter 3.
Feature 5
RISC processors have separate buses for data and code. In all the x86
processors, like all other CISC computers, there is one set of buses for the address
(e.g., AO-A24 in the 80286) and another set of buses for data (e.g., DO-DIS in the
80286) carrying opcodes and operands in and out of the CPU. To access any section of memory, regardless of whether it contains code or data operands, the same
address bus and data bus are used. In RlSC processors, there are four sets of buses:
(I) a set of data buses for carrying data (operands) in and out of the CPU, (2) a set
of address buses for accessing the data, (3) a set of buses to carry the opcodes, and
(4) a set of address buses to access the opcodes. The use of separate buses for code
and data operands is commonly referred to as Harvard architecture. In the last section we examined the Harvard architecture of the PIC 18.
Feature 6
Because CISC has such a large number of instructions, each with so many
different addressing modes, microinstructions (microcode) are used to implement
them. The implementation of microinstructions inside the CPU takes more than
40-60% of transistors in many CISC processors. In the case of RlSC, however,
due to thc small set of instructions, they are implemented using the hardwire
method. Hardwiring of RISC instructions takes no more than 10% of the transistors.
Feature 7
RISC uses load/store architecture. In CISC microprocessors, data can be
manipulated while it is still in memory. For example, in instructions such as "ADD
Reg, Memory", the microprocessor must bring the contents of the external memory location into the CPU, add it to the contents of the register, then move the
result back to the external memory location. The problem is there might be a delay
in accessing the data from external memory. Then the whole process would be
stalled, preventing other instructions from proceeding in the pipeline. In RISC,
designers did away with these kinds of instructions. In RISC, instructions can only
load from external memory into registers or store registers into external memory
locations. There is no direct way of doing arithmetic and logic operations between
a register and the contents of external memory locations. All these instructions
must be performed by first bringing both operands into the registers inside the
CPU, then performing the arithmetic or logic operation, and then sending the result
back to memory. This idea was first implemented by the Cray I supercomputer in
1976 and is commonly referred to as load/store architecture. In the last section, we
saw that the arithmetic and logic operations are between the fileReg (an internal
memory) and WREG, but none involve a ROM location and a fileReg location. For
example, there is no "ADDW ROM-Loc" instruction in PICI8.
86
In concluding this discussion of RISC processors, it is interesting to note
that RISC technology was explored by the scientists in IBM in the mid-1970s, but
it was David Patterson of the University of California at Berkeley who in 1980
brought the merits ofRISC concepts to the attention of computer scientists. It must
also be noted that in recent years CISC processors such as the Pentium have used
some of the RISC features in their design. This was the only way they could
enhance the processing power of the x86 processors and stay competitive. Of
course, they had to use lots of transistors to do the job, because they had to deal
with all the CISC instructions of the 8086/286/386 processors and the legacy software of DOS.
Review Questions
I. What do RISC and CISC stand for?
2. True or false. The CISC architecture executes the vast majority of its instructions in 2, 3, or more clock cycles, while RISC executes them in one clock.
3. RISC processors normally have a _ _ (large, small) number of general-purpose registers.
4. True or false. Instructions such as "ADD WREG, ROMmemory" do not exist
in RISC microcontrollers such as the PIC 18.
5. How many instructions does the PICI8 have? Does it qualify as RISC?
6. True or false. While CISC instructions are of variable sizes, RISC instructions
are all the same size.
7. Which of the following operations do not exist for the ADD instruction in
RISC?
(a) register to register (b) immediate to register (c) memory to memory
8. True or false. Harvard architecture uses the same address and data buses to
fetch both code and data.
SECTION 2.10: VIEWING REGISTER AND MEMORY WITH
MPLAB SIMULATOR
The PIC microcontroller has one of the best tools and support systems,
many of them free or inexpensive. MPLAB is an assembler, linker, and simulator
provided for free by Microchip Corporation and can be downloaded from the
www.microchip.com web site. See http://www.MicroDigitalEd.com for tutorials
on how to use the MPLAB assembler and simulators.
Many assemblers and C compilers come with a simulator. Simulators allow
us to view the contents of registers and memory after executing each instruction
(single-stepping). It is strongly recommended to use a simulator to single-step
some of the programs in this chapter and future chapters. Single-stepping a program with a simulator gives us a deeper understanding of microcontroller architecture, in addition to the fact that we can use it to find the nature of error in our
programs. Figures 2-15 through 2-17 show screen-shots for PIC simulators from
MPLAB.
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
87
OF8l
OF82
OF83
OFS4
OF89
OF8A
OF8B
OF8C
OF8D
OF92
OF93
OF94
OF95
OF96
OF9D
OF9E
OF9F
OFAO
OFAl
OFA2
PORTE
PORTC
PORTD
PORTE
LATA
LATB
LATC
LATD
LATE
TRISA
TRISB
TRISC
TRISD
TRISE
PIEl
PIRl
IPRl
PIE2
PIR2
IPR2
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00
00
00
00
00
00
00
00
00
00
00
00
Figure 2-15. SFR Window in MPLAB Simulator
0000
0010
0020
0030
00"10
0050
0060
9E 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00
00
00
00
00
00
00
00 00
00 00
00 00
00 00
00 00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
....... .
....... .
........
....... .
....... .
........
Figure 2-16. File Register (Data RAM) Window in MPLAB Simulator
ax25,
3
4
5
6
0006
0008
OOOA
7
oooe
OEaO
MOVLlJ 0
OF03
ADDLhl Ox3
DECF Ox2S, F, ACCESS
BNZ Ox6
MOVWF Oxfal, ACCESS
0625
ElFD
6E81
Figure 2-17. Program (Code) ROM Window in MPLAB Simulator
88
.... ..
........
....... .
........
........
....... .
""
See the following web site for a tutorial on using MPLAB:
http://www.MicroDigitaIEd.com
SUMMARY
This chapter began with an exploration of the major registers of the PIC,
including WREG, SFRs, and general-purpose data RAM, and the program counter. The use of these registers was demonstrated in the context of programming
examples. The process of creating an Assembly language program was described
from writing the source file, to assembling it, linking, and executing the program.
The PC (program counter) register always points to the next instruction to be executed. The way the PIC uses program ROM space was explored because PIC
Assembly language programmers must be aware of where programs are placed in
ROM, and how much memory is available.
An Assembly language program is composed of a series of statements that
are either instructions or pseudo-instructions, also called directives. Instructions
are translated by the assembler into machine code. Pseudo-instructions are not
translated into machine code: They direct the assembler in how to translate instructions into machine code. Some pseudo-instructions, called data directives, are used
to define data. Data is allocated in byte-size increments. The data can be in binary, hex, decimal, or ASCII formats.
Flags are useful to programmers because they indicate certain conditions,
such as carry or zero, that result from execution of instructions. The concepts of
the RISC and Harvard architectures were also explored.
The RISC architecture allows the design of much more powerful microcontrollers. It has a simple instruction set and uses of a large number of registers.
Harvard architecture allows us to bring more code and data to the CPU faster. The
use of a wider data bus in the PIC 18 allows us to fetch an instruction every cycle
because the PIC instructions are typically 2 bytes.
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
89
PROBLEMS
SECTION 2.1: THE WREG REGISTER IN THE PIC
I.
2.
3.
4.
5.
6.
7.
8.
9.
10.
II.
12.
PICI8 is a(n) _ _-bit microcontroller.
Register WREG is _ _ bits wide.
The literal value in MOVLW is
bits wide.
The largest number that can be loaded into WREG is _ _ in hex.
To load WREG with the value 65H, the pound sign is
necessary, optional, necessary) in the instruction "MOVLW #6 5H".
What is the result of the following code and where is it kept?
MOVLW
15H
ADDLW
13H
Which of the following is (are) illegal?
(b) MOVLW 50
(c) MOVLW 00
(a) MOVLW 500
(d) MOVLW 255H
(e) MOVLW 25H
(t) MOVLW F5H
(g) MOVLW mybyte, 50H
Which of the following is (are) illegal?
(a) ADDLW 300H
(b)ADDLW 50H
(c) ADDLW $500
(d) ADDLW 255H
(e) ADDLW 12H
(t) ADDLW OF5H
(g) ADDWL 25H
What is the result of the following code and where is it kept?
MOVLW 25H
ADDLW lFH
What is the result of the following code and where is it kept?
MOVLW 15H
ADDLW OEAH
The largest number that K can take for the instruction "ADDWL K" is
hex.
True or false. We have many WREG registers in the PICI8.
(not
in
SECTION 2.2: THE PIC FILE REGISTER
13. PIC data RAM consists of
(EEPROM, SRAM).
14. True or false. Data RAM in PIC is also called the file register.
IS. True or false. The SFRs are part of the file register memory space.
16. True or false. The general-purpose RAM is not part of the file register memory space.
17. True or false. All members ofPICl8 family have the same size file register.
18. If we add the SFR and general-purpose RAM sizes together we should get the
total space for the _ __
19. Find the file register size for the following PIC chips:
(a) PICl2508
(b) PICl6F84
(c) PIC I 8F8772
20. What is the difference between the EEPROM and data RAM space in the
PICI8?
21. Can we have a PIC chip with no EEPROM?
22. Can we have a PIC chip with no file register?
90
23. The access bank has
bytes space.
24. Give the address map of the SFR and GP RAM section of the access bank.
2S. What is the maximum number of banks that the PICI8 can have?
26. What is the maximum number of bytes that the PICI8 can have for the
file register?
SECTION 2.3: USING INSTRUCTIONS WITH THE DEFAULT ACCES BANK
27. What is the address range for the scratch pad section of the access bank?
28. Show a simple code to load values 30H and 97H into locations Sand 6 respectively.
29. Show a simple code to load value SSH into locations 0-8.
30. Show a simple code to load value SFH into Port B SFR.
31. True or false. We can not load literal values into the scratch pad area directly.
32. True or false. The "ADDWF fileReg, D" instruction involves a fileReg and
WREG.
33. In Question 32, to place the result in WREG, the D bit must be ~_.
34. In Question 32, to place the result in fileReg, the D bit must be ~_.
3S. Show a simple code to (a) load value IIH into locations O-S, and (b) add the
values together and place the result in WREG as they are added.
36. Repeat Problem 3S, except place the result in location S after the addition is
done.
37. Show a simple code to (a) load value ISH into location 7, and (b) add it to
WREG five times and place the result in WREG as the values are added.
WREG should be zero before the addition starts.
38. Repeat Problem 37, except place the result in location 7 as numbers are being
added together.
39. What is the difference between the MOVWF and MOVF instructions?
40. Write a simple code to complement the contents of location 8 and place the
result in WREG.
41. True or false. We can use MOVFF to copy data from any location to any location in the file register.
42. Write a simple code to copy data from location 8 to PORTC (a) using WREG
and (b) without using WREG.
SECTION 2.4: PIC STATUS REGISTER
-bit register.
43. The status register is a(n)
44. Which bits of the status register are used for the C and DC flag bits, respectively?
4S. Which bits of the status register are used for the OV and N flag bits, respectively?
46. In the ADDLW instruction, when is C raised?
47. In the ADDLW instruction, when is DC raised?
48. What is the status of the C and Z flags after the following code?
MOVLW
FFH
ADDLW
1
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
91
49. Find the C flag value after each of the following codes:
(a) MOVLW 54H
(b) MOVLW 00
(c) MOVLW FFH
ADDLW OC4H
ADDLW FFH
ADDLW 05H
50. Write a simple program in which the value 55H is added 5 times.
SECTION 2.5: PIC DATA FORMAT AND DIRECTIVES
51. State the value (in hex) used for each ofthe following data:
MYDAT_1
EQU 55
MYDAT 2
EQU D'98'
MYDAT 3
EQU A'G'
EQU Ox50
MYDAT 4
MYDAT 5
EQU D'200'
MYDAT 6
EQU A'A'
MYDAT 7
EQU AAH
MYDAT 8
EQU D'255'
EQU B'10010000'
MYDAT 9
MYDAT 10 EQU B'01111110'
MYDAT 11 EQU D' 10'
MYDAT 12 EQU D'15'
52. State the value (in hex) for each of the following data:
DAT 1
EQU 22
DAT 2
EQU 56H
DAT 3
EQU B'10011001'
DAT 4
EQU D' 32'
DAT 5
EQU OxF6
DAT 6
EQU B'11111011'
53. Show a simple code to (a) load value IIH into locations 0-5, and (b) add them
together and place the result in WREG as the values are added. Use EQU to
assign the names RO-R5 to locations 0-5.
SECTION 2.6: INTRODUCTION TO PIC ASSEMBLY PROGRAMMING
and
SECTION 2.7: ASSEMBLING AND LINKING A PIC PROGRAM
54. Assembly language is a
(low, high)-level language while C is a
-::-:-_---:- (low, high)-levellanguage.
55. Of C and Assembly language, which is more efficient in terms of code generation (i.e., the amount of ROM space it uses)?
56. Which program produces the 0 file?
57. True or false. The source file has the extension "asm".
58. Which file provides the listing of error messages?
59. True or false. The source code file can be a non-ASCII file.
60. True or false. Every source file must have ORG and END directives.
61. Do the ORG and END directives produce opcodes?
62. Why are the ORG and END directives also called pseudocode?
63. True or false. The ORG and END directives appear in the" .1st" file.
92
64.
65.
66.
67.
True or false. The linker produces the file with the extension "asm".
True or false. The linker produces the file with the extension "hex".
The file with the
extension is downloaded into PIC ROM.
Give three file extensions produced by MPLAB.
SECTION 2.8: THE PROGRAM COUNTER AND PROGRAM ROM SPACE IN
THE PIC
68. Every PICl8 family member wakes up at address _ _ when it is powered
up.
69. A programmer puts the first opcode at address 100H. What happens when the
microcontroller is powered up?
70. Find the number of bytes each of the following instructions takes:
(a) MOVLW 5H
(b) MOVLW 9FH
(c) ADDLW 50H
(d)ADDLW 0
(e) MOVLW Ox41 (f)MOVLW 20
(g) ADDLW d' 200 '
(h) GOTO
71. Write a program to (a) place each of your 5-digit ID numbers into a RAM locations starting at address 0, (b) add each digit to WREG and store the sum in
RAM location 6, and (c) use the program listing and show the ROM memory
addresses and their contents.
72. Use the program listing of your choice and show the ROM memory addresses
and their contents.
73. Find the address of the last location of on-chip program ROM for each of the
following:
(a) PIC with 48 KB
(b) PIC with 96 KB
(c) PIC with 64 KB
(d) PIC with 16 KB
(f) PIC with 128 KB
74. Show the lowest and highest values (in hex) that the PIC 18 program counter
can take.
75. A given PIC has 7FFFH as the address of the last location of its on-chip ROM.
What is the size of on-chip ROM for this PIC?
76. Repeat Question 75 for 3FFH.
77. Find the on-chip program ROM size in K for the PICI8 with the following
address ranges:
(a) 0000--1 FFF
(b) 0000-3FFF
(d) OOOO--BFFF
(c) 0000--5FFF
(f) 00000--1 FFFF
(e) OOOO--FFFF
(h) 00000--3 FFFF
(g) 00000--2FFFF
78. Find the on-chip program ROM size in K for the PICI8 with the following
address ranges:
(a) 00000--4FFFF
(b) 00000-3FFFF
(c) 00000--5 FFFF
(d) 00000--7FFFF
(e) OOOOO--BFFFF
(f) OOOOO-FFFFF
(g) 00000--17FFFF
(h) OOOOO--IFFFFF
Some of the above might not be in production yet.
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
93
79. How wide is the ROM in the PICI8 chip?
80. How wide is the data bus between the CPU and the program ROM in PICI8?
81. Show the even and odd address designation for 4K x 16. See Figure 2-11.
82. In Question 81, what is the ROM size in K?
83. Show the even and odd address designation for 16K x 16. See Figure 2-11.
84. In Question 83, what is the ROM size in K?
85. Explain Harvard architecture and how it makes processing of code and data
faster.
86. What is the drawback of using Harvard architecture for memories external to
the CPU?
87. In instruction "MOVLW K" explain why the K value cannot be larger than 255
decimal.
88. In instruction "ADDLW K" explain why the K value cannot be larger than 255
decimal.
89. In "MOVWF file Reg", explain what the size of the instruction is and how it
allows one to cover the entire range of the file register in PIC 18.
90. In "MOVFF source, dest", explain what the size of the instruction is and how
it allows one to cover the entire range of the file register in PIC 18.
91. In the instruction "GOTO target-addr" explain why the lowest bit of the program counter is O.
92. Explain why the instruction "GOTO target-addr" will not land at an odd
address.
93. In Question 92, explain why it should not.
94. Explain how the instruction "GOTO target-addr" is able to cover the entire 2M
address space of the PICI8.
SECTION 2.9. RISC ARCHITECTURE IN THE PIC
95. What do RISC and CISC stand for?
(RISC, CISC) architecture we can have 1-,2-,3-, or 4-byte instruc96. In
tions.
(RISC, CISC) architecture instructions are fixed in size.
97. In
98. In
(RISC, CISC) architecture instructions are mostly executed in one
or two cycles.
99. In
(RISC, CISC) architecture we can have an instruction to ADD a register to external memory.
100. True or false. Most instructions in CISC are executed in one or two cycles.
ANSWERS TO REVIEW QUESTIONS
SECTION 2.1: THE WREG REGISTER IN THE PIC
I.
2.
3.
4.
5.
94
MOVLW Ox34
MOVLW Ox16
ADDLW OxeD
False
FF hex and 255 in decimal
8
SECTION 2.2: THE PIC FILE REGISTER
I.
2.
3.
4.
5.
6.
7.
True
File register
True
True
8
256
4096
SECTION 2.3: USING INSTRUCTIONS WITH THE DEFAULT ACCESS BANK
I.
2.
3.
4.
5.
True
MOVLW
MOVWF
MOVLW
ADDWF
True
FF,255
WREG
Ox16
0
OxFD
0, F
SECTION 2.4: PIC STATUS REGISTER
I.
2.
3.
4.
Status register
8 bits
D5, D6, and D7
binary
1001 1111
+ 0110 0001
10000 0000
Hex
9F
+ il
100
This leads to C
~
I, DC
~
I, and Z
~
I.
+ II
A4
+
binary
1000 0010
0010 0010
1010 0100
This leads to C
~
0, DC
~
0, and Z
~
O.
Hex
67
99
+
100
binary
0110 0111
+ 1001 1001
10000 0000
This leads to C
~
I, DC
~
I, and Z
~
I.
5.
Hex
82
6.
SECTION 2.5: PIC DATA FORMAT AND DIRECTIVES
I.
2.
3.
4.
5.
6.
7.
DATAl EQU 9FH
DATA2 EQU Ox9F
DATA3 EQU H'9FI
DATAl EQU 99H
DATA2 EQU D'99'
DATA3 EQU B' 10011001'
If the value is to be changed later, it can be done once in one place instead of at every occurrence.
(a) 34H
(b) IFH
WREG~ 15H
value of location Ox20 ~ (Ox95)
OCH + I OH ~ I CH will be in tileReg location 63H
CHAPTER 2: PIC ARCHITECTURE & ASSEMBLY LANGUAGE
95
SECTION 2.6: INTRODUCTION TO PIC ASSEMBLY PROGRAMMING
I.
2.
3.
4.
5.
6.
7.
The real work is performed by instructions such as MOV and ADD. Pseudo-instructions, also
called assembly directives, instruct the assembler in doing its job.
The instruction mnemonics, pseudo-instructions
False
All except (c)
Assembler directives
True
(c)
SECTION 2.7: ASSEMBLING AND LINKING A PIC PROGRAM
I.
2.
3.
4.
5.
True
True
(a)
(b) through (e)
(d) and (e)
SECTION 2.8: THE PROGRAM COUNTER AND PROGRAM ROM SPACE IN THE PIC
I.
2.
3.
4.
5.
6.
7.
21
True
OOOOH
2
With 32K, we have 32768 (32 x I 024
4
True
~
32768) bytes, and the ROM space is 0000 to 7FFFH.
SECTION 2.9: RISC ARCHITECTURE IN THE PIC
1.
2.
3.
4.
5.
6.
7.
8.
96
else stands for complex instruction set computer; RiSe is reduced instruction set computer.
True
Small
True
75, yes
True
(c)
False
CHAPTER 3
BRANCH, CALL, AND
TIME DELAY LOOP
OBJECTIVES
Upon completion of this chapter, you will be able to:
»
»
»
»
»
»
»
»
»
»
Code PIC Assembly language instructions to create loops
Code PIC Assembly language conditional branch instructions
Explain conditions that determine each conditional branch instruction
Code GOTO (long jump) instructions for unconditional jumps
Calculate target addresses for conditional branch instructions
Code PIC subroutines
Describe the stack and its use in subroutines
Discuss pipelining in the PIC
Discuss crystal frequency versus instruction cycle time in the PIC
Code PIC programs to generate a time delay
97
In the sequence of instructions to be executed, it is often necessary to transfer program control to a different location. There are many instructions in PIC to
achieve this. This chapter covers the control transfer instructions available in PIC
Assembly language. In Section 3.1, we discuss instructions used for looping, as
well as instructions for conditional and unconditional branches (jumps). In the second section, we examine the stack and the CALL instruction. In Section 3.3,
instruction pipelining of the PICI8 is examined. Instruction timing and time delay
subroutines are also discussed in Section 3.3.
SECTION 3.1: BRANCH INSTRUCTIONS AND LOOPING
In this section we first discuss how to perform a looping action in PIC and
then the branch (jump) instructions, both conditional and unconditional.
Looping in PIC
Repeating a sequence of instructions or an operation a certain number of
times is called a loop. The loop is one of most widely used programming techniques. In the PIC, there are several ways to repeat an operation many times. One
way is to repeat the operation over and over until it is finished, as shown below:
MOVLW
ADDLW
ADDLW
ADDLW
ADDLW
ADDLW
0
3
3
3
3
3
;WREG
=
0
iadd value 3 to WREG
;add
;add
;add
;add
value
value
value
value
3
3
3
3
to
to
to
to
WREG(W
WREG(W
WREG(W
WREG(W
6)
9)
OCh)
OFh
In the above program, we add 3 to WREG 5 times. That makes 5 x 3 = 15
= OFh. One problem with the above program is that too much code space would
be needed to increase the number of repetitions to 50 or 100. A much better way
is to use a loop. There are two ways to do a loop in PIC. Next, we describe each
method.
DECFSZ instruction and looping
The DECFSZ (decrement file Reg skip zero) instruction is a widely used
instruction supported across all PIC families of microcontrollers from PIC 12 to
PIC 18. It has the following format:
DECFSZ fileReg, d ;decrement fileReg and skip next instruction if 0
In this instruction, the fileReg is decremented, and if its content is zero, it
skips the next instruction. By placing the "GOTO target" instruction right below it
we can create a loop. The target address of the "GOTO target" instruction is the
beginning of the loop, as shown in Examples 3-1 and 3-2. Figure 3-1 shows the
flowchart for the DECFSZ instruction. Study the flowchart structure in Appendix
D to get familiar with the symbols. The flowchart is a widely used method to represent a sequence of actions pictorially. Its usage for program design is recommended very strongly.
98
INSTRUCTIONS
ADD3TOWREG
AGAIN
ADDLW3
DECFSZ COUNT
SKIP THE
NEXT
INSTRUCTION
GOTOAGAIN
MOVWFPORTB
MOVE DATA
Figure 3-1. Flowchart for the DECFSZ Instruction
Example 3-1
Write a program to (a) clear WREG, and (b) add 3 to WREG ten times and place the result in
SFR of PORTB. Use the DECFSZ instruction to perform looping.
Solution:
ithis program adds value 3 to WREG ten times
COUNT
EQU Ox25
AGAIN
MOVLW
MOVWF
MOVLW
ADDLW
DECFSZ
GOTO
MOVWF
illse
d'lO
I
COUNT
0
3
COUNT,F
AGAIN
PORTB
loc 25H for counter
;WREG = 10 (decimal) for counter
; load the counter
;WREG = 0
jadd 03 to WREG (WREG = sum)
; decrement counter, skip i f count
irepeat until count becomes 0
i send sum to PORTB SFR
=
0
Notice that the DECFSZ instruction will decrement the counter (fileReg loc Ox25),
which has 10 in it. It becomes 9. Because it is not zero, it will execute the "GOTO
AGAIN" instruction. The "GOTO AGAIN" goes back to the start of the loop. Next, it
decrements, our counter becomes 8, and, because it is not zero, it executes the GOTO.
It goes on like that until the counter becomes zero. Upon the counter becoming zero,
it skips the GOTO, which gets it out of the loop, and executes the "MOVWF PORTB"
instruction. Notice that we use "DECFSZ COUNT, F" and not "DECFSZ COUNT,
W" because we want the count value to change for the next iteration. We will never get
out of the loop if we use ''DECFSZ COUNT, W" because COUNT = 9 and the decrement value is placed in WREG
CHAPTER 3: BRANCH, CALL, AND TIME DELAY LOOP
99
Using instruction 8HZ for looping
The BNZ (branch if not zero) instruction is supported by the PICI8 family and not earlier families such as PICI6 or PICI2. It uses the zero flag in the status register. The BNZ instruction is used as follows:
BACK
DECF
BNZ BACK
;start of the loop
;body of the loop
;body of the loop
;decrement fileReg, Z = 1 if fileReg = 0
;branch to BACK if Z = 0
In the last two instructions, the fileReg is decremented; if it is not zero, it
branches (jumps) back to the target address referred to by the label. Prior to the
start of the loop, the fileReg is loaded with the counter value for the number of repetitions. Notice that the BNZ instruction refers to the Z flag of the status register
affected by the previous instruction, DECF. This is shown in Example 3-2.
In the program in Example 3-2, fileReg location Ox25 is used as a counter.
The counter is first set to 10. In each iteration, the DEC instruction decrements the
fileReg and sets the flag bits accordingly. If fileReg is not zero (Z "# 0), it jumps to
the target address associated with the label "AGAIN". This looping action continues until fileReg COUNT becomes zero. After fileReg COUNT becomes zero (Z
= 0), it falls through the loop and executes the instruction immediately below it, in
this case "MOVWF PORTB". See Figure 3-2.
Notice, in the "DECF COUNT, F" instruction, that fileReg 25H is used
as a register to hold the count as it decrements instead ofWREG. IfWREG is used
as the destination of the DECF instruction, then you have an infinite loop because
COUNT remains at its original value of 10.
Example 3-2
Write a program to (a) clear WREG, then (b) add 3 to WREG ten times.
Use the zero flag and BNZ.
Solution:
;this program adds value 3 to the WREG ten times
COUNT EQU Ox25
MOVLW d'10'
MOVWF COUNT
MOVLW 0
AGAIN ADDLW 3
DECF COUNT, F
BNZ AGAIN
MOVWF PORTB
100
;use loc 25H for counter
;WREG = 10 (decimal) for counter
;load the counter
;WREG = 0
;add 03 to WREG (WREG
sum)
;decrernent counter
;repeat until COUNT = 0
;send sum to PORTB SFR
INSTRUCTIONS
MOVLWD'10'
LOAD COUNTER
MOVWFCOUNT
INTO LOCATION Ox25
MOVLWO
CLEARWREG
ADD VALUE
DECREMENT COUNTER
AGAIN
ADDLW 3
DECF COUNT, F
BNZAGAIN
YES
PLACE RESULT ON PINS
MOVWFPORTB
Figure 3-2. Flowchart for Example 3-2
Example 3-3
What is the maximum number of times that the loop in Example 3-2 can be repeated?
Solution:
Because location COUNT in fileReg is an 8-bit register, it can hold a maximum of
FFH (255 decimal); therefore, the loop can be repeated a maximum of 255 times. See
Example 3-4 to bypass this limitation.
CHAPTER 3: BRANCH, CALL, AND TIME DELAY LOOP
101
Loop inside a loop
As shown in Example 3-2, the maximum count is 255. What happens if we
want to repeat an action more times than 255? To do that, we use a loop inside a
loop, which is called a nested loop. In a nested loop, we use two registers to hold
the count. See Example 3-4.
Example 3-4
Write a program to (a) load the PORTB SFR register with the value 55H, and (b) complement Port B 700 times.
Solution:
Because 700 is larger than 255 (the maximum capacity of any register), we use two registers to hold the count. The following code shows how to use fileReg locations 25H and
26H as a register for counters.
Rl EQU Ox25
R2 EQU Ox26
COUNT 1 EQU
COUNT 2 EQU
MOVLW Ox55
MOVWF PORTB
MOVLW COUNT
MOVWF Rl
LOP 1 MOVLW COUNT
MOVWF R2
LOP 2 COMPF PORTB,
DECF R2, F
BNZ LOP 2
DECF Rl, F
BNZ LOP 1
d'lO'
d' 70
1
2
F
r
;WREG = 55h
; PORTB = 55h
iWREG = 10, outer loop count value
;load 10 into lac 25H (outer loop count)
;WREG = 70, inner loop count value
;load 70 into lac 26H
;complement Port B SFR
;dec fileReg lac 26 (inner loop)
irepeat it 70 times
;dec fileReg lac 25 (outer loop)
irepeat it 10 times
In this program, fileReg location Ox26 is used to keep the inner loop count. In the
instruction "BNZ LOP_ 2", whenever location 26H becomes 0 it falls through and
"DECF Rl, F" is executed. This instruction forces the CPU to load the inner count
with 70 if it is not zero, and the inner loop starts again. This process will continue
until location 25 becomes zero and the outer loop is finished.
MEMORY
LOCATION
25
26
102
VALUE
10
70
R1
R2
INSTRUCTIONS
LOADWREG
MOVLWOx55
LOAD PORTB
MOVWF PORTB
LOADWREG
MOVLW COUNT_1
LOAD COUNTER 1
LOADWREG
LOAD COUNTER 2
MOVWFR1
MOVLW COUNT_2
MOVWF R1
COMPF PORTB, F
DECF R2, F
NO
BNZ LOP_2
DECFR1,F
NO
BNZ LOP_1
YES
END
Figure 3-3. Flowchart for Example 3-4
CHAPTER 3: BRANCH, CALL, AND TIME DELAY LOOP
103
Looping 100,000 times
Because two registers give us a maximum value of 65025 (255 x 255 =
65025), we can use three registers to get up to more than 16 million (224) iterations.
The following code repeats an action 100,000 times:
;assign RAM lac for the Rl-R2
Rl EQU Oxl
R2 EQU Ox2
R2 EQU Ox3
COUNT_l EQU D'lOO'
COUNT_2 EQU D'lOO'
COUNT 3 EQU D'lO'
MOVLW
MOVWF
MOVLW
MOVWF
LOP 3 MOVLW
MOVWF
LOP 2 MOVLW
MOVWF
LOP 1 COMPF
DECF
BNZ
DECF
BNZ
DECF
BNZ
Ox55
PORTB
COUNT
R3
COUNT
R2
COUNT
Rl
PORTB,
Rl ,F
LOP 1
R2, F
LOP_2
R3, F
LOP 3
ifixed value for 100,000 times
3
2
1
F
Other conditional jumps
Table 3-1: PIC Conditional
Conditional branches for the PIC are
summarized in Table 3-1. More details of
each instruction are provided in Appendix A.
In Table 3-1, notice that some of the instructions, such as BZ (Branch if Z = 1) and BC
(Branch if C = 1), jump only if a certain condition is met. Next, we examine some conditional branch instructions with examples.
BZ (Branch if Z
= 1)
Branch (Jump) Instructions
Instruction
BC
BNC
BZ
BNZ
BN
BNN
BOV
BNOV
In this instruction, the Z flag is
checked. If it is high, it jumps to the target
address. For example, look at the following code.
OVER
MOVF PORTB,W
JZ OVER
Action
Branch if C - 1
Branch if C 0
Branch if Z = 1
Branch if Z 0
Branch ifN = I
Branch ifN 0
Branch if OV = 1
Branch if OV 0
*
*
*
*
;read Port B and put it in WREG
;jump if WREG is zero
In this program, if PORTB is zero, it jumps to the label OVER. It stays
there until PORTB has a value other than zero. Notice that the BZ instruction can
be used to see whether any fileReg or WREG is zero. More importantly, you don't
have to perform an arithmetic instruction such as decrement to use the BZ instruction. See Example 3-5.
104
Example 3-5
Write a program to determine if fileReg location Ox30 contains the value O. If so, put
55H in it.
Solution:
MYLOC
MOVF
BNZ
MOVLW
MOVWF
EQU Ox30
MYLOC,F
NEXT
Ox55
MYLOC
;copy MYLOC to itself
;branch if MYLOC is not zero
;put Ox55 if MYLOC has zero value
NEXT
SHC (branch if no carry, branch if CY
=0)
In this instruction, the carry flag bit in the Status register is used to make
the decision whether to jump. In executing "BNe 1 abe 1", the processor looks at
the carry flag to see if it is raised (C = I). If it is not, the CPU starts to fetch and
execute instructions from the address of the label. If C = I, it will not branch but
will execute the next instruction below BNC. Study Example 3-6 to see how BNC
is used to add numbers together when the sum is higher than FFH. Note that there
Example 3-6
Find the sum ofthe values 79H, F5H, and E2H. Put the sum in fileReg locations 5 (low
byte) and 6 (high byte).
Solution:
L_Byte EQU Ox5
H_Byte EQU Ox6
N 1
N 2
OVER
;assign RAM lac 5 to L_byte of sum
;assign RAM loc 6 to H_byte of sum
ORG Oh
MOVLW OxO
MOVWF H_Byte
ADDLW Ox79
BNC
N 1
INCF H_Byte,F
ADDLW OxF5
BNC
N 2
INCF H_Byte,F
ADDLW OxE2
BNC
OVER
INCF H_Byte,F
MOVWF L_Byte
END
;clear WREG(WREG = 0)
;H_Byte = 0
;WREG = 0 + 79H = 79H, C = 0
i i f C = 0, add next number
;C = 1, increment (now H_Byte
;WREG = 79 + F5 = 6E and C = 1
; branch i f CY = 0
;C = 1, increment (now H_Byte =
;WREG = 6E + E2 = 50 and C = 1
; branch i f C = 0
;C = 1, increment (now H_Byte
;now L_Byte = SOH, and H_Byte
0)
1)
2)
02
MEMORY
LOCATION
4 . . . - - -.....
5
6
7
0
4
4
5
5
50
L_Byte
6
02
H_Byte
6
1
7
WREG =79H
7
WREG =6EH
WREG= 50H
CHAPTER 3: BRANCH, CALL, AND TIME DELAY LOOP
105
is also a "BC 1 abe 1" instruction. In the BC instruction, if C = I it jumps to the
target address. We will give more examples of these instructions in the context of
some applications in Chapter 5.
The other conditional branch instructions in Table 3-1 are discussed in
Chapter 5 when arithmetic operations with signed numbers are discussed.
All conditional branches are short jumps
It must be noted that all conditional jumps are short jumps, meaning that
the address of the target must be within 256 bytes of the contents of the program
counter (PC). This concept is discussed next.
Example 3-7
Using the following list file of Example 3-6, verify the jump forward address calculation.
Line PC
Opcode
Mnemonic Operand
OBJECT LINE
CODE
VALUE
SOURCE TEXT
00000005
00000006
L_Byte EQU Ox5
H_Byte EQU Ox6
LOC
000000
000000
000002
000004
000006
000008
OOOOOA
oooooc
OOOOOE
000010
000012
000014
000016
OEOO
6E06
OF79
11301
2A06
OFF5
11301
2A06
OFE2
E301
2A06
6E05
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
N 1
N 2
OVER
ORG Oh
MOVLW
MOVWF
ADDLW
BNC
INCF
ADDLW
BNC
INCF
ADDLW
BNC
INCF
MOVWF
END
OxO
H_Byte
Ox79
N 1
;assign RAM Lee 5 to L_byte of sum
;assign RAM Lec 6 to H_byte of sum
;clear WREG(WREG=O)
;H_Byte = 0
;WREG = 0 + 79H = 79H, C = 0
i i f C = 0, add next number
H_Byte,F ;C = 1, increment (now H_Byte
;WREG = 79 + FS = 6E and C = 1
OxFS
N 2
;branch if CY = 0
H_Byte,F ;C = 1, increment (now H_Byte
0)
1)
OxE2
;WREG = 6E + E2 = 50 and C = 1
OVER
;branch if C = 0
H_Byte,F iC = 1, increment (now H_Byte = 2)
L_Byte inow L_Byte = SOH, and H_Byte = 02
Solution:
First notice that the BNC instruction jumps forward. The target address for a forward
jump is calculated by adding the PC of the following instruction to the second byte of
the branch instruction times 2. Recall that each instruction takes 2 bytes. In line 6 the
instruction "BNC N_1" has an opcode of E3 and an operand of 0 I at the addresses of
000006 and 000007. The 01 x 02 = 02 is the relative address, relative to the address of
the next instruction INCF, which is 000008. By adding 000002 to 000008, the target
address of the label N_I, which is OOOOOA, is generated. In the same way for line
000011, the "BNC N_2" instruction, and line 000014, the "BNC OVER" instruction
jumps forward because the relative value is positive.
106
Calculating the short branch address
All conditional branches such as BNC, BZ, and BNZ are short branches
due to the fact that they are all 2-byte instructions. In these instructions the first
byte is the opcode and the second byte is the relative address. The target address
is relative to the value of the program counter. If the second byte is positive, the
the jump is forward. If the second byte is negative, then the jump is backwards.
The second byte can be a value from -127 to + 128. To calculate the target address,
we add the second byte of the instruction times 2 to the PC of the next instruction
[target address = (2nd byte of instruction x 2) + PC]. See Example 3-7. We do the
same thing for the backward branch, although the second byte is negative. That is,
we multiply the negative number by two and add it to the PC value of the next
instruction. See Example 3-8.
Example 3-8
Verify the calculation of backward jumps for the listing of Example 3-2, shown below.
Solution:
LOC
OBJECT LINE
CODE
VALUE
00000025
000000
000000 OEOA
000002 6E25
000004 OEOO
000006 OF03
000008 0625
OOOOOA E1FD
OOOOOC 6E81
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
SOURCE TEXT
COUNT
AGAIN
EQU Ox25
ORG Oh
MOVLW d'lO'
MOVWF COUNT
MOVLW 0
ADDLW 3
jllSe loc 25H for counter
jWREG
=
10
(decimal)
for counter
;load the counter
iWREG =
0
;add 03 to WREG (WREG
sum)
DEeF COUNT, F ;decrement counter
BNZ AGAIN
jrepeat until COUNT = 0
MOVWF PORTB
;send sum to PORTB SFR
END
In the program list, "BNZ AGAIN" has opcode El and relative address FDH. The FDH
gives us -3, which means the displacement is -3 x 2 = -6. When the relative address of
-6 is added to OOOOOCH, the address of the instruction below the byte, we have -6 +
OCH = 06H (the carry is dropped). Notice that 000006 is the address of the label
AGAIN. FDH is a negative number and that means it will branch backward. For further
discussion of the addition of negative numbers, see Chapter 5.
Although we can use BNZ along with DECF to perform a loop, it is better
to use an instruction such as DCFSNZ, because it combines the decrement and
jump into a single instruction.
CHAPTER 3: BRANCH, CALL, AND TIME DELAY LOOP
107
Unconditional branch instruction
The unconditional branch is a jump in which control is transferred unconditionally to the target location. In the Plel8 there are two unconditional branches: GOTO (go to) and BRA (branch). Deciding which one to use depends on the
target address. Each instruction is explained next.
GOTO (GOTO is a long jump)
GOTO is an unconditional jump that can go to any memory location in the
2M address space of the Plel8. It is a 4-byte (32-bit) instruction in which 12 bits
are used for the opcode, and the other 20 bits represent the 20-bit address of the
target location. The 20-bit target address allows ajump to 1M of memory locations
from 00000 to FFFFFH, instead of 2M. This problem is solved by making the lowest bit of the program counter AO = 0, and the 20-bit target address of the GOTO
becomes address bits A21-AI. In this way, the GOTO can cover the entire 2M
address space of 00000-1 FFFFH and also makes sure that the target address lands
on an even address location. Because all the Plel8 instructions are 2-byte or
4-byte instructions, the GOTO will not land at the middle of an instruction. See
Figure 3-4.
1110 1111 k7 kkk
1111 k19 kkk kkkk
o
PCU
..
8-bit
$
...
k
$
kkkko
kkkks
FFFFF
PCH
PCl
8-bit
8-bit
•
.....
. . . _ - - - - 21-bit Program Counter
Figure 3-4. GOTO Instruction
Remember that although the program counter in the Plel8 is 21-bit (thereby giving a ROM address space of 2M), not all PIe 18 family members have that
much on-chip program ROM. Some of the Plel8 family members have only
4K-32K of on-chip ROM for program space; consequently, every byte is precious.
For this reason there is also a BRA (branch) instruction, which is a 2-byte instruction as opposed to the 4-byte GOTO instruction. This can save some bytes of
memory in many applications where ROM memory space is in short supply. BRA
is discussed next.
BRA (branch)
In this 2-byte (l6-bit) instruction, the first 5 bits are the opcode and the rest
(lower II bits) is the relative address of the target location. The relative address
range of OOO-FFFH is divided into forward and backward jumps; that is, within
108
-1024 to + I 023 bytes of memory relative to the address of the current PC (program counter). If the jump is forward, then the target address is positive. If the
jump is backward, then the target address is negative. In this regard, BRA is like
the conditional branch instructions except that II bits are used for the offset
address instead of 8. This is shown in detail in Figure 3-5.
11110
I Onnn 1 nnnn
-1024
S
n S
I
nnnn
1023
Program
Counter
Range
-1024
+1023
Figure 3-5. BRA (Branch Unconditionally) Instruction Address Range
Notice that this is a 2-byte instruction, and is preferred over the GOTO
because it takes less ROM space. Chapter 5 examines signed numbers.
GOTO to itself using
$ sign
In cases where there is no monitor program, we use the GOTO (jump) to
itself in order to keep the microcontroller busy. A simple way of doing that is to
use the $ sign. That means in place of this:
HERE
GOTO
HERE
we can use the following:
GOTO$
This will also work for the BRA instruction, as shown below:
OVER
BRA OVER
which is the same as:
BRA $
;$ means same line
Review Questions
I. The mnemonic BNZ stands for - - 2. True or false. "BNZ BACK" makes its decision based on the last instruction
affecting the Z flag.
3. "BNZ HERE" is a _ -byte instruction.
4. In "JZ NEXT", which register's content is checked to see if it is zero?
5. GOTO is a(n) _ -byte instruction.
CHAPTER 3: BRANCH, CALL, AND TIME DELAY LOOP
109
SECTION 3.2: CALL INSTRUCTIONS AND STACK
Another control transfer instruction is the CALL instruction, which is used
to call a subroutine. Subroutines are often used to perform tasks that need to be
performed frequently. This makes a program more structured in addition to saving
memory space. In the PIC 18 there are two instructions for call: CALL (long call)
and RCALL (relative call). Deciding which one to use depends on the target
address. Each instruction is explained next.
CALL
In this 4-byte (32-bit) instruction, the 12 bits are used for the opcode and
the other 20 bits, A21-A I, are used for the address of the target subroutine. Just as
in the GOTO instruction, the lowest bit of the program counter is 0 automatically
to ensure it lands on an even address. Therefore, CALL can be used to call subroutines located anywhere within the 2M address space of 00000-1 FFFFH for the
PICI8, as shown in Figure 3-6.
1110 1110 k7 kkk
1111 k19 kkk kkkk
0 :::;
..1010101
PCU
8-bit
k19
~
.
k :::;
kkkko
kkkk8
FFFFF
..
PCH
PCl
8-bit - -.~. . .- - 8-bit
k151 k14
..
k71 k6
.....
. . - - - - - 21-bit Program Counter
~
Figure 3-6. CALL Instruction
To make sure that the PIC knows where to come back to after execution of
the called subroutine, the microcontroller automatically saves on the stack the
address of the instruction immediately below the CALL. When a subroutine is
called, control is transferred to that subroutine, and the processor saves the PC
(program counter) of the next on the stack and begins to fetch instructions from
the new location. After finishing execution of the subroutine, the instruction
RETURN transfers control back to the caller. Every subroutine needs RETURN as
the last instruction.
Stack and stack pointer in the PIC18
The stack is read/write memory (RAM) used by the CPU to store some
very critical information temporarily. This information usually is an address, but it
could be data as well. The CPU needs this storage area because there are only a
limited number of registers. The stack in the PIC18 is 21-bit because the program
counter is 21-bit. This means that it is used for the CALL instruction to make sure
that the PIC knows where to come back to after execution of the called subroutine.
110
A 21-bit stack can take values of 00000 to I FFFFFH, just like the program counter. If the stack is RAM, there must be a register inside the CPU to point to it. The
register used to access the stack is called the SP (stack pointer) register. The PICI8
has a 5-bit stack pointer, which can take values of 00 to I FH. That gives us a total
of 32 locations where each location is 21 bits wide. This is shown in Figure 3-7.
When the PICI8 is powered up, the SP register contains value O. This means that
stack location I is the first location used for the stack because the SP points to the
last-used location. That means that location 0 of the stack is not available and we
have only 31 stack locations in the PIC 18.
STACK
POINTER
(1 F Hex)
A20
STACK
AO
11111
Stack painter
II
increments,
as information
21-bit
Stack painter
~
decrements
as information
is popped out
of stack
is pushed into
stack
(01 Hex)
00001
..-
Top of stack (first
available stack location)
Figure 3-7. PIC Stack 31 x 21
How stacks are accessed in the PIC18
The storing of CPU information such as the program counter on the stack
is called a PUSH, and loading the contents of the stack back into a CPU register is
called a POP. In other words, a register is pushed onto the stack to save it and
popped off the stack to retrieve it. The following describes each process.
Pushing onto the stack
In the PIC, the stack pointer (SP) is pointing to the last used location of the
stack. The last-used location of the stack is referred to as the top of the stack
(TOS). As data is pushed onto the stack, the stack pointer is incremented. Notice
that this is different from many other microprocessors, notably x86 processors, in
which the SP is decremented when data is pushed onto the stack. Examining
Example 3-9, we see that as each CALL is executed, the contents of the program
counter are saved on the stack and SP is incremented. Notice that for every program counter saved on the stack, SP is incremented only once.
Popping from the stack
Popping the contents of the stack back into a given register such as the program counter is the opposite process of pushing. When the RETURN instruction
CHAPTER 3: BRANCH, CALL, AND TIME DELAY LOOP
111
at the end of the subroutine is executed, the top location of the stack is copied back
to the program counter and the stack pointer is decremented once. That means the
stack is LIFO (Last-In-First-Out) memory.
CALL instruction and the role of the stack
In the PIC, the CPU uses the stack to save the address of the instruction just
below the CALL instruction. This is how the CPU knows where to resume when
it returns from the called subroutine. To understand the importance of the stack in
microcontrollers, examine the contents of the stack and stack pointer for Example
3-9. This is shown in Example 3-10.
The following points should be noted for the program in Example 3-9:
1. Notice the DELAY subroutine. Upon executing the first "CALL DELAY", the
address of the instruction right below it, "MOVLW OxAA", is pushed onto the
stack, and the PIC starts to execute instructions at address 000300H.
2. In the DELAY subroutine, first the counter MYREG is set to 255 (MYREG =
FFH); therefore, the loop is repeated 256 times. When MYREG becomes 0,
control falls to the RETURN instruction, which pops the address from the top
of the stack into the program counter and resumes executing the instructions
after the CALL.
The amount of time delay in Example 3-9 depends on the frequency of the
PIC. How to calculate the exact time will be explained in the last section of this
chapter.
Example 3-9
Toggle all the bits of the SFR register of Port B by sending to it the values 55H andAAH
continuously. Put a time delay in between each issuing of data to Port B.
Solution:
MYREG EQU
Oxos
ORG
BACK
MOVLW
MOVWF
DELAY
AGAIN
112
;use location 08 as counter
0
Ox55
PORTB
DELAY
; load WREG with 55H
isend 55H to port B
;time delay
CALL
MOVLW
OxAA
i 10ad WREG with AA (in hex)
MOVWF
PORTB
isend AAH to port B
DELAY
CALL
GOTO
BACK
;keep doing this indefinitely
this is the delay subroutine
ORG
300H
,put time delay at address 300H
MOVLW
OxFF
;WREG = 255,the counter
MOVWF
MYREG
NOP
;no operation wastes clock cycles
NOP
DECF
MYREG, F
AGAIN
;repeat until MYREG becomes 0
BNZ
jreturn to caller
RETURN
jend of asm file
END
Example 3-10
Analyze the stack for the CALL instructions in the following program.
Solution:
When the first CALL is executed, the address of the instruction "MOVLW Oxl'lA" is saved
(pushed) on the stack. The last instruction of the called subroutine must be a RETURN
instruction, which directs the CPU to pop the contents of the top location of the stack into the
PC and resume executing at address 000007. The diagrams show the stack frame after the
CALL and RETURN instructions.
LOC OBJECT CODE
VALUE
00000008
000000
000000 OEss
000002 6E81
000004 EC80 FOOl
000008 OEAA
OOOOOA 6E8l
OOOOOC EC80 FOOl
000010 EFOO FOOO
000300
000300 OEFF
000302 6E08
000304 0000
000306 0000
000308 0608
00030A E1FC
00030C 0012
BEFORE
THE FIRST
CALL
LINE SOURCE TEXT
00001 #DEFINE PORTB OxF81
00002 MYREG EQU Ox08
00003
00004
00005
ORG
0
00006 BACK
MOVLW Ox55
00007
MOVWF PORTB
00008
CALL
DELAY
00009
MOVLW OxAA
00010
MOVWF PORTB
00011
CALL
DELAY
00012
BACK
GOTO
00013
00014
this is the
00015
00016
300H
ORG
00017 DELAY MOVLW OxFF
00018
MOVWF MYREG
00019 AGAIN NOP
00020
NOP
MYREG,
00021
DECF
00022
AGAIN
BNZ
00023
RETURN
00024
END
AFTER
THE FIRST
CALL
AFTER
RETURN
juse location 08 as counter
;load
; send
;time
iload
WREG with 55H
55H to port B
delay
WREG with AA (in hex)
jsend AAH to port B
ikeep doing this indefinitely
delay subroutine
iput delay at address 300H
jWREG = 2ss,the counter
ino op wastes clock cycles
F
jrepeat until MYREG becomes 0
jreturn to caller
;end of asm file
AFTER THE
SECOND
CALL
AFTER
RETURN
:~:~:~:~:~
.-21 bit----.
SP = 0
SP = 1
SP =0
CHAPTER 3: BRANCH, CALL, AND TIME DELAY LOOP
SP = 1
SP =0
113
The upper limit of the stack
As mentioned earlier, in the PIC 18 there are only 31 RAM locations for the
stack and they are mapped to addresses 0 I to I FH. That limits the number of calls
inside of calls for a given program to 31 because stack location 00 is not available.
In PIC, the stack is used for calls and interrupts. We must remember that upon calling a subroutine, the stack keeps track of where the CPU should return after completing the subroutine. For this reason, we must be very careful not to manipulate
the stack contents. See Chapter 6 for more on this.
Calling many subroutines from the main program
In Assembly language programming, it is common to have one main program and many subroutines that are called from the main program. (See Figure
3-8.)This allows you to make each subroutine into a separate module. Each module can be tested separately and then brought together with the main program.
More importantly, in a large program the modules can be assigned to different programmers in order to shorten development time. See Chapter 6 for discussion of
modules.
iMAIN program calling subroutines
MAIN
HERE
ORG
0
CALL
CALL
CALL
SUBR 1
SUBR 2
SUBR 3
BRA
HERE
end of MAIN
istay here
SUER 1
RETURN
-------end of subroutine 1
SUBR 2
RETURN
-------end of subroutine 2
SUBR 3
RETURN
-------end of subroutine 3
END
;end of the asm file
Figure 3-8, PIC Assembly Main Program That Calls Subroutines
It needs to be emphasized that in using CALL, the target address of the
subroutine can be anywhere within the 2M memory space of the PIC 18. (See
Example 3-11.) This is not the case for the other call instruction, RCALL, which
is explained next.
RCALL (relative call)
RCALL is a 2-byte instruction in contrast to CALL, which is 4 bytes.
114
Example 3-11
Write a program to count up from 00 to FFH and send the count to SFR of Port B. Use
one CALL subroutine for sending the data to Port B and another one for time delay. Put
a time delay in between each issuing of data to Port B.
Solution:
LOC
OBJECT CODE
VALUE
LINE
SOURCE TEXT
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00000007
00000008
000000
000000
000002
000004
000008
OEOO
6E07
EC06 FOOD
EF02 FOOO
OOOOOC
OOOOOE
000012
000016
2A07
C007 FF81
EC80 FOOl
0012
00013
00014
list P.PIC18F458
#include PIBF458.INC
COUNT
MYREG
EQU
EQU
OEFF
6E08
0000
0000
0000
0608
E1FB
0012
MOVLW
MOVWF
CALL
GOTO
BACK
4
3
2
jllSe location 08 for delay
00015
00016
MOVFF
CALL
00017
00018
RETURN
ORG
300H
00021
00022
00023
00024
00025
00026
00027
00028
00029
DELAY
MOVLW
MOVWF
NOP
NOP
NOP
DECF
COUNT PORTB
DELAY
f
=
a
i send it
to PORTB
:return to caller
AGAIN
OxFF
MYREG
jWREG = 255,
the counter
ino operation wastes clock cycles
MYREG, F
BNZ
AGAIN; repeat until MYREG becomes a
RETURN
:return to caller
END
;end of asm file
AFTER
DELAY
RETURN
AFTER
CALL
DELAY
4
3
4
3
2
2
00016
1
00008
4
3
-4--21 bit---+-
SP = 1
= a
this is the delay subroutine
,'put time delay at address 300H
00020
~ ~
SP = 0
jWREG
icount
0
COUNT
DISPLAY
BACK
increment and put it in PORTB
DISPLAY INCF COUNT,F
;increment count
AFTER
CALL
DISPLAY
BEFORE
ANY CALL
illse location 07 for count-up
OxOS
o
ORG
00019
000300
000300
000302
000304
000306
000308
00030A
00030C
00030E
OxO?
SP =2
2
AFTER
DISPLAY
RETURN
~ ~
4
3
2
SP = 1
SP =0
Because RCALL is a 2-byte instruction, the target address of the subroutine must
be within 2K because only 11 bits of the 2 bytes are used for the address. There is
no difference between RCALL and CALL in terms of saving the program counter
on the stack or the function of the RETURN instruction. The only difference is that
the target address for CALL can be anywhere within the 2M address space of the
PICl8 while the target address of RCALL must be within a 2K range. In many
variations of the PIC 18 marketed by Microchip Corporation, on-chip ROM is as
low as 4K. In such cases, the use of RCALL instead of CALL can save a number
of bytes of program ROM space.
CHAPTER 3: BRANCH, CALL, AND TIME DELAY LOOP
115
Of course, in addition to using compact instructions, we can program efficiently by having a detailed knowledge of all the instructions supported by a given
microprocessor, and using them wisely. Look at Example 3-12.
Example 3-12
Rewrite the main part of Example 3-9 as efficiently as you can.
Solution:
MYREG EQU OxOS
ORG
0
;load WREG with 55H
MOVLW Ox55
BACK MOVWF PORTB
;issue value in PORTB SFR
RCALL DELAY
; time delay
COMPF PORTB,F
jcomplement Port B SFR
BRA
BACK
;keep doing this indefinitely
this is the delay subroutine
DELAY MOVLW OxFF
;WREG = 255, the counter
MOVWF MYREG
AGAIN NOP
ino operation wastes clock cycles
NOP
DECF MYREG,F
BNZ
AGAIN
;repeat until MYREG becomes 0
RETURN
;return to caller (MYREG = 0)
END
iend of asm file
Example 3-13
A developer is using the PIC IS microcontroller chip for a product. This chip has only
4K of on-chip flash ROM. Which of the instructions, CALL or RCALL, is more useful
in programming this chip?
Solution:
The RCALL instruction is more useful because it is a 2-byte instruction. It saves two
bytes each time the call instruction is used. However, we must use CALL if the target
address is beyond the 2K boundary.
Review Questions
1. How wide is the size of the stack in the PIC IS?
2. True or false. In the PIC IS, control can be transferred anywhere within the 2M
of code space by using the CALL instruction.
3. The CALL instruction is a(n) _ -byte instruction.
4. True or false. In the PIC IS, control can be transferred anywhere within the 2M
of code space by using the RCALL instruction.
5. With each CALL instruction, the stack pointer register, SP, is
=0-;----;--==:-= (incremented, decremented).
6. With each RETURN instruction, the SP is
(incremented, decremented).
7. On power-up, the PIC uses location
as the first location of the stack.
S. How deep is the size of the stack in the PIC I S?
9. The RCALL instruction is a(n) _ -byte instruction.
10.
(RCALL, CALL) takes more ROM space.
116
SECTION 3.3: PIC18 TIME DELAY AND INSTRUCTION PIPELINE
In the last section we used the DELAY subroutine. In this section we discuss how to generate various time delays and calculate exact delays for the PIC 18.
We will also discuss instruction pipelining and its impact on execution time.
Delay calculation for the PIC18
In creating a time delay using Assembly language instructions, one must be
mindful of two factors that can affect the accuracy of the delay:
1. The crystal frequency: The frequency of the crystal oscillator connected to the
OSC I and OSC2 input pins is one factor in the time delay calculation. The
duration of the clock period for the instruction cycle is a function of this crystal frequency.
2. The PIC design: Since the 1970s, both the field of IC technology and the
architectural design of microprocessors have seen great advancements. Due to
the limitations of IC technology and limited CPU design experience for many
years, the instruction cycle duration was longer. Advances in both IC technology and CPU design in the 1980s and 1990s have made the single instruction
cycle a common feature of many microcontrollers. Indeed, one way to increase
performance without losing code compatibility with the older generation of a
given family is to reduce the number of instruction cycles it takes to execute
an instruction. One might wonder how microprocessors such as PIC are able
to execute an instruction in one cycle. There are three ways to do that: (a) Use
Harvard architecture to get the maximum amount of code and data into the
CPU, (b) use RISC architecture features such as fixed-size instructions, and
finally (c) use pipelining to overlap fetching and execution of instructions. We
have examined the Harvard and RISC architectures in Chapter 2. Next, we discuss pipelining.
Pipelining
In early microprocessors such as the 8085, the CPU could either fetch or
execute at a given time. In other words, the CPU had to fetch an instruction from
memory, then execute it, and then fetch the next instruction, execute it, and so on.
The idea of pipelining in its simplest form is to allow the CPU to fetch and execute at the same time, as shown in Figure 3-9.
Non-pipeline
I
fetch 1
Pipeline
I
fetch 1
I
exec 1
I
fetch 2
I
exec 2
I
fetch 3
I
exec 3
I
exec 5
I
exec 1
fetch 2
exec 2
fetch 3
exec 3
fetch 4
exec 4
fetch 5
Figure 3-9. Pipeline vs. Non-pipeline
CHAPTER 3: BRANCH, CALL, AND TIME DELAY LOOP
117
Instruction cycle time for the PIC
It takes a certain amount of time for the CPU to execute an instruction. In
the PIC, this time is referred to as instruction cycles (referred to as machine cycles
in some other CPUs). Because all the instructions in the PICI8 are either 2-byte or
4-byte, most instructions take no more than one or two instruction cycles to execute. (Notice, however, that some instructions such as BTFSS could take up to
three instruction cycles.) Appendix A provides a list of PICI8 instructions and
their cycles. In the PIC family, the length of the instruction cycle depends on the
frequency of the oscillator connected to the PIC system. The crystal oscillator,
along with on-chip circuitry, provide the clock source for the PIC CPU (see
Chapter 8). In the PIC 18, one instruction cycle consists of four oscillator periods.
Therefore, to calculate the instruction cycle for the PIC, we take 114 of the crystal
frequency, then take its inverse, as shown in Example 3-14.
Example 3-14
The following shows the crystal frequency for three different PIC-based systems. Find
the period of the instruction cycle in each case.
(a) 4 MHz
(b) 16 MHz (c) 20 MHz
Solution:
(a) 4/4 = I MHz; instruction cycle is III MHz = I Ils (microsecond)
(b) 16 MHz/4 = 4 MHz; instruction cycle = 114 MHz = 0.25 Ils = 250 ns (nanosecond)
(c) 20 MHzl4 = 5 MHz; instruction cycle = 115 MHz = 0.2 Ils = 200 ns
Branch penalty
The overlapping of fetch and execution of the instruction is widely used in
today's microcontrollers such as PIC. For the concept of pipe lining to work, we
need a buffer or queue in which an instruction is prefetched and ready to be executed. In some circumstances, the CPU must flush out the queue. For example,
when a branch instruction is executed, the CPU starts to fetch codes from the new
memory location and the code in the queue that was fetched previously is discarded. In this case, the execution unit must wait until the fetch unit fetches the
new instruction. This is called a branch penalty. The penalty is an extra instruction
cycle to fetch the instruction from the target location instead of executing the
instruction right below the branch. Remember that the instruction below the
branch has already been fetched and is next in line to be executed when the CPU
branches to a different address. This means that while the vast majority of PIC
instructions take only one instruction cycle, some instructions take two or three
instruction cycles. These are GOTO, BRA, CALL, and all the conditional branch
instructions such as BNZ, BC, and so on. The conditional branch instruction can
take only one instruction cycle if it does not jump. For example, the BNZ will
jump if Z = 0 and that takes two instruction cycles. If Z = I, then it falls through
and it takes only one instruction cycle. See Examples 3-15 and 3-16.
118
Example 3-15
For a PIC 18 system of 4 MHz, find how long it takes to execute each of the following
instructions:
(a) MOVLW
ADDLW
CALL
(b)
(d)
(g)
(e)
(h)
DECF
NOP
BNZ
(c)
(f)
MOVWF
GOTO
Solution:
The machine cycle for a system of 4 MHz is Ills, as shown in Example 3-14. Appendix
A shows instruction cycles for each of the above instructions. Therefore, we have:
Instruction cycles
Time to execute
1
1 xl Il s
1
1
1 xl Il s
1
1
1 xl Il s
1
1
1 xl Il s
1
1
1 xl Il s
1
2
2 xl Il s
2
2
2 xl Il s
2
(2 Ils taken, 1 Ils
2/1
through)
Instruction
(a) MOVLW Ox55
(b)
(c)
(d)
(e)
(f)
(g)
(h)
DECF MYREG
MOVWF
ADDLW
NOP
GOTO
CALL
BNZ
Il s
Ils
Il s
Il s
Il s
Ils
Il s
i f it falls
Example 3-16
Find the size of the delay of the code snippet below if the crystal frequency is 4 MHz:
Solution:
From Appendix A, we have the following machine cycles for each instruction of the
DELAY subroutine:
MYREG EQU
DELAY
AGAIN
Instruction Cycle
;use location 08 as counter
Ox08
MOVLW
MOVWF
NOP
NOP
DECF
BNZ
RETURN
OxFF
MYREG
1
1
1
1
MYREG,F
AGAIN
1
2
1
Therefore, we have a time delay of [(255 x 5) + 1 + 1 + 1] x 1 I1S = 1278 I1S.
Notice that BNZ takes two instruction cycles if it jumps back, and takes only one when
falling through the loop. That means the above number should be 1277 I1S.
CHAPTER 3: BRANCH, CALL, AND TIME DELAY LOOP
119
Delay calculation for PIC18
As seen in the last section, a delay subroutine consists of two parts: (1) setting a counter, and (2) a loop. Most of the time delay is performed by the body of
the loop, as shown in Examples 3-17 and 3-18.
Example 3-18
Find the size of the delay in the following program if the crystal frequency is 4 MHz:
MYREG EQU
BACK
DELAY
AGAIN
iuse location 08 as counter
oxos
ORG
MOVLW
MOVWF
CALL
MOVLW
MOVWF
CALL
GOTO
a
Ox55
PORTB
DELAY
OxAA
PORTB
DELAY
BACK
; load WREG with 55H
; send 55H to port B
;time delay
; load WREG with AA (in hex)
isend AAH to port B
; keep doing this indefinitely
this is the delay subroutine
ORG
300H
;put time delay at address 300H
MOVLW
OxFA
;WREG = 250, the counter
MYREG
MOVWF
NOP
ina operation wastes clock cycles
NOP
NOP
DECF
MYREG, F
BNZ
AGAIN
; repeat until MYREG becomes a
RETURN
ireturn to caller
END
iend of asm file
Solution:
From Appendix A, we have the following machine cycles for each instruction of the
DELAY subroutine:
Instruction CYcle
DELAY
AGAIN
MOVLW
MOVWF
NOP
NOP
NOP
DEeF
BNZ
RETURN
OxFA
1
MYREG
1
1
MYREG, F
AGAIN
1
1
1
2
1
Therefore, we have a time delay of[(250 x 6) + 1 + 1 + I] x lllS
=
1503 IlS.
Very often we calculate the time delay based on the instructions inside the
loop and ignore the clock cycles associated with the instructions outside the loop.
120
In Example 3-16, the largest value the MYREG register can take is 255;
therefore, one way to increase the delay is to use NOP instructions in the loop.
NOP, which stands for "no operation," simply wastes time, but takes 2 bytes of
program ROM space and that is too heavy a price to pay for just one instruction
cycle. A better way is to use a nested loop
Loop inside a loop delay
Another way to get a large delay is to use a loop inside a loop, which is also
called a nested loop. See Example 3-18. Compare that with Example 3-19 to see
the disadvantage of using many NOPs.
Example 3-18
For a instruction cycle of 1 ~s, find the time delay in the following subroutine:
R2
EQU
R3
EQU
DELAY
AGAIN
HERE
Ox7
OxS
MOVLW
MOVWF
MOVLW
MOVWF
NOP
NOP
DECF
BNZ
DECF
BNZ
RETURN
Instruction CYcle
D'200'
1
R2
1
D'250'
1
R3
1
1
1
R3, F
HERE
R2, F
AGAIN
1
2
1
2
1
Solution:
For the HERE loop, we have (5 x 250) 1 ~s = 1250 ~s. The AGAIN loop repeats the
HERE loop 200 times; therefore, we have 200 x 1250 ~s = 250000 ~s, if we do not
include the overhead. However, the following instructions of the outer loop add to the
delay:
AGAIN
MOVLW
MOVWF
D'250'
R3
1
DECF
BNZ
R2, F
AGAIN
1
1
2
The above instructions at the beginning and end of the AGAIN loop add 5 x 200 x 1 ~s
1000 ~s to the time delay. We should also subtract 200 ~s for the times BNZ HERE
falls through. As a result we have 250000 + 1000 - 200 = 250800 ~s = 250.8 milliseconds for the total time delay associated with the above DELAY subroutine. Notice that
in the case of a nested loop, as in all other time delay loops, the time is approximate
because we have ignored the first few instructions and the last instruction, RETURN, in
the subroutine. NOP is a 2-byte instruction. There are 11 instructions in the above
DELAY program, and all the instructions are 2-byte instructions. That means that the
loop delay takes 22 bytes of ROM code space.
=
CHAPTER 3: BRANCH, CALL, AND TIME DELAY LOOP
121
Example 3-19
Find the time delay for the following subroutine, assuming a crystal frequency of 4
MHz. Discuss the disadvantage of this over Example 3-18.
MYREG EQU
Ox8
Machine Cycle
DELAY
MOVLW
MOVWF
AGAIN
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DEeF
BNZ
RETURN
D' 200'
MYREG
MYREG,
AGAIN
1
1
F
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
Solution:
The time delay inside the AGAIN loop is [200(13 + 2)] x 1 Ils = 3000 Ils. NOP is a
2-byte instruction, even though it does not do anything except to waste cycle time.
There are 17 instructions in the above DELAY program, and all the instructions are
2-byte instructions. This means the loop delay takes 34 bytes of ROM code space, and
gives us only a 3000 JlS delay. That is the reason we use a nested loop instead of NOP
instructions to create a time delay. Chapter 9 shows how to use PIC timers to create
delays much more efficiently.
From these discussions we conclude that the use of instructions in generating time delay is not the most reliable method. To get more accurate time delay
we use timers, as described in Chapter 9. We can use MPLAB's simulator to verify delay time and number of cycles used. Meanwhile, to get an accurate time
delay for a given PIC microcontroller, we must use an oscilloscope to measure the
exact time delay.
122
Example 3-20
Write a program to toggle all the bits of SFR PORTB every I s. Assume that the crystal frequency is 10 MHz and the system is using a PIC 18F458.
Solution:
;tested using MPLAB with PIC18F4S8 operating at 10 MHz
R2
EQU
Ox2
R3
EQU
Ox3
R4
EQU
Ox4
BACK
MOVLW
MOVWF
CALL
COMF
GOTO
OxSS
i10ad WREG with SSH
PORTB
isend SSH to PORTB B
DELAY SOOMS itime delay
PORTB
; complement PORTB
BACK
ikeep doing this indefinitely
this is the delay subroutine
DELAY SOOMSEC
D' 20 I
MOVLW
MOVWF
R4
DilDO'
BACK
MOVLW
MOVWF
R3
AGAIN
MOVLW
D ' 250 1
MOVWF
R2
HERE
NOP
NOP
R2, F
DECF
BNZ
HERE
R3, F
DECF
AGAIN
BNZ
R4, F
DECF
BACK
BNZ
RETURN
Delay 20 x 100 x 250 x 5 x 400 ns = 1,000,000,000 ns = 1,000,000 Ils = 1 s.
In this calculation, we have not included the overhead associated with the two outer
loops. Use the MPLAB simulator to verify the delay.
PIC multistage execution pipeline
We can use a superpipeline to speed up execution of instructions. In superpipe lining, the process of executing instructions is split into many small steps that
are all executed in parallel. In this way, the execution of many instructions is overlapped. One limitation of superpipelining is that the speed of execution is limited
to the slowest stage of the pipeline. Compare this to making pizza. You can split
the process of making pizza into many stages, such as flattening the dough, putting on the toppings, and baking, but the process is limited to the slowest stage,
baking, no matter how fast the rest of the stages are performed. What happens if
we use two or three ovens for baking pizzas to speed up the process? This may
CHAPTER 3: BRANCH, CALL, AND TIME DELAY LOOP
123
work for making pizza but not for executing programs, because in the execution
of instructions we must make sure that the sequence of instructions is kept intact
and that there is no out-of-step execution. In the PIC 18, the execution unit takes 4
clock periods of the oscillator, as shown in Figure 3-10.
01
DECODE
02
READ
03
04
I PROCESS I WRITE TO I
Figure 3-10. Pipeline Activity After the lustruction Has Been Fetched
Figure 3-10 explains why we divide the oscillator by 4 to get the instruction cycle. In Q I, we decode the instruction that is already fetched and sitting in
the queue. In Q2, the operand is fetched from the file register. In Q3, the operation
is performed: The adding of the two numbers is done. In Q4, the result is written
into the destination register. In reality, one can construct the PIC 18 superpipeline
for four instructions, and is shown in Figure 3-11.
Instruction
Exec 1
I
Exec 2
DIRIPIW
Fetch 2
Exec 3
DIRIPIW
Fetch 3
Exec 4
DIRIPIW
Fetch 4
D I RI P Iwi
D = Decode the instruction
Fetch 1
MOVLW 5
ADDLW9
ADDLW7
ADDLW2
=Read the operand
P = Process (eg. ADDLW)
W =Write the result to destination register
R
Figure 3-11. Pipeline Activity for Both Fetch and Execute
Notice, in many computer architecture books the process stage is referred
to as execute and write to is called write back.
Review Questions
I. True or false. In the PIC 18, the instruction cycle lasts 4 clock periods of the
crystal frequency.
2. The minimum number of instruction cycles needed to execute a PlCI8 instruction is
3. For Question 2, what is the maximum number of cycles needed, and for which
instructions?
4. Find the instruction cycle for a crystal frequency of 12 MHz.
124
5. Assuming a crystal frequency of 4 MHz, find the time delay associated with
the loop section of the following DELAY subroutine:
DELAY
HERE
MOVLW
MOVWF
NOP
NOP
NOP
NOP
NOP
DECF
BNZ
RETURN
MYREG,
HERE
F
6. True or false. In the PIC 18, the instruction cycle lasts 6 clock periods of the
crystal frequency.
7. Find the machine cycle for a PIC 18 if the crystal frequency is 8 MHz.
8. True or false. In the PIC, the instruction fetching and execution are done at the
same time.
9. True or false. BRA and CALL will always take 2 instruction cycles.
10. True or false. The BNZ instruction will always take 2 instruction cycles.
SUMMARY
The flow of a program proceeds sequentially, from instruction to instruction, unless a control transfer instruction is executed. The various types of control
transfer instructions in Assembly language include conditional and unconditional
branches, and call instructions.
Looping in PIC Assembly language is performed using an instruction to
decrement a counter and to jump to the top of the loop if the counter is not zero.
This is accomplished with the BNZ instruction. Other branch instructions jump
conditionally, based on the value of the carry flag, the Z flag, or other bits of the
status register. Unconditional branches can be long or short, depending on the
location of the target address. Special attention must be given to the effect of
CALL and RCALL instructions on the stack.
PROBLEMS
SECTION 3.1: BRANCH INSTRUCTIONS AND LOOPING
I. In the PIC, looping action with the instruction "BNZ target" is limited to
iterations.
2. If a conditional branch is not taken, what is the next instruction to be
executed?
3. In calculating the target address for a branch, a displacement is added to the
contents of register _ _:---:
4. The mnemonic BRA stands for
and it is a(n)
-byte instruction.
5. The GOTO instruction is a(n)
-byte instruction.
6. What is the advantage of using BRA over GOTO?
CHAPTER 3: BRANCH, CALL, AND TIME DELAY LOOP
125
7. True or false. The target of a BNZ can be anywhere in the 2M address space.
8. True or false. All PIC branch instructions can branch to anywhere in the 2M
address space.
9. Which of the following instructions are 2-byte instructions.
(a) BZ
(b) BNC
(c) GOTO
(d) BRA
10. Dissect the BRA instruction, indicating how many bits are used for the operand
and the opcode, and indicate how far it can branch.
II. True or false. All conditional branches are 2-byte instructions.
12. Show code for a nested loop to perform an action 1,000 times.
13. Show code for a nested loop to perform an action 100,000 times.
14. Find the number of times the following loop is performed:
BACK
HERE
MOVLW
MOVWF
MOVLW
MOVWF
DECF
BNZ
DECF
BNZ
D' 200'
REGA
D 1 lDO'
REGB
REGB,F
HERE
REGA,F
BACK
15. The target address of a BNZ is backward if the second byte of opcode is
-:-_ _ (negative, positive).
16. The target address of a BNZ is forward if the second byte of opcode is
____ (negative, positive).
SECTION 3.2: CALL INSTRUCTIONS AND STACK
17. CALL is a(n) _-byte instruction.
18. RCALL is a(n) _-byte instruction.
19. True or false. The RCALL target address can be anywhere in the 2M address
space.
20. True or false. The CALL target address can be anywhere in the 2M address
space.
21. When CALL is executed, how many locations of the stack are used?
22. When RCALL is executed, how many locations of the stack are used?
23. Upon reset, the first available location of the stack is _-:-_ _
24. Describe the action associated with the RETURN instruction.
25. Give the size of the stack in PICI8.
26. In PIC 18, which address is pushed into the stack and the stack pointer when a
call instruction is executed.
SECTION 3.3: PICI8 TIME DELAY AND INSTRUCTION PIPELINE
27.
28.
29.
30.
126
Find the
Find the
Find the
Find the
oscillator frequency if the instruction cycle = 1.25 JlS.
instruction cycle if the crystal frequency is 20 MHz.
instruction cycle if the crystal frequency is 10 MHz.
instruction cycle if the crystal frequency is 16 MHz.
31. True or false. The CALL and RCALL instructions take the same amount of
time to execute even though one is a 4-byte instruction and the other is a 2-byte
instruction.
32. Find the time delay for the delay subroutine shown below if the system has a
PIC 18 with a frequency of 4 MHz:
BACK
HERE
MOVLW
MOVWF
MOVLW
MOVWF
NOP
DECF
BNZ
DECF
BNZ
D'200'
REGA
D'IOO'
REGB
REGB,F
HERE
REGA,F
BACK
33. Find the time delay for the delay subroutine shown below if the system has a
PICl8 with a frequency of 16 MHz:
BACK
HERE
MOVLW
MOVWF
MOVLW
MOVWF
NOP
NOP
DECF
BNZ
DECF
BNZ
Dr 200'
REGA
DIIGO'
REGB
REGB,F
HERE
REGA,F
BACK
34. Find the time delay for the delay subroutine shown below if the system has a
PIC 18 with a frequency of 4 MHz:
MOVLW D I 200
BACK
HERE
MOVWF REGA
MOVLW D' 250
MOVWF REGB
NOP
DECF
BNZ
DECF
BNZ
1
r
REGB
HERE
REGA
BACK
35. Find the time delay for the delay subroutine shown below if the system has a
PICI8 with a frequency of 10 MHz:
BACK
HERE
MOVLW
MOVWF
MOVLW
MOVWF
NOP
NOP
NOP
DECF
BNZ
DECF
BNZ
D'200'
REGB
REGB,F
HERE
REGA, F
BACK
CHAPTER 3: BRANCH, CALL, AND TIME DELAY LOOP
127
ANSWERS TO REVIEW QUESTIONS
SECTION 3.1: BRANCH INSTRUCTIONS AND LOOPING
1.
2.
3.
4.
5.
Branch if not zero
True
2
Z flag of status register
4
SECTION 3.2: CALL INSTRUCTIONS AND STACK
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
21-bit
True
4
False
Incremented
Decremented
1
31 locations (21 X31)
2
CALL
SECTION 3.3: PICIS TIME DELAY AND INSTRUCTION PIPELINE
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
128
True
I
2 and CALL. Also. the DECFSZ instruction can take up to 3 cycles
12 MHz / 4 ~ 3 MHz, and MC ~ 113 MHz ~ 0.333 Ils
[100 (1 + 1 + 1 + 1 + 1 + 1 + 2)] X I Ils ~ 800!lS ~ O.S milliseconds
False. It takes 4 clocks.
8 MHz / 4 ~ 2 MHz; machine cycle is 1 /2 MHz ~ 500 ns
True
True
False. Only ifit branches to the target address.
CHAPTER 4
PIC 1/0 PORT
PROGRAMMING
OBJECTIVES
Upon completion of this chapter, you will be able to:
»
»
»
»
»
»
»
List all the ports of the PIC18
Describe the dual role of PIC18 pins
Code Assembly language to use the ports for input or output
Explain the dual role of Ports A, B, C, and D
Code PIC instructions for 1/0 handling
Code 1/0 bit-manipulation programs for the PIC
Explain the bit-addressability of PIC ports
129
This chapter describes I/O port programming of the PICI8 with many
examples. In Section 4-1, we describe I/O access using byte-size data and in
Section 4-2, bit manipulation of the I/O ports is discussed in detail.
SECTION 4.1: 1/0 PORT PROGRAMMING IN PIC18
In the PICl8 family, there are many ports for I/O operations, depending on
which family member you choose. Examine Figure 4-1 for the PIC 18F458 40-pin
chip. A total of 33 pins are set aside for the five ports PORTA, PORTB, PORTC,
PORTD, and PORTE. The rest of the pins are designated as Vdd (Vee), Vss (GND),
OSCI, OSC2, MCLR (reset), and another set ofVdd and Vss' They are discussed
in Chapter 8.
40 PIN DIP
MClRIVpp
RB7/PGD
RAO/ANO/C VREF
RB6/PGC
RA1/AN1
3
RA2/AN2N REF •
4
PIC18F458
RA3/AN3NREF +
RA41T0CKI
38
RB5/PGM
37
RB4
RB3/CANRX
RB2/CANTXlINT2
RA5/AN4/SS/lVDIN
RB1/INT1
REO/AN5/RD
RBOIINTO
RE1/AN6IWR/C10UT
RE2/AN7/CS/C20UT
Voo
Vss
Voo
Vss
RD7/PSP7/P1 D
OSC1/ClKI
RD5/PSP5/P1 B
OSC2/ClKO/RA6
RD6/PSP6/P1C
RD4/PSP4/ECCP1/P1A
RCOIT1 OSO!T1 ClKI
RC7/RXIDT
RC1!T10SI
RC6/TXlCK
RC2/CCP1
RC5/SDO
RC3/SCKlSCl
RC4/SDI/SDA
RDO/PSPO/C1IN+
RD3/PSP3/C2IN-
RD1/PSP1/C1IN-
RD2/PSP2/C2IN+
Figure 4-1. PICF458 Pin Diagram
110 port pins and their functions
The number of ports in the PIC 18 family varies depending on the number
of pins on the chip. The 18-pin PIC 18 has ports A and B only, while the 64-pin version has ports A through F, and the 80-pin PIC 18 has ports A through L, as shown
in Table 4-1. The 40-pin PIC 18F458 has five ports. They are PORTA, PORTB,
PORTC, PORTD, and PORTE. To use any of these ports as an input or output port,
it must be programmed, as we will explain throughout this section. In addition to
130
Table 4-1: Number of Ports in PIC18 Family Members
Pins
18-pin
28-pin
40-pin
PIC18F1220 PIC18F2220 PIC18F458
Chip
PortA
X
X
X
Port B
X
X
X
Port C
X
X
Port D
X
Port E
X
Port F
Port G
Port H
Port J
Port K
Port L
Note: X indicates that the port is available.
64-pin
80-pin
PIC18F6525 PIC18F8525
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
being used for simple 1/0, each port has some other functions such as ADC, timers,
interrupts, and serial communication pins. Figure 4-1 also shows alternate functions for the PICI8F458 pins. We will study all these alternate functions in future
chapters. In this chapter we focus on the simple I/O function ofthe PIC 18 family.
Not all ports have 8 pins. For example, in the PIC 18F458, Port A has 7 pins; Ports
B, C, and D each have 8 pins; and Port E has only 3 pins. Each port has three SFRs
associated with it, as shown in Table 4-2. They are designated as PORTx, TRISx,
and LATx. For example, for Port B we have PORTB, TRISB, and LATB. Note that
TRIS stands for TRIState and LAT stands for
Table 4-2: Ports' SFR
LATch. Next, we describe how to access the Addresses for PIC18F458
SFRs associated with the ports.
Port
Address
PORTA
F80H
TRIS register role in outputting
PORTB
F81H
data
PORTC
F82H
PORTD
F83H
Each of the Ports A-E in the PICI8F458
PORTE
F84H
can be used for input or output. The TRISx SFR
LATA
F89H
is used solely for the purpose of making a given
LATB
F8AH
port an input or output port. For example, to
LATC
F8BH
make a port an output, we write Os to the TRISx
LATD
F8CH
register. In other words, to output data to any of
LATE
F8DH
the pins of the Port B, we must first put Os into
TRISA
F92H
the TRISB register to make it an output port, and
TRISB
F93H
then send the data to the Port B SFR itself.
TRISC
F94H
TRISD
F95H
TRISE
F96H
CHAPTER 4: PIC 110 PORT PROGRAMMING
131
The following code will toggle all 8 bits of Port B forever with some time
delay in between "on" and "off' states:
MOVLW
MOVWF
MOVLW
MOVWF
CALL
MOVLW
MOVWF
CALL
GOTO
Ll
;WREG = 00
; make Port B an output port 0000 0000
;WREG = 55h
;put 55h on port B pins
OxO
TRISB
Ox55
PORTB
DELAY
OxAA
PORTB
DELAY
Ll
;WREG = AAh
iPut AAh on port B pins
It must be noted that unless we activate the TRIS bit (set it to zero), the data
will not go from the port register to the pins of the PIC. This means that if we
remove the first two lines of the above code, the 55H and AAH values will not get
to the pins. They will be sitting in the SFR of Port B inside the CPU.
To see the role of the TRISx register in allowing the data to go from Portx
to the pins, examine Figure 4-3 and Figure 4-4. If you are unfamiliar with the internals of logic gates, see Appendix C for an overview. Notice that the CMOS "on"
and "off' states in Figure 4-2 are taken from Appendix C.
Note that upon reset, all ports have value FFH in their TRIS registers. This
means all ports are configured as input as we will see next.
Voo
J
1-19
Voo
Vee
J
0-19
OFF
V"
J
ON
1-19
V"
(GNO)
P-TYPE 'ON'
J
0-19
ON
V"
(GNO)
P-TYPE 'OFF'
Voo
V'"
(GNO)
(GNO)
N-TYPE 'ON'
N-TYPE 'OFF'
PMOS
INPUT ----;5'"'V---i
·ON·
t--;;;-;--
9
OV
PMOS
OUTPUT
NMOS
V"
(GNO)
Figure 4-2. CMOS States for P and N Transistors
132
OFF
INPUT ----;:;-;--1
OV
t--;,.-;-5V
NMOS
OUTPUT
£RDLAT
0
•
0
DATA BUS
O~
D
"-
WRPORT
0
ClK
•
1
V DD
•
1
1
'LP OFF
0
DATA LATCH
ZERO
~
~D
1
"-
WRTRIS
1
o~
0
ClK
1,cN
]
1
Vss
TRIS LATCH
TRIS=O
C
TTL or
SCHMITT
TRIGGER
RDTRIS
En
r-...
RDPORT
FIgure 4-3. Outputting (Writing) 0 to a Pin
D
0
~
I
V
the PIC18
In
RDLAT
S;-'
1
•
DATA BUS
1
D
"-
~RPORT
ClK
o~
0
0
•
0
o
DATA LATCH
•
~
V DD
0
n..P ON
~
ON E
~
-0
WRTRIS
TRI S=O
D
"ClK
'"'
OJ
0....2..
O:~
1
0
1
OFF
Vss
TRIS LATCH
'\
RD TRIS
.-1..
0
..J
D
En
RDPORT
TTL or
SCH MITT
TRIG GER
I
V
Figure 4-4. Outputting (Writing) 1 to a Pin in the PIC18
CHAPTER 4: PIC 110 PORT PROGRAMMING
133
TRIS register role in inputting data
To make a port an input port, we must first put 1s into the TRISx register
for that port, and then bring in (read) the data present at the pins. Notice that 0
stands for out and 1 for in. This is easy to remember because 0 and 0 look alike
the same way that I looks like 1. The following code will get the data present at
the pins of port C and send it to port B indefinitely, after adding the value 5 to it:
L2
MOVLW
MOVWF
MOVLW
MOVWF
MOVF
ADDLW
MOVWF
GOTO
B'OOOOOooo'
TRISB
B'11111111'
TRISC
PORTC,W
5
PORTB
L2
;WREG
0000000 (binary)
iPort B an output port(O for 0)
;WREG
11111111 (binary)
; Port C an input port (1 for I)
;ffiove data from Port C to WREG
; add some value to it
;send it to Port B
; continue forever
Another, more efficient, version of the program is as follows:
L2
CLRF
SETF
MOVF
ADDLW
MOVWF
BRA
TRISB
TRISC
PORTC,W
;clear TRISB (Port B an output port)
;set TRISC (Port C an input port)
;get data from port C
;add some value
;send it to port B
5
PORTB
L2
Again, it must be noted that unless we activate the TRIS bits (by putting Is
there), the data will not be brought into the WREG register from the pins of Port
C. To see the role of the TRISx register in allowing the data to come into the CPU
from the pins, examine Figures 4-5 and 4-6.
£RDLAT
..
0
DATA BUS
0
D
"-
WRPORT
CLK
X
Or----'
X
aX
1
1
DATA LATCH
1
WRTRIS
TRIS=1
~
ZERO
~
1
D
"-
CLK
X
or-!-
0
a
o "N
J
OFF
0
Vss
TRIS LATCH
..
0
/l
~:
0 0
-I
0
DO
En~'-
v
FIgure 4-5. Inputtmg (Readmg) 0 from a Pm m the PIel8
134
OFF
o ,....
ROTRIS
RDPORT
:r
V DD
~
1
DATA BUS
D
...!W~R~P~O~R~T~j--1~~~l~K~~Q~X~==~X~~=>__~I~P OFF
DATA LATCH
D
Q
"-
WRTRIS
ClK
ONE
x
0
0
Q 0
Vss
TRIS LATCH
TRIS=1
N OFF
RDTRIS
..
..
Q
D
En
~
TIL or
SCHMITI
TRIGGER
....-
RDPORT
Figure 4-6. Inputting (Reading) 1 from a Pin in the PIC18
PortA
Port A occupies a total of 7 pins (RAO-RA6), but for the PIC 18F458, pin
A6 is used for the OSC2 pin. A6 is not available if we use a crystal oscillator to
provide frequency to the PICI8 chip, as we will see in Chapter 8.
To use the pins of Port A as both input and output ports, each bit must be
connected externally to the pin by enabling the bits of the TRISA register. For
example, the following code will continuously send out to Port A the alternating
values of 55H and AAH:
;toggle all bits of PORTA
Ll
MOVLW
MOVWF
MOVLW
MOVWF
CALL
MOVLW
MOVWF
CALL
GOTO
B'OOOOOOOO'
TRISA
Ox55
PORTA
DELAY
OxAA
PORTA
DELAY
Ll
;WREG = 00000000 (binary)
;make Port A an output port
;WREG = 55h
;put 55h on Port A pins
(0 for Out)
;WREG = AAh
iPut AAh on Port A pins
It must be noted that 55H (01010101) when complemented becomes AAH
(10101010). Although by sending 55H and AAH to Port A continuously, we toggle all 8 bits of the Port A register, only 6 pins (RAO-RA5) will show the toggling
data.
CHAPTER 4: PIC I/O PORT PROGRAMMING
135
Port A as input
In order to make all the bits of Port A an input, TRISA must be programmed by writing I to all the bits. In the following code, Port A is configured
first as an input port by writing all I s to register TRISA, and then data is received
from Port A and saved in some RAM location of the fileReg:
MYREG EQU
MOVLW
MOVWF
MOVF
MOVWF
OX20
isave
it here
B'11111111' ;WREG = 11111111 (binary)
TRISA
;make Port A an input port (1 for In)
PORTA,W
;move from fileReg of Port A to WREG
MYREG
;save it in fileReg of MYREG
Port B
Port B occupies a total of 8 pins (RBO~RB7). To use the pins of Port B as
both input and output ports, each bit must be connected externally to the pin by
enabling the bits of register TRISB.
For example, the following code will continuously send out the alternating
values of 55H and AAH to Port B:
; toggle all bits of PORTB
L1
MOVLW
MOVWF
MOVLW
MOVWF
CALL
MOVLW
MOVWF
CALL
GO TO
B'OOOOOOOO' ;WREG
00
TRISB
imake Port B an output port
Ox55
iWREG = 55h
PORTB
iput 55h on port B pins
DELAY
OxAA
;WREG = AAh
PORTB
iput AAh on port B pins
DELAY
L1
Port B as input
In order to make all the bits of Port B an input, TRISB must be programmed by writing I to all the bits. In the following code, Port B is configured
first as an input port by writing all I s to register TRISB, and then data is received
from Port B and saved in some RAM location of the fileReg:
MYREG EQU
MOVLW
MOVWF
MOVF
MOVWF
136
OX25
B'11111111'
TRISB
PORTB,W
MYREG
isave
it here
;WREG = 11111111 (binary)
imake Port B an input port (1 for In)
imove from fileReg of Port B to WREG
isave it in fileReg
Dual role of Ports A and B
The PIC 18 multiplexes an analog-to-digital converter through Port A to
save 110 pins. The alternate functions of the pins for PortA are shown in Table 4-3.
We will show how to use Port A's ADC in Chapter 13. Because many projects use
an ADC, we do not use Port A for simple 110 functions. The PIC 18 multiplexes
some other functions through Port B to save pins. The alternate functions of the
pins for Port B are shown in Table 4-4. We will show how to use the alternate functions of Port B in future chapters.
Table 4-3: Port A Alternate
Functious
Table 4-4: Port B Alternate
Functions
Bit
RAO
RAI
RA2
RA3
RA4
RA5
RA6
Bit
RBO
RBI
RB2
RB3
RB4
RB5
RB6
RB7
Function
ANOICVREF
ANI
AN2NREFAN3NREH
TOCKI
AN4/SS/LVDIN
OSC2/CLKO
Function
INTO
INTI
INT2/CANTX
CANRX
PGM
PGC
PGD
Port C
Port C occupies a total of 8 pins (RCO-RC7). To use the pins of Port C as
both input and output ports, each bit must be connected externally to the pin by
enabling the bits of register TRISC. For example, the following code will continuously send out the alternating values of 55H and AAH to Port C:
;toggle all bits of PORTB
Ll
MOVLW
MOVWF
MOVLW
MOVWF
CALL
MOVLW
MOVWF
CALL
GOTO
B'OOOOOOOO' ;WREG = 00
TRISC
;make Port C an output port
Ox55
;WREG = 55h
PORTC
iPut 55h on Port C pins
DELAY
OxAA
;WREG = AAh
PORTC
iput AAh on Port C pins
DELAY
Ll
CHAPTER 4: PIC 1/0 PORT PROGRAMMING
137
Port C as input
In order to make all the bits of Port C an input, TRISC must be programmed by writing 1 to all the bits. In the following code, Port C is configured
first as an input port by writing all 1s to register TRISC, and then data is received
from Port C and saved in some RAM location of the fileReg:
MYREG
MOVLW
MOVWF
MOVF
MOVWF
EQU Ox20
B'11111111'
TRISC
PORTC,W
MYREG
; save it here
;WREG = 11111111 (binary)
jmake Port C an input port (1 for In)
iffiove from fileReg of Port C to WREG
isave it in fileReg
Port 0
Port 0 occupies a total of 8 pins (ROO-R07). To use the pins of Port 0 as
both input and output ports, each bit must be connected externally to the pin by
enabling the bits of register TRISO. For example, the following code will continuously send out to Port 0 the alternating values of 55H and AAH:
;toggle all bits of PORTD
Ll
CLRF
MOVLW
MOVWF
CALL
MOVLW
MOVWF
CALL
BRA
TRISD
Ox55
PORTD
DELAY
OxAA
PORTD
DELAY
Ll
imake Port D an output port
;WREG
iPut
= 55h
55h on Port D pins
;WREG = AAh
iPut AAh on Port D pins
jwe can use GOTO
Port 0 as input
In order to make all the bits of Port 0 an input, TRISO must be programmed by writing I to all the bits. In the following code, Port 0 is configured
first as an input port by writing all I s to register TRISO, and then data is received
from Port 0 and saved in some RAM location of the fileReg:
MYREG
SETF
MOVF
MOVWF
138
EQU Ox20
TRISD
PORTD,W
MYREG
isave it here
;TRISD
iffiove
isave
= 11111111 (binary)
from Port D to WREG
it in fileReg
=
PORTD
Input
Dual role of Ports C and D
The alternate functions of the pins for Port C are shown in Table 4-S. We
will show how to use Port C's alternate functions in future chapters. The alternate
functions of the pins for Port D are shown in Table 4-6. We will show how to use
Port D's alternate functions in future chapters.
Table 4-5: Port C Alternate
Functions
Table 4-6: Port D Alternate
Fnnctions
Bit
RCO
RCI
RC2
RC3
RC4
RCS
RC6
RC7
Bit
RDO
RDl
RD2
RD3
RD4
RDS
RD6
RD7
Fnnction
n OSO/TI CKI
nosl
CCPl
SCKlSCL
SDI/SDA
SDO
DUCK
RXlDT
Function
PSPO/CIIN+
PSPIIC1INPSP2/C2IN+
PSP3/C2INPSP4/ECCP liP 1A
PSPSIP1B
PSP6/P1C
PSP7/P1D
Port E
Port E occupies a total of 3 pins (REO-RE2) in the PIC 18F4S8/4S80. Port
E is used for 3 additional analog inputs or simple I/O: ANS, AN6, and AN7. Just
like other ports, Port E has alternate functions. We will show how to use them in
future chapters.
Different ways of accessing the entire 8 bits
In the following code, as in many previous I/O examples, the entire 8 bits
of Port B are accessed:
;toggle all bits of PORTB
Ll
MOVLW
MOVWF
MOVLW
MOVWF
CALL
MOVLW
MOVWF
CALL
GOTO
OxO
TRISB
Ox55
PORTB
DELAY
OxAA
PORTB
DELAY
Ll
iWREG =
00
imake Port B an output port
;WREG = 55h
iput 55h on Port B pins
;WREG = AAh
iPut AAh on Port B pins
CHAPTER 4: PIC I/O PORT PROGRAMMING
139
The previous code toggles all the bits of Port B continuously. Another variation of the above code follows:
Ll
CLRF
MOVLW
MOVWF
CALL
MOVLW
MOVWF
CALL
GOTO
TRISB
Ox55
PORTB
DELAY
OxAA
PORTB
DELAY
Ll
imake Port B an output port
;WREG = 55h
iput 55h on Port B pins
;WREG
=
AAh
iput AAh on Port B pins
The following is another way of doing the same thing:
L2
CLRF
MOVLW
MOVWF
COMF
CALL
BRA
TRISB
Ox55
PORTB
PORTB, F
DELAY
L2
imake Port B an output port
;WREG
=
55h
iPut 55h on Port B pins
; toggle bits of Port B
The above code uses a technique called read-modifY-write.
Read followed by write I/O operation
Due to the timing issue, we must be careful not to have two 1/0 operations
one right after the other. Examine the following rewrite of an earlier code fragment
in which data was read from PORTC and sent to PORTB:
L4
CLRF
SETF
MOVF
NOP
MOVWF
BRA
TRISB jclear TRISB to make PORTB an output port
TRISC
i set TRISC all Is (Port C as Input)
PORTC,W
ig et data from Port C into WREG
jNEED some NOP to ensure data is in WREG
;before it is sent to Port B
PORTB
L4
ikeep doing it
We need a NOP (or some other instruction) to make sure that the data is
written into WREG before it is read for outputting to Port B. This is called data
dependency in CPU design. This type of data dependency is commonly referred to
as RAW (Read-After-Write). The NOP will introduce a bubble into the pipeline to
remove data dependency due to RAW. See Figure 4-7. One way to avoid this problem is to use the MOVFF instruction, which is a 4-byte instruction. This is coded
as follows:
L5
140
CLRF
SETF
MOVFF
BRA
TRISB
TRISC
PORTC,PORTB
L5
imake Port B an output port
;TRISC
=
FFh (Port C Input)
from Port C and send to PORTB
ikeep doing it
ig et
INSTRUCTION
Fetch 1
IDIRlplwl.
1-1
..
MOVF PORTC,W
;Read PORTC into WREG
MOVWF PORTS
;Write WREG to PORTS
Time IS
too short
The RAW (Read - After - Write) for two consecutive instructions.
INSTRUCTION
Fetch!
MOVF PORTC,W
IDIRlplwl
I
I
Fetch 2
I
I•
DI NI NI N
Fetch 3
D I Rip I wi
NOP
;Bubble in Pipeline
MOVWFPORTS
N = No Operation
o = Decode the instruction
R = Read the operand
P = Process
W
= Write the result to destination
register
Figure 4-7. Pipeline for Read Followed by Write I/O
Ports status upon reset
Upon reset, all ports have value
FFH on their TRIS register, as shown in
Table 4-7. This makes them input ports
upon reset.
Table 4-7: Reset Values ofTRIS
Registers for PIC18
Register
Reset Value (Binary)
~T~R~I~SA~;""'=~~':";'I~I~I;I:":l1~I~I=d[b
TRISB
11111111
~~~--------~~~~--TRISC
IIIIIIII
~~~--------~~~~--TRISD
III 1111 I
Note: All ports are input ports upon
reset.
Review Questions
I.
2.
3.
4.
5.
6.
7.
There are total of ____ ports in the PIC18F458.
True or false. All of the PIC l8F458 ports have 8 pins.
List all PICI8F458 ports that have 8 pins.
True or false. Upon power-up, the VO pins are configured as output ports.
Code a simple program to send 99H to Port B and Port C.
To make Port B an output port, we must place
in register ~____
To make Port B an input port, we must place
in register
CHAPTER 4: PIC I/O PORT PROGRAMMING
141
Example 4-1
Write a test program for the PIC18 chip to toggle all the bits ofPORTB, PORTC, and
PORTD every 1/4 of a second. Assume a crystal frequency of 4 MHz.
Solution:
;tested with MPLAB for the PIC18F458 and XTAL
4 MHz
list P~PIC18F458
#include P18F458.INC
R1 equ oxO?
R2 equ Ox08
ORG 0
L3
CLRF
CLRF
CLRF
MOVLW
MOVWF
MOVWF
MOVWF
COMF
COMF
COMF
CALL
BRA
TRISB
TRISC
TRISD
Ox55
PORTB
PORTC
PORTD
PORTB,F
PORTC,F
PORTD,F
QDELAY
L3
; make Port B an output port
imake Port C an output port
; make Port D an output port
;WREG
55h
iPut 55h on Port B pins
iPut 55h on Port C pins
iPut 55h on Port D pins
;toggle bits of Port B
; toggle bits of Port C
;toggle bits of Port D
;quarter of a second delay
~
;-----------1/4 SECOND DELAY
QDELAY
MOVLW Dj 200 I
MOVWF R1
MOVLW D'250 I
Dl
MOVWF R2
NOP
D2
NOP
DECF R2, F
BNZ D2
DECF Rl, F
BNZ D1
RETURN
END
Calculations:
4MHz/4=IMHz
1 1 1 MHz = 1 IlS
Delay = 250 x 200 x 5 MC x 1 Ils = 250,000 Ils (if we include the overhead, we will
have 250,800. See Example 3-17 in the previous chapter.)
Use the MPLAB simulator to verifY the delay size.
142
SECTION 4.2: 1/0 BIT MANIPULATION PROGRAMMING
In this section we further examine the PIC 18 I/O instructions. We pay special attention to 1/0 bit manipulation because it is a powerful and widely used feature of the PIC family.
1/0 pOrts and bit-addressability
Sometimes we need to access only I or 2 bits of the port instead of the
entire 8 bits. A powerful feature of PIC 1/0 ports is their capability to access individual bits of the port without altering the rest of the bits in that port. For all PIC
ports, we can access either all 8 bits or any single bit without altering the rest.
Table 4-8 lists the single-bit instructions for the PIC 18. Although the instructions
in Table 4-9 can be used for any registers in the data RAM file register, I/O port
operations use them most often. We will see the use of these instructions throughout future chapters.
Table 4-8: Single-Bit (Bit-Oriented) Instructions for PIC18
Instruction
BSF
fileReg,bit
BCF fileReg,bit
BTG fileReg,bit
BTFSC fileReg,bit
BTFSS fileReg,bit
Function
Bit Set fileReg (set the bit: bit - 1)
Bit Clear fileReg (clear the bit: bit = 0)
Bit Toggle fileReg (complement the bit)
Bit test fileReg, skip if clear (skip next instruction ifbit - 0)
Bit test fileReg, skip if set (skip next instruction ifbit = 1)
Table 4-9: Single-Bit Addressability of Ports for PIC18F458/4580
PORT
RAO
RAI
RA2
RA3
RA4
RA5
PORTB
RBO
RBI
RB2
RB3
RB4
RB5
RB6
RB7
PORTC
RCO
RCI
RC2
RC3
RC4
RC5
RC6
RC7
PORTD
RDO
RDI
RD2
RD3
RD4
RD5
RD6
RD7
PORTE
REO
REI
RE2
Port Bit
DO
Dl
D2
D3
D4
D5
D6
D7
Next we describe all these instructions and examine their usage.
BSF (bit set fileReg)
To set HIGH a single bit of a given fileReg, we use the syntax "BSF
f i 1 eReg, bi t num" where fileReg can be any location in the file register and
bit_num is the desired bit number from 0 to 7. Although the bit-oriented instructions can be used for manipulation of bits DO-D7 of any file register, they are
mostly used for 110 ports in embedded systems. For example, "BSF PORTB, 5"
sets HIGH bit 5 of Port B.
CHAPTER 4: PIC 1/0 PORT PROGRAMMING
143
Example 4-2
An LED is connected to each pin of Port D. Write a program to turn on each LED from
pin DO to pin D7. Call a delay module before turning on the next LED.
Solution:
CLRF
BSF
CALL
BSF
CALL
BSF
CALL
BSF
CALL
BSF
CALL
BSF
CALL
BSF
CALL
BSF
CALL
TRISD
PORTD,O
DELAY
PORTD,l
DELAY
PORTD,2
DELAY
PORTD,3
DELAY
PORTD,4
DELAY
PORTD,S
DELAY
PORTD,6
DELAY
PORTD,7
DELAY
imake PORTD an output port
ibit set turns on RDO
jdelay before next one
jturn on RDI
;delay before next one
RDO
L....IA'270
V'A..,A,___
LED
~~~
PIC
RD7
l.-r;:A
L....I'V',,",___
LED
~Z~
BCF (bit clear file Reg)
To clear a single bit of a given file Reg, we use the syntax "BCF
f ileReg, bit_number". Remember that for lIO ports, we must activate the
appropriate bit in the TRlSx register if we want the pin to reflect the changes. For
example, the following code toggles pin RB2 continuously:
BCF
AGAIN BSF
CALL
BCF
CALL
BRA
144
TRISB,
PORTB,
DELAY
PORTE,
DELAY
AGAIN
2
2
;bit = 0, make RB2 an output pin
ibit set (RB2 = high)
2
;bit clear(RB2
=
low)
Example 4-3
Write the following programs:
(a) Create a square wave of 50% duty cycle on bit 0 of Port C.
(b) Create a square wave of 66% duty cycle on bit 3 of Port C.
Solution:
(a) The 50% duty cycle means that the "on" and "off" states (or the high and low portions ofthe pulse) have the same length. Therefore, we toggle RCO with a time delay
between each state.
HERE
BCF
BSF
CALL
BCF
CALL
BRA
iclear TRIS bit for RCa = out
iset to HIGH RCa (RCa = 1)
TRISC,O
PORTC, a
DELAY
PORTC, a
DELAY
HERE
; call the delay subroutine
iReD
=
0
ikeep doing it
Another way to write the above program is:
HERE
BCF
BTG
CALL
BRA
imake RCO = out
jcomplement bit 0 of PORTC
icall the delay subroutine
TRISC,O
PORTC,O
DELAY
HERE
jkeep doing it
PIC18F458
RCO
I--
(b) A 66% duty cycle means that the "on" state is twice the "off" state.
BACK
BCF
BSF
CALL
CALL
BCF
CALL
BRA
TRISC,3
PORTC,3
DELAY
DELAY
PORTC,3
DELAY
BACK
iclear TRISC3 bit for output
iRe3
=
1
icall the delay subroutine
,·twice for 66%
Re3 = 0
icall delay once for 33%
i
ikeep doing it
PIC18F458
RC3
r--
CHAPTER 4: PIC 1/0 PORT PROGRAMMING
145
BTG (bit toggle tileReg)
To toggle a single bit of a given fileReg, we use the syntax "BTG
fileReg,
BACK
BCF
BTG
CALL
BRA
bit number".
TRISB, 2
PORTB, 2
DELAY
BACK
;make RB2 an output pin
;toggle pin RB2 only
Notice that RB2 is the third bit of Port B (the first bit is RBO, the second
bit is RBI, etc.). This is shown in Table 4-9. See Example 4-2 for an example of
bit manipulation ofI/O bits.
Notice in Example 4-2 that unused portions of Port C are undisturbed. This
single-bit addressability of I/O ports is one of most powerful features of the PIC
microcontroller and is one of the reasons that many designers choose the PIC over
other microcontrollers. We will see the use of the bit-addressability ofl/O ports in
future chapters.
Checking an input pin
To make decisions based on the status of a given bit in the file register, we
use the instructions BTFSC (bit test fileReg skip if clear) and BTFSS (bit test
fileReg skip if set). These single-bit instructions are widely used for I/O operations. They allow you to monitor a single pin and make a decision depending on
whether it is 0 or 1. Again it must be noted that the instructions BTFSC and BTFSS
can be used for any bits of the file register, including the I/O ports A, B, C, D, and
so on.
BTFSS (bit test tileReg, skip it set)
To monitor the status of a single bit for HIGH, we use the BTFSS instruction. This instruction tests the bit and skips the next instruction if it is HIGH.
Example 4-4 shows how it is used.
o :::;
o :::;
f
:::; FF
b
:::;
7
BTFSC (bit test tileReg, skip it clear)
To monitor the status of a single bit for LOW, we use the BTFSC instruction. This instruction tests the bit and skips the instruction right below it if the bit
is LOW. Example 4-5 shows how it is used.
o :::;
o :::;
146
f
b
:::; FF
:::; 7
Example 4-4
Write a program to perform the following:
(a) Keep monitoring the RB2 bit until it becomes HIGH;
(b) When RB2 becomes HIGH, write value 45H to Port C, and also send a HIGH-toLOW pulse to RD3.
Solution:
BSF
CLRF
BCF
MOVLW
AGAIN BTFSS
BRA
MOVWF
BSF
BCF
TRISB,2
TRISC
PORTD, 3
Ox4S
PORTB,2
AGAIN
PORTC
PORTD,3
PORTD,3
jmake RB2 an input
imake PORTC an output port
irnake RD3 an output
jWREG = 4Sh
;bit test RB2 for HIGH
ikeep checking i f LOW
;issue WREG to Port C
;bit set fileReg RD3 (H-to-L)
;bit clear fileReg RD3 (L)
In this program, instruction "BTFSS PORTB, 2" stays in the loop as long as
RB2 is LOW. When RB2 becomes HIGH, it skips the branch instruction to get out of
the loop, and writes the value 45H to Port C. It also sends a HIGH-to-LOW pulse to
RD3.
Example 4-5
Assume that bit RB3 is an input and represents the condition of a door alarm. If it goes
LOW, it means that the door is open. Monitor the bit continuously. Whenever it goes
LOW, send a HIGH-to-LOW pulse to port RC5 to turn on a buzzer.
Solution:
HERE
BSF
BCF
BTFSC
BRA
BSF
BCF
BRA
TRISB,3
TRISC,S
PORTB, 3
HERE
PORTC,S
PORTC,S
HERE
make RB3 an input
imake RCS an output
ikeep monitoring RB3 for HIGH
jstay in the loop
imake RCS HIGH
imake RCS LOW for H-to-L
i
PIC
4.7k
Switch
t---tRB3
-11
V
~
,--_R_C..J5
CHAPTER 4: PIC I/O PORT PROGRAMMING
147
Monitoring a single bit
We can also use the bit test instructions to monitor the status of a single bit
and make a decision to perfonn an action. See Examples 4-6 and 4-7.
Example 4-6
A switch is connected to pin RB2. Write a program to check the status of SW and perfonn the following:
(a) IfSW = O. send the letter 'N' to PORTD.
(b) IfSW = I, send the letter 'Y' to PORTD.
Solution:
BSF
CLRF
AGAIN BTFSS
BRA
MOVLW
MOVWF
GOTO
OVER MOVLW
MOVWF
GOTO
imake RB2 an input
jmake PORTD an output port
ibit test RB2 for HIGH
i i t must be LOW
iWREG
'Y' ASCII letter Y
; issue WREG to PORTD
iwe can use BRA too
letter N
;WREG
'N' ASCII
WREG
PORTD
iissue
to
jwe can use BRA too
TRISB,2
TRISD
PORTB, 2
OVER
A'yr
~
PORTD
AGAIN
AINI
~
PORTD
AGAIN
IN$TRI JCTIQNS
I
MAKE INPUT
I
MAKE OUTPUT
~
I
BSF TRtSB, 2
I
CLRF TRISO
YES
AGAIN
IS IT ONE?
BTFSS PORTS, 2
NO
I
JUMP TO OVER
I-
SRAOVER
I
LOAD ASCII 'Y'
I
MOVLWA'Y'
I
SEND TO PORTO
I
MOVWFPQRTD
REPEAT
I
GOTOAGAIN
I
LOAD ASCii 'N'
I
I
SEND TO PORTO
..
!
!
..
!
l
REPEAT
148
OVER
MOVLWA'N'
I
MOVWF PORTO
I
GOTOAGAIN
Example 4-7
A switch is connected to pin RB2. Write a program to check the status of SW and perform the following:
(a) If SW = 0, send letter 'N' to PORTD.
(b) IfSW = 1, send letter 'Y' to PORTD.
Use the BTFSC instruction to check the SW status. This is another version of Example
4-6 using the BTFSC instruction instead of BTFSS.
Solution:
BSF
CLRF
AGAIN BTFSC
BRA
MOVLW
MOVWF
BRA
OVER MOVLW
MOVWF
BRA
TRISB,2
TRISD
PORTB, 2
OVER
A'NI
PORTD
AGAIN
A'Y'
PORTD
AGAIN
jmake RB2 an input
;make PORTD an output port
;bit test RB2 for LOW
jit must be HIGH
i WREG = 'N' ASCII letter N
; issue WREG to PORTD
;we can use GOTO
jWREG = 'Y' ASCII letter Y
iissue WREG to PORTD
jwe can use GOTO
INSTRUCTIONS
BSF TRlse, 2
CLRFTRISD
AGAIN
BTFSC PORTa, 2
BRA OVER
MOVLWA'N'
MOVWFPORTD
BRA AGAIN
OVER
MOVLWA'Y'
MOVWFPORTD
BRA AGAIN
CHAPTER 4: PIC 110 PORT PROGRAMMING
149
Reading a single bit
We can also use the bit test instructions to read the status of a single bit and
send it to another bit or save it. This is shown in Examples 4-8 and 4-9.
Example 4-8
A switch is connected to pin RBO and an LED to pin RB7. Write a program to get the
status ofSW and send it to the LED.
Solution:
BSF
BCF
AGAIN BTFSS
GOTO
BSF
GOTO
OVER BCF
GOTO
TRISB,O
TRISB,?
PORTB,O
OVER
PORTB,?
AGAIN
PORTB,?
AGAIN
;make RBO an input
;make RB7 an output
;bit test RBO for HIGH
;it must be LOW (BRA is OK too)
iwe
can use BRA too
iwe can use BRA too
'i.'Ii'
PIC
4.7k
RBO
Switch
RB7
'1
270
17~ LED
Example 4-9
A switch is connected to pin RBO. Write a program to get the status of SW and save it
in DO of fileReg location Ox20.
Solution:
MYBITREG EQU Ox20 ;set aside loc Ox20 reg
BSF
AGAIN BTFSS
GOTO
BSF
GOTO
OVER BCF
GOTO
TRISB,O
PORTB, 0
OVER
MYBITREG,O
AGAIN
MYBITREG,O
AGAIN
;make RBO an input
;bit test RBO for HIGH
jit must be LOW (BRA is OK too)
iset bit 0 of fileReg
iwe can use BRA too
iclear bit 0 of fileReg
iwe can use BRA too
PIC
4.7k
t----iRBO
SwiOC~1
150
Reading input pins vs. LATx port
In reading a port, some instructions read the status of the port pins while
others read the status of an internal port latch called LATx. Therefore, when reading ports there are two possibilities:
I. Read the status of the input pin.
2. Read the internal latch of the LAT register.
We must make a distinction between these two categories of instructions
because confusion between them is a major source of errors in PIC programming,
especially where external hardware is concerned. We will discuss these instructions shortly. However, readers must study and understand the material on this
topic and on the internal working of ports that is given in Appendix C.2. Examine
the structure of the ports in Figure 4-8 once again. In addition to the PORTx and
TRISx register, the LATx register is the third important register associated with the
PICI8 ports.
~
DATA BUS
X
t
0
'elK
WRPORT
0
0
WRTRIS
TRIS=X
Q
'elK
v"
0
P OFF
0
DATA LATCH
X
0
0
X
0
0
0 '
N OFF
v"
TRIS LATCH
RDTRIS
TIL or
SCHMITT
TRIGGER
RDPORT
Figure 4-8. LATx Register Role in Reading a Port or Latch
Reading LATx for ports
Some instructions read the contents of an internal port latch instead of
reading the status of an external pin. Table 4-10 provides a list of these instructions. For example, consider the "COMF PORTE" instruction. The sequence of
actions taken when such an instruction is executed is as follows:
1. The instruction reads the internal latch of the LATB and brings that data into
the CPU.
CHAPTER 4: PIC 110 PORT PROGRAMMING
151
2. This data is complemented.
3. The result is rewritten back to the LATB latch.
4. The data on the pins are changed only if the TRISB bits are cleared to Os.
It is very rare that we use an instruction to read the latch register, such as
"COMF LATB, F", although it is a valid instruction.
From the above discussion, we conclude that the instructions that read the
port latch normally read a latch value, perform an operation, then rewrite it back
to the port latch. This is called read-modifY-write. To use the read-modify-write,
the port must be configured as output.
Table 4-10: Some of the Read-Modify-Write Instructions
Instruction
AOOWF
BSF
BCF
COMF
INCF
SUBWF
XORWF
fileReg,d
fileReg,bit
fileReg,bit
fileReg,d
fileReg,d
fileReg,d
fileReg,d
Function
Add WREG to f
Bit Set fileReg (set the bit: bit = 1)
Bit Clear fileReg (clear the bit: bit = 0)
Complement f
Increment f
Subtract WREG from f
Exclusive-OR WREG with f
Review Questions
I. True or false. The instruction "BSF PORTB, I" makes pin RB 1 HIGH while
leaving other pins of PORTB unchanged, if bit 1 of the TRISB bits is configured for output.
2. Show one way to toggle the pin RB7 continuously using PIC instructions.
3. Using the instruction "BTFSS PORTC, 5" assumes that bit RC5 is an
_ _ _ _ (input, output) pin.
4. Write instructions to get the status of RB2 and put it on RBO.
5. Write instructions to toggle both bits ofRD7 and ROO continuously.
CAUTION
We strongly recommend that you study Section C.2 (Appendix C)
before connecting any external hardware to your PIC system. Failure
to use the right instruction or the right connection to port pins can
damage the ports of your PIC chip.
152
SUMMARY
This chapter focused on the 110 ports of the PIC. The five ports of the
P[C1SF45S, PORTA, PORTB, PORTC, PORTD, and PORTE, were explored.
These ports can be used for input or output. All the ports have alternate functions.
The three registers associated with each port are PORTx, TRISx, and LATx. Their
role in 110 manipulation was examined. Then, I/O instructions of the PIC were
explained, and numerous examples were given. We also showed the bit-addressability of PIC ports.
PROBLEMS
SECTION 4.1: I/O PORT PROGRAMM[NG IN PIC IS
The P[C1SF45S has a DIP package of ~ins.
[n PIC lSF45S, how many pins are assigned to Vee and GND?
In the P[C1SF45S, how many pins are designated as I/O port pins?
How many pins are designated as PORTA in the 40-pin DIP package and what
are their numbers?
5. How many pins are designated as PORTB in the 40-pin DIP package and what
are their numbers?
6. How many pins are designated as PORTC in the 40-pin DIP package and what
are their numbers?
7. How many pins are designated as PORTD in the 40-pin DIP package and what
are their numbers?
S. Upon reset, all the bits of ports are configured as _ _ (input, output).
9. For the PIC1S, which register must be programmed in order to be used as simple I/O?
10. Explain the role of TRISx and PORTx in 110 operations.
11. Write a program to get S-bit data from PORTC and send it to ports PORTB and
PORTD.
12. Write a program to get 8-bit data from PORTD and send it to ports PORTB and
PORTC.
13. Which pins are for RxD and TxD?
14. Give RAM data location in the file register assigned to Ports A-C and their
TR1S registers for the PIC1SF45S.
15. Write a program to toggle all the bits ofPORTB and PORTC continuously
(a) using AAH and 55H (b) using the COMF instruction.
1.
2.
3.
4.
SECTION 4.2: I/O BIT MANIPULATION PROGRAMMING
16. Which ports of the PIC IS are bit-addressable?
17. What is the advantage of bit-address ability for PIC ports?
I S. When RB2 is accessed as a single-bit port, it is designated as _ __
19. Is the instruction "COMF PORTE" a valid instruction?
CHAPTER 4: PIC 110 PORT PROGRAMMING
153
20. Write a program to toggle RB2 and RB5 continuously without disturbing the
rest of the bits.
21. Write a program to toggle RD3, RD7, and RC5 continuously without disturbing the rest of the bits.
22. Write a program to monitor bit RC3. When it is HIGH, send 55H to PORTD.
23. Write a program to monitor the RB7 bit. When it is LOW, send 55H and AAH
to PORTC continuously.
24. Write a program to monitor the REO bit. When it is HIGH, send 99H to
PORTB. If it is LOW, send 66H to PORTe.
25. Write a program to monitor the RB5 bit. When it is HIGH, make a LOW-toHIGH-to-LOW pulse on RB3.
26. Write a program to get the status of RC3 and put it on RC4.
27. The RB4 refers to which bit ofPORTB?
28. Create a flowchart and write a program to get the statuses of RD7 and RD6 and
put them on RCO and RC7, respectively.
ANSWERS TO REVIEW QUESTIONS
SECTION 4.1: I/O PORT PROGRAMMING IN PIC18
1.
2.
3.
4.
5.
5
False
PORTB, PORTC, and PORTD
False
MOVLW ox99
MOVWF PORTB
MOVWF PORTC
6.
7.
00, TRISB
FFH, TRISB
SECTION 4.2: I/O BIT MANIPULATION PROGRAMMING
1.
True
2.
BCF TRISB,7
Hl BTG PORTB,7
BRA Hl
3.
4.
Input
AGAIN
OVER
5.
H2
154
BSF
BCF
BTFSS
BRA
BSF
BRA
BCF
BRA
TRISB,2
TRISB,O
PORTB,2
OVER
PORTB,O
AGAIN
PORTB,O
AGAIN
BCF
BCF
BTG
BTG
BRA
TRISD,O
TRISD,7
PORTD,O
PORTD,7
H2
CHAPTER 5
ARITHMETIC, LOGIC
INSTRUCTIONS, AND
PROGRAMS
OBJECTIVES
Upon completion of this chapter, you will be able to:
»
»
»
»
»
»
»
»
»
»
»
»
Define the range of numbers possible in PIC unsigned data
Code addition and subtraction instructions for unsigned data
Perform addition of BCD data
Code PIC unsigned data multiplication instructions
Code PIC programs for division
Code PIC Assembly language logic instructions AND, OR, and EX-OR
Use PIC logic instructions for bit manipulation
Use compare and skip instructions for program control
Code PIC rotate instructions and data serialization
Explain the BCD (binary coded decimal) system of data representation
Contrast and compare packed and unpacked BCD data
Code PIC programs for ASCII and BCD data conversion
155
This chapter describes all PIC arithmetic and logic instructions. Program
examples are given to illustrate the application of these instructions. In Section 5.1
we discuss instructions and programs related to addition, subtraction, multiplication, and division of unsigned numbers. Signed numbers are discussed in Section
5.2. In Section 5.3, we discuss the logic instructions AND, OR, and XOR, as well
as the COMPARE instruction. The ROTATE instruction and data serialization are
discussed in Section 5.4. In Section 5.5 we provide some real-world applications
such as BCD and ASCII conversion.
SECTION 5.1: ARITHMETIC INSTRUCTIONS
Unsigned numbers are defined as data in which all the bits are used to represent data, and no bits are set aside for the positive or negative sign. This means
that the operand can be between 00 and FFH (0 to 255 decimal) for 8-bit data.
Addition of unsigned numbers
In order to add numbers together in the PIC, the WREG register must be
involved. One fonn of the ADD instruction is
ADDLW
K
;WREG
=
WREG + K
The sum is stored in the WREG register. The instruction could change any
of the C, ~C, Z, N, or OV bits of the status register, depending on the operands
involved. The effect of the AOOLW instruction on Nand OV is discussed in
Section 5.3 because these bits are relevant mainly in signed number operations.
Look at Example 5-1.
Example 5-1
Show how the flag register is affected by the following instructions.
MOVLW OxFS
ADDLW OxB
;WREG
;WREG
FS hex
FS + DB
00 and C = 1
Solution:
FSH
1111 0101
+ OBH
+ 0000 1011
100H
0000 0000
After the addition, register WREG contains 00 and the flags are as follows:
C = 1 because there is a carry out from 07.
Z = 1 because the result in WREG is zero.
DC = 1 because there is a carry from 03 to 04.
ADDWF and addition of individual bytes
Instruction "ADDWF fileReg, d" allows the addition ofWREG and
individual bytes residing in RAM locations of the file register. Notice that WREG
must be involved because memory-to-memory arithmetic operations are never
156
allowed in PIC Assembly language. To calculate the sum of any number of
operands, the carry flag should be checked after the addition of each operand.
Example 5-2 uses location 7 of the file register to accumulate carries as the
operands are added to WREG. In Chapter 6, the loop version of this program will
be shown for any number of bytes.
Example 5-2
Assume that file register RAM locations 40-43H have the following hex values. Write
a program to find the sum of the values. At the end of the program, location 6 of the file
register should contain the low byte and location 7 the high byte of the sum.
40
41
42
43
(7D)
(EB)
(C5)
(5B)
Solution:
L_Byte EQU
H_Byte EQU
N 1
N 2
N 3
N 4
MOVLW
MOVWF
ADDWF
BNC
INCF
ADDWF
BNC
INCF
ADDWF
BNC
INCF
ADDWF
BNC
INCF
MOVWF
Ox6
ox7
;assign RAM location 6 to L_byte of sum
;assign RAM location 7 to H_byte of sum
a
;clear WREG (WREG = 0)
;H_Byte = a
;WREG = a + 7DH = 7DH , C = a
;branch if C = 0
;increment (now H_Byte = 0)
;WREG = 7D + EB = 68H and C = 1
H_Byte
Ox40,W
N 1
H_Byte,F
Ox41,W
N 2
H_Byte,F
Ox42,W
N 3
H_Byte
Ox43,W
N 4
H_Byte,F
L_Byte
;C = 1, increment (now H_Byte = 1)
;WREG = 68 + C5 = 2D and C = 1
;C = 1, increment (now H_Byte = 2)
;WREG = 2D + 5B
88H and C = a
; (H_Byte = 2)
;now L_Byte = 88h
At the end the fileReg location 6 = (8B), and location 7 = (02) because 7D + EB + C5
+ 5B + 30 = 28BH. We can use the register indirect addressing mode to do this program much more efficiently. Chapter 6 shows how to do that.
ADDWFC and addition of 16-bit numbers
When adding two l6-bit data operands, we need to be concerned with the
propagation of a carry from the lower byte to the higher byte. This is called multibyte addition to distinguish it from the addition of individual bytes. The instruction ADDWFC (ADDW and fileReg with carry) is used on such occasions.
CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS
157
For example, look at the addition of 3CE7H + 3BSDH, as shown next.
1
+
3C E7
lJLJill
78 74
When the first byte is added, there is a carry (E7 + SD = 74, CY = I). The
carry is propagated to the higher byte, which results in 3C + 3B + I = 7S (all in
hex). Example 5-3 shows the above steps in a PIC program.
Example 5-3
Write a program to add two 16-bit numbers. The numbers are 3CE7H and 3BSDH.
Assume that fileReg location 6 = (SD) and location 7 = (3B). Place the sum in fileReg
locations 6 and 7; location 6 should have the lower byte.
Solution:
; location 6
; location 7
MOVLW OxE7
ADDWF Ox6,F
MOVLW Ox3C
ADDWFC Ox7,F
(8D)
(3B)
;load the low byte now (WREG = E7H)
;F = W + F = E7 + 8D = 74 and CY = 1
;load the high byte (WREG = 3CH)
;F = W + F + carry, adding the upper byte
;with Carry from lower byte
;F = 3C + 3B + 1 = 78H (all in hex)
Notice the use of ADDWF for the lower byte and ADDWFC for the higher byte.
BCD (binary coded decimal) number system
BCD stands for binary coded decimal. BCD is needed because in everyday
life we use the digits 0 to 9 for numbers, not binary or hex numBCD
bers. Binary representation of 0 to 9 is called BCD (see Figure Digi t
0000
a
5-1). In computer literature, one encounters two terms for BCD
1
0001
numbers: (I) unpacked BCD, and (2) packed BCD. We describe
0010
2
0011
3
each one next.
Unpacked BCD
4
5
6
7
8
9
0100
0101
0110
0111
1000
1001
In unpacked BCD, the lower 4 bits of the number represent the BCD number, and the rest of the bits are O. Example:
"0000 100 I" and "0000 0101" are unpacked BCD for 9 and 5,
respectively. Unpacked BCD requires I byte of memory, or an
Figure 5-1. BCD Code
S-bit register, to contain it.
Packed BCD
In packed BCD, a single byte has two BCD numbers in it: one in the lower
4 bits, and one in the upper 4 bits. For example, "0101 1001" is packed BCD for
59H. Only I byte of memory is needed to store the packed BCD operands. Thus
158
one reason to use packed BCD is that it is twice as efficient in storing data.
There is a problem with adding BCD numbers, which must be corrected.
The problem is that after adding packed BCD numbers, the result is no longer
BCD. Look at the following.
MOVLW Ox17
ADDLW Ox28
Adding these two numbers gives 0011 IIII B (3FH), which is not BCD! A
BCD number can only have digits from 0000 to 1001 (or 0 to 9). In other words,
adding two BCD numbers must give a BCD result. The result above should have
been 17 + 28 = 45 (01000101). To correct this problem, the programmer must add
6 (0 II 0) to the low digit: 3F + 06 = 45H. The same problem could have happened
in the upper digit (for example, in 52H + 87H = D9H). Again, 6 must be added to
the upper digit (D9H + 60H = 139H) to ensure that the result is BCD (52 + 87 =
139). This problem is so pervasive that most microprocessors such as the PIC 18
have an instruction to deal with it. In the PIC 18 instruction "DAW" is designed to
correct the BCD addition problem. This is discussed next.
DAW instruction
The DAW (decimal adjust WREG) instruction in the PIC 18 is provided to
correct the aforementioned problem associated with BCD addition. The mnemonic "DAW" works only with an operand in the WREG register. The DAW instruction
will add 6 to the lower nibble or higher nibble if needed; otherwise, it will leave
the result alone. The following example will clarify these points.
MOVLW Ox47
ADDLW Ox25
DAW
=
;WREG = 47H first BCD operand
;hex(binary) addition (WREG = 6CH)
;adjust for BCD addition (WREG = 72H)
After the program is executed, register WREG will contain 72H (47 + 25
72). Note that the "DAW" instruction works only on WREG.
Summary of DAW action
After any instruction,
I. If the lower nibble (4 bits) is greater than 9, or if DC = I, add 0110 to the lower
4 bits.
2. If the upper nibble is greater than 9, or ifC = I, add 0110 to the upper 4 bits.
In reality there is no use for the DC (auxiliary carry) flag bit other than for
BCD addition and correction.
MOVLW Oxoo
ADDLW Ox09
ADDLW Ox08
DAW
;WREG = 0
Ox09
;WREG
Oxll, DC = 1
;WREG
Ox17 (9 + 8 = 17)
i WREG
As another example, examine the case of adding 55H and 77H. This will
result in CCH, which is incorrect as far as BCD is concerned.
CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS
159
Hex
BCD
57
+ 77
CE
+ QQ
134
0101
0111
+
1100
+ 0110
1 0011
0111
0111
1110
0110
0100
Note C
=
1
Note that unlike other processors, the prc does not require the use of arithmetic instructions prior to execution of the "DAW" instruction. Look at the following case where no arithmetic instruction is used.
MOVLW oxoc
DAW
:WREG
:WREG
00001100
00001100 + 00000110
00010010
Ox12
Examine Example 5-4.
Example 5-4
Assume that 5 BCD data items are stored in RAM locations starting at 40H, as shown
below. Write a program to find the sum of all the numbers. The result must be in BCD.
40
41
42
43
(71)
(88)
(69)
(97 )
EQU
EQU
Ox6
Ox7
;assign RAM loc 6 to L_Byte of sum
iassign RAM loc 7 to H_Byte of sum
0
iclear WREG (WREG = 0)
:H_Byte = 0
:WREG = 0 + 7lH = 71H, C
:WREG = 71H
ibranch i f C = 0
Solution:
L_Byte
H_Byte
N 1
N 2
N 3
N 4
MOVLW
MOVWF
ADDWF
DAW
BNC
INCF
ADDWF
DAW
BNC
INCF
ADDWF
DAW
BNC
INCF
ADDWF
DAW
BNC
INCF
MOVWF
H_Byte
Ox40,W
N 1
H_Byte,F
Ox41,W
N 2
H_Byte,F
Ox42,W
N 3
H_Byte
Ox43,W
N 4
H_Byte,F
L_Byte
;WREG
;WREG
0
71 + 88
F9H
59H AND C = 1
:C = 1, increment (now H_Byte = 1)
:WREG
59 + 69 = C2 and Carry = 0
;WREG = 28 and C = 1
:C = 1, increment (now H Byte = 2)
:WREG
28 + 97 = BFH and C = 0
25 and C = 1
:WREG
i (now H_Byte = 3)
; Now L_Byte = 25H
After this code executes, fileReg location 6 = (03), and WREG = 25 because 71 + 88
+ 69 + 97 = 325H. We can use the register indirect addressing mode and looping to do
this program much more efficiently. Chapter 6 shows how to do that.
160
Subtraction of unsigned numbers
In many microprocessors, there are two different instructions for subtraction: SUB and SUBB (subtract with borrow). In the PIC18 we have four instructions for subtraction: SUBLW, SUBWF, SUBWFB, and SUBFWB. The last two
are subtract with borrow. Notice that we use the C (carry) flag for the borrow. We
now will examine each of these commands.
SUBLW K (WREG = K - WREG)
In subtraction, the PIC microcontrollers (indeed, all modem CPUs) use the
2's complement method. Although every CPU contains adder circuitry, it would be
too cumbersome (and take too many transistors) to design separate subtracter circuitry. For this reason, the PIC uses adder circuitry to perform the subtraction command. Assuming that the PIC is executing a simple subtract instruction and that C
= 0 prior to the execution of the instruction, one can summarize the steps of the
hardware of the CPU in executing the SUBLW instruction for unsigned numbers
as follows:
l. Take the 2's complement of the subtrahend (WREG operand).
2. Add it to the minuend (K operand).
These two steps are performed for every SUB instruction by the internal
hardware of the CPU, regardless of the source of the operands, provided that the
addressing mode is supported. It is after these two steps that the result is obtained
and the flags are set. Example 5-5 illustrates the two steps.
Example 5-5
Show the steps involved in the following.
MOVLW Ox23
SUBLW ox3F
;load 23H into WREG (WREG
;WREG ~ 3F - WREG
23H)
Solution:
K
- WREG
3F
23
lC
0011 1111
0010 0011
0011 1111
1101 1101 (2's complement)
1 0001 1100
C ~ 1, D7 ~ N ~ 0 (result is positive)
+
The flags would be set as follows: C = 1, N = 0 (notice that D7 is the negative flag). The
programmer must look at the N (or C) flag to determine ifthe result is positive or negative.
After the execution of SUB, ifN = 0 (or C = I), the result is positive; ifN
= I (or C = 0), the result is negative and the destination has the 2's complement of
the result. Normally, the result is left in 2's complement, but the NEGF (negate,
which is 2's complement) instruction can be used to change it. Another SUB
instruction in PIC is SUBWF (Destination = fileReg - WREG). This is shown in
Example 5-6 along with the NEGF instruction.
CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS
161
Example 5-6
Write a program to subtract 4C - 6E.
Solution:
MYREG EQU Ox20
MOVLW Ox4C
MOVWF MYREG
MOVLW Ox6E
SUBWF MYREG,W
BNN
NEXT
NEGF WREG
NEXT MOVWF MYREG
;load WREG (WREG
4CH)
;MYREG = 4CH
;WREG
6EH
;WREG = MYREG - WREG. 4C - 6E = DE, N = 1
;if N = a (C = 1), jump to NEXT target
;take 2'8 complement of WREG
isave the result in MYREG
The following are the steps after the SUBWF instruction:
4C
-QJ>
0100 1100
0110 1110
-22
2' 8 comp =
0100 1100
1001 0010
1101 1110
After SUBWF, we have N = I (or C = 0), and the result is negative, in 2's complement.
Then it falls through and NEGF will be executed. The NEGF instruction will take the
2's complement, and we have MYREG = 22H.
SUBWFB (dest = fi/eReg - W - Borrow) subtract with borrow
This instruction is used for multibyte numbers and will take care of the borrow of the lower byte. If C = 0 prior to executing the SUBWFB instruction, it also
subtracts I from the result. See Example 5-7.
SUBFWB (dest = WREG - fi/eReg - Borrow)
This instruction is also used for multibyte numbers and will take care of the
borrow of the lower byte. Notice the difference between SUBWFB and SUBFWB.
See Appendix A for the description of these two instructions.
Example 5-7
Write a program to subtract two 16-bit numbers. The numbers are 2762H - 1296H.
Assume fileReg location 6 = (62) and location 7 = (27). Place the difference in fileReg
locations 6 and 7; loc 6 should have the lower byte.
Solution:
loc 6
loc 7
(62)
(27)
MOVLW Ox96
SUBWF Ox6,F ;F
MOVLW Ox12
SUBWFB OX7,F
;load the low byte (WREG = 96H)
F - W = 62 - 96 = CCH, C = borrow = 0, N
;load the high byte (WREG = 12H)
;F
F - W - b, sub byte with the borrow
;F = 27 - 12 - 1 = 14H
=
1
After the SUBWF, loc 6 has = 62H - 96H = CCH and the carry flag is set to 0, indicating there is a borrow (notice, N = I). Because C = 0, when SUBWFB is executed the
fileReg location 7 has = 27H - 12H - I = 14H. Therefore, we have 2762H - 1296H =
14CCH.
162
The C flag in subtraction for PIC
Notice that the PIC 18 is different from other CPU's such as the x86 and the
8051 when it comes to the carry flag in subtract operations. In those CPUs, the
carry is inverted by the CPU itself and we examine the C flag to see if the result
is positive or negative. In the PlCI8, ifC = 0, the result is negative. That is the reason in subtract with borrow we have F = F - W - b. Use the MPLAB simulator to
gain additional insight into this important issue.
Multiplication of unsigned numbers
The PIC supports byte-by-byte multiplication only. The bytes are assumed
to be unsigned data. The syntax is as follows:
MULLW
K
;W x K and 16-bit is result is in PRODH:PRODL
In byte-by-byte multiplication, one of the operands must be in the WREG
register, and the second operand must be a literal K value. After multiplication, the
result is in the special function registers PRODH and PRODL; the lower byte is in
PRODL, and the upper byte is in PRODH. See Table 5-1. The following example
multiplies 25H by 65H.
MOVLW Ox25
MULLW Ox65
;load 25H to WREG (WREG = 25H)
;25H * 65H = E99 where
;PRODH = OEH and PRODL = 99H
Table 5-1: Unsigned Multiplication Summary (MULLW K)
Multiplication Byte 1
Byte x Byte
WREG
Byte2
K
Result
PRODH - high byte, PRODL - low byte
Note: Multiplication of operands larger than 8-bit takes some manipulation.
Division of unsigned numbers
There is no single instruction for the division of bytelbyte numbers in the
PIC 18. We can write a program to perform division by repeated subtraction. In
dividing a byte by a byte, the numerator is placed in a fileReg and the denominator is subtracted from it repeatedly. The quotient is the number of times we subtracted and the remainder is in fileReg upon completion. See the following
example.
NUM
MYQ
MYNMB
MYDEN
B1
EQU
EQU
EQU
EQU
CLRF
MOVLW
MOVWF
MOVLW
INCF
SUBWF
BC
DECF
ADDWF
Ox19
Ox20
D I 9S'
iset aside fileReg
D'10'
MYQ
MYNMB
NUM
MYDEN
MYQ,F
NUM,F
B1
MYQ,F
NUM,F
; quotient = 0
;WREG = 95
;Dumerator = 95
iWREG = denominator = 10
;increment quotient for every 10 subtr
;subtract 10 (F = F - W)
;keep doing it until C = 0
ionce too many
;add 10 back to get remainder
CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS
163
An application for division
Sometimes an ADC (analog-to-digital converter) is connected to a port and
the ADC represents some quantity such as temperature or pressure. The 8-bit ADC
provides data in hex in the range of OO-FFH. This hex data must be converted to
decimal. We do that by dividing it by lO repeatedly, saving the remainders, as
shown in Example 5-8.
Example 5-8
Assume that file register location Oxl5 has value FD (hex). Write a program to convert
it to decimal. Save the digits in locations Ox22, Ox23, and Ox24, where the least-significant digit is in Ox22
Solution:
#include <PI8F458.INC>
;PIC Assembly Language Program for division (by repeated subtraction)
; (Byte/Byte)
NUME
QU
RMND L
RMND M
RMND H
MYNUM
MYDEN
D 1
D 2
HERE
EQU
Ox15
Ox20
EQU
EQU
Ox22
EQU
Ox23
EQU
Ox24
EQU
OxFD
D' 10 1
EQU
ORG
OH
MOVLW MYNUM
MOVWF NUME
MOVLW MYDEN
CLRF QU, F
INCF QU,F
SUBWF NUME
BC
D 1
ADDWF NUME
DECF QU, F
MOVFF NUME, RMND _ L
MOVFF QU,NUME
CLRF QU
INCF QU,F
SUBWF NUME
BC
D 2
ADDWF NUME
DECF QU,F
MOVFF NUME,RMND_M
MOVFF QU,RMND_H
GOTO HERE
END
iRAM location for NUME
iRAM location for quotient
;FDH = 253 in decimal
;253/10
istart at address 0
;WREG
=
253, the numerator
iload numerator
iWREG = 10, the denominator
iclear quotient
;increment quotient for every sub
i8Ub WREG from NUME value
;if positive go back (C = 1 for positive)
ionce too many,
this is our first digit
ionce too many for quotient
isave the first digit
;repeat the process one more time
;clear QU
i8Ub WREG from NUME value
; (C = 1 for positive)
ionce too many
; 2nd digit
;3rd digit
jstay here forever
;end of a8m source file
To convert a single decimal digit to ASCII format, we OR it with 30H, as shown in
Sections 6.4 and 6.5.
164
Example 5-9
Analyze the program in Example 5-8 for a numerator of253.
Solution:
To convert a binary (hex) value to decimal, we divide it by 10 repeatedly until the quotient is less than 10. After each division the remainder is saved. In the case of an 8-bit
binary, such as FDH, we have 253 decimal, as shown below.
253/10
25/10
Quotient
25
2
Remainder
3 (low digiti
5 (middle digiti
2 (high digiti
Therefore, we have FDH = 253. In order to display this data, it must be converted to
ASCII, which is described in a later section in this chapter.
Review Questions
1. In multiplication of two bytes in the PIC 18, we can place one byte in register
____.and for the other one we can use value K.
2. In unsigned byte-by-byte multiplication, the product will be placed in register(s) _ _ __
3. Is "MULLW F" a valid PICIS instruction? Explain your answer.
4. In PICI8, the largest two numbers that can be multiplied are
and
5. True or false. The DAW instruction works on WREG only.
6. Is "DAW fileReg, d" a valid PICI8 instruction? Explain your answer.
7. The instruction "ADDLW K" places the sum in _ _ _ __
8. Why is the following ADD instruction illegal? "ADDLW f ileReg"
9. Rewrite the instruction above to add WREG to the fileReg.
10. The instruction "ADDWFC fileReg, W" places the sum in ______
11. Find the value of the DC and C flags in each of the following.
(al MOVLW Ox4F
ADDLW OxB1
(bl
MOVLW Ox9C
ADDLW Ox63
12. Show how the CPU would subtract 05H from 43H.
13. If C = 1, WREG = 95H, and fileReg = 4FH prior to the execution of
"SUBFWB fileReg, F", what will be the contents ofWREG and file Reg
after the subtraction?
CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS
165
SECTION 5.2: SIGNED NUMBER CONCEPTS AND
ARITHMETIC OPERATIONS
All data items used so far have been unsigned numbers, meaning that the
entire 8·bit operand was used for the magnitude. Many applications require signed
data. In this section the concept of signed numbers is discussed along with related
instructions. If your applications do not involve signed numbers, you can bypass
this section.
Concept of signed numbers in computers
In everyday life, numbers are used that could be positive or negative. For
example, a temperature of 5 degrees below zero can be represented as -5, and 20
degrees above zero as +20. Computers must be able to accommodate such numbers. To do that, computer scientists have devised the following arrangement for
the representation of signed positive and negative numbers: The most significant
bit (MSB) is set aside for the sign (+ or -), while the rest of the bits are used for
the magnitude. The sign is represented by 0 for positive (+) numbers and 1 for negative (-) numbers. Signed byte representation is discussed below.
Signed 8-bit operands
In signed byte operands, D7
(MSB) is the sign and DO to D6 are set
aside for the magnitude of the number. If
magnitude
D7 = 0, the operand is positive, and ifD7
= I, it is negative. The N flag in the sta- '--_ _ _ _ _ _ _ _ _ _ _ _ _--'
Figure 5-2. 8-Bit Signed Operand
tus register is the D7 bit.
Positive numbers
The range of positive numbers that can be
represented by the format shown in Figure 5-2 is
o to +127. If a positive number is larger than
+ 127, a 16-bit operand must be used. Because the
PIC 18 does not support 16-bit data, we will not
discuss it.
a
+1
0000 0000
0000 0001
+5
0000 0101
+127
0111 1111
Negative numbers
For negative numbers, D7 is I; however, the magnitude is represented in
its 2 's complement. Although the assembler does the conversion, it is still important to understand how the conversion works. To convert to negative number representation (2's complement), follow these steps:
1. Write the magnitude of the number in 8-bit binary (no sign).
2. Invert each bit.
3. Add 1 to it.
Examples 5-10, 5-11, and 5-12 demonstrate these three steps.
166
Example 5-10
Show how the PIC would represent -5.
Solution:
Observe the following steps.
1.
2.
3
0000 0101
1111 1010
1111 1011
5 in 8-bit binary
invert each bit
add 1 (which becomes FB in hex)
Therefore, -5 = FBH, the signed number representation in 2's complement for -5. The
D7 = N = 1 indicates that the number is negative.
Example 5-11
Show how the PIC would represent -34H.
Solution:
Observe the following steps.
1.
2.
3
0011 0100
1100 1011
1100 1100
34H given in binary
invert each bit
add 1 (which is CC in hex)
Therefore, -34 = CCH, the signed number representation in 2's complement for 34H.
The D7 = N = 1 indicates that the number is negative.
Example 5-12
Show how the PIC would represent -128.
Solution:
Observe the following steps.
1.
2.
3
1000 0000
0111 1111
1000 0000
128 in 8-bit binary
invert each bit
add 1 (which becomes 80 in hex)
Therefore, -128 = 80H, the signed number representation in 2's complement for -128.
The D7 = N = 1 indicates that the number is negative. Notice that 128 (binary
10000000) in unsigned representation is the same as signed -128 (binary 10000000).
CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS
167
From the examples above, it is clear that the range of byte-sized negative
numbers is -1 to -128. The following lists byte-sized signed number ranges:
Decimal
-128
-127
-126
Binary
1000 0000
1000 0001
1000 0010
-2
-1
+1
+2
1111
1111
0000
0000
0000
+127
0111 1111
Hex
80
81
82
.. , ......
a
1110
1111
0000
0001
0010
FE
FF
00
01
02
.........
7F
The above explains the mystery behind the relative address of -128 to + 127
in the BNZ and other conditional branch instructions discussed in Chapter 3.
Overflow problem in signed number operations
When using signed numbers, a serious problem arises that must be dealt
with. This is the overflow problem. The PIC indicates the existence of an error by
raising the OV (overflow) flag, but it is up to the programmer to take care of the
erroneous result. The CPU understands only Os and I s and ignores the human convention of positive and negative numbers. What is an overflow? If the result of an
operation on signed numbers is too large for the register, an overflow has occurred
and the programmer must be notified. Look at Example 5-13.
Example 5-13
Examine the following code and analyze the result, including the N and OV flags.
MOVLW +D' 96 '
ADDLW +D'70'
; WREG
;WREG
;WREG
0110 0000
(+96) + (+70) = 1010 0110
A6H = -90 decimal, INVALID!!
Solution:
+96
+ +70
+ 166
0110 0000
0100 0110
1010 0110
N
=
1
(negative)
and OV
=
1. Sum
=
-90
According to the CPU, the result is negative (N = I), which is wrong. The CPU sets OV
I to indicate the overflow error. Remember that the N flag is the D7 bit. If N = 0, the
sum is positive, but if N = I, the sum is negative.
=
In Example 5-13, +96 is added to +70 and the result, according to the CPU,
was -90. Why? The reason is that the result was larger than what WREG could
contain. Like all other 8-bit registers, WREG could only contain up to + 127. The
designers of the CPU created the overflow flag specifically for the purpose of
informing the programmer that the result of the signed number operation is erroneous. The N flag is D7 of the result. IfN = 0, the sum is positive (+) and ifN =
1, then the sum is negative.
168
When is the OV flag set?
In 8-bit signed number operations, OV is set to 1 if either of the following
two conditions occurs:
1. There is a carry from 06 to 07 but no carry out of 07 (C = 0).
2. There is a carry from 07 out (C = 1) but no carry from 06 to 07.
In other words, the overflow flag is set to 1 if there is a carry from 06 to
07 or from 07 out, but not both. This means that if there is a carry both from 06
to 07 and from 07 out, OV = O. In Example 5-13, because there is only a carry
from 06 to 07 and no carry from 07 out, OV = 1. Study Examples 5-14, 5-15, and
5-16 to understand the overflow flag in signed arithmetic.
Example 5-14
Observe the following, noting the role of the OV and N flags:
MOVLW -D ' 128'
ADDLW -D'2'
;WREG = 1000 0000 (WREG
;W = ( -128) + (-2)
;W = 1000000 + 11111110
;N = 0, W = 7EH = +126,
=
80H)
=
0111 1110,
invalid
Solution:
-128
- 2
- 130
1000 0000
1111 111Q
0111 1110
+
N
=
0 (positive)
and OV
=
1
According to the CPU, the result is + 126, which is wrong, and OV = 1 indicates that.
Example 5-15
Observe the following, noting the OV and N flags:
MOVLW -D'2'
ADDLW -Drs'
WREG = 1111 1110 (WREG = FEH)
jWREG = (-2) + ( -5) = -7 or F9H
jcorrect, since OV = 0
i
Solution:
-2
±-.2
-
7
l1ll 1110
1111 1011
1111 1001
and OV
=
0 and N
=
l.
Sum is negative
According to the CPU, the result is -7, which is correct, and the OV flag indicates that.
(OV= 0).
CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS
169
Example 5-16
Examine the following, noting the role of the OV and N flags:
MOVLW +D'7'
ADDLW +D' 18
I
;WREG = 0000 0111
;W
(+7) + (+18)
;W = 00000111 + 00010010 = 0001 1001
;W = (+7) + (+18) = +25, N = 0, positive and
icorrect,
OV =
0
Solution:
+ 7 0000 0111
+ +18 0001 0010
+25 0001 1001
N
=
0
(positive 25) and ov
=
0
According to the CPU, this is +25, which is correct and OV = 0 indicates that.
From the above examples, we conclude that in any signed number addition,
OV indicates whether the result is valid or not. If OV = I, the result is erroneous;
if OV = 0, the result is valid. We can state emphatically that in unsigned number
addition, we must monitor the status of C (carry flag), and in signed number addition, the OV (overflow) flag must be monitored by the programmer. In the PIC,
instructions such as BNC and BC allow the program to branch right after the addition of unsigned numbers, as we saw in Section 5.1. There are also the BOV and
the BNOV instructions for the OV flag that allow us to correct the signed number
error. We also have two branch instructions for the N flag (negative), BN and
BNN.
Instructions to create 2's complement
The PICI8 does have a special instruction to make the 2's complement of
a number. It is called NEG fileReg (negate fileReg) and is covered in the next section.
Review Questions
I.
2.
3.
4.
5.
170
In an 8-bit operand, bit _ _ is used for the sign bit.
Convert -16H to its 2's complement representation.
The range of byte-sized signed operands is to +
Show +9 and -9 in binary.
Explain the difference between a carry and an overflow.
SECTION 5.3: LOGIC AND COMPARE INSTRUCTIONS
Apart from I/O and arithmetic instructions, logic instructions are some of
most widely used instructions. In this section we cover Boolean logic instructions
such as AND, OR, Exclusive-OR (XOR), and complement. We will also study the
compare instruction.
AND
ANDLW K
;WREG
~
WREG AND K
This instruction will perform a logical AND
on the two operands and place the result in WREG.
There is also the "ANDWF
f ileReg,
d"
instruction where the destination can be WREG or
fileReg. The fileReg operand can be any register in
the data RAM file register. See Appendix A. The
AND instruction will affect the Z and N flags. N is
D7 of the result, and Z = 1 if the result is zero. The
AND instruction is often used to mask (set to 0)
certain bits of an operand. See Example 5-17.
Logical AND Function
Inputs
Output
;;X~~=iY~~",;X;;;;.A;;N.;,D;;;;..,;Y;;...
0
0
1
1
X
y
0
1
0
0
0
0
=0- X AND Y
Example 5-17
Show the results of the following.
MOVLW
ANDLW
Ox35
OxOF
;WREG ~ 35H
;W ~ W AND OFH (now W
05)
Solution:
35H
OFH
05H
0 0 1 1 0 1 0 1
0 0 0 0 1 1 1 1
0 0 0 0 0 1 0 1
;35H AND OFH
OSH,
Z
0, N
=
a
OR
IORLW K
;WREG
~
WREG Inclusive-OR K
This instruction will perform a logical OR on
the two operands and place the result in WREG.
There is also an "IORWF fileReg, d" instruction where the destination can be WREG or fileReg.
The fileReg operand can be any register in the data
RAM file register. See Appendix A. The OR instruction will affect the Z and N flags. N is D7 of the
result and Z = 1 if the result is zero. The OR instruction can be used to set certain bits of an operand to 1.
See Example 5-18.
Logical OR Function
Inputs
Output
X
0
0
XORY
0
1
I
1
Y
0
1
0
1
~=D-XORY
CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS
171
Example 5-18
(a) Show the results of the following:
MOVLW Ox04
IORLW Ox30
;WREG = 04
;now WREG = 34H
(b) Assume that Port B bit RB2 is used to control an outdoor light, and bit RB5 to control a light inside a building. Show how to tum "on" the outdoor light and tum "off' the
inside one.
Solution:
(a)
04H
30H
34H
0000 0100
0011 0000
0011 0100
04 OR 30
o
34H, Z
and N
=
0
(b)
BCF
BCF
MOVLW
IORWF
MOVLW
ANDWF
TRISB,2
TRISB,5
B'00000100'
PORTB,F
B' 11011111'
PORTB,F
imake RB2 an output
imake RB5 an output
;D2 = 1
1 only
i make RB2
iDS = 0
imask RB5
0 only
Of course, the above method is unnecessary in PIC, since we can manipulate individual
bits using bit-oriented operations. This is shown in Section 6.4.
EX-OR
XORLW K
;WREG
=
WREG XOR K
This instruction will perform a logical EX-OR on the two operands and
place the result in WREG. There is also an "XORWF fileReg, d" instruction
where the destination can be WREG or fileReg. The
fileReg operand can be any register in the data RAM Logical XOR Function
file register. See Appendix A. The EX-OR instruction will affect the Z and N flags. N is D7 of the
result and Z = I if result is zero. See Examples 5-19
and 5-20.
EX-OR can also be used to see if two registers have the same value. "XORWF fileReg, w"
will EX-OR the WREG register and a fileReg location, and put the result in WREG. If both registers
have the same value, 00 is placed in WREG. Then we
can use the BZ instruction to make a decision based
on the result. See Examples 5-20 and 5-21.
172
~I;;;n,!;p;;;u;;ts~===~O;;,u;;t;!;p;;;u;;t====
A
B
o
o
o
o
1
1
1
o
I
I
AXORB
o
~~AXORB
Another widely used application of EX-OR
operand.
MOVLW OxFF
XORWF PORTC,F
IS
to toggle the bits of an
;WREG = FFH
;EX-OR PORTC with 1111 1111 will
;change all the bits of Port C to
iopposite
Example 5-19
Show the results of the following:
MOVLW Ox54
XORLW Ox78
Solution:
54H
78H
2CH
0 1 0 1 0 1 0 0
0 1 1 1 1 0 0 0
0 0 1 0 1 1 0 0
54H XOR 78H = 2CH,
Z = 0, N = 0
Example 5-20
The EX-OR instruction can be used to test the contents of a register by EX-ORing it
with a known value. In the following code, we show how EX-ORing value 45H with
itself will raise the Z flag:
OVER
MOVF PORTB,W
XORLW Ox45
BNZ
OVER
;get a byte from PORTB into WREG
;branch if not zero
Solution:
45H
45H
00
01000101
01000101
00000000
EX-ORing a number with itself sets it to zero with Z = 1. We can use the BNZ instruction to
make the decision. EX-ORing with any other number will result in a non-zero value.
Example 5-21
Read and test PORTB to see whether it has value 45H. If it does, send 99H to PORTC;
otherwise, it stays cleared.
Solution:
CLRF
CLRF
SETF
MOVLW
XORWF
BNZ
MOVLW
MOVWF
EXIT: ...
TRISC
PORTC
TRISB
Ox45
PORTB,W
EXIT
Ox99
PORTC
;Port C = output
jPort C = 00
; Port B = input
;EX-OR with Ox45, Z = 1 i f yes
ibranch if PORTB has value other than 0
; Port C = 99h
CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS
173
COMF (complement tileReg)
Logical Inverter
This instruction complements the contents of Input
a file register. The complement action changes the Os
x
to I s and the I s to Os. This is also called 1 s compleo
ment.
Output
NOT X
o
I
CLRF
MOVLW
MOVWF
COMF
TRI8B
Ox55
PORTB
PORTB,F
;Port B
Output
;now PORTB
x ---{>o--- NOT X
AAH
NEGF (negate tileReg)
This instruction takes the 2's complement of a file register. See Example
5-22.
Example 5-22
Find the 2's complement of the value 85H. Note that 85H is -123.
Solution:
MYREG EQU Ox10
MOVLW Ox8S
MOVWF MYREG
NEGF MYREG
8SH
1'8
2'8
comp
1000 0101
0111 1010
+ 1
0111 1011
7BH
Compare instructions
The PIC 18 has three instructions for the compare operation, as shown in
Table 5-2. These instructions compare a value in the file register with the contents
of the WREG register, and make decisions based on whether fileReg is greater
than, equal to, or less than WREG. The compare instruction is really a subtraction,
except that the values of the operands do not change. In PIC 18, flags are not
changed either after the compare instruction. It must be emphasized again that in
compare instructions, the operands are not affected, regardless of the result of the
comparison. We describe each of the instructions in Table 5-2 with an example.
Table 5-2: PIC18 Compare Instructions
CPFSGT Compare FileReg with WREG, skip if greater than FileReg > WREG
CPFSEQ Compare FileReg with WREG, skip if egual
FileReg = WREG
CPFSLT Compare fileReg with WREG, skip if less than
FileReg < WREG
Note: These instructions have no effect on the flag bits of the status register. Also the values in
tileReg and WREG remain unchanged.
CPFSGT instruction
The CPFSGT compares a fileReg with WREG and skips the next instruction if fileReg is greater than WREG (F > W). See Figure 5-3 and Example 5-23.
174
INSTRUCTIONS
AGAIN
CPFSGT COUNT
SKIP THE
NEXT
INSTRUCTION
GOTOAGAIN
MOVWFPORTB
MOVE DATA
Figure 5-3. Flowchart for CPFSGT
Example 5-23
Write a program to find the greater of the two values 27 and 54, and place it in file register location Ox20.
Solution:
VAL 1 EQU
VAL 2 EQU
GREG EQU
MOVLW
MOVWF
MOVLW
CPFSGT
MOVWF
D'27'
D'54'
Ox20
VAL 1
GREG
VAL 2
GREG
GREG
;WREG
27
; GREG
27
;WREG
54
;skip if GREG> WREG
;place the greater in GREG
CPFSEQ instruction
The CPFSEQ compares a fileReg with WREG and skips the next instruction if they are equal (F = W). See Example 5-24 and Figure 5-4.
Example 5-24
Write a program to monitor PORTD continuously for the value 63H. It should stop monitoring only if PORTD = 63H.
Solution:
BACK
SETF
MOVLW
CPFSEQ
BRA
TRISD
Ox63
PORTD
BACK
; PORTD = input
;WREG = 63H
;skip BRA instruction if PORTD
CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS
63H
175
INSTRUCTIONS
AGAIN
CPFSEQ COUNT
SKIP THE
NEXT
INSTRUCTION
REPEAT
GOTOAGAIN
MOVWF PORTS
MOVE DATA
Figure 5-4. Flowchart for CPFSEQ
CPFSLT instruction
The CPFSLT compares a fileReg with WREG and skips the next instruction if fileReg is less than WREG (F < W). See Example 5-25 and Figure 5-5.
Example 5-25
Write a program to find the smaller of the two values 27 and 54, and place it in file register location 0x20.
Solution:
VAL 1 EQU
VAL 2 EQU
LREG EQU
MOVLW
MOVWF
MOVLW
CPFSLT
MOVWF
176
D'27'
D'54'
VAL 1
LREG
VAL 2
LREG
LREG
Ox20
;location for smaller of two
;WREG
27
27
;LREG
;WREG
54
;skip if LREG
<
WREG
iplace the smaller value in LREG
INSTRUCTIONS
AGAIN
CPFSLT COUNT
SKIP THE
NEXT
INSTRUCTION
GOTOAGAIN
MOVWF PORTB
MOVE DATA
Figure 5-5. Flowchart for CPFSLT
Example 5-26
Assume that Port D is an input port connected to a temperature sensor. Write a program
to read the temperature and test it for the value 75. According to the test results, place
the temperature value into the registers indicated by the following.
1fT = 75
1fT> 75
1fT < 75
then WREG = 75
then GREG = T
then LREG =T
Solution:
LREG EQU Ox20
GREG EQU Ox21
SETF
MOVLW
CPFSGT
BRA
MOVFF
BRA
LEQ
CPFSLT
BRA
MOVFF
OVER
TRISD
D'75'
PORTD
LEQ
PORTD, GREG
OVER
PORTD
OVER
PORTD, LREG
;PORTD = input
;WREG = 75 decimal
;skip BRA instruction i f PORTD > 75
; skip i f PORTD < 75
i it must be equal,
WREG
75
CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS
177
Example 5-27
Write code to determine if data on PORTB contains the value 99H. If so, write letter
'Y' to PORTC; otherwise, make PORTC = 'N'.
Solution:
CLRF
MOVLW
MOVWF
SETF
MOVLW
CPFSEQ
BRA
MOVLW
MOVWF
TRISC
A'N'
PORTC
TRISB
Ox99
PORTB
OVER
'Y'
PORTC
;PORTC = output
;WREG = 'N' (ASCII)
i PORTe
=
'N'
; PORTB = input
;WREG = 99H
;skip BRA instruction if PORTB
iPORTC
WREG
'Y'
OVER
Review Questions
1. Find the content of register WREG after the fonowing code in each case:
(a) MOVLW Ox37 (b) MOVLW Ox37
(c) MOVLW Ox37
ANDLW OxCA
2.
3.
4.
5.
6.
IORLW OxCA
XORLW OxCA
To mask certain bits of the WREG, we must AND it with _ __
To set certain bits of the WREG to I, we must OR it with
EX-ORing an operand with itself results in _ __
True or false. The CPFSLT instruction alters the contents of its operands.
What value must MYREG have in order for the fonowing code to skip the
BRA instruction?
BACK
MOVLW Ox99
CPFSLT MYREG
BRA BACK
7. Find the contents of register WREG after execution of the following code:
MOVLW 0
IORLW Ox99
XORLW OxFF
178
SECTION 5.4: ROTATE INSTRUCTION AND DATA
SERIALIZATION
In many applications there is a need to perform a bitwise rotation of an
operand. In the PICl8 the rotation instructions RRCF, RRNCF, RLCF, and
RLNCF are designed specifically for that purpose. They allow a program to rotate
the file register right or left. We explore the rotate instructions next because they
are widely used in many different applications. There are two types of rotations.
One is a simple rotation of the bits of the file register, and the other is a rotation
through the carry. Each is explained below.
Rotating the bits of file Reg right or left
RRNCF fileReg, d
;rotate fileReg right
In rotate right, the 8 bits of the
fileReg are rotated right one bit, and bit 00
exits from the least-significant bit and enters
into 07 (most-significant bit). After the rotation the result can be in fileReg or WREG,
depending on the d bit. See the code and diagram.
MREG EQU Ox20
MOVLW Ox36
MOVWF MYREG
RRNCF MYREG,F
RRNCF MYREG,F
RRNCF MYREG,F
RRNCF MYREG,F
RLNCF fileReg, d
[I
MSB - - " LSB
;WREG = DOll 0110
; MYREG
; MYREG
; MYREG
; MYREG
0001
1000
1100
0110
lOll
1101
0110
DOll
;rotate fileReg left
In rotate left, the 8 bits of the fileReg
are rotated left one bit, and bit 07 exits from
the MSB (most-significant bit) and enters into
00 (least-significant bit). After the rotation
the result can be in file Reg or WREG, depending on the d bit. See the code and diagram.
MREG EQU Ox20
MOVLW Ox72
MOVWF MYREG
RLNCF MYREG,F
RLNCF MYREG,F
(no carry)
;WREG
; MYREG
iMYREG
=
[I
(no carry)
MSB ••--LSB
0111 0010
1110 0100
1100 1001
Notice in the RRNCF and RLNCF instructions that both the Z and N flags
are affected.
CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS
179
Rotating through the carry
There are two more rotate instructions in the PIC 18. They involve the carry
flag. Each is shown next.
RRCF fileReg,
d
irotate fileReg right through carry
In RRCF, as bits are rotated
from left to right, the carry flag
enters the MSB and the LSB exits to
the carry flag. In other words, in
RRCF the C is moved to the MSB,
and the LSB is moved to the C. In
reality, the carry flag acts as if it is
part of the register, making it a 9-bit register.
l:IMSB----~. LSB ,~ C ]
MREG EQU Ox20
BCF
STATUS,C
MOVLW Ox26
MOVWF MYREG
RRCF
MYREG,F
RRCF
MYREG,F
RRCF
MYREG,F
RLCF fileReg,
;make C = a (carry is DO of status)
;WREG
0010 0110
; MYREG
; MYREG
;MYREG
d
0001 001l C
0000 1001 C
1000 0100 C
180
1
1
;rotate fileReg left through carry
In RLCF, as bits are shifted from
right to left, the carry flag enters the LSB
and the MSB exits to the carry flag. In
other words, in RLCF the C is moved to
the LSB, and the MSB is moved to the C.
See the following code and diagram.
Again the carry flag acts as if it is part of
the register, making it a 9-bit register.
MREG EQU Ox20
BSF
STATUS,C
MOVLW Ox1S
MOVWF MYREG
RLCF
MYREG,F
RLCF
MYREG,F
RLCF
MYREG,F
RLCF
MYREG,F
a
=
-S-B:=.=--=--L-SB---',J
-lr-M
;make C = 1 (carry is DO of status)
;WREG
0001 0101
;MYREG
; MYREG
; MYREG
; MYREG
0010
0101
1010
0101
1011
0110
1100
1000
C
C
C
C
a
a
a
1
Serializing data
Serializing data is a way of sending a byte of data one bit at a time through
a single pin of the microcontroller. There are two ways to transfer a byte of data
serially:
I. Using the serial port. In using the serial port, programmers have very limited
control over the sequence of data transfer. The details of serial port data transfer are discussed in Chapter 10.
2. The second method of serializing data is to transfer data one bit at a time and
control the sequence of data and spaces between them. In many new generations of devices such as LCD, ADC, and ROM, the serial versions are becoming popular because they take less space on a printed circuit board. Next, we
discuss how to use rotate instructions in serializing data.
Serializing a byte of data
Serializing data is one of the most widely used applications of the rotate
instruction. We can use the rotate instruction to transfer a byte of data serially (one
bit at a time). Example 5-28 shows how to transfer an entire byte of data serially
via any PIC pin.
Example 5-28
Write a program to transfer value 41H serially (one bit at a time) via pin RBI. Put one
high at the start and end of the data. Send the LSB first.
Solution:
RCNT
MYREG
BCF
MOVLW
MOVWF
BCF
MOVLW
MOVWF
BSF
AGAIN RRCF
BNC
BSF
BRA
OVER BCF
NEXT DECF
BNZ
BSF
EQU
EQU
Ox20
Ox21
TRISB,l
ox41
MYREG
STATUS,C
Ox8
RCNT
PORTB,l
MYREG,F
OVER
PORTB,l
NEXT
PORTB,l
RCNT,F
AGAIN
PORTB,l
ifileReg loc for counter
ifileReg loc for rotate
imake RBI an output bit
;WREG = 41
ivalue to be serialized
jC =
0
,. counter
jload the counter
;RB1 = high
jrotate right via carry
jset the carry bit to PBI
;RB1
high
CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS
181
Example 5-29 shows how to bring in a byte of data serially (one bit at a
time). We will see how to use these concepts for a serial RTC (real-time clock)
chip in Chapter 16. Example 5-30 shows how to scan the bits in a byte.
Example 5-29
Write a program to bring in a byte of data serially (one bit at a time) via pin RC7 and
save it in file register location 0x21. The byte comes in with the LSB fIrst.
Solution:
RCNT EQU
MYREG EQU
Ox20
Ox21
BSF
MOVLW
MOVWF
AGAIN BTFSC
BSF
BTFSS
BCF
RRCF
DECF
BNZ
TRISC,7
Ox8
RCNT
PORTC, 7
STATUS,C
PORTC, 7
STATUS,C
MYREG,F
RCNT,F
AGAIN
jfileReg lac for counter
ifileReg lac for incoming byte
irnake RC7 an input bit
icounter
;load the counter
; skip i f RC7
0
icarry = 1
; skip if RC7
1
;otherwise carry
=
0
;rotate right carry into MYREG
;decrement the counter
jrepeat until ReNT = a
;now loc 21H has the byte
Example 5-30
Write a program that fInds the number of 1s in a given byte.
Solution:
R1
EQU
COUNT EQU
VALREG EQU
Ox20
Ox21
Ox22
;fileReg loc for number of 1s
;fileReg loc for counter
;fileReg loc for the byte
BCF
STATUS,C
CLRF Rl
MOVLW Ox8
MOVWF COUNT
MOVLW Ox97
MOVWF VALREG
AGAIN RLCF VALREG,F
NEXT
BNC
INCF Rl,F
NEXT DECF COUNT,F
BNZ AGAIN
0
;C
iRl keeps the number of 1s
; counter
08 to rotate 8 times
~
~
;find the number of 1s in 97H
jrotate i t through the C once
; check for C
iif C
~
1 then add one to R1 reg
ig o through this 8 times
jnow lac Ox20 has the number of 1s
182
SWAPF fileReg, d
Another useful instruction is the SWAPF instruction. It works on the file
register. It swaps the lower nibble and the higher nibble. In other words, the lower
4 bits are put into the higher 4 bits, and the higher 4 bits are put into the lower 4
bits. See the diagrams below and Example 5-31.
before:
07-04
II
03-00
after:
03-00
II
07-04
0010
II
0111
SWAPF
before:
0111
II
0010
after:
SWAPF
Example 5-31
(a) Find the contents of the MYREG register in the following code.
(b) In the absence of a SWAPF instruction, how would you exchange the nibbles?
Write a simple program to show the process.
Solution:
(a)
MYREG EQU Ox20
MOVLW Ox72
MOVWF MYREG
SWAPF MYREG,F
;WREG = 72H
72H
; MYREG
;MYREG = 27H
MYREG EQU Ox20
MOVLW Ox72
MOVWF MYREG
RLNCF MYREG, F
RLNCF MYREG,F
RLNCF MYREG,F
RLNCF MYREG, F
;WREG = 0111 0010
; MYREG
0111 0010
; MYREG
1110 0100
; MYREG
1100 1001
; MYREG
1001 0011
; MYREG
0010 0111
(b)
Review Questions
I. What is the value of MYREG in the file register after the following code is
executed?
MYREG
MOVLW
MOVWF
RRNCF
RRNCF
RRNCF
RRNCF
EQU Ox40
Ox25
MYREG
MYREG,F
MYREG,F
MYREG,F
MYREG,F
CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS
183
2. What is the value of MYREG in the file register after the following code is
executed?
MYREG EQU Ox40
MOVLW Ox25
MOVWF MYREG
RLNCF MYREG,F
RLNCF MYREG,F
RLNCF MYREG,F
RLNCF MYREG,F
3. What is the value of MYREG after the following code is executed?
MYREG EQU Ox40
CLRF
MYREG
BSF
STATUS,C
RRCF
MYREG,F
BSF
STATUS,C
MYREG,F
RRCF
;C
=
1
;C
=
1
4. Does "RLCF W" give an error in the PIC?
5. What is in MYREG after the execution of the following code?
MYREG EQU Ox40
MOVLW Ox85
MOVWF MYREG
SWAPF MYREG,F
SECTION 5.5: BCD AND ASCII CONVERSION
In this section we provide some real-world examples of how to use arithmetic and logic instructions. We will cover their applications in real-world devices
in future chapters. For example, many newer microcontrollers have a real-time
clock (RTC), where the time and date are kept even when the power is off. These
microcontrollers provide the time and date in BCD. To display them, however,
they must convert BCD values to ASCII. Next, we show the application of logic
and rotate instructions in the conversion of BCD and ASCII.
ASCII numbers
On ASCII keyboards, when the key "0" is activated, "011 0000" (30R) is
provided to the computer. Similarly, 31R (0110001) is provided for key "I", and
so on, as shown in Table 5-3.
It must be noted that BCD numbers are universal although ASCII is standard in the United States (and many other countries). Because the keyboard, printers, and monitors all use ASCII, how does data get converted from ASCII to BCD,
and vice versa? These are the subjects covered next.
184
Table 5-3: ASCII and BCD Codes for Digits 0-9
Key
0
1
2
3
4
5
6
7
8
9
ASCII (hex)
30
31
32
33
34
35
36
37
38
39
Binary
011 0000
011 0001
011 0010
0110011
OIl 0100
011 0101
0110110
all 0111
all 1000
all 1001
BCD (unpacked)
00000000
00000001
00000010
00000011
00000100
00000101
00000110
000001ll
0000 1000
00001001
Packed BCD to ASCII conversion
In many systems we have what is called a real-time clock (RTC). The RTC
provides the time of day (hour, minute, second) and the date (year, month, day)
continuously, regardless of whether the power is on or off (see Chapter 16). This
data, however, is provided in packed BCD. For this data to be displayed on a
device such as an LCD, or to be printed by the printer, it must be in ASCII format.
To convert packed BCD to ASCII, you must first convert it to unpacked
BCD. Then the unpacked BCD is tagged with 011 0000 (30H). The following
demonstrates converting packed BCD to ASCII. See also Example 5-32.
Packed BCD
29H
0010 1001
Unpacked BCD
02H & 09H
0000 0010 &
0000 1001
ASCII
32H & 39H
0011 0010 &
0011 1001
Example 5-32
Assume that register WREG has packed BCD. Write a program to convert packed BCD
to two ASCII numbers and place them in file register locations 6 and 7.
Solution:
BCD VAL EQU Ox29
EQU OX06
L ASC
H ASC
EQU Ox07
MOVLW
ANDLW
IORLW
MOVWF
MOVLW
ANDLW
SWAPF
IORLW
MOVWF
;set aside file register location
;set aside file register location
BCD VAL
OxOF
Ox30
L ASC
BCD VAL
OxFO
WREG,W
Ox30
H ASC
;WREG = 29H, packed BCD
;mask the upper nibble (W = 09)
;make it an ASCII, W = 39H ('9')
;save it (L_ASC = 39H ASCII char)
iW = 29H get BCD data once more
;mask the lower nibble (W = 20H)
;swap nibbles (WREG = 02H)
;make it an ASCII, W = 32H ('2')
;save it (H_ASC = 32H ASCII char)
CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS
185
ASCII to packed BCD conversion
To convert ASCII to packed BCD, you first convert it to unpacked BCD (to
get rid of the 3), and then combine it to make packed BCD. For example, for 4 and
7 the keyboard gives 34 and 37, respectively. The goal is to produce 47H or "0100
0111", which is packed BCD. This process is illustrated next.
Key
4
7
ASCII
34
37
MYBCD EQU Ox20
MOVLW
ANDLW
MOVWF
SWAPF
Unpacked BCD
Packed BCD
00000100
00000111
01000111 which is 47H
iset aside location in file register
At4'
OxOF
MYBCD
MYBCD,F
MOVLW Al 7'
ANDLW OxOF
IORWF MYBCD,F
;WREG = 34H, hex for ASCII
;mask upper nibble (WREG
isave it in MYBCD loc
;MYBCD = 40H
iWREG = 37H , hex for ASCII
;mask upper nibble (WREG =
;MYBCD = 47H, a packed BCD
char 4
04)
char 7
07)
After this conversion, the packed BCD numbers are processed and the
result will be in packed BCD format. As we saw earlier in this chapter, a special
instruction, "DAW", requires that the data be in packed BCD format.
Review Questions
I. For the following decimal numbers, give the packed BCD and unpacked BCD
representations.
(a) 15
(b) 99
2. Show the binary and hex formats for "76" and its BCD version.
3. Does the WREG register have BCD data after the following instruction is executed?
MOVLW D'54'
4. 67H in BCD when converted to ASCII is
Hand
H.
5. Does the following convert unpacked BCD in the WREG register to ASCII?
MOVLW Ox09
ADDLW Ox30
SUMMARY
This chapter discussed arithmetic instructions for both signed and unsigned
data in the PIC. Unsigned data uses all 8 bits of the byte for data, making a range
of 0 to 255 decimal. Signed data uses 7 bits for data and 1 for the sign bit, making
a range of -128 to + 127 decimal.
Binary coded decimal (BCD) data represents the digits 0 through 9. Both
packed and unpacked BCD formats were discussed. The PTC contains special
instructions for arithmetic operations on BCD data.
In coding arithmetic instructions for the PTC, special attention has to be
given to the possibility of a carry or overflow condition.
186
This chapter defined the logic instructions AND, OR, XOR, and complement. In addition, PIC Assembly language instructions for these functions were
described. Compare and skip instructions were described as well. These functions
are often used for bit manipulation purposes.
The rotate and swap instructions of the PIC are used in many applications
such as serial devices. This chapter also described BCD and ASCII formats and
conversIOns.
PROBLEMS
SECTION 5.1: ARITHMETIC INSTRUCTIONS
I. Find the C, Z, and DC flags for each of the following:
MOVLW Ox3F
(b)
MOVLW Ox99
(a)
(c)
(e)
ADDLW
MOVLW
MOVWF
BSF
MOVLW
ADDWFC
ox45
OxFF
MYREG
STATUS,C
MOVLW
MOVWF
BSF
MOVLW
ADDWFC
OxFE
MYREG
STATUS,C
ADDLW
Ox58
(d)
MOVLW
ADDLW
OxFF
Oxl
(f)
BCF
MOVLW
MOVWF
MOVLW
ADDWFC
STATUS,C
oxFF
MYREG
0
MYREG,F
0
MYREG,F
0
MYREG,F
2. Write a program to add all the digits of your lD number and save the result in
a file register location. The result must be in BCD.
3. Write a program to add the following numbers and save the result in a file register location.
Ox25,Ox59,Ox65
4. Modify Problem 3 to make the result in BCD.
5. Write a program to (a) write the value 25H to file register RAM locations
20H-23H, and (b) add all these RAM locations contents together, and save the
result in RAM location 60H.
6. State the steps that the SUB instruction will go through for each ofthe followmg.
(a) 23H - 12H
(b) 43H - 53H
(c) 99-99
7. For Problem 6, write a program to perform each operation.
8. True or false. The "DAW" instruction works only on the WREG register.
9. Write a program to add 7F9AH to BC48H and save the result in RAM memory locations starting at 40H.
10. Write a program to subtract 7F9AH from BC48H, and save the result in RAM
memory locations starting at 40H.
II. Write a program to add BCD 7795H to 9548H and save the BCD result in
RAM memory locations starting at 40H.
12. Show how to perform 77 x 34 in the PICI8.
CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS
187
13. Show how to perform 77/3 in the PICI8.
14. True or false. The MULLW instruction works on any register of the PICI8.
15. The MULLW instruction places the result in registers
and _ __
SECTION 5.2: SIGNED NUMBER CONCEPTS AND ARITHMETIC
OPERATIONS
16. Show how the following are represented by the assembler:
(a) -23
(b) +12
(c) -28
(d) +6FH
(e) -128
(f) + 127
17. The memory addresses in computers are
(signed, unsigned) numbers.
18. Write a program for each of the following and indicate the status of the OV
flag for each:
(a) (+15) + (-12)
(b) (-123) + (-127)
(c) (+25H) + (+34H)
(d) (-127) + (+ 127)
19.
20.
21.
22.
Explain the difference between the C and OV flags and where each one is used.
When is the OV flag raised? Explain.
Which register holds the OV flag?
How do you detect the OV flag in the PICI8? How do you detect the C flag?
SECTION 5.3: LOGIC AND COMPARE INSTRUCTIONS
23. Assume that WREG = FOH. Perform the following operations. Indicate the
result and the register where it is stored.
Note: The operations are independent of each other.
(a) ANDLW Ox45
(b) IORLW Ox90
(c) XORLW Ox76
(d) ANDLW Ox90
(e) XORLW Ox90
(f) IORLW Ox90
(g) ANDLW OxFF
(i) XORLW OxEE
(h) IORLW Ox99
(j) XORLW OxAA
24. Find the contents of register WREG after each of the following instructions:
(a) MOVLW Ox65
(b)
MOVLW Ox70
ANDLW
(c) MOVLW
XORLW
(e) MOVLW
IORLW
(g) MOVLW
IORLW
Ox76
Ox95
(d)
OxAA
OxOC5 (f)
Ox12
Ox37
Ox26
IORL
MOVLW
ANDLW
MOVLW
XORLW
Ox6B
Ox5D
Ox78
Ox6A
Ox6E
25. True or false. In using the CPFSEQ instruction, we must use WREG as one of
the registers.
26. Explain how the CPFSGT instruction works.
27. Does the compare instruction affect the flag bits of the status register?
188
28. Assume that MYREG = 85H. Indicate if it skips after compare is executed in
each of the following cases:
(a)
MOVLW Ox90
(b)
MOVLW Ox70
(c)
CPFSGT
INCF
ADDLW
MOVLW
CPFSEQ
INCF
ADDLW
MYREG
MYREG,F
Ox2
ox8S
MYREG
MYREG,F
Ox2
(d)
CPFSGT
INCF
ADDLW
MOVLW
CPFSLT
INCF
ADDLW
MYREG
MYREG,F
Ox2
OxSD
MYREG
MYREG,F
Ox2
29. In Problem 28, indicate the value in MYREG.
SECTION 5.4: ROTATE INSTRUCTION AND DATA SERIALIZATION
30. Find register WREG contents after each of the following is executed:
(a) MOVLW OxS6
(b)
MOVLW Ox39
(c)
MOVWF
SWAPF
RRCF
RRCF
BCF
MOVLW
MOVWF
SWAPF
RRCF
RRCF
RRCF
MYREG
MYREG,F
MYREG,F
MYREG,F
STATUS,C
Ox4D
MYREG
MYREG,F
MYREG,F
MYREG,F
MYREG,F
( d)
BCF
MOVWF
RLCF
RLCF
BCF
MOVLW
MOVWF
SWAPF
RLCF
RLCF
STATUS,C
MYREG,F
MYREG,F
MYREG,F
STATUS,C
Ox7A
MYREG
MYREG,F
MYREG,F
MYREG,F
31. Show the code to replace the SWAPF code:
(a) using the rotate right instructions
(b) using the rotate left instructions
32. Write a program that finds the number of zeros in an 8-bit data item.
33. Write a program that finds the position of the first high in an 8-bit data item.
The data is scanned from DO to D7. Give the result for 68H.
34. Write a program that finds the position of the first high in an 8-bit data item.
The data is scanned from D7 to DO. Give the result for 68H.
35. A stepper motor uses the following sequence of binary numbers to move the
motor. How would you generate them?
1100, 0110,
0011, 1001
SECTION 5.5: BCD AND ASCII CONVERSION
36. Write a program to convert the following packed BCD numbers to ASCII.
Place the ASCII codes in data RAM locations starting at 40H.
MYBCD 1
MYBCD 2
EQU
EQU
Ox76
Ox87
CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS
189
37. Write a program to convert the following ASCII numbers to packed BCD.
Place the BCD data in RAM locations starting at 60H.
MYASC 1
MYASC_2
MYASC 3
MYASC 4
EQU
EQU
A'B'
A'7'
EQU
EQU
A ' 9'
A'2'
ANSWERS TO REVIEW QUESTIONS
SECTION 5.1: ARITHMETIC INSTRUCTIONS
I.
2.
3.
4.
5.
6.
7.
8.
9.
10.
I!.
WREG
PRODH and PRODL
No. It should be "MULWF f ileReg, F"
255 and 255.
True.
No. DAW works on WREG only.
WREG.
We cannot mix the literal value, WREG; and fileReg.
"ADDWF fileReg,F"
WREG
(a) WREG ~ 00, C ~ I, and DC ~ I
(b) WREG ~ FF, C ~ 0, and DC ~ 0
12.
-
43H
OSH
3EH
13. fileReg
~
0100 0011
0000 0101 2'8 complement
95H - 4FH - 0 ~ 46H, WREG
~
0100 0011
+ 1111 1011
0011 1110
95H
SECTION 5.2: SIGNED NUMBER CONCEPTS AND ARITHMETIC OPERATIONS
I.
2.
3.
4.
5.
D7
16H is 00010110 in binary and its 2's complement is 1110 1010 or
-16H ~ EA in hex.
-128 to +127
+9 ~ 00001001 and -9 ~ Ill10111 or F7 in hex.
An overflow is a carry into the sign bit (D7) but the carry is a carry out of register.
SECTION 5.3: LOGIC AND COMPARE INSTRUCTIONS
I.
2.
3.
4.
5.
6.
7.
190
(a) 02
(b) FFH
(c) FDH
Zero
One
All zeros
False
any value less than Ox99
66H
SECTION 5.4: ROTATE INSTRUCTION AND DATA SERIALIZATION
1.
2.
3.
4.
5.
52H
52H
COH
No, because WREG is a SFR
58H
SECTION 5.5: BCD AND ASCII CONVERSION
1.
2.
3.
4.
5.
(a) 15H ~ 0001 0101 packed BCD, 0000 0001,0000 0101 unpacked BCD
(b) 99H ~ 1001 1001 packed BCD, 00001001,00001001 unpacked BCD
3736H~00110111 00110110B
and in BCD we have 76H ~ 0111 0110B
No. We need to write it as 54H (with the H) or 0 I 0 I 0 I OOB to make it BCD. The value 54 without the "H" is interpreted as 36H by the assembler.
36H,37H
Yes, because WREG ~ 39H
CHAPTER 5: ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS
191
CHAPTER 6
BANK SWITCHING,
TABLE PROCESSING,
MACROS, AND MODULES
OBJECTIVES
Upon completion of this chapter, you will be able to:
»
»
»
»
»
»
»
»
»
»
»
»
»
»
List all the addressing modes of the PIC18 microcontroller
Contrast and compare the addressing modes
Code PIC Assembly language instructions using each addressing mode
Access the data RAM file register using various addressing modes
Code PIC18 instructions to manipulate a look-up table
Access fIxed data residing in the program ROM space
Discuss how to create macros and modules
Discuss how to access the entire 4K of RAM space in the PIC18
List the addresses for all 16 banks of the PIC18
Discuss how to access all banks of the PIC18
Discuss bank switching for the PIC18
Code PIC18 programs for ASCII and BCD data conversion
Code PIC18 programs to create and test the checksum byte
List the advantages of macros and modules in programming
193
The CPU can access data in various ways. The data could be in a register,
or in memory, or provided as an immediate value. These various ways of accessing data are called addressing modes. In this chapter we discuss PICI8 addressing
modes in the context of some examples.
The various addressing modes of a microprocessor are determined when it
is designed, and therefore cannot be changed by the programmer. The PIC 18 provides a total of four distinct addressing modes. They are as follows:
1.
2.
3.
4.
Immediate
Direct
Register indirect
Indexed-ROM
In Section 6.1 we look at immediate and direct addressing modes. In
Section 6.2 we cover accessing RAM data memory using the register indirect
mode. Section 6.3 explains how to access fixed data and look-up tables stored in
program ROM. Section 6.4 discusses the bit-addressability of the file register data
RAM space. In Section 6.5 we discuss bank switching and show how to access
banks other than the access bank. Checksum generation and BCD-ASCII conversions are discussed in Section 6.6. In Section 6.7, macros and modules are examined and modular programming is described.
SECTION 6.1: IMMEDIATE AND DIRECT ADDRESSING MODES
In this section, we examine first the immediate addressing mode and then
the direct addressing mode.
Immediate addressing mode
In this addressing mode, the operand is a literal constant. In immediate
addressing mode, as the name implies, the operand comes immediately after the
opcode when the instruction is assembled. Notice that immediate data is called a
literal in the PIC. This addressing mode can be used to load information into
WREG and selected registers, but not to any file register. The immediate addressing mode is also used for arithmetic and logic instructions. Examine the following
examples.
MOVLW Ox25
;load 25H into WREG
SUBLW D 1 621
;subtract WREG from 62
ANDLW B'01000000' ;AND WREG with 40H
We can use the EQU directive to access immediate data as shown below.
COUNT EQU Ox30
MOVLW COUNT
;WREG
=
30h
Notice that we can also use immediate addressing mode to perform arithmetic and
logic operations on WREG only. For example, "ADDLW Ox2 5" adds value 25 to WREG
194
Direct addressing mode
As mentioned in Chapter 2, the 256-byte access bank file register is split
into two sections: The lower addresses, 00 to 7FH, are assigned to the general purpose registers, and the upper addresses, F80-FFFH, to the SFR. The access bank
is the default bank when the PIC 18 is powered up. It is the minimum bank that all
PICI8 processors have. The MOVFF instruction also plays a role in choosing the
access bank. We will discuss that issue in Section 6.5 when we discuss bank
switching.
The entire data RAM file register can be accessed using either direct or
register indirect addressing modes. The register indirect addressing mode will be
discussed in the next section. In direct addressing mode, the operand data is in a
RAM memory location whose address is known, and this address is given as a part
of the instruction. Contrast this with immediate addressing mode in which the
operand data itself is provided with the instruction. While the letter "L" in the
instruction means literal (immediate), the letter "F" in the instruction signifies the
address of the file register location. See the example below, and note the letter F
in the instructions.
MOVLW Ox56
MOVWF Ox40
MOVFF Ox40,Ox50
;WREG = 56H (immediate addressing mode)
;copy WREG into fileReg RAM location 40H
;copy data from loc 40H to 50H.
The last two instructions use direct addressing mode. If we dissect the
opcode we see that the addresses are embedded in the instruction, as shown in
Figure 6-1 a.
0020
0030
1"1"1"1"
F1"1"F
1"FFF
1"F1"1"
1"1"1"1"
FF1"1"
FFF1"
1"1"1"F
FfFF
FFFF
FFFF
FFFF
1"F1"1"
FFF1"
FFFF
1"1"1"F
1"FFF
Figure 6-1a. MOVFF Direct Addressing Opcode
As shown in Figure 6-1 b, the address field is an 8-bit address and can take
values from OO-FFH. The A bit for bank switching is discussed in Section 6-4. Of
course, it is much easier to use names instead of addresses in the program, and we
have seen many examples of them in the last few chapters. It must be noted that
file register data RAM does not support immediate addressing mode. In other
words, to move data into any file register, we must first move it to WREG, and then
move it from WREG to the file register using the MOVWF instruction.
101101111AI
o<
ffff
ffff ffff <
I ffff I
FF
A - bank accessed for operation
A = 0, use default access bank
A = 1, use bank pointed to by
BSR (Bank Selector Register)
Figure 6-1b. MOVWF Direct Addressing Opcode
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
195
The difference between "INCF fileReg, W' and "INCF fileReg, P'
In direct addressing mode, when an operation is performed on a file register, we have the option of saving the result in the file register itself or in WREG
This option is a major source of errors in PIC programming and its correct use
must be emphasized. The following code increments the contents of register file
location 20H using the direct addressing mode, but the destination for the
increment result is decided by the W or F parameter:
MOVLW
MOVWF
INCF
INCF
INCF
INCF
INCF
INCF
INCF
INCF
a
;WREG = a
iloc Ox20
;loc Ox20
iloc Ox20
;loc Ox20
;loc Ox20
iloc Ox20
iloc Ox20
;loc Ox20
iloc Ox20
Ox20
Ox20,W
Ox20,W
Ox20,W
Ox20, F
Ox20,F
Ox20
Ox20
Ox20,W
(0)
(0)
(0)
(0)
(1)
(2)
,
,
,
,
,
,
WREG
WREG
WREG
WREG
WREG
WREG
(3) , WREG
(4) , WREG
(4) , WREG
a
=
=
1
1
1
1
1
1
1
5
Notice in the above code when the second parameter is not stated, it is
assumed to be fileReg (F).
DECFSZ and DECF
Other instructions that need to be examined are DECFSZ and DECF. We
can use either one for looping. In "DECFSZ fileReg, d" the fileReg is decremented, and the next instruction is skipped if the fileReg is zero. DECF does not
skip the next instruction. Contrast the two codes complementing PORTB 5 times.
The following code uses the DECFSZ instruction for looping:
B1
CLRF
MOVLW
MOVWF
CLRF
COMF
DECFSZ
GOTO
SETF
TRISB
5
MYREG
PORTB
PORTB
MYREG,F
B1
PORTB
jPort B as output
;WREG = 5
; counter = 5
jclear Port B
icomplement Port B
; decrement and skip if MYREG = 0
ig o back since it is not zero
imake PB = FFH
while the code below uses the BNZ (branch not zero) instruction:
B2
CLRF
MOVLW
MOVWF
CLRF
COMF
DECF
BNZ
SETF
TRISB
5
MYREG
PORTB
PORTB
MYREG,F
B2
PORTB
jPort B as output
;WREG = 5
; counter = 5
iclear Port B
jcomplement Port B
; decrement counter
;go back i f MYREG is not zero
; make PB = FFH
Notice that if we use "DECF MYREG, W" instead of "DECF MYREG, F" in
the BNZ program, we will never get out of the loop because the values of MY REG
196
Table 6-1: Selected PIC18 Special Function Register (SFR) Addresses
Symbol
WREG
PORTA
PORTB
PORTC
LATA
LATB
LATC
TRISA
TRlSB
TRISC
INDFO
INDFI
FSROL
FSROH
FSRIL
FSRIH
PLUSWO
PREINCO
POSTDECO
POSTINCO
TBLPTRL
TBLPTRH
TBLPTRU
TABLAT
STATUS
Name
Working register
PortA
Port B
Port C
Output latch, Port A
Output latch, Port B
Output latch, Port C
Data direction, Port A
Data direction, Port B
Data direction, Port C
Indirect addressing register 0
Indirect addressing register I
Indirect data memory address pointer 0 low
Indirect data memory address pointer 0 high
Indirect data memory address pointer I low
Indirect data memory address pointer I high
Indirect indexed address register
Preincrement register 0
Post-decrement register 0
Post-increment register 0
Table pointer, low byte
Table pointer, high byte
Table pointer, upper byte
Program memory table latch
Status flag byte
Address
FE8H
F80H
F81H
F82H
F89H
F8AH
F8BH
F92H
F93H
F94H
FEFH
FE7H
FE9H
FEAH
FEIH
FE2H
FEBH
FECH
FEDH
FEEH
FF6H
FF7H
FF8H
FF5H
FD8H
and WREG will remain 5 and 4 respectively forever.
SFR registers and their addresses
PIC 18 registers for Ports A, B, and so on are part of the group of registers
commonly referred to as SFRs (special function registers). There are many special
function registers and they are widely used, as we will discuss in future chapters.
The SFRs can be accessed by their names (which is much easier) or by their
addresses. For example, Port B has address F8IH, and Port C the address F82H,
as shown in Table 6-1. Notice how the following pairs of instructions mean the
same thing:
MOVWF OxF81
MOVWF PORTB
jis the same as
;which means copy WREG into Port B
CLRF OxF82
CLRF PORTC
;is the same as
;which means clear Port C
BSF OxFD8,O
BSF STATUS,C
iis the same as
;which make C = 1
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
197
Table 6-1 lists selected PIC 18 special function registers (SFRs) and their
addresses. The following two points should be noted about SFR addresses:
I. The special function registers have addresses between F80H and FFFH. These
addresses are below FFFH, because the PIC 18 starts assigning SFR addresses
at FFFH and goes down until all SFRs supported by that chip are assigned. Not
all the members of the PICI8 family have the same peripherals; therefore, the
number of locations used for SFRs varies among the PIC 18 family.
2. Not all the address space of F80H to FFFH is used by the SFR. The unused
locations F80H to FFFH are reserved and must not be used by the PIC 18 programmer.
Example 6-1
Write code to send 55H to Port B. Include
(a) The register names.
(b) Their addresses.
Solution:
(a)
(b)
CLRF TRISB
MOVLW Ox55
MOVWF PORTB
i
Port B output
;WREG
55H
;Port B = 55H
From Table 6-1, TRISB address = F93H and PORTB address = F81H
CLRF OxF93
MOVLW Ox55H
MOVWF OxF81
jPort B output
;WREG
55H
;Port B = 55H
Regarding direct addressing mode in the PICI8, notice the following
points:
I. If you examine the .1st file for an Assembly language program, you will see
that the SFR register names are replaced with their addresses as listed in Table
6-\.
2. The WREG register is one of the SFR registers and has address FE8H.
3. The direct addressing mode is also called register direct to contrast it with the
register indirect addressing mode discussed in the next section.
Review Problems
I.
2.
3.
4.
5.
198
Can the programmer of a microcontroller make up new addressing modes?
Show the instruction to load 1000 0000 (binary) into register WREG.
Why is "MOVLF myval ue, f ileReg" invalid?
True or false. In PIC 18, the PC (program counter) is part of the SFR.
True or false. In PICI8, the WREG register is not part of the SFR.
SECTION 6.2: REGISTER INDIRECT ADDRESSING MODE
We can use register direct or register indirect addressing modes to access
data stored in the general purpose RAM section of the file register. In the last section we showed how to use direct addressing mode, which is also called register
direct. The register indirect addressing mode is a very important addressing mode
in the PIC 18. This topic will be discussed thoroughly in this section.
Register indirect addressing mode
In the register indirect addressing mode, a register is used as a pointer to
the data RAM location. In the PICI8, three registers are used for this purpose:
FSRO, FSRI, and FSR2. FSR stands for file select register and must not be confused with SFR (special function register). The FSR is a 12-bit register allowing
access to the entire 4096 bytes of data RAM space in the PIC 18. We use LFSR
(load FSR) to load the RAM address. In other words, when FSRx are used as
pointers, they must be loaded first with the RAM addresses as shown below.
LFSR 0, Ox30
LFSR 1, Ox40
LFSR 2, Ox6F
;load FSRO with Ox30
iload FSRl with Ox40
;load FSR2 with Ox6F
Because FSRO, FSR1, and FSR2 are 12-bit registers they cannot fit into the
SFR address space unless they are split into pieces of an 8-bit size. That is exactly what PIC I 8 has done. The FSR registers have the low-byte and high-byte parts
called FSRxL and FSRxH, as shown in the SFR table of Table 6-1. In Table 6-1
we see FSROL and FSROH, representing the low and high parts of the 12-bit FSRO
register. Note that the FSRxH is only 4-bit and the upper 4 bits are not used.
Another register associated with the register indirect addressing mode is the INDF
(indirect register). Each of the FSRO, FSR1, and FSR2 registers has an INDF register associated with it, and these are called INDFO, INDFI, and INDF2. When we
move data into INDFx we are moving data into a RAM location pointed to by the
FSR. In the same way, when we read data from the INDF register, we are reading
data from a RAM location pointed to by the FSR. This is shown below.
LFSR 0, ox30
MOVWF INDFO
iFSRO
= 30H RAM location pointer
contents of WREG into RAM
;location whose address is held by
;12-bit FSRO register
iCOPY
Advantages of register indirect addressing mode
One of the advantages of register indirect addressing mode is that it makes
accessing data dynamic rather than static, as with direct addressing mode.
Example 6-2 shows three cases of copying 55H into RAM locations 40H to 45H.
Notice in solution (b) that two instructions are repeated numerous times. We can
create a loop with those two instructions as shown in solution (c). Solution (c) is
the most efficient and is possible only because of the register indirect addressing
mode. In Example 6-2, we must use "INCF FSROL, F" to increment the pointer
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
199
because there is no such instruction as "INCF FSRO, F". Looping is not possible
in direct addressing mode, and that is the main difference between the direct and
register indirect addressing modes. For example, trying to send a string of data
located in consecutive locations of data RAM is much more efficient and dynamic using register indirect addressing mode than using direct addressing mode. See
Example 6-3.
Example 6-2
Write a program to copy the value 55H into RAM memory locations 40H to 45H using
(a) Direct addressing mode.
(b) Register indirect addressing mode without a loop.
(c) A loop.
Solution:
(a)
MOVLW
MOVWF
MOVWF
MOVWF
MOVWF
MOVWF
Ox55
Ox40
Ox4l
Ox42
Ox43
Ox44
MOVLW
LFSR
MOVWF
INCF
MOVWF
INCF
MOVWF
INCF
MOVWF
INCF
MOVWF
55H
;load WREG with value 55H
WREG
WREG
; copy WREG
; copy WREG
iCOPY WREG
iCOPY
iCOPY
to
to
to
to
to
RAM
RAM
RAM
RAM
RAM
location 40H
location 41H
location 42H
location 43H
location 44H
(b)
O,Ox40
INDFO
FSROL,F
INDFO
FSROL,F
INDFO
FSROL,F
INDFO
FSROL,F
INDFO
iload with value 55H
;load the pointer. FSRO = 40H
jCopy W to RAM loc FSRO points to
jincrernent pointer. Now FSRO = 41H
jCopy W to RAM loc FSRO points to
; increment pointer. Now FSRO = 42H
;copy W to RAM loc FSRO points
; increment pointer. Now FSRO =
jCopy W to RAM loc FSRO points
; increment pointer. Now FSRO =
jCopy W to RAM loc FSRO points
to
43H
to
44H
to
(c)
Bl
COUNT
MOVLW
MOVWF
LFSR
MOVLW
MOVWF
INCF
DECF
BNZ
EQU OxlO
Ox5
COUNT
O,Ox40
Ox55
INDFO
FSROL,F
COUNT,F
Bl
;location lOH for counter
;WREG = 5
i10ad the counter, Count = 5
jload pointer. FSRO = 40H, RAM address
;WREG = 55h value to be copied
;copy WREG to RAM loc SFRO points to
jincrement FSRO pointer
;decrement the counter
jloop until counter = zero
Use the MPLAB simulator to examine RAM contents after the above program is run.
40 = (55)
41 = (55)
42 = (55)
43 = (55)
44 = (55)
200
Example 6-3
Assume that RAM locations 30-34H have a string of ASCII data, as shown below.
Write a program to get each character and send it to Port B one byte at a time. Show the
program usmg:
(a) Direct addressing mode.
(b) Register indirect addressing mode.
30 =
31 =
32 =
33 =
34 =
('H')
('E')
('L')
('L')
('0')
Solution:
(a) Using direct addressing mode
CLRF
MOVFF
MOVFF
MOVFF
MOVFF
MOVFF
TRISB
PORTB
Ox31, PORTB
Ox32, PORTB
Ox33, PORTB
Ox34, PORTB
Ox30,
;make Port B an output
;copy contents of loc Ox30 to PB
(b) Using register indirect mode
B3
COUNT REG EQU Ox20
CNTVAL EQU 5
CLRF TRISB
MOVLW CNTVAL
MOVWF COUNTREG
LFSR 2,Ox30
MOVF INDF2,W
MOVWF PORTB
INCF FSR2L
DECF COUNTREG,F
BNZ
B3
; fileReg lac for counter
icounter value
out)
; make Port B an output (TRSI
0
;WREG = 5
; load the counter, count = 5
; load pointer. FSR2 = 30H, RAM address
iCOpy RAM lac FSR2 points at to WREG
iCOpy WREG to PORTB
; increment FSR2 to point at next lac
; decrement counter
; loop until counter = zero
When simulating the above program on the MPLAB, make sure that RAM locations
30H-34H have the message "HELLO". Notice that "MOVF INDF2, w" moves data from
INDF2 into WREG.
When using the MPLAB simulator with examples in this chapter, you may
have noticed that you cannot view INDFO, POSTDECO, or PLUSWO in the watch
window. This is because these registers are not physically implemented memory
locations. Accessing these registers indicates indirect addressing. See Figure 2-4
in Chapter 2 for the registers that are not physically implemented.
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
201
Auto-increment option for FSR
Because the FSR is a 12-bit register, it can go from 000 to FFFH, which
covers the entire 4K RAM space of the PICI8. Using the "INCF FSROL, F"
instruction to increment the pointer can cause a problem when an address such as
5FFH is incremented. The instruction "INCF FSROL, F" will not propagate the
carry into the FSR I H register. The PIC 18 gives us the options of auto-increment
and auto-decrement for FSRn to overcome this problem. The syntax used for such
cases for the CLRF instruction is shown in Table 6-2.
Table 6-2: PICIS Auto-IncrementlDecrement of FSRn for CLRF Instruction
Instruction
Function
CLRF INDFn
After clearing fileReg pointed to by FSRn, the FSRn stays the same.
CLRF POSTINCn After clearing fileReg pointed to by FSRn, the FSRn is incremented.
CLRF PREINCn
The FSRn is incremented, then fileReg pointed to by FSRn is cleared.
CLRF POSTDECn After clearing fileReg pointed to by FSRn, the FSRn is decremented.
CLRF PLUSWn
Clears fileReg pointed to by (FSRn +WREG), FSRn & W unchanged.
Note: This table shows the syntax for the CLRF instruction, it works for all such instructions. The auto-decrement or auto-increment affects the entire 12 bits of the FSRn and has
no effect on status register. This means that FSRO going from FFF to 000 will not raise any
flag. The option of PLUSWn is widely used for a RAM-based look-up table. See Section
6.4.
Example 6-4
Write a program to clear 16 RAM locations starting at RAM address 60H.
Use the following:
(a) INCF FSRnL
(b) Auto-increment
Solution:
(al
COUNTREG EQU Ox10
CNTVAL EQU D' 16'
MOVLW CNTVAL
MOVWF COUNTREG
LFSR
1,Ox60
CLRF
B2
INDF1
FSR1L,F
INCF
DEeF
BNZ
ifileReg lac for counter
icounter value
;WREG = 16
jload the counter, Count =
;load pointer. FSR1 = 40H,
jclear RAM lac FSRI points
;increment FSRIL, point to
COUNTREG,F ;decrement counter
B2
;loop until counter = zero
16
RAM address
to
next lac
(bl
COUNTREG EQU Ox10
CNTVAL EQU D'16'
MOVLW CNTVAL
MOVWF COUNT REG
LFSR
l,Ox60
CLRF
B3
POSTINC1
DECF
COUNTREG,F
BNZ
B3
202
;fileReg lac for counter
jcounter value
;WREG = 16
;load the counter, Count = 16
;load pointer. SFRO = 40H, RAM address
iclear RAM, increment FSRI pointer
;decrement counter
iloop until counter = zero
Example 6-5
Write a program to copy a block of 5 bytes of data from RAM locations starting at 30H
to RAM locations starting at 60H.
Solution:
B3
COUNT REG EQU Ox10
CNTVAL EQU D'5'
MOVLW CNTVAL
MOVWF COUNTREG
LFSR
O,Ox30
1,Ox60
LFSR
POSTINCO,W
MOVF
MOVWF POSTINC1
DECF
COUNTREG,F
BNZ
B3
ifileReg lac for counter
;counter value
;WREG = 10
;load the counter, count = 10
;load pointer. FSRO = 30H, RAM address
;load pointer. FSRI = 60H, RAM address
iCOpy RAM to WREG and increment FSRO
jCOpy WREG to RAM and increment FSRI
;decrement counter
iloop until counter = zero
Before we run the above program.
30 =
('H')
31 =
('E')
32 = ('L')
33 = ('L')
34 = ('0')
After the program is run, the addresses 60-64H have the same data as 30-34H.
30 = ('H')
60 = ('H')
31 = ('E')
61 = ('E')
32 =
62 =
('L')
('L')
33 = ('L')
63 = ('L')
34 = ('0')
64 = ('0')
Example 6-6
Assume that RAM locations 40-43H have the following hex data. Write a program to
add them together and place the result in locations Ox06 and Ox07.
40
=
(7D)
41
=
(EB)
42
=
(C5)
43
=
(5B)
Solution:
COUNT REG EQU Ox20
L BYTE EQU Ox06
H BYTE EQU Ox07
CNTVAL EQU 4
MOVLW CNTVAL
MOVWF COUNTREG
0,Ox40
LFSR
WREG
CLRF
CLRF
H BYTE
ADDWF POSTINCO, W
B5
BNC
OVER
INCF
H_BYTE,F
OVER DECF
COUNTREG,F
BNZ
B5
MOVWF L BYTE
; fileReg loc for counter
; fileReg loc for L_Byte
jfileReg loc for L_Byte
icounter value
;WREG = 4
;load the counter
iload pointer. FSRO = 40H, RAM address
;clear WREG
;clear H_BYTE
jadd RAM to WREG and increment FSRO
i i f C = 0, go to next
;C = 1, add 1 to high byte
; decrement counter
iloop until counter = zero
The above is a register indirect version of Example 5-2 in Chapter 5 with a loop.
Contrast them to see the difference.
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
203
To see an example of how to use all three FSRn registers, study and simulate Example 6-7.
Example 6-7
Write a program to add the following multibyte BCD numbers and save the result.
l2896577H
+
23647839H
Solution:
B3
COUNTREG EQU Ox20
CNTVAL EQU D'4'
MOVLW CNTVAL
MOVWF COUNTREG
LFSR 0,Ox30
LFSR l,OxSO
LFSR 2,Ox60
BCF
STATUS,C
MOVF POSTINCO,W
ADDWFC POSTINC1,W
DAW
MOVWF POSTINC2
DECF COUNTREG,F
BNZ
B3
ifileReg lac for counter
icounter value
;WREG = 4
;load the counter. Count = 4
;load pointer. FSRO
30H, RAM address
;load pointer. FSRI = SOH, RAM address
;load pointer. FSR2 = 60H, RAM address
;clear carry flag for the LSB
;copy RAM to WREG and INC FSRO
;add RAM to WREG and INC FSR1
;decimal adjust WREG
;copy WREG to RAM and INC FSR2
jdecrement counter
;loop until counter = zero
Before the addition we have:
MSByte
33
(12)
53 = (23)
32
52
(64)
31
51
(65)
(78)
LSByte
30
(77)
50 = (39)
(54)
61 =
(44)
60 =
(89)
After the addition we have:
63 =
(36)
62 =
(l6)
Notice that we are using the little endian convention of storing a low byte to a low
address and a high byte to a high address. Single-step the program in MPLAB and
examine the FSRx and memory contents to gain an insight into register indirect addressing mode.
Review Questions
1.
2.
3.
4.
5.
204
The instruction "MOVWF Ox40" uses
addressing mode. Why?
What address is assigned to register FSROL?
What address is assigned to register FSROH?
The FSRn is a(n) ~_-bit register.
Which registers are allowed to be used for register indirect addressing mode if
the data is in the data RAM file register?
SECTION 6.3: LOOK-UP TABLE AND TABLE PROCESSING
So far, we have seen that the PIC 18 has a maximum of 2M of code (program) space and 4K of data RAM space. While we never use any of the data RAM
space for storing code, we can use the code space to store fixed data. In this section we discuss how to access fixed data residing in the program ROM space of
the PIC 18. First we examine how to store fixed data in the program ROM space
using the DB (define byte) directive.
DB (define byte) and fixed data in program ROM
The DB data directive is widely used to allocate ROM program (code)
memory in byte-sized chunks. In other words, DB is used to define an 8-bit fixed
data. When DB is used to define fixed data, the numbers can be in decimal, binary, hex, or ASCII formats. The DB directive is used to define ASCII strings. See
Example 6-8. In Example 6-8, notice that we must use single quotes C) for a
single character or double quotes (n) for a string.
Example 6-8
Assume that we have burned the following fixed data into program ROM of a PIC chip.
Give the contents of each ROM location starting at 500H. See Appendix F for the hex
values of the ASCII characters.
;MY DATA IN ROM
ORG 500H
DATAl DB D'28'
DATA2 DB B'00110101'
DATA3 DB Ox39
ORG 510H
DATA4 DB 'Y'
0
DATA5 DB 12 1
I
'
;notice it must be an even address
;DECIMAL(lC in hex)
;BINARY (35 in hex)
;HEX
inotice it must be an even address
; single ASCII char
1
I
1
0
1
I
15' ; ASCI I numbers
ORG 518H
DATA6 DB "Hello ALI"
END
;notice it must be an even address
;ASCII string
Solution:
DATAl
500 = (lC)
DATA2
501 = (35)
DATA3
502 = (39)
DATA4
510 = (59)
Y
DATA5
511 = (32)
2
512
(30)
0
513
(30)
0
514
(35)
5
DATA6
518
519
51A
(6C)
1
(4C)
SIB
(6C)
1
(49)
I
SIC
(6F)
(48)
H
SID
(20)
SPACE
51E
(65)
e
(41)
A
51F
L
520
0
MPASM also allows the use of DATA in place of DB to define values
greater than 255 (OxFF) but not larger than 65535 (OxFFFF).
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
205
Reading table elements in the PIC18
Example 6-8 showed how to place fixed data into program ROM. The only
problem is that the 2M of program (code) space is under the direct control of the
program counter register. This means that we need to have a special function register to point to the data to be fetched from the code space. For this reason we can
call it register indirect ROM addressing mode. This is an addressing mode widely
used to access data elements located in the program ROM space of the PICI8. This
is often called table processing.
There is a group of instructions in the PICl8 designed for table processing.
These can be used for both table read and table write. We discuss table read first
because it is the most widely used. Table 6-3 shows the instructions for table read
of the PIC 18. To read the fixed data byte, we need an address pointer that points
to the data and a register to store the data when it is brought into the CPU. TBLPTR is a 2l-bit register and is used to point to the byte to be fetched. With the 21bit register TBLPTR, we can cover the entire 2M program (code) space for the
PIC 18. The only problem is that we do not have an instruction to load the 2l-bit
address into TBLPTR.
TBLPTR is divided into three 8-bit parts. These are called TBLPTRL
(low), TBLPTRH (high), and TBLPTRU (upper), and all are part of the SFRs.
Notice that the last 2 bits ofTBLPTRU (upper) are not used and are cleared to Os.
The other SFR register used for the table processing is TABLAT. The TABLAT (TABle LATch) register is used for keeping the byte once it is fetched into the
CPU. See Example 6-9. In the next few examples, we load only the TBLPTRL and
TBLPTRH registers because the table elements are stored in the first 64K of the
PICl8 address space (OOOO-FFFFH). You must load TBLPTRU as well if the data
is residing on ROM addresses of 10000H and beyond.
Auto-increment option for TBLPTR
Because the TBLPTR is 21-bit register it can cover from 000000 to
lFFFFFH, which is the 2M ROM space of the PICI8. Using the "INCF TBLPTRL,
F" instruction to increment the pointer can cause a problem when an address such
as 5FFH is incremented. The carry will not propagate into TBLPTRH. The PICI8
gives us the options of TBLRD*+ (table read and increment), TBLRD*- (table
read and decrement), and so on, as shown in Table 6-3. See Examples 6-10, 6-11,
and 6-12.
Table 6-3: PIe1S Table Read Instructions
Instruction
Function
TBLRD*
Table read
TBLRD*+
Table read with post-inc.
TBLRD*Table read with post-dec.
TBLRD+*
Table read with pre-inc.
Note: The byte of data is read into the TABLATch
TBLPTR.
206
Description
After read, TBLPTR stays the same
Reads and increments TBLPTR
Reads and decrements TBLPTR
Increments TBLPTR and then reads
register from code space pointed to by
Example 6-9
In this program, assume that the word "USA" is burned into ROM locations starting at
500H, and that the program is burned into ROM locations starting at O. Analyze how the
program works and state where "USA" is stored after this program is run.
Solution:
ORG
OOOOH
CLRF TRI8B
MOVLW OxO
MOVWF TBLPTRL
MOVLW Ox05
MOVWF TBLPTRH
TBLRD*
MOVFF TABLAT,PORTB
INCF TBLPTRL,F
TBLRD*
MOVFF TABLAT,PORTB
INCF TBLPTRL,F
TBLRD*
MOVFF TABLAT,PORTB
GOTO HERE
HERE
;burn into ROM starting at 0
imake PB an output
;WREG = 0 look-up table low-byte addr
;look-up table low-byte addr
;WREG = 5 look-up table high-byte addr
;look-up table high-byte addr
;TABLAT = 'U' char pointed to by TABPTR
;send it to Port B
;TBLPTRL = 01 pointing to next (501)
;TABLAT = '8' char pointed to by TBLPTR
;send it to Port B
;TBLPTRL = 02 pointing to next (502)
iTABLAT = 'A' char pointed to by TBLPTR
;send it to Port B
istay here forever
;data is burned into code (program) space starting at 500H
ORG
500H
nUSA"
MYDATA DB
END
iend of program
In the above program ROM locations 500H-502H have the following contents.
500
=
('U') 501
=
('8') 502
=
('A')
We start with TBLPTR = 500H (TBLPTRH = 05 and TBLPTRL = 0). The instruction
"TBLRD*" moves the contents of ROM location 500H to TABLAT. Register TABLAT
contains 55H, the ASCII value for 'U'. This is moved to Port B. Next, TBLPTRL is
incremented to make TBLPTR = 501H. The TBLRD instruction will get the contents of
the next ROM location 501H, which holds character'S'. After this program is run, we
send the ASCII values for the characters 'U', 'S', and 'A' to Port B one character at a time.
The loop version of this program is given in the next example.
oraD
.,
OF81
OF82
PORTe
OY83
PORTD
PORTE
OF8"1
00
00
00
65
a
a
a
01000001
00000000
00000000
00000000
A
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
207
Example 6-10
Assuming that program ROM space starting at 250H contains "USA", write a program
to send all the characters to Port B one byte at a time.
Solution:
(a)
This method uses a counter
RCOUNT EQU Ox20
CNTVAL EQU Ox3
ORG
OOOOH
MOVLW Ox50
MOVWF TBLPTRL
MOVLW Ox02
MOVWF TBLPTRH
MOVLW CNTVAL
MOVWF RCOUNT
CLRF TRISB
B6
TBLRD*
MOVFF TABLAT,PORTB
INCF TBLPTRL,F
DECF RCOUNT,F
B6
BNZ
HERE GOTO HERE
icounter Icc in fileReg
icounter value
;burn into ROM starting at 0
;WREG = 50, low-byte addr
;look-up table low-byte addr
;WREG = 2, high-byte addr
;look-up table high-byte addr
iWREG = 03, counter value
;load counter
;TRSIB = 00 (Port B as output)
;read table byte pointed to by TBLPTR
;send it to Port B
;increment to point to next char
idee the counter
jrepeat if counter not zero
istay here
;data is burned into code(program)
ORG
Ox250
MYDATA DB
space starting at 250H
nUSAI!
END
(b)
B7
EXIT
This method uses null char for end of string
ORG
OOOOH
MOVLW Ox50
MOVWF TBLPTRL
MOVLW Ox02
MOVWF TBLPTRH
CLRF TRISB
TBLRD*
MOVF TABLAT,W
EXIT
BZ
MOVWF PORTB
INCF TBLPTRL,F
B7
BRA
GOTO EXIT
ORG
MYDATA DB
END
208
;burn into ROM starting at 0
;WREG = 50, low-byte addr
; look-up table low-byte addr
;WREG = 2, high-byte addr
ilook-up table high-byte addr
;TRSIB = 00 (Port B as output)
; bring in next byte
;copy to WREG (Z = 1, i f null)
jis it null char? exit if yes
; send it to Port B
iincrement pointing to next
; continue
Ox250
TlUBAn,O
;notice null
Example 6-11
Repeat Example 6-10, using auto-increment.
Solution:
B7
EXIT
ORG
OOOOH
MOVLW Ox50
MOVWF TBLPTRL
MOVLW Ox02
MOVWF TBLPTRH
CLRF TRISB
TBLRD*+
MOVF TABLAT,W
BZ
EXIT
MOVWF PORTB
BRA
B7
GOTO EXIT
ORG
MYDATA DB
END
Ox250
"USA", 0
;burn into ROM starting at 0
jWREG
50 low-byte addr
; look-up table low-byte addr
2, high-byte addr
;WREG
ilook-up table high-byte addr
;TRSIB
00 (Port B as output)
;bring in next byte and inc TBLPTR
1, i f null)
iCOPY to WREG (Z
jis it null char? exit if yes
isend it to Port B
; continue
~
~
~
~
inotice null
Example 6-12
Assume that ROM space starting at 500H contains the message "The Promise of World
Peace". Write a program to bring it into CPU one byte at a time and place the bytes in
RAM locations starting at 40H.
Solution:
B8
EXIT
ORG
OOOOH
MOVLW OxOO
MOVWF TBLPTRL
MOVLW Ox05
MOVWF TBLPTRH
LFSR 2,Ox40
TBLRD*+
MOVF TABLAT,W
EXIT
BZ
MOVWF POSTINC2
BRA
B8
GOTO EXIT
; burn into ROM starting at 0
;WREG
00 low-byte addr
; look-up table low-byte addr
OS, high-byte addr
;WREG
; look-up table high-byte addr
40H, RAM address
iload pointer. FSR2
table,
then
increment TBLPTR
iread the
to
WREG
(Z
1
i
f null)
=
iCOpy
jexit i f end of string
iCOpy WREG to RAM and INC FSR2
~
~
~
j---------------------message
ORG
Ox500
;data burned starting at Ox500
MYDATA DB liThe Promise of World Peace",O
END
Look-up table and RETLW instruction
The look-up table is a widely used concept in microcontroller programming. It allows access to elements of a frequently used table with minimum operations. As an example, assume that for a certain application we need x' values in
the range of 0 to 9. We can use a look-up table instead of calculating the values,
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
209
which takes some time. In the PIC, to get the table element we first call the lookup table, then we add a fixed value to the PCL (low-byte portion of the program
counter) to index into the look-up table. Upon return from the table, the RETLW
instruction will provide the desired look-up table element in the WREG register.
This is shown in Examples 6-13 and 6-14.
Assume that the lower three bits of Port C are connected to three switches. Write a program to send the following ASCII characters to Port D based on the status of the
switches.
000
001
010
011
100
101
110
'0'
'I'
'2'
'3'
'4'
'5'
'6'
III
'7'
0
TRISC
TRISD
PORTC,W
B'00000111'
ASCI TABLE
PORTD
B1
;TRISC = FFh (Port C as input)
;TRISD = 00 (Port D as output)
jread x from Port C into WREG
imask upper 5 bits
;get ASCII from look-up table
;copy it to Port D
; continue
Solution:
B1
ORG
SETF
CLRF
MOVF
ANDLW
CALL
MOVWF
BRA
;look-up table for ASCII numbers 0-7
ASCI TABLE
MULLW Ox2
;align it for even address for 2-byte RETLW opcode
MOVFF PRODL, WREG ;put it into WREG for indexing
ADDWF PCL
; PCL = PCL + WREG
RETLW 10 1
;ASCII for 0
RETLW '1'
;ASCII for 1
RETLW '2'
;ASCII for 2
RETLW r 3'
inotice that each ASCII value is placed
RETLW '4'
iin the ROM at an even address
RETLW '5'
RETLW
'6'
RETLW '7'
END
210
0000
0010
0020
D7F A.
OD02
CFF3
FrE8
OC32
OC33
OC34
OC35
OC36
FFFF
0030
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
.6<0.1.2.
3.4.5.6. 7 . . . . . . .
Example 6-14
Write a program to get the x value from Port B and send x 2 to Port C. Assume that
RB3-RBO has the x value of 0-9. Use a look-up table instead of a multiply instruction.
What is the value of Port C if we have 9 at Port B?
Solution:
B1
ORG
SETF
CLRF
MOVF
ANDLW
CALL
MOVWF
BRA
0
TRISB
TRISC
PORTB,W
OxOF
XSQR_TABLE
PORTC
B1
;TRISB = FFh (Port B as input)
;TRISC = 00 (Port C as output)
;read x from Port B into WREG
jmask upper bits
iget X2 from the look-up table
jCopy it to Port C
; continue
; look-up table for square of numbers 0-9
XSQR_TABLE
MULLW Ox2
;align it for even address
MOVFF PRODL, WREG iPut it into WREG for indexing
ADDWF PCL
;PCL = PCL + WREG
RETLW 0'0'
isquare of 0
RETLW 0'1'
isquare of 1
RETLW D'4'
isquare of 2
RETLW D' 9'
isquare of 3
jsquare of 4 (10 hex)
RETLW D'16'
RETLW D'25 '
isquare of 5 (19 hex)
RETLW D'36'
isquare of 6 (24 hex)
RETLW D'49'
isquare of 7 (31 hex)
RETLW D'64'
isquare of 8 (40 hex)
jsquare of 9 (51 hex)
RETLW D' 811
END
DBOF
0010
0020
0030
00"l0
0050
0060
D7F9
OD02
CFF3
OC09
OC10
FFFF
FFFF
FFFF
OC19
FFEB
OC24
FFfF
FFFF
FFFF
FrYF
FFFF
FFFF
FFFF FFFF FFFF FFFF
FFFF
FFFF
FFFF
EC09
FOOD
26F9
BIll
OC31
OC4:0
oe51
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
OC04
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
OCOl
........
• • • • • •$•
........ ....... .
........ ....... .
........ ....... .
........ ....... .
From the screen shot above, notice that location 001A has the "RETLW D' 0 ," opcode
and operand, the square ofO. Location OOIC has 01, the square of I. Location 001E has
04, the square of 2. Location 0020 has 09, the square of 3. Location 0022 has 10, the
square of 4 (4 x 4 = 16 = 10H) and so on. Notice that the odd addresses have the opcode
for RETLW, which is OC hex. If we have 9 at Port B, then Port C will have 51 H, which
is the hex value of decimal 81 (9 2 = 81).
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
211
Accessing a look-up table in RAM
The look-up table elements can also be in RAM instead of ROM.
Sometimes we need to bring in the elements of the look-up table from RAM
because the elements are dynamic and can change. The PIel8 allows us to do that
using the FSR as pointer. For example, the instruction "MOVFF PLUSW2, PORTD"
will bring elements of the look-up table pointed to by the address location formed
by the addition of FSR2 + WREG. In this case, WREG is used as an index into the
look-up table. See Examples 6-15 and 6-16.
Example 6-15
Repeat Example 6-13 assuming that the look-up table elements are in data RAM locations starting at address 20H as shown below.
20 = ('0')
21 =('1')
22 = ('2')
23 = ('3')
24 = ('4')
25 = ('5')
26 = ('6')
27 = ('7')
Solution:
B1
ORG
SETF
CLRF
LFSR
MOVF
ANDLW
MOVFF
BRA
END
0
TRISC
TRISD
2,Ox20
PORTC, W
B'OOOOOlll'
PLUSW2,PORTD
B1
;TRISC = FFh (Port C as input)
;TRISD = 00 (Port D as output)
;load pointer. FSR2 = 20H, RAM address
jread x from Port C into WREG
imask upper 5 bits
;get data pointed to by FSR2 + WREG
When simulating this program on your MPLAB, make sure the RAM locations 20-27H
have the elements of the look-up table. Notice that the "MOVFF PLUSW2, PORTD" instruction will bring the value from its RAM location and put it on PORTO.
OFBl
212
00
00
aD
00
00
00
00
aD
00
DO
00
00
....... .
31
32
33
34
35
36
37
aD
00
00
00
00
00
00
00
01234567
00
00
00
00
00
00
00
aD
00
00
00
DO
00
DO
DO
o
PORTE
~ PORT,::,
07
OF83
PORTD
37
7
SS
OF84
PORTE
00
o
00000000
nOllnn111
00110111
00000000
.
7
Example 6-16
Write a program to get the x value from Port B and send x' + 2x + 3 to Port C. Assume
PB3-PBO has the x value of 0-9. Use a look-up table instead of a multiply instruction.
Solution:
ORG
SETF
CLRF
B1
MOVF
ANDLW
CALL
MOVWF
BRA
XSQR_TABLE
MULLW
MOVFF
ADDWF
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
RETLW
END
0
TRISB
TRISC
PORTB,W
OxOF
XSQR_TABLE
PORTC
B1
;TRISB = FFh (Port B as input)
;TRISC = 00 (Port C as output)
iread x from Port B into WREG
jmask upper bits
jget x' from the look-up table
iCOpy it to Port C
; continue
Ox2
;align it for even address
PRODL, WREG iPut it into WREG for indexing
PCL
;PCL = PCL + WREG
i (0) 2 + 2 (0) + 3
D r 3'
3
i (1) 2 + 2 (1) + 3
6
D ' 6'
Dr 11'
11
; (2)' + 2 (2) + 3
; (3) 2 + 2 (3) + 3
18
D r 18 '
Dr 27 r
; (4) 2 + 2 (4) + 3
27
; (5) 2 + 2 (5) + 3
38
D'38 '
Dr 51'
51
; (6)' + 2 (6) + 3
i (7) 2 + 2 (7) + 3
D'66 1
66
i (8) 2 + 2 (8) + 3
D'S3'
83
D'102'
102
; (9)' + 2 (9) + 3
Writing table elements in PIC18
In PICl8 we also have the TBLWRT instruction, which allows us to write
(store) data into program ROM space. While the TBLRD instruction can be used
with any family member of the PIel8 regardless of the type of ROM it has, the
TBLWRT can be used only with PICl8 chips that have flash ROM for the program
ROM space. The TBLWRT instruction will not work for PICl8 chips with OTP
(one-time programmable) or mask ROM. In mask ROM, the information (code
and data) is burned into the ROM during the chip fabrication by the Microchip
Corp. Because writing to flash ROM involves manipulating the configuration bits
it is discussed in Chapter 14.
Review Questions
1. The instruction "TBLRD*" uses register
2.
3.
4.
5.
6.
7.
as address pointer.
What register is incremented upon execution of the TBLRD* instruction?
What register is holding data, once it is read by the TBLRD* instruction?
What is the size ofTBLPTR? How much ROM space does it cover?
What register is incremented upon execution of the TBLRD*+ instruction?
What is the difference between the TBLRD*+ and TBLRD+* instructions?
True or false. The TBLWT instruction works with all ROM versions of the
PIClS family.
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
213
SECTION 6.4: BIT-ADDRESSABILITY OF DATA RAM
Many microprocessors such as the 386 or Pentium allow programs to
access registers and I/O ports in byte size only. In other words, if you need to check
a single bit of an I/O port, you must read the entire byte first and then manipulate
the whole byte with some logic instructions to get hold of the desired single bit.
This is not the case with the PIC as we saw in Chapter 4. Indeed, one of the most
important features of the PIC is its ability to access the file register's RAM location in bits as well as bytes. This means that all I/O ports, SFRs, and general purpose RAM areas for the PIC 18 are bit-addressable because they are part ofthe file
register data RAM. WREG is also bit-addressable because it is part of the SFRs.
This is a very powerful feature of the PIC I 8 family. In this section, we provide
more programming examples of the bit-addressable option of the PICI8 family.
Bit-addressable file register data RAM
The entire 4096 bytes of file register data RAM of the PIC I 8 are bitaddressable. This means that while ROM program space is only byte-addressable,
the 4K of data RAM is both byte- and bit-addressable. To distinguish between the
byte-addressable and bit-addressable options of data RAM, the PIC I 8 provides
two categories of instructions: bit-oriented and byte-oriented instructions. Bit-oriented instructions are called bit-addressable, while byte-oriented instructions are
referred to byte-addressable.
The bit-oriented instructions are given in Table 6-4. Notice that the
bit-oriented instructions use only one addressing mode, the direct addressing
mode. In the first three sections of this chapter we showed various addressing
modes of byte-addressable space of the PICI8, among them register indirect
addressing mode for both data RAM and program (code) ROM. Note that there is
no register indirect addressing mode for bit-oriented instructions in the PIC I 8.
File register bit-addressability
As we discussed in Chapter 2, the PICI8 can have up to 4096 bytes of file
register data RAM depending on the family member. We can access either the
entire 8 bits or any single bit without altering the rest. When accessing a file register in a single-bit manner, we use the syntax "Bit-Oriented-instr fileReg,
x" where fileReg is any register in the file register and X is the desired bit number
from 0 to 7 for data bits 00 to 07. For example, the instruction "BTG Ox20, 7"
will toggle 07 of RAM location 20H. As we mentioned earlier in this chapter,
every register, including WREG, is assigned a byte address in the file register and
Table 6-4: Single-Bit (Bit-Oriented) Instructions for PIelS
Instruction
Function
BSF fileReg,bit
Bit Set fileReg (set the bit: bit - I)
BCF fileReg,bit
Bit Clear fileReg (clear the bit: bit = 0)
BTG fileReg,bit
Bit Toggle fileReg (complement the bit)
BTFSC fileReg,bit
Bit test fileReg, skip if clear (skip next instruction if bit - 0)
BTFSS fileReg,bit
Bit test fileReg, skip if set (skip next instruction if bit = I)
Note: fileReg can be any location of file register data RAM.
214
ports PORTA-PORTE are part of the file register. For example, "BSF PORTB, 5"
sets high bit RB5 of Port B. Notice that when code such as "BSF PORTB, 5" is
assembled, it becomes "8A81 " because Port B has the RAM address of 81 H in the
access bank. Examine the next few examples in this section to gain insight into the
bit addressibility of the file register in the PIC 18.
Example 6-17
A switch is connected to pin RC7. Write a program to check the status of the switch and
perform the following:
(a) If switch = 0, send letter 'N' to Port D.
(b) If switch = I, send letter 'Y' to Port D.
Solution:
BSF
CLRF
AGAIN BTFSS
BRA
MOVLW
MOVWF
GOTO
OVER MOVLW
MOVWF
GOTO
TRISC,7
TRISD
PORTC, 7
OVER
Aryl
PORTD
AGAIN
A'N '
PORTD
AGAIN
imake RC7 an input
jmake Port D an output port
;bit test RC7 for HIGH
;it must be LOW
;WREG = 'Y' ASCII letter Y
;issue WREG to PD
iwe could use BRA instead
;WREG = 'N' ASCII letter N
iissue WREG to PORTD
iwe can use BRA too
Example 6-18
Write a program to toggle RBI a total of200 times. Use file register RAM location
32H to hold your counter value.
Solution:
MYREG EQU Ox32
CNTVAL EQU D'200'
MOVLW CNTVAL
MOVWF MYREG
BCF
TRISB,l
AGAIN BTG
PORTB,l
DECF MYREG,F
BNZ
AGAIN
iset aside loc Ox20 reg
;load counter into WREG
;load the count into MYREG location
;TRISB bit = 0, make RBl an output
;toggle bit RBl
jdecrement MYREG
;continue until counter is zero
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
215
Example 6-19
A switch is connected to pin RC7. Write a program to get the status of the switch and
perform the following.
(a) IfRC7 = 0, increment Port B.
(b) If RC7 = I, decrement Port B.
Solution:
BSF
CLRF
AGAIN BTFSS
BRA
INCF
GOTO
OVER DECF
GOTO
TRISC,7
TRISB
PORTC, 7
OVER
PORTB,F
AGAIN
PORTB,F
AGAIN
irnake RC7 an input
imake Port B an output port
;bit test RC7 for HIGH
; it must be LOW
; increment
jWe can use BRA too
; decrement
jwe can use BRA too
Example 6-20
A switch is connected to pin RBO. Write a program to get the status of the switch and
save it in DO of fileReg location Ox20.
Solution:
MYBITREG EQU Ox20
TRISB,O
BSF
AGAIN BTFSS PORTB, 0
GOTO OVER
MYBITREG,O
BSF
GOTO AGAIN
MYBITREG,O
OVER BCF
GOTO AGAIN
;set aside lac Ox20 reg
;make REO an input
;bit test RBO, skip if set
;it must be LOW (BRA is OK too)
;set bit DO = 1
jwe can use BRA too
;clear DO
(DO = 0)
jwe can use BRA too
Example 6-21
Write a program to see if the RAM location 37H contains an even value. If so, send it
to Port B. If not, make it even and then send it to Port B.
Solution:
MYREG EQU Ox37
CLRF TRISB
AGAIN BTFSS MYREG,O
GOTO OVER
MYREG,O
BCF
OVER MOVFF MYREG,PORTB
GOTO AGAIN
216
i8et aside loc ox37 reg
imake Port B an output port
ibit test DO, skip i f set
;it must be LOW
;clear bit DO = 0
jCopy it to Port B
jwe can use BRA too
Example 6-22
Write a program for Port B to count up from 0000 to IIII (binary).
Solution:
CLRF
CLRF
AGAIN INCF
BTFSS
BRA
GOTO
TRISB
PORTB
PORTB,F
PORTB, 4
AGAIN
;TRISB
0, make PB output
=
iPort B
=
a
jincrement Port B
;test D4 bit of Port B
$
Notice how it counts up from 0000 to IIII and, when it becomes 10000, skips the loop.
Example 6-23
Write a program to check the status of the D7 bit of file register location Ox20 and make
the following decisions:
(a) IfD7 = 0, send "NO" to Port B.
(b) IfD7 = I, send "YES" to Port B.
Solution:
MYREG EQU Ox20
CLRF TRISB
AGAIN BTFSS MYREG,7
OVER
BRA
MOVLW A'y'
MOVWF PORTB
OVER
MOVLW
AIEl
MOVWF
MOVLW
MOVWF
GOTO
MOVLW
MOVWF
MOVLW
MOVWF
GOTO
PORTB
A'S'
PORTB
AGAIN
A'N'
PORTB
AIO'
PORTB
AGAIN
imake Port B an output port
;bit test for HIGH
i i t must be LOW
;WREG = 'Y'
;issue WREG
;WREG = 'E'
jissue WREG
i WREG = 'S'
;issue WREG
iwe
can use
;WREG = 'N'
;issue WREG
,·WREG = '0'
;issue WREG
jwe
can use
ASCII letter
to Port B
ASCII letter
to Port B
ASCII letter
to Port B
BRA too
ASCII letter
to Port B
ASCII letter
to Port B
BRA too
Y
Y
Y
N
Y
Status register bit-addressability
Of the bit-addressable registers, we will concentrate on the familiar status
register. The rest will be discussed in future chapters.
Now let's see how we can use bit-addressability of the status register. As
we discussed in Chapter 2, 5 bits in the status register are set aside for the flags C,
DC, Z, N, and OV. See Figure 6-2 and Example 6-24.
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
217
07
x
x
x
N
I OV I
DO
Z
DC
C
C - Carry flag
OV - Overflow flag
DC - Digital Carry flag
N - Negative flag
Z - Zero flag
x - 05, 06, and 07 are not implemented, and reserved for
future use.
Figure 6-2. Bits of the Status Register
Example 6-24
While we have instructions such as BC (branch carry) and BZ (branch zero) to check
the carry and zero flag bits, show how would you use the status register flag to check
the (a) C and (b) Z flags.
Solution:
(a) The C flag is DO of the status register; therefore, we can use the following instruction to check the C flag:
BTFSS STATUS,C
;bit test C,
skip if C
=
1
(b) The Z flag is D3 of the status register; therefore, we can use the following instruction to check the Z flag:
BTFSS STATUS,Z
;bit test Z, skip if Z
=
1
Review Questions
1. True or false. All I/O ports ofthe PIC 18 are bit-addressable.
2. True or false. The status register ofthe PICI8 is bit-addressable.
3. True or false. All file register RAM locations of the PIC are bit-addressable.
4. Indicate which of the following registers are bit-addressable.
(a) Port A (b) Port B
(c) WREG
(d) status register (e) 21-bit PC
5. Of the 4096 bytes of RAM in the PICI8, how many bytes are bit-addressable?
6. How would you check to see whether bit Dl of RAM location 3 is HIGH or
LOW?
7. State what each instruction does.
(a) BSF ox20,1
(b)
(e)
BCF ox32,7
(d) BSF PORTB, 4
BSF STATUS, 1
8. Show how to clear the carry flag.
218
(c) BSF Ox12,2
SECTION 6.5: BANK SWITCHING IN THE PIC18
The PICIS microcontroller has a maximum of 4K of data RAM space.
Although not all members of the family have the entire RAM installed, every
member of the family has at least the access bank for the file register. The file register RAM is divided into banks of 256 bytes each, which gives us a total of 16
banks in the PICIS. The minimum bank that every PICIS has is called the access
bank, as we discussed in Chapter 2. The access bank is made of 12S bytes oflower
addresses and 12S bytes of higher addresses. While the lower 12S bytes of address
space 000--07FH are used for general-purpose RAM, the higher 12S bytes are dedicated to the SFRs (special function registers) residing in address space
FSO-FFFH. The vast majority of the PICIS chips we see on the Microchip web site
have more than just the access bank. In this section we show how to use bank
switching to take advantage of the entire data RAM space of the PIC IS.
The A bit and bank switching
All the instructions we have used so far assumed the access bank as the
default bank. This was achieved by ignoring the letter A in instructions such as
"MOVWF fileReg, A". In other words, the instruction "MOVWF fileReg" is really
"MOVWF f ileReg, A" where the A bit can be 0 or 1. If A = 0, then the access bank
is the default bank. If A = I, however, then the instruction will use the bank selector register (BSR) to select the bank instead of using the access bank. If A is not
stated in a given instruction, it means A = 0 and the access bank is the default bank.
That is what we have done so far for the simple reason of making the PIC IS
Assembly language easier to understand and master. Next, we examine the role of
the BSR register in bank switching.
The BSR register and bank switching
To use banks other than the access bank, we need to set bit A = I in the coding of the instruction. With A = 1, we use the BSR (bank select register) to choose
the desired bank. The BSR is an S-bit register and is part of the SFRs. Of the S bits
of the BSR, only 4 least-significant bits are used in the PICIS. The upper 4 bits are
set to zero and are ignored by the PICIS. The 4-bit BSR gives us 16 banks, and
because each bank is 256 bytes, we cover the entire 4096 (16 x 256 = 4096) bytes
of the data RAM file register using bank switching. The 4K (4096) bytes of the
data RAM are organized as banks 0 to F, where the lowest bank, 0, has an address
of OO-FFH, and the highest bank is bank F with the addresses of FOO-FFFH. In
the PICIS, the last 128 bytes of bank F are always set aside for the SFRs, while
general purpose registers always start at address 0 of bank O. Upon power-on reset,
BSR = 0 (0000 binary), which indicates that only the lowest addresses of data
RAM, from 000 to OFFH, can be used for the general-purpose register in addition
to the SFRs, which always reside in the last half of bank F. Similarly, if we make
BSR = I (0001 binary), then PICIS selects bank I using the 100-IFFH addresses in addition to the SFRs, which use only the last half of the bank with addresses
of F80-FFFH. To select bank 2, we load BSR with the value 02 (0010 binary),
which allows access to the bank addresses 200-2FF in addition to the SFR
addresses of FSO-FFFH. As we can see, no matter how much data RAM we have
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
219
in the PIC IS, the OP register always starts at address 000 and goes up, while the
SFRs start at the other end of the 4 KB, at address FFF, and come down. At the
present time PIC is using only the highest 12S bytes of bank F (FSOH-FFFH
address) for the SFRs. In the future they might start to use the rest of bank F and
may even use bank E for SFRs, if the special functions embedded into the PIC IS
keep increasing. Although the number of bytes in bank F used for SFRs in the
PIC IS chip varies depending on the functions embedded into the chip, the SFRs
always start at address FFF and go down. This point must be emphasized. For
example, in the case of the access bank, the last half of bank F is set aside for
SFRs, even though in some family members not all 12S bytes are needed due to
the limited number of functions supported by that chip. See Table 6-5 for data
RAM file registers of some PICIS chips. Note that although we can use any of the
addressing modes, such as immediate, direct, or register indirect to access the OP
register regions, we use only direct addressing mode in accessing the SFR registers. To gain a better understanding of the bank switching, we use the PICISF45S
chip to show some examples.
8-bit
Bank 0
RAM
Bank 1
Access
Bank
RAM
SFR
Bank 14
Bank 15
SFR
Figure 6-3. Data RAM Registers
Table 6-5: Data RAM Bank for Selected PIC18 Chips
File Register
SFR
Available space for GPR
(Bytes)
=
(Bytes) +
(Bytes)
PICISFI220 512
256
256
1792
256
1536
PICISF452
PIC 1SF2220 76S
256
512
PICISF45S
1792
256
1536
15S
393S
PICISFS722
4096
Note: The newer versions of the PICISF45S!452 are the PICISF45S0!4520.
Extracted from http://www.microchip.com
220
Bank switching and "INCF F, D, A" instruction
The PIC 18F458 has a total of 1792 bytes for the data RAM file register.
The bank organization for the PICl8F458 is shown in Figure 6-3. All the examples we have seen so far ignored the A bit in the instruction, which means that A
= O. With A = 0, the access bank is the default bank. Now to use banks other than
the access bank, two things must be done:
I. Load the BSR with the desired bank number, and
2. Make A = 1 in the instruction itself.
Therefore, instruction "INCF MYREG, F, 1" has a totally different meaning from "INCF MYREG, F, 0". The A = 1 means to use the bank pointed to by
BSR. In the following code, we first load the bank number into the BSR register
using the MOVLB instruction, and then manipulate the contents of RAM location
Ox240 (location 40 of bank 2):
MYREG EQU
MOVLB
MOVLW
MOVWF
INCF
INCF
INCF
Ox40
Ox2
0
MYREG,
MYREG,
MYREG,
MYREG,
1
F,
F,
F,
iload 2 into BSR (use bank 2)
;WREG " 0
jloc Ox240
(0) , WREG
0, Notice A
(1) , WREG
1 jloc Ox240
0, Notice A
(2) , WREG
1 ;loc Ox240
0, Notice A
(3) , WREG = 0
1 iloc Ox240
=
1
=
1
=
1
Contrast the above program with the one below:
MOVLB
MOVLW
MOVWF
INCF
INCF
INCF
Ox2
0
MYREG
MYREG,
MYREG,
MYREG,
iload 2 into BSR (use bank 2)
;WREG
"
0
(0) , WREG
(1) , WREG
(2) , WREG
(3) , WREG
iloc Ox40
;loc Ox40
iloc Ox40
;loc Ox40
F
F
F
0
0, Notice A
0, Notice A
0
=
=
0
0
Although we loaded BSR, because the A bit was not indicated, MPASM
defaults it to zero, which means to use location Ox40 of the access bank. The A bit
in the instruction field is given in Figure 6-4.
10010110DAI
ffff
I ffff I
D - destination for operation
A - bank accessed for operation
o
=F, destination is file Reg
=W, destination is WREG
A =0, use default access bank
A = 1, use bank pointed to by
D
D
BSR (Bank Selector Register)
~
f
~
FF
Figure 6-4. A Bit in the Instruction Field for INCF
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
221
Examine the following code to see the role of the D and A bits:
MOVLB
MOVLW
MOVWF
INCF
INCF
INCF
INCF
INCF
INCF
INCF
Ox2
0
Ox20,1
Ox20 f W, 1
Dx20,W,l
Ox2Q, W, 1
Ox20,F,1
Dx20,F,l
Ox20, F, 1
Ox20,F,l
;load 2 into BSR (use bank 2)
;WREG = 0
; lac 0x220 = (0) , WREl3 :::: 0, D = W, A = 1 rreans Bank 2
(0) , WREG
1, D
iloc Ox220
W, A
1
(0) , WREG
;loc Ox220
1, D
W, A
1
(0) , WREG
;loc Ox220
1, D
W, A
1
(1) , WREG
1, D
iloc Ox220
F, A
1
(2) , WREG
;loc Ox220
1, D
F, A
1
jloc Ox220
(3) , WREG
1, D
F, A
1
(4) , I,REG
iloc Ox220
1, D
F, A
1
Simulate the next few examples with MPLAB and examine the data RAM
memory to see how bank switching works.
Example 6-25
Write a program to copy the value 55H into RAM memory locations 340H to 345H
using:
(a) direct addressing mode.
(b) a loop.
Solution:
(a)
MOVLB
MOVLW
MOVWF
MOVWF
MOVWF
MOVWF
MOVWF
Ox3
Ox55
Ox40, 1
Dx41, 1
Ox42, 1
Ox43, 1
Ox44, 1
iBANK 3
;load WREG with value 55H
; copy WREG to RAM location
iCOpy WREG to RAM location
iCOpy WREG to RAM location
iCOpy WREG to RAM location
; copy WREG to RAM location
340H
341H
342H
343H
344H
(b)
CODNT EQU Oxl0
MOVLB Ox3
MOVLW Ox5
MOVWF CODNT
LFSR 0,Ox340
MOVLW Ox55
Bl
MOVWF INDFO, 0
INCF FSROL
DECF CODNT,F,O
BNZ
Bl
;loc 10h
; BANK
;WREG
iload
;load
;WREG
;copy
3
= 5
the counter, count = 5
pointer. FSRO = 40H, RAM address
= 55h value to be copied
WREG to RAM loc FSRO points to
;increment FSROL pointer
;decrement the counter
;loop until counter:::: zero
The following shows RAM contents after the above program is run:
340 = (55)
341 = (55)
342 = (55)
343 = (55)
344 = (55)
222
0320
0330
·'8"+55
0350
0360
00 00 DO 00 00 00 00 00 00
00
00 00 00 00 00 00 00 00 00 DO 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 DO 00 DO 00 00 00 00
00
55
55
55
........ ....... .
........
........
........ ....... .
uuuuu ...
....... .
Figure 6-5. Data RAM Shown for Example 6-25
Table 6-6 shows the banks for various sizes of the data RAM in the PICI8
chip.
Table 6-6: PICIS Data Memory Range
Data Memory
64
128
256
512
640
768
1024
1280
1536
1792
2048
2304
2560
2816
3072
3328
3584
3840
3968
Banks
0, 15
0, 15
0, 15
0-1, 15
0-2, 15
0-2, 15
0-3, 15
0-4, 15
0-5, 15
0-6, 15
0-7, 15
0-8, 15
0-9, 15
0-10, 15
0-11,15
0-12, 15
0-13, 15
0-14, 15
0-15
MOVFF and banks
The great thing about the MOVFF instruction is that there is no need to
worry about bank switching because it can move data anywhere within the 4K of
RAM space. See Figure 6-4. Also see Example 6-26.
Examining Data RAM space using MPLAB simulator
The MPLAB simulator is a great tool to examine data RAM contents. We
encourage its use to examine and verify the results of programs using data RAM.
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
223
Example 6-26
Assume RAM locations 330-334H of the PIC18F458 have the string of ASCII data
shown below. Write a program to get each character and send it to Port B one byte at a
time. Show the program using
(a) direct addressing mode.
(b) register indirect addressing mode.
330 = ('H')
331 = ('E')
332 = ('L')
333 = ('L')
334 = ('0')
Solution:
(a) Using direct addressing mode
CLRF TRISB
MOVFF Ox330,
MOVFF Ox33l,
MOVFF Ox332,
MOVFF Ox333,
MOVFF Ox334,
PORTB
PORTB
PORTB
PORTB
PORTB
imake Port B an output
contents of lac Ox330 to PB
iCOPY
(b) Using register indirect addressing mode
COUNTREG EQU Ox20
CNTVAL EQU 5
CLRF TRISB
MOVLW CNTVAL
MOVWF COUNTREG
LFSR 2,Qx330
B3
MOVF INDF2,W
MOVWF PORTB
INCF FSR2L
DECF COUNTREG,F
BNZ
B3
0300
0310
0320
0330
00 00 00 00 00
00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
48 65 6C 6C 6f 00 00 00
;fileReg loc 20 for counter
; counter value
out)
irnake Port B an output (TRSIB
;WREG = 5
i10ad the counter, count = 5
iload pointer. FSR2 = 330H, RAM address
iCOpy RAM loc FSR2 points at to WREG
iCOPY WREG to PORTB
; increment FSR2 to point at next loc
; decrement counter
; loop until counter = zero
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Figure 6-6. Example 6-26 Data RAM Dump in MPLAB
224
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
....... .
....... .
........
Hello ...
........
........
........
....... .
........
.. . ....
Example 6-27
Write a program for the PICI8F452 chip to put FFH into 16 RAM locations starting at
RAM address 160H. Use:
(a) INCF FSRnL.
(b) auto-increment.
Solution:
(a)
COUNTREG EQU oxlO
CNTVAL EQU D' 16'
MOVLW CNTVAL
MOVWF COUNTREG
LFSR 1,Ox160
MOVLW OxFF
B2
MOVWF INDFl,O
INCF FSRIL
DECF COUNTREG,F
BNZ
B2
ifileReg Icc for counter
icounter value
;WREG = 16
iload the counter, count = 16
;load pointer. FSRI = 60H, RAM address
;load OxFF
iffiove W to RAM lac FSRI points to
;increment FSRIL, point to next lac
;decrement counter
iloop until counter = zero
(b)
COUNTREG EQU OxlO
CNTVAL EQU D' 16 '
MOVLW CNTVAL
MOVWF COUNTREG
LFSR 1,Ox160
MOVLW OxFF
B3
MOVWF POST INC 1 , a
DECF COUNTREG,F
BNZ
B3
•
ifileReg lac for counter
icounter value
;WREG = 16
;load the counter, count = 16
;load pointer. FSRI = 160H, RAM address
iload OxFF
;decrement counter
;loop until counter
zero
i"J Ll ilxi
F,le ReglSte"
-=mmmmmmmmmmmmmmmmm~
0140
01S0
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0170
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Fi"M- FF
0180
0190
He,
FF
rr rr
FF
FF
rr rr
FF
FF FF rr FF FF FF rr
....... .
....... .
....... .
....... .
....... .
....... .
........
........
........
........
........
........
~
sJ'fIlboIc
Figure 6-7. Data Example 6-27 Data RAM Dump
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
225
Example 6-28
Write a program to copy a block of data from RAM locations 330H-33FH to
360H-36FH.
Solution:
COUNTREG EQU Ox20
CNTVAL EQU OxOF
CLRF TRISB
MOVLW CNTVAL
MOVWF COUNTREG,1
LFSR 1, Ox33 0
LFSR 2,Ox360
B3
MOVFF INDFl, INDF2
INCF FSRIL
INCF FSR2L
DECF COUNTREG,F
BNZ
B3
0350
0360
00
00
00
00
6C
6C
6F
00
00
00
00
00
00
00
00
00
00
00
00
20
00
00
00
00
ifileReg loc 20 for counter
icounter value = 15
;make Port B an output (TRSIB
FFH)
;WREG = 15
;load the counter, count = 15
;load pointer. FSRI
330H, RAM address
i10ad pointer. FSR2 = 360H, RAM address
jincrement FSRI to point at next loc
iincrement FSR2 to point at next loc
;decrement counter
until counter = zero
i100P
57
6F
72
6C
64
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
21 DO
00 00
00 00
00 00
00 00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Hello No rId
....... .
....... .
....... .
....... .
I ••••
........
........
........
........
Hello 00 rId! ....
0340
00 00 00 00 00
0350
00 00 00 00 00 00
MFEB'.48 65 6C 6C 6F 20
0370
00 00 00 00 00 00
Figure 6-8. Before and
00
00 00 00 00 00
00 00 DO 00 00 00 00
57 6F 72 6C 64 21 00
00 00 00 00 00 00 00
00
00
00 00 00
00 00 00
00 00 00
....... . ........
....... . ........
Hello No rld
....... . ........
I ••••
is Run
Review Questions
1. True or false. The PICI8 uses the last bank for the SFRs.
2. True or false. The PICl8 uses a total of256 bytes for each bank.
3. True or false. The first 128 bytes of RAM in the PICI8 are used for the access
bank.
4. Give the address for the upper RAM used for SFR.
5. Show how to put value 99H into RAM location 202H in the PIC18F458.
6. Show how to put value 55H into RAM location 408H in a PICI8 with 4K of
RAM.
7. True or false. The MOVFF instruction can copy a byte from any RAM location to any other RAM location in the PICI8.
8. The BSR register is a(n) __-bit register, but only _ bits of it are used for
bank selection.
226
SECTION 6.6: CHECKSUM AND ASCII SUBROUTINES
In this section we look at some widely used subroutines such as checksum
byte, BCD, and ASCII conversion. We will also examine the use of a stack in the
PICI8.
Checksum byte in ROM
To ensure the integrity of ROM contents, every system must perform a
checksum calculation. The checksum will detect any corruption of the contents of
ROM. One cause of ROM corruption is current surge, either when the system is
turned on, or during operation. To ensure data integrity in ROM, the checksum
process uses what is called a checksum byte. The checksum byte is an extra byte
that is tagged to the end of a series of bytes of data. To calculate the checksum byte
of a series of bytes of data, the following steps can be taken:
I. Add the bytes together and drop the carries.
2. Take the 2's complement of the total sum, and that is the checksum byte, which
becomes the last byte of the series.
To perform a checksum operation, add all the bytes, including the checksum byte. The result must be zero. If it is not zero, one or more bytes of data have
been changed (corrupted). To clarify these important concepts, see Example 6-29.
Checksum program
The checksum generation and testing program is given in subroutine form.
We have divided Program 6-1 into three subroutines (or subprograms). These three
subroutines perform the following operations:
I. Retrieve the data from code ROM.
2. Calculate the checksum byte.
3. Test the checksum byte for any data error.
Each of these subroutines can be used in other applications. Example 6-29
shows how to manually calculate the checksum for a list of values. Also see
Program 6-1.
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
227
Example 6-29
Assume that we have 4 bytes of hexadecimal data: 25H, 62H, 3FH, and 52H.
(a) Find the checksum byte.
(b) Perform the checksum operation to ensure data integrity.
(c) Ifthe second byte, 62H, has been changed to 22H, show how the checksum method
detects the error.
Solution:
(a)
Find the checksum byte.
+
+
+
(b)
25H
62H
3FH
52H
118H
(Dropping the carry of!, we have 18H. Its 2's complement is E8H. Therefore
checksum byte is E8H.)
Perform the checksum operation to ensure data integrity.
25H
62H
+
3FH
+ 52H
+
E8H
200H
+
(Dropping the carries, we see 00, indicating that data is not corrupted.)
(c)
If the second byte 62H has been changed to 22H, show how the checksum
method detects the error.
25H
22H
+
3FH
+
52H
+
E8H
lCOH
+
(Dropping the carry, we get COH, which is not 00. This means that data
is corrupted.)
;PROG 6-1: CALCULATING AND TESTING CHECKSUM BYTE
#include P18F458.inc
RAM ADDR
COUNTREG
CNTVAL
CNTVALl
EQU
EQU
EQU
EQU
40H
Ox20
4
5
; RAM space to place the bytes
;fileReg lac for counter
icounter value = 4 for adding 4 bytes
;cQunter value = 5 for adding 5 bytes
; including checksum byte
;------------main program
ORG
CALL
CALL
CALL
BRA
228
0
COPY DATA
CAL CHKSUM
TEST CHKSUM
$
;--------copying data from code ROM address 500H to data RAM loc
COPY_DATA
MOVLW low (MYBYTE)
;WREG = 00 LOW-byte addr
MOVWF TBLPTRL
;ROM data LOW-byte addr
MOVLW hi (MYBYTE)
;WREG = 5, HIGH-byte addr
MOVWF TBLPTRH
;ROM data HIGH-byte addr
MOVLW upper (MYBYTE)
;WREG = 00 upper-byte addr
MOVWF TBLPRTRU
;ROM data upper-byte addr
LFSR O,RAM_ADDR
;FSRO = RAM_ADDR, place to save
TBLRD*+
;bring in next byte and inc TBLPTR
Cl
MOVF TABLAT,W
;copy to WREG (Z = 1, if null)
jis it null char? exit if yes
BZ
EXIT
MOVWF POSTINCO
jCOpy WREG to RAM and inc pointer
BRA
Cl
EXIT RETURN
;-----calculating checksum byte
CAL_CHKSUM
MOVLW CNTVAL
;WREG = 4
MOVWF COUNTREG
;load the counter, count = 4
LFSR O,RAM_ADDR
; load pointer. FSRO = 40H
CLRF WREG
ADDWF POSTINCO,W
C2
;add RAM to WREG and increment FSRO
DECF COUNTREG,F
; decrement counter
BNZ
C2
; loop until counter = zero
;1' s camp
XORLW OxFF
j2'compl
ADDLW 1
MOVWF POSTINCO
RETURN
;----------testing checksum byte
TEST CHKSUM
MOVLW CNTVALl
;WREG = 5
MOVWF COUNT REG
iload the counter, count = 5
CLRF TRISB
; PORTB = output
LFSR O,RAM_ADDR
;load pointer. FSRO = 40H
CLRF WREG
jadd RAM and increment FSRO
C3
ADDWF POSTINCO,W
DECF COUNTREG,F
;decrement counter
BNZ
iloop until counter = zero
C3
iEX-OR to see if WREG = zero
XORLW OxO
BZ
G 1
jis result zero? then good
MOVLW 'B'
MOVWF PORTB
iif not, data is bad
RETURN
MOVLW tG'
G 1
MOVWF PORTB
;data is not corrupted
RETURN
;----------my data in program ROM
ORG Ox500
MYBYTE DB Ox25, Ox62, Ox3F, Ox52, OxOO
END
Note the usage of the keywords low, hi, and upper, to indicate the 21-bit address of the
program ROM.
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
229
BCD to ASCII conversion program
Many RTCs (real-time clocks) provide time and date in BCD fonnat. To
display the BCD data on an LCD or a PC screen, we need to convert it to ASCII.
Program 6-2 (a) transfers packed BCD data from program ROM to data RAM, (b)
converts packed BCD to ASCII, and (c) sends the ASCII to port B for display. We
will use a portion of this program in Chapter 16. The displaying of data on LCD
will be shown in Chapter 12. See Chapter 5 for the BCD to ASCII conversion algorithm.
;PROG 6-2, CONVERTING PACKED BCD TO ASCII
#include P18F458.inc
RAM ADDR
ASC RAM
COUNTREG
CNTVAL
CNTVALI
EQU
EQU
EQU
EQU
EQU
Ox40
Ox50
Ox20
D'4'
D'8'
ifi1eReg lac for counter
;counter value of BCD bytes
icounter value of ASCII bytes
;------------main program
ORG
0
CALL COpy DATA
CALL BCD ASC CONV
CALL DISPLAY
BRA
$
;--------copying data from code ROM to data RAM
COPY DATA
MOVLW low (MYBYTE)
;WREG = 00 LOW-byte addr
MOVWF TBLPTRL
;ROM data LOW-byte addr
MOVLW hi (MYBYTE)
;WREG = 5, HIGH-byte addr
MOVWF TBLPTRH
;ROM data HIGH-byte addr
MOVLW upper (MYBYTE)
;WREG = 00 upper-byte addr
MOVWF TBLPRTRU
;ROM data upper-byte addr
LFSR O,RAM_ADDR
jFSRO = RAM_ADDR, place to save
TBLRD*+
Cl
;bring in next byte and inc TBLPTR
MOVF TABLAT, W
;copy to WREG (Z = 1, if null)
BZ
EXIT
jis it null char? exit if yes
MOVWF POSTINCO
jCopy WREG to RAM and inc pointer
BRA
Cl
EXIT RETURN
;-----convert packed BCD to ASCII
BCD ASC CONV
MOVLW CNTVAL
;get the counter value
MOVWF COUNTREG
; load the counter
LFSR O,RAM_ADDR
;FSRO = RAM_ADR BCD byte pointer
LFSR I,ASC_RAM
;FSRI = ASC RAM ASCII byte pointer
.
MOVF INDFO,W
B2
jCopy BCD to WREG
ANDLW OxOF
;mask the upper nibble (W = 09)
IORLW Ox30
;rnake i t an ASCII
MOVWF POSTINCI
iCOPY to RAM and increment FSRI
MOVF POSTINCO,W
inote the use of instruction
ANDLW OxFO
imask the lower nibble (W = 20H)
SWAPF WREG
IORLW Ox30
; make it an ASCII
MOVWF POSTINCI
jCopy to RAM and increment FSRI
DECF COUNTREG,F
; decrement counter
BNZ
B2
iloop until counter = zero
230
RETURN
;-----send ASCII data to port B
DISPLAY
; make PORTB output (TRSIB = FFH)
CLRF TRISB
MOVLW CNTVALl
iWREG = 8, send 8 bytes of data
MOVWF COUNTREG
i10ad the counter, count = 8
LFSR 2,ASC_RAM
;load pointer. FSR2 = 50H
B3
MOVF POSTINC2,W
iCOPY RAM to WREG and inc pointer
MOVWF PORTB
iCoPY WREG to PORTB
; decrement counter
DECF COUNTREG,F
BNZ
B3
iloop until counter
zero
RETURN
;----------my BCD data in program ROM
ORG Ox500
MYBYTE DB Ox25, Ox67, Ox39, Ox52, OxOO
END
0000
0010
0020
0030
oo.qo
00
00
00
25
00
00
00
00
32 37 36 39 33 32 35 00
00 00 00 00 00 00 00 00 00
·".;;.35
0060
00 00
00
00 00 00 00
00 00 00 00
67 :39 52 00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
........
....... . ........
........ ....... .
........ ....... .
.... ........
52769325 ........
........ ....... .
~g9R
Figure 6-9. Results of Program 6-2 After it Ran.
Binary (hex) to ASCII conversion program
Many ADC (analog-to-digital converter) chips provide output data in binary (hex). To display the data on an LCD or PC screen, we need to convert it to
ASCII. The code for the binary-to-ASCII conversion is shown in Program 6-3.
Notice that the subroutine gets a byte of 8-bit binary (hex) data from Port Band
converts it to decimal digits, and the second subroutine converts the decimal digits to ASCII digits and saves them. We are saving the low digit in the lower address
location and the high digit in higher address location. This is referred to as the
little-endian convention (i.e., low-byte to low-location and high-byte to high-location). All PIC 18 products use the little-endian convention. For the binary-to-ASCII
conversion algorithm see Chapter 5.
;PROG 6-3, CONVERTING BIN (HEX)
#include P18F458.INC
NUME
QU
RMND L
RMND M
RMND - H
EQU
EQU
EQU
EQU
EQU
OxOO
Ox20
Ox30
Ox31
Ox32
TO ASCII
; RAM
; RAM
ithe
ithe
ithe
loc for NUME
loc for quotient
least significant digit loc
middle significant digit loc
most significant digit loc
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
231
EQU
MYDEN
D'lO'
COUNTREG
EQU Ox10
CNTVAL
EQU d'3'
UNPBCD_ADDR EQU Ox30
ASCII_RESULT EQU Ox40
;~----------main
ORG
SETF
CALL
CALL
BRA
;value for divide by 10
ifileReg lac for counter
icounter value
program
0
TRISB
BIN DEC CON
DEC ASCII CON
$
imake PORTB input
;-----converting BIN(HEX) TO DEC (OO-FF TO 000-255)
BIN DEC CON
MOVFF PORTB,WREG
;get the binary data from PORTB
MOVWF NUME
;load numerator
MOVLW MYDEN
iWREG = 10, the denominator
iclear quotient
CLRF QU
D 1
;inc quotient for every subtraction
INCF QU
SUBWF NUME
;subtract WREG from NUMB value
BC
D 1
iif positive go back
ADDWF NUME
ionce too many, first digit
DECF QU
ionce too many for quotient
MOVFF NUME,RMND_L
isave the first digit
MOVFF QU,NUME
jrepeat the process one more time
CLRF QU
;clear QU
D 2
INCF QU
SUBWF NUME
isubtract WREG from NUMB value
BC
D 2
ADDWF NUME
jonce too many
DECF QU
MOVFF NUME,RMND- M
;2nd digit
MOVFF QU,RMND_H
i 3rd digit
RETURN
;----converting unpacked BCD digits to displayable ASCII digits
DEC ASCII CON
MOVLW CNTVAL
MOVWF COUNTREG
LFSR O,UNPBCD_ADDR
LFSR 1,ASCII RESULT
B3
MOVF POSTINCO, W
ADDLW Ox30
MOVWF POSTINC1
DECF COUNTREG,F
B3
BNZ
RETURN
END
232
;WREG
=
10
;load the counter, count
10
;load pointer FSRO
;load pointer FSR1
; copy RAM to WREG, increment FSRO
; make it an ASCII
iCOPY WREG and increment FSR1
; decrement counter
iloop until counter = zero
;end of the program
0000
0010
0020
0030
0040
00 00 00 00
00 00 00 00
08 00 00 00
38 30 30 30
00
00
00
30
00
00
00
30
00
00
00
30
00
00
00
30
00
00
00
30
00 00
00
00 00 00 00
00 00 00 00
30 30 30 30
00
00
00
30
00
00
00
30
00
00
00
30
........
....... . ........
....... . ........
....... .
80000000 00000000
Figure 6-10. Results of Program 6-3 After it Ran. (Note the contents of locations 0030H,
00400, and 0041H.)
Using memory banks for a stack
The stack in the PICI8 is 31 bytes deep and 21 bits wide. Because the program counter is 21 bits wide, the stack must be 21 bits wide also, as we discussed
in Chapter 2. This stack is used mainly to save addresses for call and interrupt subroutines. Unlike other microprocessors, the stack in the PIC 18 is not part of the
data RAM space. Having access to such a large number of banks, however, makes
a traditional stack unnecessary. In traditional CPUs (e.g., the x86) a limited number of registers forced us to push main registers into the stack at the beginning of
a called subroutine, before we could use the main registers for data manipulation.
In the case of the PIC 18, all we have to do is to change the default bank to a new
bank when we go into the subroutine. In other words, if we want to store a program's data on a stack in a given subroutine, we can use one of the banks of data
RAM space instead of the 31 x 21-bit stack. Besides the fact that the 21-bit wide
stack does not lend itself to storing 8-bit data, we must reserve all the 31 x 21-bit
stack for calls and interrupts. Notice that we can still use the access bank for the
storage of global variables. Global variables are discussed in the next section.
Review Questions
I. For the following ASCII numbers, give the ASCII and packed BCD representations.
(a) '5', '7' (b) '9', '4'
2. Show the hex format for "2005" and its BCD version.
3. Does the WREG register have BCD data after the following instruction is executed? Assume that the default the radix for the MPASM is decimal.
MOVLW 95
4. 33H in BCD when converted to ASCII is
Hand
H.
5. Find the ASCII value for the binary 11110010 if we want to display it on a
computer screen as a 3-digit decimal number.
6. The checksum byte method is used to test data integrity in __(RAM, ROM).
7. Find the checksum byte for the following hex values: 88H, 99H, AAH, BBH,
CCH,DDH
8. True or false. If we add all the bytes, including the checksum byte, and the
result is FFH, there is no error in the data.
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
233
SECTION 6.7: MACROS AND MODULES
In this section we explore macros and modules and their use in Assembly
language programming. The fonnat and usage of macros are defined, and many
examples of their applications are explored. In addition, this section demonstrates
modular programming along with rules for writing modules and linking them
together. Some very useful modules will be given, along with methods of passing
parameters among various modules. Dividing a program into several modules (in
C programming these are called functions) allows us to use modules in other applications. It is common practice to divide a program into several modules, test each
module, and put them into a library.
What is macro and how is it issued?
There are applications in Assembly language programming where a group
of instructions perfonns a task that is used repeatedly. For example, moving data
into a RAM location is done repeatedly in the same program. It does not make
sense to rewrite this code every time it is needed. Therefore, to reduce the time that
it takes to write code and reduce the possibility of errors, the concept of macros
was born. Macros allow the programmer to write the task (code to perform a specific job) once only, and to invoke it whenever it is needed.
MACRO definition
Every macro definition must have three parts, as follows:
name
MACRO
dummyl, dummy2, ... , dummyN
ENDM
The MACRO directive indicates the beginning of the macro definition and
the ENDM directive signals the end. What goes in between the MACRO and
ENDM directives is called the body of the macro. The name must be unique and
must follow Assembly language naming conventions. The dummies are names, or
parameters, or even registers that are mentioned in the body of the macro. After
the macro has been written, it can be invoked (or called) by its name, and appropriate values are substituted for dummy parameters. Moving literal data into file
register data RAM is a widely used service, but there is no instruction for that. We
can use a macro to do the job as shown in the following code:
MOVLF MACRO K, MYREG
MOVLW K
MOVWF MYREG
ENDM
The above is the macro definition. Note that dummy arguments of K and
MYREG are mentioned in the body of macro.
The following are three examples of how to use the above macro:
234
l.
MOVLF
Ox55,
2. VAL I
RAM LOC
MOVLF
3. MOVLF
Ox20
isend value 55H to lac 20H
EQU Ox55
EQU Ox20
VAL_I, RAM LOC
Ox55,
PORTB
jsend value 55H to Port B
The instruction "MOVLF Ox5, Ox2 0" invokes the macro. The assembler
expands the macro by providing the following code in the .Ist file:
M
M
MOVLW 5
MOVWF Ox20
The M indicates that the code is from the macro.
LOCAL directive
In the discussion of macros so far, the examples chosen do not have a label
or name in the body of the macro. This is because if a macro is expanded more
than once in a program and there are labels in the label field of the body of the
macro, these labels must be declared as LOCAL. Otherwise, an assembler error
would be generated when the same label was encountered in two or more places.
The following rules must be observed in the body of the macro:
I. All labels in the label field must be declared LOCAL.
2. The LOCAL directive must be right after the MACRO directive. In other
words, it must be placed even before comments and the body of the macro;
otherwise, the assembler gives an error.
3. The LOCAL directive can be used to declare all names and labels at once as
follows:
namel, name2, name3
LOCAL
or one at a time as:
namel
LOCAL
name2
LOCAL
name3
LOCAL
To clarify these points, look at the following macro for time delay:
DELAY_I MACRO VI, TREG
LOCAL BACK
MOVLW VI
MOVWF TREG
BACK NOP
NOP
NOP
NOP
DECF TREG,F
BNZ
BACK
ENDM
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
235
Notice that the "BACK" label is defined as LOCAL right after the MACRO
directive. Defining this label anywhere else causes an error. The use of a LOCAL
directive allows the assembler to define the labels separately each time it encounters them. Examining the list file shows that when the macro is expanded for the
first time, the list file has "??OOOO", for the second time it has "??OOO I ", and for
the third time it has "??0002" in place of the "BACK" label, indicating that the
"BACK" label is local. To clarify this concept, see Program 6-4 without the LOCAL
directive to see how the assembler will give an error. The following code is another macro for a time delay with a nested loop:
DELAY_2 MACRO VI, V2, RI, R2
LOCAL BACK
LOCAL AGAIN
MOVLW V2
MOVWF R2
AGAIN MOVLW VI
MOVWF RI
BACK NOP
NOP
NOP
NOP
DECF RI,F
BNZ
BACK
DECF R2,F
BNZ
AGAIN
ENDM
Now examine Program 6-4 to see how to use a macro in a program.
,
0
_________________________________________
iProgram 6-4:
_
toggling port B using macros
#include P18F458.INC
;---------------sending data to fileReg macro
MOVLF MACRO K, MYREG
MOVLW K
MOVWF MYREG
ENDM
i----------------------------time delay macro
DELAY_I MACRO VI, TREG
LOCAL BACK
MOVLW VI
MOVWF TREG
BACK NOP
NOP
NOP
NOP
DECF TREG,F
BACK
BNZ
ENDM
j----------------------------program starts
ORG
CLRF
236
0
TRISB
;Port B as an output
Ox55,PORTB
MOVLF
DELAY 1 Ox200,OxlO
MOVLF
OxAA,PORTB
DELAY 1 Ox200,OxlO
BRA
OVER
END
i--------------------end of file
OVER
INCLUDE directive
Assume that several macros are used in every program. Must they be
rewritten every time? The answer is no, if the concept of the INCLUDE directive
is known. The INCLUDE directive allows a programmer to write macros and save
them in a file, and later bring them into any program file. For example, assume that
the following widely used macros were written and then saved under the filename
"MYMACROI. MAC".
Assuming that these macros are saved on a disk under the filename
the INCLUDE directive can be used to bring this file into any
".asm" file and then the program can call upon any of the macros as many times
as needed. When a file includes all macros, the macros are listed at the beginning
of the ".1st" file and, as they are expanded, will be part of the program. To understand this, see Program 6-5.
"MYMACROl . MAC",
jProgram 6-5: toggling Port B using macros
#include P18F458.INC
#include nMYMACRQl.MAC1! ;get macros from macro file
;----------------------------program starts
OVER
ORG
0
CLRF TRISB
MOVLF Ox55,PORTB
DELAY 1
iPort B as an output
Ox200,OxlO
MOVLF OxAA,PORTB
DELAY 1
Ox200,OxlO
BRA
OVER
END
;--------------------end of file
NOEXPAND/EXPAND directive
When viewing the .Ist file with macros, we see them fully displayed. The
expand directive is set by default, and it shows the macro at every location it is
called. This is fine for two or three iterations, but when there are more, it can
become cumbersome. Using the noexpand directive, we can tum off the display of
macros in the list file.
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
237
00001 ;Program 6-4:toggling Port B using macros
00002
#include P18F458.INC
00003
NOEXPAND
00004
;---------------sending data to fileReg macro
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
MOVLF MACRO K, MYREG
MOVLW
K
MOVWF
MYREG
ENDM
00023
;----------------------------program starts
;----------------------------time delay macro
DELAY 1 MACRO VI, TREG
LOCAL
BACK
MOVLW
VI
MOVWF
TREG
BACK NOP
NOP
NOP
NOP
DECF
TREG,F
BNZ
BACK
ENDM
000000
00024
000000 6A93 00025
00026 OVER
00027
00028
00029
00002A D7EB 00030
00031
ORG
CLRF
MOVLF
DELAY 1
MOVLF
DELAY 1
BRA
END
0
TRISB
Ox55,PORTB
Ox200,Ox10
OxAA, PORTB
Ox200,Ox10
OVER
iPort B as an output
Figure 6-11. List File with NOEXPAND Option for Program 6-4
238
00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
;Program 6-4:toggling Port B using macros
#include P18F458.INC
EXPAND
;---------------sending data to fileReg macro
MOVLF MACRO K, MYREG
MOVLW K
MOVWF MYREG
ENDM
00023
;----------------------------program starts
ORG
0
CLRF TRISB ;Port B as an output
OVER MOVLF Ox55,PORTB
MOVLW Ox55
MOVWF PORTB
DELAY 1 Ox200,Ox10
LOCAL BACK
MOVLW Ox200
MOVWF Ox10
BACK NOP
NOP
NOP
NOP
DECF Ox10, F
BNZ
BACK
MOVLF OxAA,PORTB
MOVLW OxAA
MOVWF PORTB
DELAY 1 Ox200,Ox10
LOCAL BACK
MOVLW Ox200
MOVWF Ox10
BACK NOP
NOP
NOP
NOP
DECF Ox10,F
BNZ
BACK
BRA
OVER
END
000000
00024
000000 6A93 00025
00026
000002 OE55
M
M
000004 6E81
00027
0000
M
000006 OEOO
M
000008 6E10
M
OOOOOA 0000
M
OOOOOC 0000
M
OOOOOE 0000
M
000010 0000
M
000012 0610
M
000014 E1FA
M
00028
000016 OEAA
M
000018 6E81
M
00029
0000
M
00001A OEOO
M
00001C 6E10
M
00001E 0000
M
000020 0000
M
000022 0000
M
000024 0000
M
000026 0610
M
000028 E1FA
M
00002A D7EB 00030
00031
i----------------------------time delay macro
DELAY 1 MACRO VI, TREG
LOCAL BACK
MOVLW VI
MOVWF TREG
BACK NOP
NOP
NOP
NOP
DECF TREG,F
BNZ
BACK
ENDM
Figure 6-12. List File with EXPAND Option for Program 6-4
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
239
Macros
VS.
subroutines
Macros and subroutines are useful in writing assembly programs, but each
have limitations. Macros increase code size everytime they are invoked. For example, if you call a 10-instruction macro 10 times, the code size is increased by 100
instructions. Whereas, if you call the same subroutine 10 times, the code size is
only that of the subroutine instructions. The only problem with subroutines is that
they use stack space when called, and this can cause problems when there are nested calls (a subroutine calling another subroutine). The nested call can lead to a
stack overflow and cause the program to crash. The PIC 18 has provisions for stack
overflow, discussed in the PIC 18 Reference Manual.
Modules
It is common practice in writing software packages to break down the project into small modules and distribute the task of writing those modules among several programmers. This not only makes the project more manageable but also has
other advantages, such as:
1. Each module can be written, debugged, and tested individually.
2. The failure of one module does not stop the entire project.
3. The task ofiocating and isolating any problem is easier and less time consummg.
4. One can use the modules to link with high-level languages such as C.
5. Parallel development shortens considerably the time required to complete a
project.
Next we explain how to write and link modules to create a single executable program.
Writing modules
In programs given in the last section, a main procedure was written that
called many other subroutines. In those examples, if one subroutine did not work
properly, the entire program would have to be rewritten and reassembled. A more
efficient way to develop software is to treat each subroutine as a separate program
(or module) with a separate filename. Then each one can be assembled and tested.
After testing each program and making sure that each works, they can all be
brought together (linked) to make a single program. To enable these modules to be
linked together, certain Assembly language directives must be used. Among these
directives, the two most widely used are EXTERN (external) and GLOBAL. The
GLOBAL directive is the same as PUBLIC in other Assembly language programs.
Each is discussed below.
240
EXTERN directive
The EXTERN directive is used to notify the assembler and linker that certain names and variables that are not defined in the present module are defined
externally somewhere else. In the absence of the EXTERN directive, the assembler would show an error because it cannot find where the names are defined. The
EXTERN directive has the following format:
EXTERN name I
EXTERN name2
;each name can be in a separate EXTERN
EXTERN namel, name2
;or many can be listed in the same EXTERN
GLOBAL directive
Names or parameters defined as EXTERN (indicating that they are defined
outside the present module) must be defined as GLOBAL in the module where
they are defined. Defining a name as GLOBAL (PUBLIC) allows the assembler
and linker to match it with its EXTERN counterpart(s). The following is the format for the GLOBAL directive:
GLOBAL namel
GLOBAL name2
;each name can be in a separate directive
GLOBAL namel, name2
;or many can be listed in the same GLOBAL
Program 6-6 should help to clarify these concepts. It demonstrates that for
every EXTERN definition there is a GLOBAL directive defined in another module. Notice the entry and exit points of the program. Modules that are called by the
main module have their own END directives. See Program 6-6.
,"-------------------------------------------------,PROG 6-6: MAIN.ASM - CALCULATING AND TESTING CHECKSUM BYTE
#include P18F458.INC
RAM ADDR
COUNTREG
CNTVAL
CNTVALl
EQU
EQU
EQU
EQU
40H
Ox20
4
5
;fileReg loc for counter
;counter value
;counter value
EXTERN CAL CHKSUM
EXTERN TEST CHKSUM
PGM CODE
;------------main program
ORG
CALL
CALL
CALL
BRA
0
COPY_DATA
CAL CHKSUM
TEST_CHKSUM
$
;this subroutine is in this file
;this sub is in external file
;this sub is in external file
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
241
;--------copying data from code ROM to data RAM
COPY DATA
MOVLW low (MYBYTE)
;WREG = 00 LOW-byte addr.
MOVWF TBLPTRL
;ROM data LOW-byte addr.
MOVLW hi (MYBYTE)
;WREG = 5, HIGH-byte addr.
MOVWF TBLPTRH
;ROM data HIGH-byte addr.
MOVLW upper (MYBYTE)
;WREG = 00 upper-byte addr.
MOVWF TBLPRTRU
;ROM data upper-byte addr.
LFSR O,RAM_ADDR
;FSRO = RAM_ADDR, place to save
TBLRD*+
C1
;bring in next byte and inc TBLPTR
MOVF TABLAT,W
;copy to WREG (Z = 1, if null)
BZ
EXIT
;is it null char? exit if yes
MOVWF POSTINCO
;copy WREG to RAM and inc pointer
BRA
C1
EXIT RETURN
;----------my data in program ROM
ORG Ox500
MYBYTE DB Ox25, Ox62, Ox3F, Ox52, OxOD
END
,
0
______
--------------------------------------------
;PROG 6-6: CALCCSB.ASM - CALCULATING CHECKSUM BYTE
#include P18F458.inc
RAM ADDR
COUNTREG
CNTVAL
CNTVAL1
EQU
EQU
EQU
EQU
40H
Ox20
4
5
;fileReg loc for counter
;counter value
;counter value
GLOBAL CAL CHKSUM
;we use this to inform the linker that
;the code segment has the name PGM
PGM CODE
CAL CHKSUM
MOVLW CNTVAL
MOVWF COUNTREG
LFSR O,RAM_ADDR
CLRF WREG
C2
ADDWF POSTINCO, W
DECF COUNTREG,F
C2
BNZ
XORLW OxFF
ADDLW 1
MOVWF POSTINCO
RETURN
END
;WREG = 4
;load the counter
;load pointer. FSRO
=
40H
;add RAM to WREG and increment FSRO
;decrement counter
;loop until counter = zero
; l' s comp
;2'compl
,"-------------------------------------------------;PROG 6-6: TESTCSB.ASM - TESTING CHECKSUM BYTE
#include P18F458.inc
RAM ADDR
COUNTREG
CNTVAL
CNTVAL1
242
EQU
EQU
EQU
EQU
40H
Ox20
4
5
ifileReg loc for counter
; counter value
icounter value
GLOBAL TEST CHKSUM
PGM CODE
TEST CHKSUM
MOVLW CNTVALI
MOVWF COUNTREG
CLRF TRISB
LFSR O,Ox40
CLRF WREG
ADDWF POSTINCO,W
C3
DECF COUNTREG,F
BNZ
C3
XORLW OxO
BZ
G 1
;WREG
=
5
;load the counter
iload pointer.
FSRD
=
4DH
iadd RAM and increment FSRO
;decrement counter
iloop until counter = zero
;EX-OR to see if zero
;is result zero? then good
MOVLW IB'
MOVWF PORTB
RETURN
G 1
iif not,
data is bad
MOVLW 'G'
MOVWF PORTB
RETURN
END
;data is not corrupted
Linking modules together
Assuming that each program module in Program 6-6 is assembled separately and saved under the filenames MAIN.O, CALCCSB.O, and TESTCSB.O,
the following shows how to link them together with MPLINK in order to generate
a single executable file:
> MPLinkexe" "18f458.lkr" "MAIN.O" "CALCCSB.O" ''TESTCSB.O'' /o"PRG&6.COF"
Program 6-6 shows how the EXTERN and GLOBAL directives can also
be applied to data variables. The linker program resolves external references by
matching GLOBAL and EXTERN names. The linker program will search through
the files specified in the MPLINK command for the external subroutines.
The MPLAB IDE handles the compiling and linking in one step. This aids
in program development by reducing time and errors in typing the command line
call.
Review Questions
I. Discuss the benefits of macro programming.
2. List the three parts of a macro.
3. Explain and contrast the macro definition, invoking the macro, and expanding
the macro.
4. True or false. A label defined within a macro is automatically understood by
the assembler to be local.
5. The
directive is used within a module to indicate that the named variable or subroutine can be used by another module.
6. The
directive is used within a module to indicate that the named variable or subroutine was defined in another module.
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
243
SUMMARY
This chapter described the addressing modes of the PIC 18. Immediate
addressing mode uses a constant for the operand. Direct or register indirect
addressing modes can be used to access data stored in data RAM file registers of
the PIC 18. Register indirect addressing mode uses a register as a pointer to the
data. The advantage of this is that it makes addressing dynamic rather than static.
Indexed ROM addressing mode is widely used in accessing data elements of lookup table entries located in the program ROM space of the PIC 18. The PIC 18
allows the reading of fixed data stored in program ROM space, in addition to writing to ROM if the PIC 18 is of the flash type.
A group of registers called SFRs (special function registers) can be
accessed by their names or their addresses. We also discussed the bit-addressable
data RAM locations and ports and showed how to use single-bit instructions to
access them directly. The topic of bank switching was discussed, and we showed
how to use BSR registers to access all 16 banks of RAM in the PICI8.
We discussed how to break up a program into several or many subroutines
and write and test each one separately. Macros and modules were also explored
and their advantages were discussed.
PROBLEMS
SECTION 6.1: IMMEDIATE AND DIRECT ADDRESSING MODES
I. Which of the following are invalid uses of immediate addressing mode?
(a) MOVLW Ox24 (b) MOVLW MYREG, Ox30
(c) MOVLW Ox60
2. Identify the addressing mode for each of the following:
(a) MOVWF PORTB (b) MOVLW Ox50
(c) MOVWF MYREG
(d) MOVLW 0
(e) MOVFF MYBREG, YOUREG
(t) MOVWF YOURREG
3. Indicate the address assigned to each of the following:
(a) PORTB
(b) WREG
(c) PORTC
(d) PORTO (e) PCL
(t) PCH
(g) PCU
(h) TRISC
(i) TRISB
U) STATUS (k) FSROL
4. Which bank is used for SFRs?
5. In accessing the SFRs, we must use
addressing mode.
6. What does the following instruction do? "MOVLW OxFO"
7. What does the following instruction do? "MOVWF PORTC"
8. What does the following instruction do? "MOVF PORTC, W"
9. "CLRF MYREG" is a(n)
(valid, invalid) instruction.
10. The byte addresses assigned to the 128 bytes oflower data RAM are ~~ to
II. The byte addresses assigned to the SFRs are ~~ to ~~.
12. Indicate the byte addresses assigned to both of the following. Is there a gap
244
between them?
(a) RAM locations of access bank
(b) SFR of access bank
13. Write a program to add the following data and place the result in RAM location 20H: The data values are 6, 9, 2, 5, 7
SECTION 6.2: REGISTER INDIRECT ADDRESSING MODE
14. Which registers are allowed to be used as a pointer for register indirect
addressing mode when accessing data RAM? Give their names and show how
they are loaded.
IS. Write a program to copy FFH into RAM locations SOH to 6FH.
16. Write a program to copy 10 bytes of data starting at RAM address 40H to
RAM locations starting at 70H.
17. What is the size of the FSRx register?
18. Give the SFR registers related to the FSRO and FSRI.
19. Write a program to clear RAM locations 0 to 7FH.
20. Write a program to toggle RAM locations SOH to SFH.
21. Explain the role of the INDFx register.
22. How much RAM space does the FSRx register cover?
SECTION 6.3: LOOK-UP TABLE AND TABLE PROCESSING
23. Compile and state the contents of each ROM location for the following data:
MYDAT 1:
MYDAT 2:
MYDAT 3:
ORG
DB
DB
DB
200H
11 Earthll
11987-65 11
"GABEH 981!
24. Compile and state the contents of each ROM location for the following data:
ORG
340H
DAT_I: DB Ox22,Ox56,
B'10011001', D'32',
OxF6, B'11111011'
2S. Which register is allowed to be used as a pointer for register indirect address-
ing mode when accessing data stored in program ROM? Give the name and
show how it is loaded.
26. Explain the role ofthe TABLAT register.
27. What is the size of the TBLPTR register? How much ROM space does it
cover?
28. Give the SFR registers related to the TBLPTR.
29. Write a program to read the following message from ROM and place it in data
RAM starting at SO:
MYDATA
ORG Ox600
DB
"1-800-999-9999",0
30. Write a program to findy where y = x' + 2x + S, and x is between 0 and 9.
31. Write a program to find y where y = 20x + S, and x is between 0 and 9.
32. Write a program to read the following message from ROM and place it in data
RAM starting at 40:
ORG Ox700
MYDATA
DB
liThe earth is but one country", 0
33. True or false. The table read instruction works for all PIC18 family members.
34. True or false. The table write instruction works for PIC 18 family members
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
245
with flash ROM.
35. Assume that the lower four bits of PORTB are connected to four switches.
Write a program to send the following ASCII characters to a PORTC, based on
the status of the switches:
0000
0001
0010
DOli
0100
0101
OliO
Olll
1000
1001
1010
1011
liDO
1101
lllO
Illl
'0'
' I'
'2'
'3'
'4'
'5'
'6'
'7'
'8'
'9'
'A'
'B'
'c'
'D'
'E'
'F'
SECTION 6.4: BIT-ADDRESSABILITY OF DATA RAM
36. Write a program to generate a square wave with 75% duty cycle on bit RB5.
37. Write a program to generate a square wave with 80% duty cycle on bit RC7.
38. Write a program to monitor RB4. When it goes HIGH, the program will generate a sound (square wave of 50% duty cycle) on pin RB7.
39. Write a program to monitor RCI. When it goes LOW, the program will send
the value 55H to RDO.
40. What register does the carry flag belong to?
41. What bit address is assigned to the Z flag?
42. Which of the following instructions are valid? If valid, indicate which bit is
altered.
(c) BCF WREG,l
(a) BSF PORTB,l(b) BSF PORTC.3
(d) BCF Ox30, 1 (e) BCF PORTD,O
(f) BST STATUS, C
(g) CLRF WREG, 3 (h) CLRF FSRO
(valid, invalid) instruction.
43. "BTG PORTB, 0" is a(n)
44. Which of the I/O ports ofPORTB, PORTC, and PORTD are bit-addressable?
45. Which of the registers of the PICI8 are bit-addressable?
46. Give an instruction to clear the carry flag.
47. Show how would you check whether the C flag is HIGH.
48. Show how would you check whether the Z flag is HIGH.
49. Give the bit locations in the status register assigned to the flag bits C, Z, DC,
and Ov.
50. True or false. The bit addresses 0--7 are assigned to each RAM location of
OOO--FFFH.
246
51. True or false. SFR registers are not bit-addressable.
52. Write instructions to save the C flag bit in bit 4 oflocation 10.
53. Write instructions to save the DC flag bit in bit 2 of location 16H.
54. Write instructions to save the Z flag bit in bit 7 oflocation 12H.
55. Write instructions to see whether the DO and DI bits of register WREG are
HIGH. If so, divide register WREG by 4.
56. Write a program to see whether the D7 bit of register WREG is HIGH. If so,
send a message to the LCD stating that WREG has a negative number.
57. Write a program to set HIGH all the bits of RAM location 20H using the following methods:
(a) byte addresses (b) bit addresses
58. Write a program to see whether the WREG register is divisible by 8.
59. Write a program to find the number of zeros in file register location 05.
SECTION 6.5: BANK SWITCHING IN THE PICI8
60. What addressing mode is used to access the SFRs?
61. What addressing mode is used to access the last 128 bytes of RAM in the
PICI8?
62. Give the address range ofthe lower and the upper 128 bytes of the access bank.
63. In the PICI8, the SFRs use the same addresses across all members and they are
from
to _ _,-.
64. The PICI8 can have a maximum of
banks.
65. Explain the difference between these two instructions.
(a)ADDwF MYREG, F, 1
(b)ADDWF MYREG, F,
°
66. Which addressing modes are used to access various banks?
67. Write a program to put 55H into RAM locations ICO-ICFH.
68. Write a program to copy the contents of RAM locations 20-2FH to RAM locations 2DO-2DFH.
69. Explain the difference between these two instructions.
(a) CLRF MYREG, F, 1
(b) CLRF MYREG, F,
°
70. Explain the difference between these two instructions.
(a) SETF MYREG,W,l
(b) SETF MYREG,W,O
71. Explain the difference between these two instructions.
(a) INCF MYREG,F,l
(b)INCF MYREG,F,O
SECTION 6.6: CHECKSUM AND ASCII SUBROUTINES
72. Find the checksum byte for the following ASCII message: "Hello"
73. True or false. If we add all bytes, including the checksum byte, and the result
is OOH, there is no error in the data.
74. Write a program to (a) get the data "Hello, my fellow world citizens" from program ROM, (b) calculate the checksum byte, and (c) test the checksum byte
for any data error.
(BINARY,
75. To display data on LCD or PC monitors, it must be in
BCD, ASCII).
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
247
76. Assume that the lower 4 bits ofPB are connected to four switches. Write a program to send the following ASCII characters to PD based on the status of the
switches:
0000
0001
0010
0011
0100
0101
0110
Olll
1000
IDOl
'0'
'I'
'2'
'3'
'4'
'5'
'6'
'7'
'8'
'9'
77. Write a program to convert a series of packed BCD numbers to ASCII. Assume
that the packed BCD is located in ROM locations starting at 700H. Place the
ASCII codes in RAM locations starting at 40H.
MYDATA
ORG 700H
DB
76H,87H,98H,43H
78. Write a program to convert a series of ASCII numbers to packed BCD. Assume
that the ASCII data is located in ROM locations starting at 300H. Place the
BCD data in RAM locations starting at 60H.
MYDATA
ORG 300H
DB
"87675649"
79. Write a program to get an 8-bit binary number from PD, convert it to ASCII,
and save the result in RAM locations 40H, 41H, and 42H. What is the result if
PD has 1000 11 0 I binary as input?
SECTION 6.7: MACROS AND MODULES
80.
81.
82.
83.
Give two advantages of macros.
Which uses more program ROM space: a macro or a module?
Give three reasons to write programs with modules.
If a label or parameter is not defined in a given module, it must be declared as
84. If a label or parameter is used by other modules, it must be declared as
____ in the present module.
85. Repeat Problem 79 using macros and modules.
248
ANSWERS TO REVIEW QUESTIONS
SECTION 6.1: IMMEDIATE AND DIRECT ADDRESSING MODES
1.
2.
3.
4.
5.
No
MOVLW B'IOOOOOOO'
PIC does not allow us to move a literal value directly to file register locations.
True
False
SECTION 6.2: REGISTER INDIRECT ADDRESSING MODE
I.
2.
3.
4.
5.
Direct. The memory location address is Ox40.
The lower S bits of the 12-bit address of the data RAM file register. The address is OFE9H.
The upper 4 bits of the 12-bit address of the data RAM file register. The address is OFEAH.
12-bit
FSRO, FSRl, and FSR2
SECTION 6.3: LOOK-UP TABLE AND TABLE PROCESSING
1.
2.
3.
4.
5.
6.
7.
TBLPTR
TBLPTR
TABLAT
21-bit, 2 MB
TBLPTR
In TBLRD*+ the element is read first, and then TBLPTR is incremented, while in TBLRD+*,
TBLPTR is incremented first, and then the element is fetched.
False. Only with flash ROM.
SECTION 6.4: BIT-ADDRESSABILITY OF DATA RAM
1.
2.
3.
4.
5.
6.
7.
S.
True
True
True
a, b, c, and d
All of them
BTFSS Ox03,1
(a) It sets to HIGH bit I of RAM location 20H.
(b) It clears bit 7 of RAM location 32H.
(c) It sets to HIGH bit 2 of RAM location 12H.
(d) It sets to HIGH bit 4 of PORTB.
(e) It sets to HIGH bit I of the status register.
BCF STATUS,C
SECTION 6.5: BANK SWITCHING IN THE PICIS
1.
2.
3.
4.
5.
True
True
True
FSO-FFFH
MYREG
MOVLB
MOVLW
MOVWF
EQU
Ox2
Ox02
Ox99
MYREG,l
;load 2 into BSR (use bank 2)
;WREG
99h
CHAPTER 6: BANK SWITCHING, TABLES, MACROS, AND MODULES
249
6.
7.
8.
MYREG
MOVLB
MOVLW
MOVWF
EQU
OxOB
Ox4
Ox55
MYREG,l
;load 4 into BSR (use bank 4)
;WREG=55h
True
8-bit,4
SECTION 6.6: CHECKSUM AND ASCII SUBROUTINES
1.
2.
3.
4.
5.
6.
7.
8.
The 35H and 37H give 57H in BCD. The 39H and 34H give 94H.
The ASCII data is 32H, 30H, 30H, 35H, while 05 and 20H are for BCD.
No. To make it BCD, the radix must be set to hex.
33H and 33H
242 or 32H, 34H and 32H
ROM
88H + 99H + AAH + BBH + CCH + DDH ~ 42FH. Dropping the carries we have 2FH, and
its 2's complement is D I H.
False
SECTION 6.7: MACROS AND MODULES
I.
Macro programming can save the programmer time by allowing a set of frequently repeated
instructions to be invoked within the program with a single line. This can also make the code
2.
3.
The three parts of a macro are the MACRO directive, the body, and the ENDM directive.
The macro definition is the list of statements the macro will perform. It begins with the
MACRO directive and ends with the ENDM directive. The macro is invoked whenever it is
called from within an Assembly language program. The macro is expanded when the
Assembly program replaces the line invoking the macro with the Assembly language code in
the body of the macro.
False. A label that is to be local to a macro must be declared local with the LOCAL directive.
GLOBAL
EXTERN
easier to read.
4.
5.
6.
250
CHAPTER 7
PIC PROGRAMMING
INC
OBJECTIVES
Upon completion of this chapter, you will be able to:
»
»
»
»
»
»
»
»
Examine C data types for the PICIS
Code CIS programs for time delay and 1/0 operations
Code CIS programs for 110 bit manipulation
Code CIS programs for logic and arithmetic operations
Code CIS programs for ASCn and BCD data conversion
Code CIS programs for binary (hex) to decimal conversion
Code CIS programs for data serialization
Understand CIS C compiler RAM and ROM allocation
251
Why program the PIC18 in C?
Compilers produce hex files that we download into the ROM of the microcontroller. The size of the hex file produced by the compiler is one of the main
concerns of microcontroller programmers for two reasons:
I. Microcontrollers have limited on-chip ROM.
2. The code space for the PIC 18 is limited to 2M.
How does the choice of programming language affect the compiled program size? While Assembly language produces a hex file that is much smaller than
C, programming in Assembly language is often tedious and time consuming. On
the other hand, C programming is less time consuming and much easier to write,
but the hex file size produced is much larger than if we used Assembly language.
The following are some of the major reasons for writing programs in C instead of
Assembly:
I.
2.
3.
4.
It is easier and less time consuming to write in C than in Assembly.
C is easier to modify and update.
You can use code available in function libraries.
C code is portable to other microcontrollers with little or no modification.
Several third-party companies develop C compilers for the PIC microcontroller. Our goal is not to recommend one over another, but to provide you with the
fundamentals ofC programming for the PICI8. You can use the compiler of your
choice for the chapter examples and programs. For this book we have chosen
Microchip's CI8 C compiler to integrate with MPLAB IDE. Microchip has a student version of the CI8 C compiler available for download from their web site. See
http://www.MicroDigitalEd.com for tutorials on the CI8 C compiler and MPLAB
simulator.
C programming for the PICI8 is the main topic of this chapter. In Section
7.1, we discuss data types, and time delays. 1/0 programming is shown in Section
7.2. The logic operations AND, OR, XOR, inverter, and shift are discussed in
Section 7.3. Section 7.4 describes ASCII and BCD conversions and checksums. In
Section 7.5, data serialization for the PICI8 is shown. In Section 7.6, we show how
the CI8 C compiler uses program ROM for data storage. We will examine CI8
data RAM allocation in Section 7.7.
SECTION 7.1: DATA TYPES AND TIME DELAYS IN C
In this section we first discuss C data types for the PIC 18 and then provide
code for time delay functions.
C data types for the PIC18
One of the goals of C 18 programmers is to create smaller hex files, so it is
worthwhile to re-examine C data types for C 18. In other words, a good understanding of C data types for the C 18 can help programmers to create smaller hex
252
files. In this section we focus on the specific C data types that are most useful and
widely used for the PICl8 microcontroller. Table 7-1 shows data types and sizes.
Table 7-1: Some Data Types Widely Used by CIS
Size in Bits Data Range/Usage
8-bit
oto 255
-128 to +127
8-bit
16-bit
o to 65,535
-32,768 to +32,767
16-bit
o to 65,535
16-bit
-32,768 to +32,767
16-bit
24-bit
o to 16,777,215
24-bit
-8,388,608 to +8,388,607
o to 4,294,967,295
32-bit
32-bit -2,147,483,648 to +2,147,483,648
Data Type
unsigned char
char
unsigned int
int
unsigned short
short
unsigned short long
short long
unsigned long
long
Unsigned char
Because the PIC 18 is an 8-bit microcontroller, the character data type is the
most natural choice for many applications. The unsigned char is an 8-bit data type
that takes a value in the range of 0--255 (OO--FFH). It is one of the most widely
used data types for the PIC 18. In many situations, such as setting a counter value,
where there is no need for signed data, we should use the unsigned char instead of
the signed char. Remember that C compilers use the signed char as the default
unless we put the keyword unsigned in front of the char (see Example 7-1). We can
also use the unsigned char data type for a string of ASCII characters, including
extended ASCII characters. Example 7-2 shows a string of ASCII characters. See
Example 7-3 for toggling ports.
In declaring variables, we must pay careful attention to the size of the data
and try to use unsigned char instead ofint if possible. Because the PICI8 microcontroller has a limited number of registers and data RAM locations, using int in
place of char can lead to a larger-size hex file. Such misuse of data types in compilers such as Microsoft Visual C++ for x86 IBM PCs is not a significant issue.
Example 7-1
Write a CI8 program to send values OO--FF to Port B.
Solution:
#include <P1BF45B.h>
Ilfor TRISB and PORTB declarations
void main(void)
(
unsigned char Z;
TRISB
=
limake Port B an output
0;
for(z=Ojz<=255iZ++)
PORTB =
while (1) ;
Zi
IINEEDED IF RUNNING IN HARDWARE
Run the above program on your simulator to see how Port B displays values OO--FFH in
binary. Notice that "while(l)" is needed if this program is running in hardware.
CHAPTER 7: PIC PROGRAMMING IN C
253
Example 7-2
Write a CI8 program to send hex values for ASCII characters ofO, 1,2,3,4,5, A, B,
C, and D to Port B.
Solution:
#include <PIBF45B.h>
void main (void)
(
unsigned char mynum[]= 11012345ABCD II ;//data is stored in RAM
unsigned char Zi
TRISB = 0;
Ilmake Port B an output
for(z=Oiz<lOi Z ++)
PORTB = mynum[zl;
while(l);
Iistay here forever
Run the above program on your simulator to see how Port B displays values 30H,
31H, 32H, 33H, 34H, 35H, 41H, 42H, 43H, and 44H (the hex values for ASCII 0, 1,
2, etc.). Notice that the last statement "while(l}" is needed only if we run the program
in hardware. This is like "GOTO $" or "BRA $" in Assembly language.
Example 7-3
Write a C 18 program to toggle all the bits of Port B continuously.
Solution:
II Toggle PB forever
#include <PIBF45B.h>
void main(void)
(
TRISB = 0;
for (;;)
Ilmake Port B an output
Ilrepeat forever
{
PORTB = Ox55;
PORTB = OxAA;
II0x indicates the data is in hex (binary)
Run the above program on your simulator to see how Port B toggles continuously.
0F76
OF80
lF8
OF82
OF83
,'"'
SFR Nome
TXERRCNT
I
I
Hex
_.
I
PORTA
00
00
~
PORTe
PORTD
00
00
o
o
Binary
nn
Figure 7-1. Examining the Special Function Registers Usmg MPLAB
254
I
~
.
~
:~
Signed char
The signed char is an 8-bit data type that uses the most significant bit (D7
of D7~DO) to represent the ~ or + value. As a result, we have only 7 bits for the
magnitude of the signed number, giving us values from ~128 to + 127. In situations
where + and ~ are needed to represent a given quantity such as temperature, the
use of the signed char data type is necessary.
Again, notice that if we do not use the keyword unsigned, the default is the
signed value. For that reason we should stick with the unsigned char unless the
data needs to be represented as signed numbers.
Example 7-4
Write a CI8 program to send values of -4 to +4 to Port B.
Solution:
//sign numbers
#include <P18F458.h>
void main (void)
{
char mynum[]= {+1,-l,+2,-2,+3,-3,+4,-4}i
unsigned char Zi
TRISB
=
0;
/ /make Port B an output
for(z=Oi z <8i Z++)
PORTB = mynum[z];
while (1) ;
//stay here forever
Run the above program on your simulator to see how PORTB displays values of I, FFH,
2, FEH, 3, FDH, 4, and FCH (the hex values for +1, ~I, +2, ~2, etc.). See Chapter 5 for
discussion of signed numbers.
Unsigned int
The unsigned int is a 16-bit data type that takes a value in the range of 0 to
65,535 (OOOO-FFFFH). In the PICI8, unsigned int is used to define 16-bit variables such as memory addresses. It is also used to set counter values of more than
256. Because the PICI8 is an 8-bit microcontroller and the int data type takes two
bytes of RAM, we must not use the int data type unless we have to. Because registers and memory accesses are in 8-bit chunks, the misuse of int variables will
result in a larger hex file. Such misuse is not a problem in PCs with 512 megabytes
of memory, the 32-bit Pentium's registers and memory accesses, and a bus speed
of 133 MHz. For prCI8 programming, however, do not use signed int in places
where unsigned char will do the job. Of course, the compiler will not generate an
error for this misuse, but the overhead in hex file size will be noticeable. Also, in
situations where there is no need for signed data (such as setting counter values),
we should use unsigned int instead of signed int. This gives a much wider range
for data declaration. Again, remember that the C compiler uses signed int as the
default unless we specifY the keyword unsigned.
CHAPTER 7: PIC PROGRAMMING IN C
255
Signed int
Signed int is a 16-bit data type that uses the most significant bit (D IS of
DIS-DO) to represent the - or + value. As a result, we have only IS bits for the
magnitude of the number, or values from -32,768 to +32,767.
Other data types
The unsigned int is limited to values 0-65,535 (OOOO-FFFFH). The C 18 C
compiler supports both short long and long data types, if we want values greater
than 16-bit. See Table 7-1. The short long value is 24 bits wide, while the long
value is 32 bits wide.
Example 7-5
Write a CI8 program to toggle all bits of Port B 50,000 times.
Solution:
#include <P18F458.h>
void main(void)
{
unsigned int Zi
TRISB = 0;
for(z=0;z<=50000;z++)
//make Port B an output
{
PORTB
PORTB
Ox55;
OxAAj
}
while(l);
//stay here forever
Run the above program on your simulator to see how Port B toggles continuously.
Notice that the maximum value for unsigned int is 65,535.
Example 7-6
Write a C 18 program to toggle all bits of Port B 100,000 times.
Solution:
//toggle PB 100,00 times
#include <P18F458.h>
void main(void)
{
unsigned short long Zi
unsigned int Xi
TRISB = 0;
for(z=0;z<=100000;z++)
{
PORTB
Ox55;
PORTB
OxAAi
while (1);
256
//make Port B an output
//stay here forever
Time delay
There are two ways to create a time delay in C 18:
I. Using a simple for loop
2. Using the PIC18 timers
In either case, when we write a time delay we must use the oscilloscope to
measure the duration of our time delay. Next, we use the for loop to create time
delays. The use of the PIC 18 timer to create time delays is postponed until
Chapter 9.
In creating a time delay using a for loop, we must be mindful of two factors that can affect the accuracy of the delay:
1. The crystal frequency connected to the OSC I-OSC2 input pins is the most
important factor in the time delay calculation. The duration of the clock period for the instruction cycle is a function of this crystal frequency.
2. The second factor that affects the time delay is the compiler used to compile
the C program. When we program in Assembly language, we can control the
exact instructions and their sequences used in the delay subroutine. In the case
of C programs, it is the C compiler that converts the C statements and functions to Assembly language instructions. As a result, different compilers produce different code. In other words, if we compile a given C program with different compilers, each compiler produces different-size hex code.
F or the above reasons, when we write time delays for C, we must use the
oscilloscope to measure the exact duration. Look at Examples 7-7 and 7-8.
Example 7-7
Write a C 18 program to toggle all the bits of Port B ports continuously with a 250 ms
delay. Assume that the system is PIC18F458 with XTAL = 10 MHz.
Solution:
#include <P18F458.h>
void MSDelay(unsigned int)
void main(void)
(
TRISB = 0;
while (1)
i
//make Port B an output
//repeat forever
(
PORTB = Ox55;
MSDelay(250) ;
PORTB = OxAA;
MSDelay(250) ;
}
void MSDelay(unsigned int itime)
(
unsigned int ii unsigned char j;
for(i=Oii<itimeji++)
for{j=Ojj<165;j++) ;
CHAPTER 7: PIC PROGRAMMING IN C
257
Example 7-8
Write a C 18 program to toggle all the bits of Port C and Port 0 continuously with a 250
ms delay.
Solution:
Iithis program is tested for the PIC18F458 with XTAL
#include <P18F458.h>
void MSOelay(unsigned int);
void main(void)
10 MHz
{
TRISC = 0;
TRISO = 0;
while (1)
Ilmake Ports C and 0 output
Ilanother way to do it forever
(
PORTC = Ox55;
PORTO = Ox55;
MSDelay(250);
PORTC = OxAA;
PORTO = OxAA;
MSOelay(250);
void MSDelay(unsigned int itime)
unsigned int i; unsigned char j;
for(i=O;i<itime;i++)
for(j=0;j<l65;j++) ;
IS;<nch I In.lrucbon Cycle.
I Zero I TOne
TotalS_ed
6275n
251.015600
251.03OaOO
(mSec.)
Processor Frequency
~ Clear Sirm.J~ion
Siopwalch
627539
{MHz J
Time 0 n Reset
10.0000ClJ
MPLAB's simulator has a stopwatch function that allows us to
view the time delay before we
program the microcontroller.
Figure 7-2. Time Delay Measurement for Example 7-8 Using MPLAB
Review Questions
I. Give the magnitude of the unsigned char and signed char data types.
2. Give the magnitude of the unsigned int and signed int data types.
3. If we are declaring a variable for a person's age, we should use the _ data
type.
4. True or false. Using a for loop to create a time delay is not recommended if
you want your code be portable to other PIC 18-based systems.
5. Give two factors that can affect the delay size.
258
SECTION 7.2: 1/0 PROGRAMMING IN C
In this section we look at C programming of the VO ports for the PIC 18.
We look at both byte and bit VO programming.
Byte size I/O
As we stated in Chapter 4, ports PORTA-PORTO are byte accessible. We
use the PORTA-PORTO labels as defined in the Cl8 header file. See Example 7-9.
Examine the next few examples to get a better understanding of how ports are
accessed in C J 8.
Example 7-9
LEOs are connected to bits in Port B and Port C. Write a C J 8 program that shows the
count from 0 to FFH (0000 0000 to 1111 1111 in binary) on the LEDs.
Solution:
#include <P18F458.h>
#define LED PORTe
void main (void)
(
TRISB
0;
TRIse
0;
PORTB
00;
LED = 0;
for(;; )
//notice how we can define Port C
//make Port B an output
//make Port e an output
/ /clear Port B
/ /clear Port e
//repeat forever
{
//increment Port B
//increment Port e
PORTB++j
LED++j
Spe"a'
oraD
OF82
OF83
PORTA.
PORTB
PORTe
PORTD
or84
PORTE
OrBl
or70
oraD
or90
orAD
orao
orca
orDO
00 00 00 00
00
00
7f 00
00 00 5f 00
00 00 00 00
00 00 00
1C 00 05 00
00
00
00
00
00
00
00
18
18
00
00
0
24
24
0
0
00011000
OOQ11000
00000000
00000000
00
00
07
rr 00
00 00
00 00
H
00
H
18 18 00 00
00
00 00 00
00 02 00
00 00 00 00
00
00 00 00 00 rr 00 00
00 00 00 05
00
00
00
00
H
00
00
00
· .- ... ..
· ... ....
· . . . - ...
Figure 7-3. Example 7-9 Results After 24 Iterations
CHAPTER 7: PIC PROGRAMMING IN C
259
Example 7-10
Write a C 18 program to get a byte of data from Port B, wait 112 second, and then send
it to Port C.
Solution:
#include <P18F458.h>
void MSDelay(unsigned int);
void main (void)
{
unsigned char mybyte;
TRISB = OxFF;
TRISC = 0;
while (1)
{
mybyte = PORTB;
MSDelay(500);
PORTC = mybyte;
}
//Port B as input
//Port C as output
//get a byte from Port B
//send it to Port C
void MSDelay(unsigned int itime)
unsigned int i;
unsigned char j;
for(i=O;i<itimeii++}
for(j=0;j<l65;j++) ;
Example 7-11
Write a C 18 program to get a byte of data from Port C. If it is less than 100, send it to
Port B; otherwise, send it to Port D.
Solution:
#include <P18F458.h>
void main(void)
{
unsigned char mybyte;
TRISC
OxFF;
TRISB = 0;
TRISD = 0;
while (1)
//make Port C an input
//both Port Band D as output
{
mybyte = PORTC;
if (mybyte < 100)
PORTB
mybyte;
//get a byte from PORTC
//send it to PORTB i f less than 100
else
PORTD
}
260
mybyte;
//send it to PORTD i f more than 100
Bit-addressable 1/0 programming
The lIO ports of PIC 18 are bit-addressable. We can access a single bit without disturbing the rest of the port. We use PORTxbits. Rxy to access a single
bit of Portx, where x is the port A, B, C, or D, and y is the bit (0-7) of that port.
For example, PORTBbits.RB7 indicates PORTB.7. We access the TRISx registers
in the same way where TRISBbits.TRISB7 indicates the D7 of the TRISB. Table
7-2 shows the single-bit addresses of a PICI8. Study the next few examples to
become familiar with the syntax.
Table 7-2: Sin&le-Bit Addresses of PIC18F458/4580 Ports
PORTA
RAO
RAI
RA2
RA3
RA4
RA5
PORTB
RBO
RBI
RB2
RB3
RB4
RB5
RB6
RB7
PORTC
RCO
RCI
RC2
RC3
RC4
RC5
RC6
RC7
PORTD
RDO
RDI
RD2
RD3
RD4
RD5
RD6
RD7
PORTE
REO
REI
RE2
Port's Bit
DO
D1
D2
D3
D4
D5
D6
D7
PORT bits structure
Figure 7-4 shows the structure for the Port B bits as given by the CI8 C
compiler. You can find the structure of the ports in the microcontroller header file.
extern volatile near unsigned char
extern volatile near union
PORTB;
struct {
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
RBO:l;
RBl:l;
RB2:1;
RB3:1;
RB4:1;
RB5:1;
RB6:1;
RB7:1;
};
struct {
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
INTO:l;
INTl:l;
CANTX:l;
CANRX:l;
: 1;
PGM:l;
PGC:l;
PGD:l;
};
PORTBbits;
Figure 7-4. Port B Bit Structure
CHAPTER 7: PIC PROGRAMMING IN C
261
Example 7-12
Write a C 18 program to toggle only bit RB4 continuously without disturbing the rest of
the bits of Port B.
Solution:
#include <P1SF45S.h,
#define mybit PORTBbits.RB4
void main(void)
Iideclare single bit
{
Ilmake RB4 an output
TRISBbits.TRISB4=0;
while (1)
{
mybit
mybit
Iiturn on RB4
Iiturn off RB4
1;
0;
Example 7-13
Write a C I 8 program to monitor bit PC5. lf it is HIGH, send 55H to Port B; otherwise,
send AAH to Port D.
Solution:
#include <P1SF45S.h,
#define mybit PORTCbits . RC5
void main(void)
TRISCbits . TRISC5
TRISD = 0;
while(l)
1;
I/notice single-bit declaration
IIRC5 as input
IIPo r ts C and D output
{
if(mybit == 1)
PORTD
Ox55;
e l se
OxAA;
PORTD
orBD
orSl
OFaD
orBl
ore2
PORTA
PORTB
00
00
00
o
o
00000000
00000000
PORTA
PORTH
PORTe
00
00
o
00000000
a
00000000
20
32
00 1 00000
Figure 7-5. Example 7-13 Results on MPLAB Simulator
262
Example 7-14
A door sensor is connected to the RB I pin, and a buzzer is connected to RC7. Write a
C I8 program to monitor the door sensor, and when it opens, sound the buzzer. You can
sound the buzzer by sending a square wave of a few hundred Hz frequency to it.
Solution:
#include < P18F458 . h >
void MSDelay (unsigned int) ;
#define Dsensor PORTBbits.RB1
#define buzzer PORTCbits . RC7
void main {void )
{
// PORTB.1 as an input
// make PORTC . 7 an output
TRISBbits.TRISB1 = 1;
TRISCbits . TRISC7 = 0;
while (Dsensor -{
buzzer = 0;
1)
MSDelay ( 200) ;
buzzer = 1;
MSDelay ( 200 ) ;
}
while (1) ;
// stay here forever
}
void MSDelay(unsigned int itime)
{
unsigned int i;
unsigned c har j;
for(i=Oii <itimeii++ )
for ( j=0;j<l65;j++) ;
}
~
Tngger Podion
5'''0 Cent"
~
-'==
°EndO
T'igger pc.
~I!;IN
I
TineB.ue Modo
jcyc (v I SirI<>Ie
Illdd S.,... I
I
r+~~~~
RB1
-
r-
Re7
l
, , , , , , , ,
0'0 '
50010
,
'--
, , , ,
111:010
'--
,,, , ,,, ,, ,,,, ,
15OOJ.O
2IlXll.0
250010
~o
I
Figure 7-6. MPLAB LogiC Analyzer for Example 7-14
CHAPTER 7: PIC PROGRAMMING IN C
263
Example 7-1S
The data pins of an LCD are connected to Port B. The information is latched into the
LCD whenever its Enable pin goes from HIGH to LOW. Write a C I8 program to send
"The Earth is but One Country" to this LCD.
Solution:
#include <P18F458.h ,
#define LCDData PORTB
#define En PORTCbits.RC2
void main (void)
// LCDData declaration
li the Enable pin
{
unsigned char message[)
unsigned char Z;
TRISB = 0;
TRISCbits.TRISC2
0;
f o r(z=0;z <28;z++ )
li The Earth is but One Country";
// Port B as output
// PortC.2 as output
// send all the 28 characters
{
LCDData = message[z];
// a
En=li
En=Oi
HIGH-
// -to-LOW pulse to latch the LCD data
}
while ( 1 ) ;
// stay here forever
Run the above program on your simulator to see how PORTB displays each character
of the message. Meanwhile, monitor bit PC.2 after each character is issued.
~
T'iggeI pc .
TIggeI' P~ltion
5'''' 0
~
...
~I
CerlOf O End 0
r+ ~ ~ .cJ8.J
Tne8ase Mode
~v l 5....
I icyc
CIoai
I AddS~ I
l@~
J
n
RC2
n
RB7
RBG
I
RB5
I
I
RB4
I
I
RB3
RB2
I
I
I
I
RB1 -
I
RBO
11~.~
,,
f
ii, , , I I I •
110.0
1200
I
,I I ,
1300
ii
i
I
140.0
,
iii
f
150.0
,,,
i
I,
160.0
Figure 7-7. M PLAB Logic Analyzer Results for Example 7-15
264
I
I
i I
170.0
,,,
iii
180. 0
Iii
j
1!JJ.0
j
I
Example 7-16
Write a C 18 program to toggle all the bits of Port B, Port C, and Port D continuously
with a 250 ms delay.
Solution:
#include <P18F458.h>
void MSDelay(unsigned int);
void main(void)
{
TRISB
0;
TRIse
0;
TRISD
0;
while(l)
lido it forever
{
PORTB
Ox55;
Ox55;
PORTe
PORTD
Ox55;
MSDelay(250) ;
PORTB
OxAA;
PORTe ~ OxAA;
PORTD ~ OxAA;
MSDelay(250) ;
11250 rns delay
void MSDelay(unsigned int itirne)
unsigned int ii
unsigned char ji
for(i=Oii<itimeii++)
for(j=0;j<l65;j++) ;
Example 7-17
Write a C 18 program to tum bit 5 of Port B on and off 50,000 times.
Solution:
#include <P18F458.h>
#define MYBIT PORTBbits.RB5
void rnain(void)
{
unsigned int Z;
Ilrnake PORTB.S an output
TRISBbits.TRISBS = 0;
for(z=O;z<SOOOO;z++)
{
MYBIT
1;
MYBIT
0;
while(l);
Iistay here forever
CHAPTER 7: PIC PROGRAMMING IN C
265
Example 7-18
Write a C 18 program to get the status of bit RBO, and send it to RC7 continuously.
Solution:
#include <P18F458.h>
#define inbit PORTBbits.RBO
#define outbit PORTCbits.RC7
void main (void)
{
TRISBbits.TRISBO = 1;
TRISCbits.TRISC7 = 0;
while (1)
Ilmake RBO an input
I/make RC7 an output
{
I/get a bit from RBO
Iland send it to RC7
outbit = inbit;
3:
#include <P18F458.h>
#define inbit PORTBbits.RBO
#define outbit PORTCbits.RC7
4:
void main (void)
1:
2:
5:
{
6:
0000E2
7·
0000E4
8093
9E94
8:
0000F2
D7F9
TRISBbits. TRISBO = 1;
BSF Oxf93, 0, ACCESS
TRISCbits.TRISC7 = 0;
BCF Oxf94, Ox7, ACCESS
while (1)
BRA Oxe6
9:
outbit
=
inbit;
Iland send it to RC7
}
12 :
13 :
0000F4
Ilget bit from RBO
MOVF Oxf81, W, ACCESS
ANDLW Ox1
BZ OxfO
BSF Oxf82, Ox7, ACCESS
BRA Oxf2
BCF Oxf82, Ox7, ACCESS
5081
OB01
E002
8E82
D001
9E82
11 :
0012
}
RETURN a
FIgure 7-8. DIsassembly of Example 7-18
Review Questions
I. The address of PORTB is ---..,.--.,,-,-,-
266
Ilmake RC7 an output
{
10:
0000E6
0000E8
OOOOEA
OOOOEC
OOOOEE
OOOOFO
2.
3.
4.
5.
Ilmake RBO an input
Write a short program that toggles all bits of PORTC.
Write a short program that toggles only bit 0 of PORTB.
True or false. All bits of PORTB are bit addressable.
True or false. All bits of TRISB are bit addressable.
SECTION 7.3: LOGIC OPERATIONS IN C
One of the most important and powerful features of the C language is its
ability to perform bit manipulation. Because many books on C do not cover this
important topic, it is appropriate to discuss it in this section. This section describes
the action of bit-wise logic operators and provides some examples of how they are
used.
Table 7-3: Bit-wise Logic Operators for C
A
0
0
I
1
B
0
1
0
1
AND
OR
EX-OR
A&B
0
0
0
1
AlB
0
AI\B
0
1
1
I
1
0
1
Inverter
Y=-B
I
0
Bit-wise operators in C
While every C programmer is familiar with the logical operators AND
(&&), OR (II), and NOT (!), many C programmers are less familiar with the bitwise operators AND (&), OR (I), EX-OR (1\), inverter (-), shift right (»), and shift
left «<). These bit-wise operators are widely used in software engineering for
embedded systems and control; consequently, their understanding and mastery are
critical in microprocessor-based system design and interfacing. See Table 7-3.
The following shows some examples using the C bit-wise operators:
I.
2.
3.
4.
Ox35 & OxOF = Ox05
Ox04 I Ox68 = Ox6C
Ox54 1\ Ox78 = Ox2C
-Ox55 = OxAA
/*
/*
/*
/*
ANDing */
ORing: */
XORing */
Inverting 55H */
Bit-wise shift operation in C
There are two bit-wise shift operators in C: (I) shift right ( »), and (2)
shift left (<<).
Their format in C is as follows:
data» number of bits to be shifted right
data «number of bits to be shifted left
The following shows
1. Ox9A» 3 = Ox13
2. Ox77» 4 = Ox07
3. Ox6« 4 = Ox60
some examples of shift operators in C:
/* shifting right 3 times */
/* shifting right 4 times */
/* shifting left 4 times */
Study Examples 7-19 through 7-22. These show how the bit-wise operators
are used in C.
CHAPTER 7: PIC PROGRAMMING IN C
267
Example 7-19
Run the following program on your simulator and examine the results.
Solution:
#include <P18F458.h>
(void)
void main
{
TRISB
TRIse =
TRISD =
PORTB =
PORTe =
PORTD =
PORTB =
PORTe =
PORTD
PORTB =
while (1)
~
~
0;
0;
0;
Ox35
Ox04
Ox54
Ilmake Ports B, e,
Iland D output ports
&
OxOF;
I
Ox68;
A
Ox78;
-Ox55;
Ox9A » 3 ;
Ox77 » 4;
Ox6 « 4;
;
I lANDing
IIORing
IIXORing
Ilinverting
/Ishifting right 3 times
Iishifting right 4 times
I/shifting left 4 times
Iistay here forever
}
Example 7-20
Write a C 18 program to toggle all the bits of Port B and Port C continuously with a 250
ms delay. Use the inverting operator.
Solution:
#include <PIBF458.h>
void MSDelay(unsigned int);
void main(void)
{
TRISB = 0;
TRIse = 0;
PORTB = Ox55;
PORTe = OxAA;
while (1)
(
PORTB = -PORTB;
PORTe = -PORTe;
MSDelay(250) ;
/Imake Ports Band e output
void MSDelay(unsigned int itime)
(
unsigned int ii
unsigned char ji
for(i=Oii<itime;i++)
for(j=O;j<l65;j++) ;
268
Example 7-21
Rewrite the C 18 program to toggle all the bits of Port B, Port C, and Port D continuously with a 250 ms delay. Use the EX-OR operator.
Solution:
#include <P18F458.h>
void MSDelay(unsigned int);
void rnain(void}
{
TRISB = 0;
TRISC = 0;
TRISD = 0;
PORTB=Ox55;
PORTC=Ox55 ;
PORTD=Ox55;
while (1)
//make Ports B,C,
and D output
{
PORTB=PORTBAOxFF;
PORTC=PORTCAOxFF;
PORTD=PORTDAOxFF;
MSDelay(250);
void MSDelay(unsigned int itime)
unsigned int ii
unsigned char ji
for(i=Oji<itimeji++)
for(j=O;j<l65;j++) ;
Example 7-22
Rewrite the C 18 program to get bit RBO and send it to RC7 after inverting it.
Solution:
#include <P18F4550.h>
#define inbit PORTBbits.RBO
#define outbit PORTCbits.RC7
void main (void)
{
TRISBbits.TRISBO = 1;
TRISCbits.TRISC7 = 0;
while(l)
//make PORTB.O an input
//make PORTC.7 an output
{
Qutbit
=
-inhiti
CHAPTER 7: PIC PROGRAMMING IN C
//get a bit from RBO
269
Example 7-23
Write a PIC C 18 program to read the RBO and RB I bits and issue an ASCLI character
to PO according to the following table:
RBI
RBO
o
o
o
send '0'
send' I'
send '2'
send ' 3'
I
o
to
to
to
to
PORTO (notice ASCII '0' is Ox30)
PORTD
PORTO
PORTD
Solution:
#include <P18F458.h>
void main (void)
{
unsigned char Zj
TRISB = OxFF;
TRISD = 0;
while (1)
(
z = PORTB;
Z = Z & Ox3;
switch(z)
//make Port B an input
//make Port D an output
// repeat forever
//read PORTB
//mask the unused bits
//make decision
(
case(O):
{
j
/ /issue ASCII 0
=
'1' i
/ / issue ASCII 1
=
'2';
/ / issue ASCII 2
PORTD =
13 ' ;
/ /issue ASCII 3
PORTD =
'0'
break;
}
case (1) :
{
PORTD
break;
}
case (2) :
{
PORTD
break;
}
case(3):
{
break;
}
oreo
PORTA
orSl
PORTB
Of82
PORTe
PORTD
PORTE
OF83
or84
270
00
02
00
32
00
o
2
o
50
a
00000000
00000010
00000000
00110010
00000000
Review Questions
1. Find the content of PORTB after the following C code in each case:
(a) PORTB=Ox37&OxCA;
(b) PORTB=Ox37I OxCA;
A
(c) PORTB=Ox37 OxCA;
2.
3.
4.
5.
To mask certain bits we must AND them with
To set high certain bits we must OR them with _ _ .
EX-ORing a value with itself results in _ __
Find the contents ofPORTC after execution of the following code:
---
PORTC
PORTC
PORTC
0;
PORTC I Ox99;
-PORTC;
SECTION 7.4: DATA CONVERSION PROGRAMS IN C
Recall that BCD numbers were discussed in Chapters 5 and 6. As stated
there, many newer microcontrollers have a real-time clock (RTC) where the time
and date are kept even when the power is off. Very often the RTC provides the time
and date in packed BCD. To display them, however, it must convert them to
ASCII. In this section we show the application of logic and rotate instructions in
the conversion of BCD and ASCII.
ASCII numbers
On ASCII keyboards, when the key "0" is activated, "0 II 0000" (30H) is
provided to the computer. Similarly, 31H (0110001) is provided for the key "1",
and so on, as shown in Table 7-4.
Table 7-4: ASCII Code for Digits 0-9
Key
0
1
2
3
4
5
6
7
8
9
ASCII (hex)
30
31
32
33
34
35
36
37
38
39
Binary
011 0000
011 0001
011 0010
0110011
011 0100
011 0101
0110110
011 0111
011 1000
011 1001
CHAPTER 7: PIC PROGRAMMING IN C
BCD (unpacked)
00000000
00000001
00000010
00000011
00000100
00000101
0000 OliO
00000111
00001000
0000 1001
271
Packed BCD to ASCII conversion
The RTC provides the time of day (hour, minute, second) and the date
(year, month, day) continuously, regardless of whether the power is on or off. This
data is provided in packed BCD, however. To convert packed BCD to ASCII, you
must first convert it to unpacked BCD. Then the unpacked BCD is tagged with Oil
0000 (30H). The following demonstrates converting from packed BCD to ASCII.
See also Example 7-24.
Packed BCD
Ox29
00101001
Unpacked BCD
Ox02, Ox09
00000010,00001001
ASCII
Ox32, Ox39
00110010,00111001
ASCII to packed BCD conversion
To convert ASCII to packed BCD, you first convert it to unpacked BCD (to
get rid ofthe 3), and then combine to make packed BCD. For example, 4 and 7 on
the keyboard give 34H and 37H, respectively. The goal is to produce 47H or "0100
0111 ", which is packed BCD.
Key
ASCII
4
34
7
37
Unpacked BCD
00000100
00000111
Packed BCD
01000111 or 47H
After this conversion, the packed BCD numbers are processed and the
result will be in packed BCD format. Chapter 16 discusses the RTC chip and uses
the BCD and ASCII conversion programs shown in Examples 7-24 and 7-25.
Example 7-24
Write a CI8 program to convert packed BCD 0x29 to ASCII and display the bytes on
PORTB and PORTe.
Solution:
#include <P18F458.h>
void main (void)
{
unsigned char X, y, Z;
unsigned char mybyte = Ox29j
TRISB = 0;
TRISC = 0;
x = mybyte & OxOF;
PORTB = x I Ox30;
y = mybyte & OxFO;
y = y »
4;
PORTC = y I Ox30;
}
272
//make Ports Band C output
//mask upper 4 bits
/ /make it ASCII
//mask lower 4 bits
//shift it to lower 4 bits
/ /make it ASCII
~ ..
..
~.
rl
OF80
OF81
I
srR N.....
PORTA
I
Hex
I
or8 2
PORTe
32
Of8 3
or84
PORTD
PORTE
00
00
Binary
J
Char
;~
a
00
50 00 1100 1 0
a
o
00000000
00000000
2
:rv
Figure 7-9. Result of Example 7-24 on MPLAB Simulator.
Example 7-25
Write a CI8 program to convert ASCII digits of'4' and '7' to packed BCD and display
it on PORTB.
Solution:
#include <P1BF45B.h>
void main (void)
{
unsigned char bcdbyte ;
unsigned char w
'4' ;
unsigned char z = '7';
TRISB = 0;
w
w & OxOF ;
w = w « 4;
z = z & OxOF i
bcdbyte = w I z;
PORTB = bcdbyte;
//make Port B an output
//mask 3
//shift left to make upper BCD digit
//mask 3
//combine to make packed BCD
.G@ . . . . .
0510
0520
0530
0540
00
00
00 00 00 00
00 00 00 00
00 00 00 00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
....... .
....... .
..... .. .
.... ... .
.... ... .
... .... .
... .... .
.. .... ..
.... ... .
He,
or80
orSl
PORTA
PORTB
OY82
or83
PORTe
PORTD
Or8'1
PORTE
or89
LATA.
LATB
araA.
00
.7
00
00
00
00
.7
a
71
a
a
a
a
71
01000 11 1
00000000
00000000
00000000
00000000
0 1 000111
Figure 7-10. Result of Example 7-25 on MPLAB Simulator
CHAPTER 7: PIC PROGRAMMING IN C
273
Checksum byte in ROM
To ensure the integrity of ROM contents, every system must perform the
checksum calculation. The checksum will detect any corruption of the contents of
ROM. One of the causes of ROM corruption is current surge, either when the system is turned on or during operation. To ensure data integrity in ROM, the checksum process uses what is called a checksum byte. The checksum byte is an extra
byte that is tagged to the end of a series of bytes of data. To calculate the checksum byte of a series of bytes of data, the following steps can be taken:
1. Add the bytes together and drop the carries.
2. Take the 2's complement of the total sum. This is the checksum byte, which
becomes the last byte of the series.
To perform the checksum operation, add all the bytes, including the checksum byte. The result must be zero. If it is not zero, one or more bytes of data have
been changed (corrupted). To clarify these important concepts, see Examples 7-26
through 7-28.
Example 7-26
Assume that we have 4 bytes of hexadecimal data: 25H, 62H, 3FH, and 52H.
(a) Find the checksum byte, (b) perform the checksum operation to ensure data
integrity, and (c) if the second byte, 62H, has been changed to 22H, show how checksum detects the error.
Solution:
(a)
Find the checksum byte.
+
+
+
25H
62H
3FH
52H
118H (dropping carry of I and taking 2's complement, we get E8H)
(b)
Perform the checksum operation to ensure data integrity.
+
+
+
+
25H
62H
3FH
52H
EBH
200H (dropping the carries we get 00, which means data is not corrupted)
(c)
If the second byte, 62H, has been changed to 22H, show how checksum detects
the error.
+
+
+
+
274
25H
22H
3FH
52H
EeH
leOH (dropping the carry, we get COH, which means data is corrupted)
Example 7-27
Write a Cl8 program to calculate the checksum byte for the data given in Example 7-26.
Solution:
#include <P1BF45B.h>
void main (void)
(
unsigned char mydata[]
=
{Ox25,Ox62,Ox3F,Ox52};
unsigned char sum = 0;
unsigned char Xi
unsigned char chksumbyte;
TRISB = 0;
TRISC = 0;
for(x=Oix<4;x++)
//make Ports Band C output
{
PORTC = mydata[x];
sum = sum + mydata[x];
PORTB = sum;
//issue each byte to PORTC
//add them together
//issue the sum to PORTB
}
//make 2's complement (invert +1)
//show the checksum byte
chksumbyte = -sum + 1;
PORTB = chksumbyte;
Single-step the above program on the MPLAB simulator and examine the contents of
PORTB and PORTe. Notice that each byte is put on PORTC as they are added.
Example 7-28
Write a Cl8 program to perform step (b) of Example 7-26. If the data is good, send
ASCII character 'G' to PORTD. Otherwise, send 'B' to PORTD.
Solution:
#include <P1BF45B.h>
void main (void)
{
unsigned char mydata[]
= {Ox25,OX62,ox3F,Ox52,OxEB};
unsigned char chksum
unsigned char Xi
0;
=
TRISD = 0;
//make Port D an output
for (x=O; x<5; X++)
chksum = chksum + mydata[x];
//add them together
i f (chksum __ 0)
PORTD =
'G';
else
PORTD =
'B Ii
Change one or two values in the mydata array and simulate the program to see the
results.
CHAPTER 7: PIC PROGRAMMING IN C
275
Binary (hex) to decimal and ASCII conversion in C18
The printf function is part ofthe standard I/O library in C and can do many
things including converting data from binary (hex) to decimal, or vice versa. But
printf takes a lot of memory space and increases your hex file substantially. For
this reason, in systems based on the PIC18 microcontroller, it is better to write our
own conversion function instead of using printf.
One of the most widely used conversions is binary to decimal conversion.
In devices such as ADCs (Analog-to-Digital Converters), the data is provided to
the microcontroller in binary. In some RTCs, the time and dates are also provided
in binary. In order to display binary data, we need to convert it to decimal and then
to ASCII. Because the hexadecimal format is a convenient way of representing
binary data, we refer to the binary data as hex. The binary data OO-FFH converted to decimal will give us 000 to 255. One way to do that is to divide it by 10 and
keep the remainder, as was shown in Chapters 5 and 6. For example, 11111101 or
FDH is 253 in decimal. The following is one version of an algorithm for conversion of hex (binary) to decimal:
Hex
FD/OA
19/OA
Ouotient
19
2
Remainder
3 (low digit) LSD
5 (middle digit)
2 (high digit) (MSD)
Example 7-29 shows the C program for that algorithm.
Example 7-29
Write a C18 program to convert 11111101 (FD hex) to decimal and display the digits on
PORTB, PORTC, and PORTD.
Solution:
#include <P18F458.h>
void main{void)
{
unsigned char X, binbyte,
TRISB
0;
TRISC = 0;
TRISD = 0;
binbyte = oxFD;
x = binbyte / 10;
d1
binbyte % 10;
d2 = x % 10;
d3 = x / 10;
PORTB
d1;
PORTC
d2;
PORTD
d3;
}
276
dl, d2, d3;
//Ports B, C, and D output
//binary (hex) byte
/ /divide by 10
//find remainder (LSD)
/ /middle digit
//most-significant digit (MSD)
Review Questions
1. For the following decimal numbers, give the packed BCD and unpacked BCD
representations:
(a) 15
(b) 99
2. Show the binary and hex formats for "76" and its packed BCD version.
3. 67H in BCD when converted to ASCII is
Hand
H.
4. Does the following convert unpacked BCD to ASCII?
mydata~Ox09+0x30;
5.
6.
7.
8.
9.
Why is the use of packed BCD preferable to ASCII?
Which takes more memory space: packed BCD or ASCII?
In Question 6, which is more universal?
Find the checksum byte for the following values; 22H, 76H, 5FH, 8CH, 99H.
To test data integrity, we add the bytes together, including the checksum byte.
The result must be equal to _ _ if the data is not corrupted.
10. An ADC provides an output of 0010 0110. How do we display that on the
screen?
SECTION 7.5: DATA SERIALIZATION IN C
Serializing data is a way of sending a byte of data one bit at a time through
a single pin of a microcontroller. There are two ways to transfer a byte of data serially:
1. Using the serial port. In using the serial port, the programmer has very limited
control over the sequence of data transfer. The details of serial port data transfer are discussed in Chapter 10.
2. The second method of serializing data is to transfer data one bit a time and control the sequence of data and spaces between them. In many new generations
of devices such as LCD, ADC, and EEPROM, the serial versions are becoming popular because they take less space on a printed circuit board. Although
we can use standards such as PC and CAN, not all devices support such standards. For this reason we need to be familiar with data serialization using the
C language.
Examine the next four examples to see how data serialization is done in C.
CHAPTER 7: PIC PROGRAMMING IN C
277
Example 7-30
Write a CI8 program to send out the value 44H serially one bit at a time via RCO. The
LSB should go out first.
Solution:
IISerializing data via RCO
#include <P18F458.h>
#define PCO PORTCbits.RCO
void main (void)
(SHIFTING RIGHT)
(
unsigned char conbyte
= Ox44;
unsigned char regALSB;
unsigned char x',
regALSB = conbyte;
TRISCbits.TRISCO = 0;
for(x=Ojx<8;x++)
Ilmake RCO an output
{
PCO = regALSB & OxOl;
regALSB = regALSB » l ',
}
}
PIN
I I
I I -8
fileReg
D7
DO
Figure 7-11. Shlftmg Bits Out (LSB Gomg FIrst)
Example 7-31
Write a C 18 program to send out the value 44H serially one bit at a time via RCO. The
MSB should go out first.
Solution:
IISerializing data via RCO
#include <P18F458.h>
#define PCO PORTCbits.RCO
void main (void)
(SHIFTING LEFT)
(
unsigned char conbyte = Ox8S;
unsigned char regAMSB;
unsigned char X;
regAMSB = conbyte;
TRISCbits.TRISCO
0;
for(x=Ojx<8jx++)
Ilmake RCO an output
{
PCO = (regAMSB » 7)
regAMSB = regAMSB «
278
& Ox01;
1;
Example 7-32
Write a C 18 program to bring in a byte of data serially one bit at a time via the RBO pin.
Place the byte on Port D. The LSB should come in first.
Solution:
IIBringing in data via RBO
#include <P18F458.h>
#define PBO PORTBbits.RBO
void rnain(void)
(
unsigned char X;
unsigned char REGA=Oj
TRISBbits.TRISBO = l',
TRISD = 0;
(SHIFTING RIGHT)
IIRBO as input
IIPort D as output
for(x=Oix<8jx++)
{
REGA = REGA » 1;
REGA 1= (PBO & OxOl)
«
7 ,.
I
PORTD = REGA;
I
PIN
8
-I I
fileReg
07
I I
DO
FIgure 7-12. ShIftIng BIts In (BrIng In LSB FIrst)
Example 7-33
Write a C 18 program to bring in a byte of data serially one bit at a time via the RBO pin.
The MSB should come in first.
Solution:
IIBringing in data via RBO
#include <P18F458.h>
#define PBO PORTBbits.RBO
void main (void)
(SHIFTING LEFT)
{
unsigned char Xi
unsigned char REGA=O;
TRISBbits.TRISBO = 1;
TRISD = 0;
for(x=Ojx<8jx++)
IIRBO as input
IIPort D as output
{
REGA = REGA « 1;
REGA 1= PBO & OxOl;
I
PORTD = REGA;
CHAPTER 7: PIC PROGRAMMING IN C
279
SECTION 7.6: PROGRAM ROM ALLOCATION IN C18
Using program (code) space for predefined fixed data is a widely used
option in the PIC 18, as we saw in Chapter 6. In that chapter we saw how to use
Assembly language instructions to access the data stored in the program code
space. In this chapter, we explore the same concept using the C 18 C compiler. We
will also examine the far and near storage qualifier for ROM.
RAM data space vs. code data space
In the PIC 18 we have two spaces in which to store data. They are as follows:
.....-
8~bit
wide
~
I. The 4096 bytes of data RAM
OOOOOOh
RESET VECTOR
space with address range
HIGH PRIORITY
OOOOOBh INTERRUPT VECTOR
OOO-FFFH. As we have seen in
previous chapters, many PICI8
LOW PRIORITY
00001Bh INTERRUPT
chips have much less than 4096
VECTOR
bytes for the file register data
RAM. We also have seen how
ON·CHIP PROGRAM
we can read (from) or write
MEMORY
(into) this RAM space directly or
indirectly.
2. The 2M of code (program) space
with
addresses
of
EXTERNAU
000000-1 FFFFFH. This 2M
UNIMPLEMENTED
PROGRAM MEMORY
bytes of on-chip ROM space is
(READ AS '0' IN
used for storing programs
MICROCONTROLLER
MODE)
(opcodes) and therefore is direct1y under control of the program
1FFFFFh
counter (PC). As we have seen in
the previous chapters, many Figure 7-13. PIC1S Program ROM Space
PIC 18 chips have much less than
2M of on-chip program ROM. We have also seen how to access the program
ROM for the purpose of data storage using the TBLRD instruction (see
Chapter 6). There is one problem with using this program code space for storage of fixed data: The more code space we use for data, the less is left for our
program code. For example, if we have a PICI8 chip such as the PICI8F252
with only 4K of on-chip ROM, and we use IK to store a look-up table, only
3K is left for the program. For some applications, this can be a problem. For
this reason Microchip has added EEPROM memory to the PICI8 to be used
for data storage. The EEPROM option of PIC 18 is discussed in Chapter 14.
Next, we will examine how the CI8 compiler uses on-chip ROM space, and
discuss how it places data into program ROM.
280
Table 7-5: Program ROM Size for Some PIC18F Family Members
On-Chip Code ROM
Code Address Range
(Bytes)
(Hex)
PICI8F2220
PICI8F2410
PICI8F458/4580
PICI8F6680
PICI8F8722
4K
16K
32K
64K
128K
OOOOO--OOFFF
00000--03FFF
00000--07FFF
OOOOO--OFFFF
OOOOO- IFFFF
Allocating program space to data
In all our C 18 examples so far, byte-size variables were stored in the data
RAM . As we saw in Chapter 6, it is common practice to use the on-chip program
ROM for the purpose of storing fixed data such as strings. This is specially useful
since we have limited amount of file register data RAM. To make the C 18 compiler use the program (code) ROM space for the fixed data, we use the keyword
rom as shown in tbe following lines of C code:
rom char mynum []
rom char weekdays
II Hello ll
=
=
;
7, month= 12;
//use code space for data
//use code space for data
The following code shows how to use program space for data in C18:
// Program 7-1
#include <P18F458.h,
rom canst char mynum []
=
II 0123456789 " i
/Iuses program
//ROM space for fixed (constant)
data
void main (void)
(
unsigned char Zj
TRISB = 0;
for(z=Ojz<lOiZ++)
PORTB=mynum [z J ;
~ODO
FrD9
52£6
ODED
6A.r ?
6193
6 £F 6
ooro
or16
21D1
D7F2
52£5
0100
0110
0120
FO OD EE2S FOOD
rOOD D7FD 0012
FrOD FFFT rrFT
//make Port B an output
6AD F
OEOl
52£5
6Ar B
SODY
22 17
e FE ?
ge01
080A.
0008
FrOg
[ C16
£ 30B
SOTS
0012
FOOD
SODr
6 E81
EElS
Ee6S
•• • R.j.j .P ...•. P
. j ... n . . . . . .. ,P.n
.• ... R.R ....... .
.. \ .... j ...... e .
01 23456789
o
•••••
FFFT rrFT rrFr rrFr rrrr
Figure 7-14. Fixed Data Placed in Program ROM as Shown in MPLAB
CHAPTER 7: PIC PROGRAMMING IN C
281
NEAR and FAR for code
As we have discussed earlier, the PIC 18 microcontroller has a maximum
of 2M of on-chip program ROM space. Not every family member, however, comes
with that much on-chip program ROM. Some PIC I8 chips come with as little as
4K and some come with 128K of program ROM. To make a more efficient use of
the code space, the C 18 compiler allows the use of near and far storage qualifiers
to indicate in what region the data and code should be placed. The near qualifier
is used to indicate that a program memory data variable is located in the first 64K
of the program ROM. In order to indicate that a data variable in program ROM can
be found anywhere in the 2M ROM space, we must use the far qualifier. See Table
7-6. Also see Program 7-2A. Note that the far storage qualifier is the default for
the C I 8 if we do not specify it in our program.
Table 7-6: NEAR and FAR Usage for ROM
Storage qualifier
near
far
ROM
In program space ofOOOO-FFFFH (64 kB)
In program space ofOOOOOO-IFFFFFH (2 MB)
//PrograJJl 7-2A
#include <P 18F458.h >
near rom canst char mydata[]
void main (void)
"HELLO"; / /p rogram ROM data
{
unsigned char Z;
TRISB = 0;
for(z=Oiz<SiZ++)
PORTB = mydata[z];
//make Port B an output
ODeD
0765
Droo
5B66
........
DODO
00[0
rFD9
52E6
6.193
.P ..... P
Dora
0100
DUO
D7Br 0012 CFD9 FFE6 cr:n
6ADF SODr 0805 E30B SODF
6A.r? or16 6Er6 OE01 22F7 0008 SaYS 6E81
2ADY D71"2 52E5 52E5 erE? FrDg 0012 EElS
r OOD EE25 rooD 6Are ge01 [ C16 FOOD Ee65
rOOD D7FO 0012
Notice 4 digits for address (OOOO-FFFF)
Figure 7-15. Using Near Storage Qualifier as Shown by MPLAB
282
. j ... n ..
" ..
,P.n
• -, •• R.R
........
.. , ... . j
...... e .
•••••. HE LLO .•...
In Program 7-2A, if we change the near to far and compile for the
PICI8F8722 chip (which has 128K of program ROM), we have the following:
//Program 7-2B
#include <P18F8722.h>
far rom const char mydata[]= "HELLO"; //program ROM data
void main(void )
(
unsigned char Zj
TRISB = 0;
for(z=Oiz<SjZ++)
PORTB = mydata[z];
00000
OOOEO
FrDg 52E6
6EOO OE01
// make Port B an output
6193
6E01
2403
6ADF
so Dr
OEOO
6E02
eFor
6£F3
5001
rrF?
oooro
6AOS
5000
00100
00110
001Z0
200S
6E81
EEll
6ErB CrF"l
2ADr
D7E1
rooD
ttz!:
0805
!:Jle
FD03
QE3a
. . . R.j.j
6104
2004
6[r.q
erFJ rrr6
S2E5 erE?
0008
5002
SOTS
FrDg
0012
.n ... n .. · n ••••• j
. j .P. $.n · P • . n.P
.n .... • ..•••• P
. n. • •• • R .R .• ••••
00130
FOOD
....... .
rrFT
I! •• • • • • •
· P •..• B.
.j . . . . . .
HELLO •..
Notite 5 digits for hex address (OOOOO--FFFFF)
Figure 7-16. Far Storage Qualifier as Shown in MPLAB
Pragma and allocating a fixed address to data and code
As we saw in Chapter 6, the MPLAB assembler allows us to place data or
code at a specific ROM address using the ORG directive. To do the same thing in
the C I 8 C compiler we use the #pragma section directive, where "section" is a portion of an application (code or data) that can be assigned an specific memory
address location. In the case of the on-chip ROM program memory, we have two
options: (I) code, and (2) romdata. The #pragma directive is used for the program
because it contains executable instructions, while the #pragma romdata directive
is used for fixed data such as strings and look-up tables. Next we explore the use
of #pragma to allocate ROM addresses for the code and data.
Putting code in a specific ROM address
To place the code (containing executable instructions) at a specific address
location of the program ROM, we use the #pragma code directive. Examine the
Program 7-3 to see how the C code for the MSDeiay function is placed at the ROM
address of Ox300.
CHAPTER 7: PIC PROGRAMMING IN C
283
({Program 7-3
#include <P18F458.h>
#pragma code main
=
OxSO
void MSDelay(unsigned int) ;
void main(void)
{
unsigned char mydata[]
unsigned char
({ place the main at ROM addr Ox50
"HELLO" ;
Zi
({ make Port B an output
TRISB = 0;
for (z=Oiz<Si Z ++)
{
PORTB = mydata[z];
MSDelay(250) ;
#pragma code MSDelay = Ox300
({place delay at ROM addr Ox300
void MSDelay (unsigned int itime)
(
unsigned i n t ij
unsigned char j;
for{i=Oji<itime;i++ )
for ( j=O;j<l65;j++) ;
Running the above programs on the MPLAB simulator and examining the
program code space, we see that the main and MSDeiay functions are located at
the ROM addresses Ox50 and Ox300, respectively.
r1[6
43
44
45
[::1 pl()~HVn
I
Opcode
erEl
frD9
KeNrr rSRIL,
NOP
OE07
IlOVLV Ox?
L1n~
I
lddr~~~
I Opcod~ I
OZfC
FrFF
02r[
rrrF
...ElE2.
0302
0304
0306
Hexl .10_11 S"mboIc
CfD9
Label
QlgJtj1
I
Dbs:!5sell'tlly
I!"
~
NOP
NOP
lISDele.y "ovrr rSR2L, POSTINCl
rrE6
erEl
NOP
HovrT
FrD9
"'
..
Figure 7-17. Screen Shot for Program 7-3
284
FSR2L
_.
Memory 1
383
384
385
386
387
388
<
0054
0056
0058
rSRIL, rSRZ L
NOP
~-~d-i.l.:
F
m
Putting data in a specific ROM address
To place the data (containing variables and constants, strings, and look-up
tables) at a specific address of program ROM, we use the #pragma romdata directive. Examine the Program 7-4 to see how the C code assigns the program ROM
address of Ox200 to the string "Hello".
// PrograJ1l 7-4
#include <P18F458.h >
#pragma romdata mydata = Ox200 // place mydata at ROM addr Ox200
near rom canst char mydata[J= lIHELLO";
//ROM data
void main (void)
(
unsigned char Z;
// make Port B an output
TRISB = 0;
for(z=Oiz<Si Z ++ )
PORTB = mydata[z];
Run the above program on the MPLAB simulator. Examine the program
code space to see the string "HELLO" located at the ROM address starting at
Ox50.
OlFO
0200
0210
0220
0230
4C4C
rrFr FrFT
rrFr rrFT
rFFF
004F
FFFF
rrFr
FFFF
rrFF FFFT
FrFF rrFF FFFT
FFFF FrFT rrFr FFFF
rrFr rrFr rrFr rTFT
rrrr rrFr rrFr rTFr
rFFF FFFT FFFT rrFr
........
....... . ........
........ ...... ..
... .... . ... .....
HELLO •..
Figure 7-18. Screen Shot for Program 7-4
Review Questions
I. The PIC J 8 family has a maximum of __ of program ROM space.
2. The PIC 18F8722 has __ K of program ROM
3. True or false. The program (code) ROM space can be used for data storage, but
the data space cannot be used for code.
4. True or false. Using the program ROM space for data means the data is fixed
and static.
5. If we have a message string with a size of over 1000 bytes, then we use
_ _ _ (program ROM , data RAM ) to store it.
CHAPTER 7: PIC PROGRAMMING IN C
285
SECTION 7.7: DATA RAM ALLOCATION IN C18
In this chapter, we explore the data RAM file register usage and its allocation by the C18 C compiler. We will also explore the near and far data storage qualifiers for data RAM. In addition, we will examine how to place a given data or
stack at a fixed address using the C 18 compiler.
RAM data space usage by the C18 C compiler
As we have seen in Chapters 2 through 6, PICl8 family members can have
a maximum of 4K of data RAM, but not all the members come with 4K of RAM.
As we have seen before, the data RAM can vary from 256 bytes to 4096 depending on the chip. That means all members of the PIC 18 family come with at least
one bank of RAM, which is called the access bank. In Assembly language programming, the 128 bytes of the data RAM are used for the SFRs and the remaining RAM is used for the scratch pad. The C 18 compiler does the same thing by
leaving the SFR region undisturbed and allocating the rest of the RAM to the stack
and the variables declared by the C program. See Program 7-5.
//Prograsn 7-5
#include <P18 F458.h>
void main (void)
{
unsigned char x=S,y=9j
unsigned char Zj
TRISB
0;
z
=
//uses data RAM to store data
//make Port B an output
x + Yi
PORTB
z;
Running the above program on the MPLAB simulator, we can examine the
data RAM space to locate x, y, and z as shown in Figure 7-19.
D4EO
O"1TO
0510
OS20
0530
00
00
00
00
00
00
00
00
05
00
00
00
00
00
00
00
00
00
00
00
DE
00
00
00
00
00
DE
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
Figure 7-19. Screen Shot for Program 7-5
286
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
........
........
........
..... ...
........
...... ..
........
An array needs contiguous RAM locations for the array elements, which
means the size of the array is limjted to the size of data RAM in a given PICl 8
chip. See Program 7-6 below.
IIProgr= 7 - 6
#include <P18F458.h>
void main(vo id )
(
unsigned c har mynum [] =
'10123456789 " ;
/ l uses RAM space
li to store data
unsigned char Z;
TRISB = 0 ;
for ( z= Oi z < lO i Z ++ )
PORTH = rnynurn[z];
Ilrnake Port B an output
Running the above program on the MPLAB simulator and examining the
data RAM space, we can locate values 30H, 3 1H, 32H, .. .., 41 H, 42H, 43H, 44H,
and so on (the hex values for ASCII ' 0', ' I', ' 2', etc., as shown below).
04DO
Di EO
D4ro
0520
0530
00
00
00
00
00
00
00
00
30
00
00
00
00
00
31
00
00
00
00
00
32
00
00
00
00
00
33
00
00
00
00
00
34
00
00
00
00
00
35
00
00
00
00
00
36
00
00
00
00
00
37
00
00
00
00
00
38
00
00
00
00
00
39
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.. .. . . . . ..... ...
....... . .... ....
. 0 123 4 56789 .... .
..... .. . ... .....
.. . .. . . . ..... . . .
.. . .. . . . . .. . ... .
Figure 7-20. Screen Shot for Program 7-6
In the case of arrays with a large number of elements, such as 100, examine the code below:
IIProgr= 7 - 7
#include <P18F458.h>
void rnain (void )
(
unsigned char rny data[lOO];
unsigned c har x, z = OxFFi
TRISB = 0 ;
11 100-byte space in RAM
Il rnake Po rt B an output
f o r (x=O i x <10 0 i X ++ )
{
rnydata[x] = z;
PORTH = z;
Ii save it in RAM
Il give a copy to PORTH too
z--;
Il count down
Running the above program on the MPLAB si mulator, we can locate values FF H, FEH, FDH, and so on in the data RAM file register, as shown in Figure
7-2 1.
CHAPTER 7: PIC PROGRAMMING IN C
287
0510
0520
0530
0540
0550
0560
Fa
EO
DO
CO
BO
AO
EF
DF
CF
BF
EE
DE
CE
BE
ED
DD
CD
BD
AF AE AD
9F 9E 9D
EC
DC
CC
BC
AC
9C
EB
DB
CB
BB
AB
6'
E9 Ea
DA D9 Da D7
CA C9 ca C7
BA B9 Ba B7
AA A9 Aa A7
EA
D6 D5 D. D3
C6 C5 C. C3
B6 B5 B. B3
16 AS 14 A3
E2
D2
C2
B2
A2
.. . . ... . .... ....
D1
C1
B1
11
00 00 00 00 00 00 00 00 00 00
.... ... .
. . . . . ...
....... .
....... .
••..• d ..
........
........
... .....
........
.... ... .
Figure 7-21. Screen Shot for Program 7-7
Change the size of the array and the targeted PIC 18 chip (e.g., PIC 18F252)
and monitor the RAM space allocation by the C compiler.
NEAR and FAR for data
The C 18 compiler has two storage qualifiers for data RAM allocation
called near and far. The far and near qualifiers are used to indicate which sections
of data RAM are to be used for the storage of declared variables. The keyword
near will limit the C 18 C compiler usage of RAM to the access bank for the data
declaration, while the keyword far will put the entire data RAM at the disposal of
C compilers. See Table 7-7. This means that programs written for the PICI8 chips
with a limited data RAM cannot have too many arrays with a large number of elements. Using C 18, compile and simulate Programs 7-8a and 7-8b to see the impact
of near and far in RAM allocation. See Table 7-7.
Table 7-7: NEAR and FAR Usage for Data RAM
Storage qualifier
near
far
RAM
In access bank
Anywhere in data RAM file register (default)
//Program 7-8a
#include <P18F458 . h>
near unsigned char mydata[lOO];
void main (void)
//lOO-byte space in RAM
{
unsigned char X, Z
TRISB = 0;
for(x=O ; x<100;x++)
{
z--;
mydata [x]
Z;
PORTB = Z;
288
0;
//make Port B an output
//count down
//save it in RAM
//give a copy to PORTB too
//Program 7-8b
#include <P18F458.h ,
void main {v o id )
(
far unsigned char rnydata[lOO];
unsigned char x, z = 0;
TRISB = 0;
f o r (x=O;x<lOO;x++ )
//lOO-byte space in RAM
// rnake Port B an output
(
// count down
// save it in RAM
// give a copy to PORTB too
Z--i
rnydata [x]
PORTB = z;
z;
Putting data in a specific RAM address
As we saw in Chapter 6, the MPLAB assembler allows us to place data at
a speci fic RAM address using a combination of MOVLW and MOVWF instructions. To place data at a specific data RAM address in the C 18 C compiler, we use
the #pragma directive. In the last section we examined the use of the #pragma
directive to set the ROM memory address. The #pragma directive can also be used
to set the data RAM address. There are two options for #pragma when it is used
for the data RAM: (I) idata, and (2) udata, where idata stands for initiali zed data
and udata stands for uninitialized data. The idata (initialized data) and udata
(uninitialized data) options are widely used by the CI8 to assign an explicit
address in RAM data. For example, the following code uses idata to place the data
string " HELLO" at RAM address starting at Ox 150:
//Program 7-9 (using idata)
#include <P18F458 . h ,
#pragrna idata rnydata = Ox150
unsigned char mydata[]=
IIHELLOI1;
/ / RAM data
void main (void)
(
unsigned char Zi
TRISB = 0;
for(z=Oiz <Si Z ++)
PORTB = rnydata[z];
// rnake Port B an output
We can verify the above concept by simulating the program on the
MPLAB and examining the RAM at address Ox ]50.
HELL O . ..
0170
0180
00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00
00 00
00 00
Figure 7-22. Screen Shot for Program 7-9
CHAPTER 7: PIC PROGRAMMING IN C
289
The following is a repeat of an earlier program and shows how to assign a
fixed address of Ox200 using udata.
IIProgram 7-10 (using udata)
#include <P1BF45B .h,
#pragma udata mycount = Ox200
Il assign RAM address Ox200
I I (bank 2)
far unsigned char mycount[lOO];
void main(void)
11100-byte space in RAM
{
unsigned char X,Z=Oi
TRISB = 0;
for(x=O;x<lOO;x++)
Ilmake Port B an output
{
Il count down
Iisave it in RAM
Ilgive a copy to PORTB too
Z- - i
mycount[x]=z;
PORTB=z;
Irwa,
~
1 00 1011021031041051061071081091 OJ. lOB
ff FE FD fC fB fA f9 FB F7 f6 rs f4
Ef EE ED EC EB EA E9 EB E7 E6 ES E4
Df DE DD DC DB DA D9 DB D7 D6 DS D.
Cf CE CD CC CB CA C9 C8 C7 C6 C5 C.
Bf BE BD BC BB BA B9 BB B7 B6 85 B.
Af AE AD AC AB .0..0. .0.9 AB .0.7 .0.6 AS A4
9f 9E 9D 9C 00 00 00 00 00 00 00 00
0200
0210
0220
0230
02"10
0250
0260
I OC laD I OE I or I
f3
E3
D3
C3
B3
.0.3
00
F2
E2
D2
C2
B2
.0.2
00
fl
El
Dl
Cl
Bl
.0.1
00
Fa
EO
DO
CO
BO
.0.0
00
0
••••••
I He>< . s~
Figure 7-23. Screen Shot for Program 7-\0
The following program shows how to assign a fixed address usi ng both
udata and idata.
/j Program 7-11 (assigning udata and idata to a fixed address)
#pragma idata x = OxlOO
Ilassign fixed RAM address OxlOO to var x
unsigned char X=5i
I/both data are initialized data
#pragma idata y = OxlO l
Ilassign fixed RAM address oxlOl to var y
unsigned char y=9 ;
Ilboth data are initialized data
#pragma udata z = Oxl02
Ilassign fixed RAM address Oxl02 to var z
unsigned char Zi
flit is uninitialized data
#include <PlBF45B.h,
void main (void)
{
TRISB
0;
z
Yi
=
x +
PORTB
Ilmake Port B an output
z;
Although ass igning fix ed addresses to a string of data in the data RAM can
be justified, this practice is not recommended for individual variables, because it
is the job of the compi ler to assign addresses dynamica lly.
290
U~
ASCII
........ . . . . . . . • Cl
....... . ........
....... .
...... . . .. ..... .
....... . ...... ..
..... ... ........ Iv
....... . .. ..... .
•
ooro
00
0100
00
00 00 00 00
00 00 00 00
00 00 00 00
DUO
0120
0130
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
........
........ ....... .
........ ....... .
........
Figure 7-24. Screen Shot for Program 7-11
Overlay storage class
In an attempt to use the data space of the PIC 18 more efficiently, the C 18
compiler introduces the overlay storage class. The overlay conserves memory by
allowing two variables to share the same physical address as long as they are not
active at the same time. Compare the following two functions.
unsigned char proga(void)
(
overlay unsigned char x
0;
x = x + 1;
return
Xj
and
unsigned char progb(void)
(
overlay unsigned char y
OJ
Y = Y + 2;
return Yi
Because the x and y variables are not active at the same time, the C 18 C
compiler uses the same physical address location in the file register for both of
them. If we remove the keyword overlay in the above programs, the CI8 will
assign two different locations to the x and y variables. The C 18 will also use two
different physical locations for the variables when the variables are dependent on
each other and are both active. Look at the following cases.
unsigned char progc(void)
(
overlay unsigned char x
0;
x = progd()
return x;
and
unsigned char progd(void)
{
overlay unsigned char y
0;
y = y + 2;
return y;
CHAPTER 7: PIC PROGRAMMING IN C
291
In the previous programs, the C 18 compiler assigned a separate RAM location to x and y, even though we used the keyword overlay. Because progc calls
function progd, the variables are dependent on each other and they are both active
at the same item. Note that the C 18 C compiler supports all the ANSI C standard
storage classes such as auto, extern, static, and so on. The overlay is a new storage
class and applies to local variables.
To gain a better understanding of this concept, examine Example 7-34. It
shows three different versions of a program that sends the string "HELLO" to Port
8. Simulate each program with the C 18 compiler and compare data storage methods. Also, compile each program and compare the hex file size to see the impact
of the data storage method on the hex file size.
292
Example 7-34
Compare and contrast the following programs and discuss the advantages and disadvantages of each:
(a)
#include <P18F458.h>
void main(void)
{
TRISB
PORTB
PORTB
PORTB
PORTB
PORTB
//make Port B an output
0;
'H' ;
IE' ;
r
L
I
i
L' i
'0 I i
r
(b)
#include <P18F458.h>
void main(void}
(
unsigned char mydata[]
unsigned char Zi
TRISB = 0;
11
HELLO II
,.
//make Port B an output
for(z=Oiz<Si Z ++)
PORTB
=
mydata[z];
(c)
#include <P18F458.h>
void main(void)
(
rom unsigned char mydata[]
unsigned char Zj
TRISB = 0;
for(z=Oiz<Si Z++)
PORTB = mydata[z];
nHELLo n
;
jJnotice keyword rom
//make Port B an output
Solution:
All the programs send out "HELLO" to PORTB one character at a time. They do the
same thing in different ways. The first way is short and simple, but the individual characters are embedded into the program. If we change the characters, the whole program
changes. This method also mixes the code and data together. The second one uses the
RAM data space to store array elements; therefore, the size of the array is limited to file
register size. The third one uses a separate area of the program code space for data. This
allows the size of the array to be as big as you want provided that you have enough onchip program ROM. The more program code space you use for data, however, the less
space is left for your program code. Both the (b) and (c) programs are easily upgradable
if we want to change the string itself or make it longer. That is not the case for program
(a).
CHAPTER 7: PIC PROGRAMMING IN C
293
Review Questions
I.
2.
3.
4.
The PIC 18 has a maximum of
of data RAM.
The PIC 18F8722 has __ of data RAM space.
True or false. The data space can be used for code.
Which space would you use to declare the following values for C18?
(a) the number of days in a week
(b) the number of months in a year
(c) a counter for a delay
5. True or false. The near storage qualifier is used to place the variables in access
RAM.
See the following web site for PIC18 C compilers:
http://www.microchip.com
The following web site has a tutorial for MPLAB and C18:
http://www.MicroDigitaIEd.com
Running any of the C18 programs on the PIC18F hardware, the following points must be noted:
1. Disable the WatchDog Timer in the configuration bits.
2. Place "while(1 );" at the end of the program to
prevent the program from executing again. This
plays the role of "HERE BRA HERE" in Assembly
language.
SUMMARY
This chapter dealt with C 18 programming, specifically I/O programming
and time delays in C. We also showed the logic operators AND, OR, XOR, and
complement. In addition, some applications for these operators were discussed.
This chapter described BCD and ASCII formats and conversions in C. We also
compared and contrasted the use of code space and RAM data space in C. The
widely used technique of data serialization was also discussed.
294
PROBLEMS
SECTION 7.1: DATA TYPES AND TIME DELAYS IN C
I. Indicate what data type you would use for the following variables:
(a) the temperature
(b) the number of days in a week
(c) the number of days in a year
(d) the number of months in a year
(e) the counter to keep the number of people getting on a bus
(1) the counter to keep the number of people going to a class
(g) an address of 64K RAM space
(h) the age of a person
(i) a string for a message to welcome people to a building
2. Give the hex value that is sent to the port for each of the following C statements:
(al PORTB=14;
(b) PORTB=OxIS; (c) PORTB='A';
(1) PORTB=Ox45;
(d) PORTB=7;
(e) PORTB=32;
(g) PORTB=255;
(h) PORTB=OxOF;
3. Give two factors that can affect time delay code size in the PICIS microcontroller.
4. Of the two factors in Problem 3, which can be set by the system designer?
5. Can the programmer set the number of clock cycles used to execute an instruction? Explain your answer.
6. Explain why various C compilers produce different hex file sizes.
SECTION 7.2: 1/0 PROGRAMMING IN C
7. What is the difference between the PORTBbits.RB4 and TRISBbits.TRISB4?
S. Write a CIS program to toggle all bits ofPORTB every 200 ms.
9. Write a CIS program to toggle bits RBI and RB7 every 200 ms.
10. Write a time delay function for 100 ms.
II. Write a C IS program to toggle only bit RBO every 200 ms.
12. Write a CIS program to count up PORTB from 0-99 continuously.
SECTION 7.3: LOGIC OPERATIONS IN C
13. Indicate the data on the ports for each of the following:
Note: The operations are independent of each other.
(al
(el
(el
(gl
(il
PORTB=OxFO&Ox4S;
A
PORTB=OxFO Ox76;
A
PORTC=OxFO Ox90;
PORTC=OxFO&OxFF;
PORTC=OxFOAOxEE;
(bl
(dl
(fl
(hi
(j I
PORTB=OxFO&OxS6;
PORTC=OxFO&Ox90;
PORTC=OXFOlox90;
PORTC=OxFO I Ox99;
PORTC=OxFOAOxAA;
14. Find the contents of the port after each of the following operations:
(al
(el
(el
(gl
PORTB=Ox6S&Ox76;
A
PORTC=Ox9S OxAA;
PORTC=Oxcsl Ox12;
PORTB=ox3710x26;
CHAPTER 7: PIC PROGRAMMING IN C
(bl
(dl
(fl
PORTB=Ox70Iox6B;
PORTC=OxSD&Ox78;
A
PORTD=Ox6A Ox6E;
295
15. Find the port value after each of the following is executed:
(a)
(e)
PORTB=Ox65»2;
PORTB=OxD4»3;
(b)
(d)
PORTC=Ox39«2;
PORTB=OxA7«2;
16. Show the C code to swap Ox95 to make it Ox59.
17. Write a C program that finds the number of zeros in an 8-bit data item.
18. A stepper motor uses the following sequence of binary numbers to move the
motor. How would you generate them in C18?
1100,0110,0011,1001
SECTION 7.4: DATA CONVERSION PROGRAMS IN C
19. Write a program to convert the following series of packed BCD numbers to
ASCII. Assume that the packed BCD is located in data RAM.
76H,87H,98H,43H
20. Write a program to convert the following series of ASCII numbers to packed
BCD. Assume that the ASCII data is located in data RAM.
"8767 11
21. Write a program to get an 8-bit binary number from PORTB, convert it to
ASCII, and save the result if the input is packed BCD of 0(},-{)x99. Assume
that PORTB has 1000 100 I binary as input.
SECTION 7.6: PROGRAM ROM ALLOCATION IN CI8
22. Indicate what type of memory (data RAM or code ROM space) you would use
for the following variables:
(a) the temperature
(b) the number of days in a week
(c) the number of days in a year
(d) the number of months in a year
23. True or false. When using program ROM for data, the total size of the array
should not exceed 256.
24. Why do we use the ROM code space for video game characters and shapes?
25. What is the advantage of using program ROM space for data?
26. What is the drawback of using program ROM space for data?
27. Write a CI8 program to send your first and last names to PORTC. Use the program ROM space for the data.
28. What is the difference between far and near storage?
29. What is the difference between #pragma code and #pragma romdata?
30. In Problem 27, show how to place the last name at ROM address Ox200 and
the first name at address Ox220.
3 I. Indicate the size of the program ROM space for each of the following chips:
(a) PICI8F452/4520
(b) PIC 18F458/4580 (c) PIC18F8722
32. In Problem 3 I, discuss what impact the ROM space has on your decision on
the amount of the memory to be allocated to data.
296
SECTION 7.7: DATA RAM ALLOCATION IN C
33. Indicate what type of memory (data RAM, or code ROM space) you would use
for the following variables:
(a) the counter to keep the number of people getting on a bus
(b) the counter to keep the number of people going to a class
(c) an address of64K RAM space
(d) the age of a person
(e) a string for a message to welcome people to building
34. Indicate the size of the data RAM space for each of the following chips:
(b) PIC I 8F458/4580 (c) PIC I 8F8722
(a) PICI8F452/4520
35. Discuss why the total size of an array should be limited to 256 bytes ifpossible.
36. Why will we not use the data RAM space for video game characters and
shapes?
37. What is the drawback of using RAM data space for fixed data?
38. What is the advantage of using data RAM space for variables?
39. What is the difference between #pragma udata and #pragma idata?
40. In Problem 27, show how to place the names at RAM address Ox300.
41. Explain when we use overlay for variables.
42. True or false. Overlay is used for variables that are not active at the same time.
ANSWERS TO REVIEW QUESTIONS
SECTION 7.1: DATA TYPES AND TIME DELAY IN C
I.
2.
3.
4.
5.
0 to 255 for unsigned char and -128 to + 127 for signed char
0 to 65,535 for unsigned int and -32,768 to +32,767 for signed int
Unsigned char
True
(al Crystal frequency ofPICI8 system
(b l PIC 18 machine cycle timing
(cl compiler used for C
SECTION 7.2: VO PROGRAMMING IN C
I.
2.
F81H
void main ()
TRISC
PORTC
PORTC
0;
Ox55j
OxAAi
}
3.
#def ine PBObi t
PORTBbi ts. RBO
void main ()
{
TRISBbits.TRISBO
PBObit
0;
PBObit = 1;
0;
}
4.
5.
True
True
CHAPTER 7: PIC PROGRAMMING IN C
297
SECTION 7.3: LOGIC OPERATIONS IN C
1.
(a) 02
(b) FFH
(c) FDH
2.
3.
4.
5.
Zeros
One
All zeros
66H
SECTION 7.4: DATA CONVERSION PROGRAMS IN C
(a) 15H = 0001 0101 packed BCD, 0000 0001,0000 0101 unpacked BCD
(b) 99H = 1001 1001 packed BCD, 0000 1001,0000 1001 unpacked BCD
2. 3736H = 00110111 00110110B
and in packed BCD we have 76H = 0111 OIIOB
3. 36,37
4. Yes, because mydata = Ox39.
5. Space savings
6. ASCII
7. BCD
8. E4H
9.0
10. First, convert from binary to decimal, then convert to ASCII, and then send results to the
screen and we will see 038.
1.
SECTION 7.6: PROGRAM ROM ALLOCATION IN CI8
1.
2.
3.
4.
5.
2M
128
True
True
Program ROM
SECTION 7.7: DATA RAM ALLOCATION IN CI8
1.
2.
3.
4.
5.
4K
4096 bytes
False
(a) ROM space, (b) ROM space, (c) RAM space
True
298
CHAPTER 8
PIC18F HARDWARE
CONNECTION AND
ROM LOADERS
OBJECTIVES
Upon completion of this chapter, you will be able to:
»
»
»
»
»
»
»
»
»
»
Explain the function of the reset pin of the PIC18F microcontroller
Show the hardware connection ofthe PIC18F chip
Show the use of a crystal oscillator for a clock source
Explain how to design a PIC18F-based system
Explain the role of brown-out reset voltage (BOR) in system reset
Explain the role of the CONFIG registers in PIC18-based systems
Show the design ofthe PIC Trainer
Code a test program in Assembly and C for testing the PIC18
Show how to download programs into the PIC18F system using
Microchip PICkit 2
Explain the Intel hex file characteristics for 32-bit and 16-bit addresses
299
This chapter describes the process of physically connecting and testing
PICl8F-based systems. In the first section we describe the functions of
PICI8F458 pins. The configuration registers of the PICI8 and how they are set are
explored in Section 8.2. In Section 8.3 we explain the characteristics of Intel hex
files that are produced by MPLAB. In Section 8.4 we discuss the various methods
ofloading a program into the microcontroller. It also shows the hardware connection for a PIC 18 Trainer using the PIC 18F452/458 (PIC l8F4520/4580) chips.
SECTION 8.1: PIC18F458/452 PIN CONNECTION
The PICI8F458 family members come in different packages, such as DIP
(dual in-line package), QFP (quad flat package), and LLC (leadless chip carrier).
They all have many pins that are dedicated to various functions such as 1/0, ADC,
timer, and interrupts. Note that Microchip provides an 18-pin version of the PICI8
family with a reduced number of I/O ports for less demanding applications.
Because the vast majority of developers use the 40-pin chip, however, we will concentrate on that. Figure 8-1 shows the pins for the PIC18F458.
40 PIN DIP
MClRIV pp
RB7/PGD
RAO/ANO/CVREF
RB6/PGC
RA1/AN1
3
RA2/AN2NREF •
4
RB5/PGM
PIC18F458
RA3/AN3NREF +
RA4rrOCKI
RB4
RB3/CANRX
RB2/CANTXlINT2
RA5/AN4/SS/lVDIN
RB111NT1
REO/AN5/RD
RE1/AN6IWRlClOUT
RBOIINTO
Voo
RE2/AN7/CS/C20UT
Vss
Voo
RD7/PSP7/P1 D
Vss
OSC1/ClKI
RD6/PSP6/P1C
OSC2/ClKO/RA6
RD5/PSP5/P 1B
RD4/PSP4/ECCP1/P1A
Rcom osorr1 ClKI
RC7/RXlDT
RC1/TlOS1
RC6/TXlCK
RC2/CCP1
RC5/SDO
RC3/SCKlSCl
RDO/PSPO/C1IN+
RD3/PSP3/C2IN-
RD1/PSP1/C1IN-
RD2/PSP2/C2IN+
Figure 8-1. PIC18F458 Pin Diagram
300
RC4/SDI/SDA
Examining Figure 8-1, note that of the 40 pins, a total of33 are set aside
for the five ports A, B, C, D, and E, with their alternate functions. The rest of the
pins are designated as Vdd, GND (Vss), OSCI, OSC2, and MCLR (master clear
reset). Next, we describe the function of each pin.
Vdd(Vcc)
Two pins are used to provide supply voltage to the chip. The typical voltage source is +SY. Some PIC 18F family members have lower voltage for Vdd pins
in order to reduce the noise and power dissipation of the PIC system. We can
choose other options for the Vdd voltage level by setting the bits in the configuration register. The configuration register for V dd is discussed in the next section.
Vss (GND)
Two pins are also used for ground. In chips with 40 pins and more, it is
common to have multiple pins for VCC and GND. This will help reduce the noise
(ground bounce) in high-frequency systems, as discussed in Appendix C.
OSC1 and OSC2
The PICI8F has many options for the clock source. Most often a quartz
crystal oscillator is connected to input pins OSC I and OSC2. The quartz crystal
oscillator connected to the OSC I and OSC2 pins also needs two capacitors. One
side of each capacitor is connected to the ground as shown in Figure 8-3. Note that
PICI8F microcontrollers can have speeds of 0 Hz to 40 MHz.
We can choose options for the clock frequency by setting bits in the configuration register. The config register for the oscillator is discussed in the next
section.
MCLR
Pin I (in the PICI8F4S8 40-pin DIP) is the MCLR (master clear reset) pin.
It is an input and is active-LOW (normally HIGH). When a LOW pulse is applied
to this pin, the microcontroller will reset and terminate all activities. This is often
referred to as a power-on reset (POR).
Program counter value upon reset
Activating a MCLR reset will cause
all values in the registers to be lost. Table 8-1
provides a partial list ofPICI8F registers and
their values after power-on reset. From Table
8-1 we note that the value of the PC (program
counter) is 0 upon reset, forcing the CPU to
fetch the first opcode from ROM memory
location 00000. This means that we must
place the first byte of opcode in ROM location 0 because that is where the CPU expects
to find the first instruction.
Table 8-1: RESET Values for
Some PIC18 Registers
Reset Value (hex)
Register
PC
000000
WREG
00
SP
00
TRISA-TRISE
FF
CHAPTER 8: PIC18F HARDWARE CONNECTION & ROM LOADERS
301
Figures 8-2a and 8-2b show two ways of connecting the MCLR pin to the
power-on reset circuitry. Figure 8-2b uses a momentary switch for reset circuitry.
The most difficult time for any system is during the power-up. The CPU needs
both a stable clock source and a stable voltage level to function properly. The
PlCI8 chips come with some features that help the reset process. We can choose
these features by setting the bits in the configuration register. The configuration
register for the reset pin is discussed in the next section. There are other sources of
reset in the PlCI8 family, and they are discussed in future chapters.
The pins discussed so far must be connected no matter which family member is used. They are the minimum pin connections that every PICI8 must have.
See Figure 8-3.
Vdd
Vdd
-r
-r-
t-----!Vdd
+----IVdd
10K
10K <
<
r-
' - - - - - I MCLR
Momentary
Switch
Figure 8-2a. PIC18F458
Power-On Reset Circuit
-
<
<
-l
~
Figure 8-2b. PIC18F458
Power-On Reset with a
Momentary Switch
Vdd
P18F458
11 Vdd
32 Vdd
10K
~
OSC1 13
<
-
~1
MCLRNpp
::!::
D
OSC2 14
--.
2~
.
10MHz
•
22
Reset
I
Switch ..,
12 Vss
31 Vss
•
Figure 8-3. Minimum Connection for PIC18F458
302
MCLR
The number of 1/0 ports varies among the PIC 18 family members, as we
saw in Chapter 4. The following is another look at them for the PIC18F458.
Ports A, B, C, 0, and E
As shown in Figure 8-1 (and discussed in Chapter 4), the ports PORTA,
PORTB, PORTC, PORTD, and PORTE use a total of 33 pins. All the ports upon
RESET are configured as input, because TRISA-TRISE have the value FFH on
them. Tables 8-2 through 8-5 provide summaries of features of ports
PORTA-PORTE and their alternative functions. We will study the alternative
functions of these pins in future chapters, as we discuss the PIC 18 features.
Table 8-2: PORTA/PORTE
Alternate Functions
Table 8-3: PORTB Alternate
Functions
Bit
RAO
RAI
RA2
RA3
RA4
RA5
RA6
REO
REI
RE2
Bit
RBO
RBI
RB2
RB3
RB4
RB5
RB6
RB7
Function
ANOICVREF
ANI
AN2NREFAN3NREF+
TOCKI
AN4/SSILVDIN
OSC2/CLKO
AN5/RD
AN6/WRlClOU
AN7/CS/C20UT
Function
INTO
INTI
INT2/CANTX
CANRX
PGM
PGC
PGD
Table 8-4: PORTC Alternate
Functions
Table 8-5: PORTD Alternate
Functions
Bit
RCO
RCI
RC2
RC3
RC4
RC5
RC6
RC7
Bit
RDO
RDI
Function
TI OSO/Tl CKI
TlOSI
CCPI
SCKlSCL
SDI/SDA
SDO
TX/CK
RX/DT
RD2
RD3
RD4
RD5
RD6
RD7
Function
PSPOICIIN+
PSPIICIINPSP2/C2IN+
PSP3/C2INPSP4/ECCPI/PIA
PSP5/PIB
PSP6/PIC
PSP7/PID
Review Questions
I. Which pin is used to reset the PICI8F458 chip?
2. Upon power-up, the program counter (PC) has a value of __ .
3. Upon power-up, the PICI8F458 fetches the first opcode from ROM address
location -----,---4. MCLR is an active(LOW, HIGH) pin.
5. How many Vdd and Gnd pins are in the PICI8F458 chip?
CHAPTER 8: PIC18F HARDWARE CONNECTION & ROM LOADERS
303
SECTION 8.2: PIC18 CONFIGURATION REGISTERS
There are some features of the PICl8 that we , - - - - - - - - - - - - ,
OOOOOOH
can choose by programming the bits of the configuration registers. These features will reduce system
Flash ROM
cost by eliminating any need for external components. The configuration registers are located at the
address starting at 300000H, as shown in Figure 84. Notice that the address 300000H is outside the
range OOOOOO-IFFFFFH, the address space belonging to program ROM. We write 8-bit values into the I' ...
configuration register one byte at a time using the
CONFIG directive in the source code, as we will see 1------1 1FFFFFH
200000H
soon. In other words, we provide the values and register name in our application program and let the
ROM programmer load them into the config register I' ...
along with the application program itself. The con""",=.,--1 300000 H
figuration registers can be accessed from the user
program using table reads and writes. In this section
I~ 300002H
300001
H
G2f
300003H
we examine some of the basic configuration regis300006H
ters such as reset, clock source, and Vdd voltage.
300008H
MicroChip website provides the complete list of ---EE ~ 300009H
configuration registers for the PIC microcontrollers. ---cc ~ 30000AH
30000BH
For the configuration registers of a given member of ~ \,j,
30000CH
~
G7H
30000DH
the PIC 18 family, see the "Configuration Register
Settings Addendum" document on the Microchip I 'fweb site. Table 8-6 gives a short description of the
configuration registers. It must be noted that if a
=jD~E"V~I[t:::j 3FFFFEH
3FFFFFH
configuration register is incorrectly programmed, it
can cause the system to fail. An example of this is '=----,;:--:-::===,-----'
FIgure 8-4. CONFIG
changing the clock type connected to the microcontroller.
Register Memory Map
::J~I~F'iCGi1~
~
t
Table 8-6: PIC18F458 Configuration Registers
Address (Hex)
300001
300002
300003
300006
300008
300009
30000A
30000B
30000C
30000D
3FFFFE
3FFFFF
304
Name
CONFIGIH
CONFIG2L
CONFIG2H
CONFIG4L
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
DEVIDI
DEVID2
General Description
Oscillator selection
Brown out
Watchdog enable
Background debugger and ISCP
Code protection
EEPROM and boot block protection
Write protection
Write protection
Read protection
Boot block read protection
Device ID and revision
Device ID
CONFIG1 H register and oscillator clock source
The CONFIG IH register is located at address Ox300001 and is set aside for
the clock oscillator, as shown in Figure 8-5. The following is a description of the
options for the CONFIG I H register.
U-o
U-O
R/P-1
10SCSEN
I
u-o
U-o
R/P-1
RlP-1
R/P-1
FOSC2
FOSC1
FOSCO
~7
~o
bit 7-6
Unimplemented: Read as '0'
bit 5
OSCSEN: Oscillator System Clock Switch Enable bit
1 ;;; Oscillator system clock switch option is disabled (main oscillator is source)
0= Oscillator system clock switch option is enabled (OSCillator switching is enabled)
bit 4-3
Unimplemented: Read as '0'
bit 2-0
FOSC2:FOSCO: Oscillator Selection bits
111 = RC oscillator w/OSC2 configured as RA6
110 = HS oscillator with PLL enabled/clock frequency = (4 x Fosc)
101 = EC osciliatorw/OSC2 configured as RA6
100 = EC oscillator w/OSC2 configured as divide-by-4 clock output
011 = RC oscillator
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
Legend:
R = Readable bit
P = Programmable bit
-n = Value when device is unprogrammed
U = Unimplemented bit, read as '0'
u = Unchanged from programmed state
Figure 8-5. CONFIGIH Register for Frequency Selection
FOSC2-FOSCO
The three bits of FOSC2, FOSC 1, and FOSCO are used to select the clock
frequency to the CPU. The default choice is RC (Ill), which uses the on-chip
oscillator with the help of an externally connected resistor and capacitor. In this
option, all we have to do is to connect the OSC 1 pin to the RC circuit. The values
of Rand C detennine the clock speed. Providing clock to the CPU in this manner
leaves the OSC2 (bit 6 of PORTA) available to be used as an 110 pin. We can use
option 101 (EC: external clock) and provide an external clock source to the pin
OSC I and let A6 be used as an I/O pin. We can do the same thing with option 100
while OSC2 provides us with an Osc/4 frequency. This Osc/4 clock can be used to
synchronize all the system activities with the CPU. The most widely used option
is to connect the OSC 1 and OSC2 pins to a crystal (or ceramic) oscillator, as
shown in Figure 8-6. There are four choices for the crystal oscillator option. They
are PPLHS, HS, XT, and LP. The main difference among them is the frequency
range as shown in Table 8-7. The LP (low power) option uses the lowest power
CHAPTER 8: PIC18F HARDWARE CONNECTION & ROM LOADERS
305
while the highest power consumption belongs to the PPLHS (phase lock loop high
speed) option. Notice that the higher the frequency, the more power is dissipated
by the CPU, as discussed in Appendix C. We use the HS (high speed) option for
many of the circuits discussed in this textbook. If we connect pins OSC I-OSC2 to
a 10 MHz crystal oscillator and choose the PPLHS option, then the CPU works on
40 MHz because the PPLHS uses phase lock loop to quadruple the clock source
provided to the CPU. The PLLHS also has the highest power dissipation. Notice
that the RC option (Ill) is the cheapest while the LP option (000) has the lowest
power dissipation.
C2
r - -,i t - - - . - - - - j OSC2
"
30pF
1
OSC/4 - - - - - - j OSC2
0
C1
"
T
1---4~----!-----I
30~F
OSC1
.---------------iGND
Figure 8-6a. OSCI-OSC2 Connection
to Crystal Oscillator
EXTERNAL
OSCILLATOR - - - 1 OSC1
SIGNAL
r-----I GND
J-
Figure 8-6b. OSC Connection to an
External Clock Source
OSCSEN
The OSCSEN bit (D5) of CONFIGIH allows the CPU to switch to an
internal clock source, which has a fixed frequency of 32 kHz. Switching the clock
source from the external oscillator connected to the OSC I and OSC2 pins to an
internal 32 kHz clock source will reduce power dissipation to an absolute minimum in many systems running on battery power. Using this option, along with the
LP option for the crystal frequency, can reduce CPU power consumption to the
nanowatt range. Notice that this low-frequency 32 kHz clock source is in addition
to the external clock source
connected to the OSC 1 and Table 8-7: PIC18F458 Oscillator Frequency
OSC2 pins. This secondary Choices and Capacitor Range
clock source of 32 kHz is Osc choice
Crystal Freq Cl range
C2 range
independent
of
the LP
32 kHz
33 pF
33 pF
OSC I-OSC2 clock source LP
200 kHz
15 pF
IS pF
and will continue to provide XT
47-{)5 pF
200 kHz
47-65 pF
the clock to the CPU in the XT
1 MHz
IS pF
15 pF
event that the crystal fre- XT
4 MHz
15 pF
15 pF
quency goes bad. In this text- HS
4 MHz
15 pF
15 pF
book we disable this second- HS
8 MHz
15-33 pF
15-33 pF
ary clock source and use the HS
20 MHz
15-33 pF
15-33 pF
OSC I-OSC2 oscillator as HS
25 MHz
15-33 pF
15-33 pF
the main clock source.
306
OSCillator frequency and instruction clock cycle
We examined the instruction cycle time in Chapters 2 through 4 and
showed how to create time delay subroutines. In PIC18 microcontrollers, the
instruction cycle time is based on 114 of the clock source provided to the OSC pins.
This is examined once more in Example 8-1.
Example 8-1
Find the instruction cycle time for the PIC18F458 chip with the following crystal
oscillator connected to the OSCI and OSC2 pins. The option for CONFIGlH IS
shown for each crystal speed.
(a) 4 MHz, XT
(b) 10 MHz, HS
(c) 20 MHz, HS
Solution:
All the options in CONFIGlH use 114 of the clock source for the instruction cycle
time.
(a) 4 MHzl4 = 1 MHz and instruction cycle time is 111 MHz = I !1S
(b) 10 MHzl4 = 2.5 MHz and instruction cycle time is 112.5 MHz = 0.4 !1S = 400 ns
(c) 20 MHzl4 = 5 MHz and instruction cycle time is 115 MHz = 0.2 !1S = 200 ns
If we use 10 MHz crystal oscillator speed and choose the HSPLL option (instead of
HS), then the CPU has 40 MHz for the clock source. This means that the instruction
cycle time is 1110 MHz = 0.1 !1S = 100 ns because 40 MHzl4 = 10 MHz.
Table 8-8: CONFIGIH Options Using CONFIG Directive in MPLAB
Oscillator Selection
Low Power
OSC -LP
LP
Crystal
OSC=XT
XT
High Speed
OSC=HS
HS
Resistor/Capacitor
OSC=RC
RC
External Clock
OSC =EC
EC, OSC2 as Clock Out
External Clock
OSC = ECIO
EC, OSC2 as RA6
High Speed Phase
HS-PLL Enabled
OSC = HSPLL
Lock Loop
External Clock
OSC= RCIO
EC, OSC2 as RA6
Oscillator Switch Enable
OSCS - ON
Enabled
OSCS = OFF
Disabled
CHAPTER 8: PIC18F HARDWARE CONNECTION & ROM LOADERS
307
CONFIG directive
Table 8-8 shows the syntax choices for the CONFIG I H byte supported by
the MPLAB. Whenever we load an application into the PICl8 program ROM, we
need to load the CONFIG bytes into the configuration registers as well. This is
done by using the CONFIG directive in the source program. In the source code,
we use the CONFIG directive to set the CONFIG 1H values according to Table 8-8
as shown below:
CONFIG
CONFIG
osc = HS
oscs = OFF
ihigh-speed oscillator
;disable Ose switch
Or, we can combine them into a single statement, as follows:
CONFIG
asc
ases
= HS,
=
OFF
ioscillatoY,
no
Osc switch
CONFIG2L register and reset voltage
CONFIG2L is located at address Ox300002 and is set aside for the purpose
of providing stable voltage and clock frequency during reset. See Figure 8-7. The
most difficult time for a system is during power-up. The CPU needs both a stable
clock source and a stable voltage level to function properly. Two internal timers
help us achieve that: they are called the power-up timer (PWRT) and the oscillator start-up timer (OST). These two internal timers help to reduce the delay associated with the frequency and voltage sources during the power-up process. PWRT
U-o
U-o
U-o
U-O
RlP-1
R/P-1
R/P-1
R/P-1
I BORV1 I BORVO I BOREN IpWRTENI
bit 0
bit 7
bit 7-4
Unimplemented: Read as '0'
bit 3-2
BORV1:BORVO: Brown-out Reset voltage bits
11 = VBOR set to 2.0V
10 = VBOR set to 2.7V
01 = VBOR set to 4.2V
00 = VBOR setto 4.5V
bit 1
BOREN: Brown-out Reset Enable bit
1 = Brown-out Reset enabled
o = Brown-out Reset disabled
bit 0
PWRTEN: Power-up Timer Enable bit
1 = PWRT disabled
o = PWRT enabled
Legend:
R = Readable bit
P = Programmable bit
-n ;;;; Value when device is unprogrammed
U = Unimplemented bit, read as '0'
u = Unchanged from programmed state
Figure 8-7. CONFIG2L Configuration Register for Reset Voltage
308
provides a fixed delay during power-up, which
keeps the CPU in the reset state until the power
supply stabilizes. The OST timer does the same
thing for the crystal oscillator. These two onchip timers eliminate the need for external circuitry for voltage and frequency stabilization
during the power-up. CONFlG2L allows us to
set the voltage and frequency to keep the CPU
in the reset state until both the clock and power
supply are stable. Next, we discuss options for
the bits for this important configuration register.
Table 8-9: CONFIG2L
Selection for PIC18F458
Brown-out Voltage
BORV -45
BORV=42
BORV= 27
BORV -20
4.5
4.2
2.7
2.0
Power-up Timer
PWRT-ON
PWRT=OFF
Enabled
Disabled
Brown-out Reset
BOR=ON
BOR=OFF
Enabled
Disabled
V
V
V
V
BORV1 :BORVO
Occasionally, the power source provided to the Vee (Vdd) pin fluctuates,
causing the CPU to malfunction. The PIC 18 family has a provision for this which
is called brown-out reset voltage. The brown-out reset voltage (BORV) bits in
CONFlG2L allow us to set the minimum voltage for Vdd- Ifit falls below that, the
CPU will go into the reset state and stop all activities. This is needed because the
voltage connected to the V dd (Vee) pins can be set according to the oscillator frequency connected to the OSCI and OSC2 pins. At the high frequency of 40 MHz
with V dd = 5 V, we set BORV to 4.5 V. That means that if V dd falls below the
BORV of 4.5 V, the CPU will go into the reset state and stop execution of programs
without losing any data in registers. For a low-power system with a frequency of
2 MHz and below, we can connect the Vdd to 2 V and set BORV to 1.8 V. In such
a situation if V dd falls below 1.8 V, the CPU will go into the reset state, and when
V dd rises above that level it will come out of reset and continue the program execution. Therefore, the BORVI :BORVO bits of CONFlG2L will be set according to
the Vdd voltage supplied to the Vdd pins and the oscillator frequency connected to
the OSC 1 and OSC2 pins. In this book, we set BORV = 4.5 V because V dd = 5 V
and the crystal oscillator is 10 MHz.
BOREN
This will enable the option BORVI :BORVO discussed above.
PWRTEN
This bit will enable the power-up timer (PWRT). The PWRT provides a
fixed delay during power-up, which keeps the CPU in the reset state until the
power supply is stabilized.
Table 8-9 provides the syntax options for CONFIG2L as supported by the
CHAPTER 8: PIC18F HARDWARE CONNECTION & ROM LOADERS
309
MPLAB. We use the CONFIG directive to set the values according to Table 8-9 as
shown below:
CONFIG BORV~45
CONFIG PWRT ~ ON
CONFIG BOR~ON
;for Vdd ~ 5 V, OSC
;use power-timer
10 MHz
;enable BORV option
Or, we can combine them into a single statement as follows:
CONFIG BORV
~
45, PWRT
ON,
~
BOR~ON
CONFIG2H register and watchdog timer
CONFIG2H is located at address Ox300003 and is set aside for the watchdog timer. In recent years, microcontrollers have come with a piece of hardware
called a watchdog timer. We can use the watchdog timer to force the microcontroller into the known state of reset when the system is hung up or out of control
due to execution of an incorrect sequence of codes. There are many uses for watchdog timers in embedded systems. One application is to use the watchdog timer to
prevent a system from going into an infinite loop due to a software bug. Another
application of the watchdog timer can be to catch events that cause the system to
U-o
U-O
U-O
U-O
RlP-1
RlP-1
RlP-1
RlP-1
! WDTPS2! WDTPS1! WDTPSO! WDTEN !
~7
~o
bit 7-4
Unimplemented: Read as '0'
bit 3-2
WDTPS2:WDTPSO: Watchdog Timer Postscale Select bits
111
~
1:128
110
~
1:64
101 = 1:32
100=1:16
011 = 1:8
010 = 1:4
001 = 1:2
000=1:1
Note: The Watchdog Timer postscale select bits configuration used in the PIC 18FXXX
devices has changed from the configuration used in the PIC 18C)()(X devices.
bit 0
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0= WDT disabled (control is placed on the SWDTEN bit)
Legend:
R = Readable bit
P = Programmable bit
-n ;:;; Value when device is unprogrammed
U = Unimplemented bit, read as '0'
u = Unchanged from programmed state
Figure 8-8. CONFIG2H Configuration Register for Watchdog Timer
310
hang. These problems can happen due to corruption of the program ROM caused
by a power surge, an electrically noisy environment, or inadvertent changes to the
program counter. In such situations, the watchdog timer will force the system into
a known state of reset, from which the system can recover. In some applications,
the system can be put to sleep if there is no activity, thereby saving battery power.
In such applications, one can use the watchdog timer to monitor the keyboard and,
when there is activity on the keyboard, to awaken the system to process the information. Figure 8-8 shows the CONFlG2H register.
WDTEN
This bit will enable the watchdog timer.
WDTPS2:WDTPSO
The watchdog timer pre scalar bits allow programming the WDT for up to
2 minutes. Appendix A discusses SLEEP instruction with the WDT.
For the applications in this textbook,
we tum off the watchdog timer. We can tum
off the watchdog timer in the MPLAB or use
the CONFlG directive in the source code to
set CONFIG2H values according to
Table 8-10, as shown below:
CONFIG WDT
~
Table 8-10: CONFIG2H
Selection for PIC18F458
Watchdog Timer
WDT=ON
WDT=OFF
Enabled
Disabled
OFF
CONFIG4L register and background debugger
CONFlG4L is located at address Ox300006 and is set aside for the purpose
of enabling the background debugger, among other things. See Figure 8-9. Table
8-11 shows the selection options for CONFlG4L. The following are its options.
DEBUG
lfwe connect the PlCl8 system to an
in-circuit debugger, then we lose the RB6 and
RB7 pins of PORTB. By disabling the background debugger option in the CONFIG4L
byte, we can use the RB6 and RB7 pins for
general purpose 1/0.
STVREN
The DO bit is used for stack overflow.
As we discussed in Chapter 3, the PICI8 has
only 31 locations for the stack. By enabling
the DO bit we will cause the system go into a
reset state if stack overflows (or underflows).
LVP
The D2 bit is set aside for the lowvoltage in-circuit serial programming (ICSP)
Table 8-11: CONFIG4L
Selection for PIC18F458
Background Debugger Enable
DEBUG - ON
Enabled
DEBUG = OFF
Disabled
Low-Voltage ICSP
LVP = ON
LVP = OFF
Enabled
Disabled
Stack Overflow Reset
STVR = ON
Enabled
STVR=OFF
Disabled
CHAPTER 8: PIC18F HARDWARE CONNECTION & ROM LOADERS
311
via pin RB5. We can disable it and use the RBS pin as an I/O.
Table 8-11 shows the CONFIG4L byte selection syntax used by the
MPLAB assembler. For the applications in this textbook, we turn off all the
options of debugger, LVP, and stack overflow using the CONFIG directive as follows:
CONFIG DEBUG
=
OFF, LVP
=
OFF, STVR
=
OFF
The first four CONFIG registers are the minimum number of registers that
we need for any PICI8F452 or 458-based system. The rest of the CONFIG registers are dedicated to program and data protection. See the Microchip website.
U-o
RlP-1
1 DEBUG 1
U-o
1- 1
U-o
U-o
RlP-1
LVP
bit 7
bit 7
U-O
1
-
RlP-1
ISTVRENI
bit 0
DEBUG: Background Debugger Enable bit
1 = Background Debugger disabled. RB6 and RB7 configured as general purpose I/O I
0= Background Debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug.
bit 6-3
Unimplemented: Read as '0'
bit 2
LVP: Low-Voltage ICSP Enable bit
1 = Low-Voltage ICSP enabled
0= Low-Voltage ICSP disabled
bit 1
Unimplemented: Read as '0'
bit 0
STVREN: Stack FUll/Underflow Reset Enable bit
1 = Stack Full/Underflow will cause Reset
0= Stack Full/Underflow will not cause Reset
Legend:
R = Readable bit
C = Clearable bit
-n ;;;: Value when device is unprogrammed
U = Unimplemented bit. read as '0'
u :;; Unchanged from programmed state
Figure 8-9. CONFIG4L Coufiguration Register for Background Debugger
CONFIGURATION SETTINGS TO BE NOTED
I. Note that each member of the PIC 18 family has its own values for the configuration
registers. They are provided in a document called "PIC 18 CONFIGURATION SETTINGs ADDENDUM" and can be found at the following web site:
2. Microchip Corp. recommends using the CONFIG directive instead of _CONFIG
for the PICI8 family. Although the _CONFTG directive (notice, _CONFIG has
two undersigns) works with the PICI8, it is not recommended. According to
Microchip, we should not use both of them in the same program.
312
The LIST directive
The LIST directive is another component used in the source code for a
program that we intend to burn into the PIC ROM. The LIST directive informs the
MPLAB assembler about some ofthe options, such as the Intel hex file format, the
radix for data format, the printout of the source code, and so on. Table 8-12 provides some of the major options of the LIST directive used in this textbook.
For an example of how to use the LIST directive, look at the following setting.
LIST
P=18F458, F=INTHX32, MM=OFF, R=HEX, ST=OFF X=OFF
It must be noted that some of the options in Table 8-12 can be set by the
MPLAB assembler itself. To ensure that they are set when we share source files,
however, we use the LIST directive to set them.
Table 8-12: Some LIST Directive Options
B = nnn
C = nnn
F = format
MM = {ON/OFF}
N =nnn
P = type
R = radix
ST = {ON/OFF}
x = {ON/OFF}
Set tab space. (Default is 8.)
Set column width for the print-out. (Default is 132.)
Set the hex file output. The choices are INHX32,
INHX8M, or INHX8S. Default is INHX8M.
(See next section on this.)
Print memory map in list file. (Default is on.)
Set lines per page in the print-out. (Default is 60.)
Set microcontroller type. (Example: P = prc 18F458.)
Set radix, the data format used throughout the source code.
The options are hex, dec, and oct. (Default is hex.)
Print symbol table in list file. (Default is on.)
Tum macro expansion on or off. (Default is on.)
Putting it all together
All the programs we showed in the first seven chapters were intended to be
simulated. In order to create a ready-to-burn program, however, we must provide
all the configuration register bytes, and set the desired options of the LIST directive in the source code before assembling and linking the program. By doing so,
the hex output file provided by the MPLAB assembler can be burned into the program ROM of the PICI8 chip using a ROM burner. We can also send this hex file
to anyone, knowing that it will work because all the configuration registers are
already set. We can use the following skeleton source code for the programs that
we intend to bum into ROM.
CHAPTER 8: PIC18F HARDWARE CONNECTION & ROM LOADERS
313
iskeleton of a PIelS Assembly language program
LIST P=PICI8F458, F=INHX32, MM=OFF,
N=O, ST=OFF, R=HEX
#include PI8F458.INC
CONFIG OSC=HS, OSCS=OFF
;high-speed XTAL as clk src
CONFIG WDT=OFF
idisable watchdog timer
iBrown-out Reset Volt = 4.5 V and Power-up Timer is on
CONFIG BORV=45, PWRT=ON, BOR=ON
ino Background debug, no Reset if stack overflows
;and pin PBS = I/O
CONFIG DEBUG=OFF, LVP=OFF, STVR=OFF
ORG 0
END
As an example, examine the following program. It will toggle all the bits
of PORTS with some delay in between the "on" and "off' states
;Test Program 8-1: Toggling PORTB for the PIC18F458 and
; XTAL = 10 MHz
LIST P=PICI8F458, F=INHX32, N=O, ST=OFF, R=HEX
#include PI8F458.INC
CONFIG OSC = HS, OSCS = OFF
CONFIG WDT = OFF
CONFIG BORV = 45, PWRT = ON, BOR = ON
CONFIG DEBUG = OFF, LVP = OFF, STVR = OFF
Rl
EQU
Ox07
R2
EQU
Ox08
R3
EQU
Ox09
L3
ORG 0
CLRF
MOVLW
MOVWF
COMF
CALL
BRA
TRISB
Ox55
PORTB
PORTB,F
QDELAY
L3
imake Port B an output port
;WREG = s5h
iput ssh on port B pins
;toggle bits of Port B
;quarter of a second delay
; continue
;-----------1/4 SECOND DELAY
QDELAY
MOVLW D12'
MOVWF Rl
Dl
MOVLW D 1250 '
MOVWF R2
D2
MOVLW D'250 I
MOVWF R3
D3
NOP
NOP
DECF R3, F
D3
BNZ
DECF R2, F
D2
BNZ
DECF Rl, F
Dl
BNZ
RETURN
END
314
Setting the CON FIG registers in the MPLAB C18 C compiler
In Chapter 7 we covered C programming of the PICI8F using the CI8 C
compiler. Those programs were intended to be simulated. To create a burnable C
program, we must ensure that the configuration registers are set. One way to do
that is to use #pragma. We can use the following skeleton for C 18 code for the programs that we intend to burn into ROM.
iskeleton of a PIelS
#pragma config
#pragma config
#pragma config
#pragma config
CIS C language program
OSC = HS, OSCS = OFF
BORV = 45, PWRT = ON, BOR = ON
WDT = OFF
DEBUG = OFF, LVP = OFF, STVR = OFF
void main (void)
As an example, examine the following C 18 program. It will toggle all the
bits of PORTB with some delay between the "on" and "off' states.
;Test Program 8-2, Toggling PORTB for the PIC18F458 and
;XTAL = 10 MHz
#pragma config OSC = HS, OSCS = OFF
#pragma config PWRT = OFF, BOR = ON, BORV = 45
#pragma config WDT = OFF
#pragma config DEBUG = OFF, LVP = OFF , STVR = OFF
#include <PIBF458.h>
void msdelay(unsigned int ms);
void main (void)
(
TRISB = 0;
while (1)
(
PORTB = Ox55;
msdelay(500);
PORTB = OxAA;
msdelay(500) ;
((make Port B an output
}
((this delay is for a 10 MHz clock
void msdelay(unsigned int ms)
(
unsigned int Xi
unsigned char Z;
for(x=Ojx<msi x ++)
for(z=Oi z <165iZ++)i
CHAPTER 8: PIC18F HARDWARE CONNECTION & ROM LOADERS
315
Review Questions
I. A given PIC 18F458-based system has a crystal frequency of 16 MHz with HS
selected for the CONFIG I H. What is the instruction cycle time for the CPU?
2. Which address is used for the CONFIG I H register?
3. True or false. Upon power-up, both voltage and frequency are stable instantly.
4. The LP option for the OSC I-OSC2 frequency works for the frequency range
of
to
kHz.
5. Which configuration register is used to disable the watchdog timer? What is its
address?
6. True or false. Upon power-up, the power-up timer keeps the CPU in the reset
state until the voltage source is stable.
7. True or false. The configuration registers are located within the ROM program
address space.
8. True or false. The brown-out reset voltage (BORV) can be set at a lower voltage for a system with low crystal frequencies.
9. True or false. The higher the clock frequency for the system, the lower the
power dissipation.
10. If we have the statement BORV = 42 in a given source code, what is the lowest Vdd voltage level at which the CPU goes into the reset state?
SECTION 8.3: EXPLAINING THE INTEL HEX FILE FOR PIC18
Intel hex file is a widely used file format designed to standardize the loading (transferring) of executable machine code into a ROM chip. Therefore, the
loaders that come with every ROM burner (programmer) support the Intel hex file
format. In many Windows-based assemblers such as MPLAB, the Intel hex file is
produced according to the settings you set. In the PIC MPLAB environment, the
object file is fed into the linker program to produce the Intel hex file. The hex file
is used by the loader of an EPROM programmer such as the PICkit 2 programmer
to transfer (load) the file into the ROM chip. The MPLAB assembler can produce
three types of Intel hex files. They are (a) INHX8M, (b) INHX32, and (c)
INHX8S. See Table 8-13. In this section we will explain each one with some
examples.
Table 8-13: Intel Hex File Formats Produced by MPLAB (See
hUp:l!www.microchip.com)
Format Name
Intel Hex format
Intel Hex 32 format
Intel Split Hex
Format Type
INHX8M
INHX32
INHX8S
File Extension
.hex
.hex
.hxl and .hxh
Max. ROM Address
16-bit address
32-bit address
16-bit address for each
Analyzing the Intel hex (INHX8M) file
We choose the Intel hex type of INHX8M, INHX32, or INHX8S by using
the LIST directive or setting the options in the MPLAB assembler itself. If we do
not choose one, the MPLAB assembler selects INHX32 by default. Next, we will
316
analyze the hex file belonging to the list file for INHX8M. The INHX8M file is
produced by the MPLAB assembler by choosing the INHX8M option in the LIST
directive (or setting the MPLAB assembler). The file has the .hex extension. The
INHX8M is used for PIC chips with program ROM space of up to 64K in size. To
get Intel hex files for chips with more than 64K of program ROM space, we must
use the INHX32 option. Figure 8-10 shows the Intel hex file of INHX8M for the
test program whose list file was given earlier. Notice that we have chosen
INHX8M in the LIST directive. Since the ROM burner (loader) uses the hex file
to download the opcode into ROM, the hex file must provide the following: (1) the
number of bytes of information to be loaded, (2) the information itself, and (3) the
starting address where the information must be placed. Each line of the hex file
consists of six parts as follows:
:BBAAAATTHHHHH. ...... HHHHCC
The following describes each part:
I. ":" Each line starts with a colon.
2. BB, the count byte. This tells the loader how many bytes are in the line. BB
can range from 00 to 16 (lOin hex).
3. AAAA is for the address. This is a 16-bit address for the INHX8M. The loader
places the first byte of data into this memory address.
4. TT is for type. This field is either 00 or 0 I. If it is 00, it means that there are
more lines to come after this line. If it is 0 I, it means that this is the last line
and the loading should stop after this line.
5. HH ...... H is the real information (data or code). There is a maximum of 16
bytes in this part. The loader places this information into successive memory
locations of ROM. Because the PIC 18 chips have 16-bit-wide program ROM
space, the information in this field is presented as low byte followed by the
high byte.
:10000000936A550E816E811E07ECOOFOFCD7020E3C
:10001000076EFAOEOB6EFAOE096E0000000009065F
:OC002000FCE10806F8E10706F4El12001C
:0300010022020ECA
:010006008079
:060008000FCOOFEOOF40E5
:OOOOOOOlFF
Separating the fields,
we get the following:
:BB
:10
:10
:OC
AAAA
0000
0010
0020
TT HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
00 936A550E816E811E07ECOOFOFCD7020E
00 076EFAOE086EFAOE096EOOOOOOOO0906
00 FCE10806F8E10706F4El1200
CC
3C
SF
1C
: 03
:01
:06
:00
0001
0006
0008
0000
00 22020E
00 80
00 OFCOOFEOOF40
01
CA
79
ES
FF
Figure 8-10. Intel Hex File Test Program with the INHX8M Option
CHAPTER 8: PIC18F HARDWARE COl\'NECTION & ROM LOADERS
317
6. CC is a single byte. This last byte is the checksum byte of everything in that
line. The checksum byte is used for error checking. Checksum bytes are discussed in detail in Chapters 6 and 7. Notice that the checksum byte at the end
of each line represents the checksum byte for everything in that line and not
just for the data portion.
Now, compare the data portion of the Intel hex file in Figure 8-10 with the
information under the OB] field of the .1st file in Figure 8-11. Notice that they are
LOC
OBJ
LINE
00003 LIST P=PIC18F458,F=INHX8M,N=0,ST=OFF,R=HEX
00004 #inc1ude P18F45B.INC
22 02 OE 80 OF
CO OF EO OF 40
00005
CONFIG
OSC=HS, OSCS=OFF
00006
00007
00008
00009
CONFIG
CONFIG
CONFIG
BORV=45,PWRT=ON, BOR=ON
WDT=OFF
DEBUG=OFF, LVP=OFF, STVR=OFF
00000007
00000008
00000009
00010 R1 EQU Ox07
00011 R2 EQU OxOB
00012 R3 EQU Ox09
000000
000000
000002
000004
000006
000008
OOOOOC
00014
00015
00016
00017
00018 L3
00019
00020
OOOOOE
OOOOOE
000010
000012
000014
000016
000018
00001A
00001C
00001E
000020
000022
000024
000026
000028
00002A
6A93
OE55
6E81
1E81
EC07 FOOO
D7FC
OE02
6E07
OEFA
6E08
OEFA
6E09
0000
0000
0609
E1FC
0608
E1F8
0607
E1F4
0012
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
ORG 0
CLRF
MOVLW
MOVWF
COMF
CALL
BRA
TRISB
Ox55
PORTB
PORTB,F
QDELAY
L3
;-----------1/4 SECOND DELAY
QDELAY
MQVLW D'2'
MOVWF R1
MOVLW D' 250 I
D1
MOVWF R2
MOVLW D' 250'
D2
MOVWF R3
D3
NOP
NOP
DECF R3, F
BNZ
D3
DECF R2, F
BNZ
D2
DECF R1, F
BNZ
D1
RETURN
END
Figure 8-11. List File for Test Program with the INHX8M Option
(Comments and other lines are deleted for space and simplicity.)
318
identical, as they should be. The extra information is added by the Intel hex file
format. You can run the C language version of the test program and verifY its operation. Your C compiler will provide you both the .1st file and Intel hex file if you
want to explore the Intel hex file concept.
Examine the next three examples to gain insight into the Intel hex file.
Example 8-2
From Figure 8-10, analyze the six parts of line 3.
Solution:
After the colon (:), we have OC, which means that 12 bytes of data are in this line.
0020H is the address at which the data starts. Next, 00 means that this is not the last line
of the record. Then the data, which is 12 bytes, is as follows:
FCE10806F8E10706F4E1l200. Finally, the last byte, lC, is the checksum byte.
Example 8-3
Compare the data portion of the Intel hex file of Figure 8-10 with the opcodes in the list
file of the test program given in Figure 8-11. Do they match?
Solution:
In the first line of Figure 8-10, the data portion starts with 936AH, where the low byte
is followed by the high byte. That means it is 6A93, the opcode for the instruction" CLRF
TRISB", as shown in the list file of Figure 8-11. The last byte of the data in line 3 is
1200, which is the opcode for the "RETURN" instruction in the list file.
Example 8-4
VerifY the checksum byte for line 3 of Figure 8-10. VerifY also that the information is
not corrupted.
Solution:
OC + 20 + FC + E1 + 08 + 06 + FB + E1 + 07 + 06 + F4 + E1 + 12 + 00
= 5E4 in hex. Dropping the carries (5) gives E4H, and its 2's complement is ICH, which
is the last byte of line 4.
If we add all the information in line 4, including the checksum byte, and drop the carries we should get oc + 20 + FC + E1 + 08 + 06 + F8 + E1 + 07 + 06 + F4
+ E1 + 12 + 00 = 600H.
CHAPTER 8: PIC18F HARDWARE CONNECTION & ROM LOADERS
319
Analyzing the Intel hex file of INHX32
For PIC chips with program ROM space
of more than 64K, we must choose the INHX32
OOOOOOOOH
option. Figure 8-13 shows the Intel hex file for
the test program (Figure 8-14) assembled with the
4 Gigabytes
INHX32 option instead of INHX8M. Notice that
f- Space ROM - t-INHX8M is used for chips with a ROM size of
64K or less, while ROM chips with more than
FFFFFFFFH
64K use INHX32. The 32-bit space in the
INHX32 is for the address. That means that the Figure 8-12. ROM Space for
INHX32 can be used for ROM chips with address Chips with 32-bit Addressing
space of I byte to 4 gigabytes, because 232 =
4 gigabytes, as shown in Figure 8-12.
Notice that the MPLAB produces a file with the .hex extension for the
INHX32, just like the INHX8M. The INHX32 is very similar to the INHX8M,
except that the TT field has extra options to accommodate the 32-bit address ofthe
ROM chip. As with the INHX8M, each line of the hex file consists of six parts.
-
:BBAAAATTHHHHH ....... HHHHCC
The following describes each part.
I. ":" Each line starts with a colon.
2. BB, the count byte. This tells the loader how many bytes are in the line. BB
can range from 00 to 16 (lOin hex).
3. AAAA is a A 15-AO address, or all zeros, depending on the TT status.
4. TT is for the record type. This field has four possibilities as follows:
00 = Data record is in field HHHH
01 = End of file record. It means this is the last line and the loading should stop
after this line.
02 = Segment address record.
04 = Linear address record in the HHHH field (A31-AI6 portion of A31-AO
is given in the HHHH field). Notice that if TT = 04, then the HHHH has the
upper addresses of A31-A16 and AAAA = 0000.
5. HH. ..... H is the real information (data, address, or code). There is a maximum
of 16 bytes in this part. The loader places this information into successive
memory locations of ROM. Because the PICI8 chips have 16-bit ROM, the
information in this field is presented as low byte followed by the high byte.
6. CC is a single byte. This last byte is the checksum byte of everything in that
line. The checksum byte is used for error checking. Checksum bytes were discussed in detail in Chapters 6 and 7. Notice that the checksum byte at the end
of each Iine represents the checksum byte for everything in that line and not
just for the data portion.
320
,020000040000FA
,OE000000936A550E816E811E78EC94FOFCD749
,020000040001F9
,1028F000020E076EFAOE086EFAOE096E0000000056
,OE2900000906FCE10806F8E10706F4El120002
,020000040030CA
,0600010022020E830180C3
,06000800FFCOFFEOFF4015
,OOOOOOOIFF
Separating the fields we get the following:
,BB
,02
,DE
,02
,10
,DE
,02
,06
,06
,00
AAAA
0000
0000
0000
28FO
2900
0000
0001
0008
0000
TT
04
00
04
00
00
04
00
00
01
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
0000
936A550E816E811E78EC94FOFCD7
0001
020E076EFAOE086EFAOE096EOOOOOOOO
0906FCE10806F8E10706F4El1200
0030
22020E830180
FFCOFFEOFF40
CC
FA
49
F9
56
02
CA
C3
15
FF
Figure 8-13. Iutel Hex (INHX32) File Test Program as Provided by the Assembler
Example 8-5
From Figure 8-13, analyze the six parts of (a) line 3, and (b) line 4.
Solution:
(a) In line 3, after the colon (:), we have 02 which means that 2 bytes of data are in this
line. The AAAA = 0000 and TT = 04 mean that the upper 16 bits of the address are provided by the HHHH field. That is exactly what we see where the 16-bit address of
000128FOH is given in the HHHH field, which is 0001.
(b) In line 4, after the colon (:), we have IOH (which is 16 in decimal) as the number of
bytes in this line. The AAAA = 28FO is the lower 16-bit address where information will
be burned. Next, 00 means that this is not the last line of the record. Then the data,
which is 16 bytes, is as follows: 020E076EFAOE086EFAOE096EOOOOOOoo. Finally, the
last byte, 56, is the checksum byte.
CHAPTER 8: PIC18F HARDWARE CONNECTION & ROM LOADERS
321
LOC
LINE
00003 LIST P=PIC18F8720,F=INHX32,N=0,ST=OFF,R=HEX
;INTX32 for> 64KB
00004
#inc1ude P18F8720.INC
00001
LIST
01306
LIST
22 02 OE 83
00005
CONFIG OSC=HS, OSCS=OFF
01 80 FF CO FF EO FF 40
00006
CONFIG BORV=45,PWRT=ON, BOR=ON
00007
CONFIG WDT=OFF
00008
CONFIG DEBUG=OFF, LVP=OFF, STVR=OFF
OBJ
00000007
00000008
00000009
000000
000000
000002
000004
000006
000008
OOOOOC
012BFO
0128FO
0128FO
0128F2
0128F4
012BF6
0128F8
0128FA
0128FC
0128FE
012900
012902
012904
012906
012908
01290A
01290C
6A93
OE55
6E81
1E81
EC78 F094
D7FC
OE02
6E07
OEFA
6E08
OEFA
6E09
0000
0000
0609
E1FC
0608
E1F8
0607
E1F4
0012
00010 R1 equ Ox07
00011 R2 equ Ox08
00012 R3 equ Ox09
00014
00015
00016
00017
00018 L3
00019
00020
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
ORG 0
CLRF
MOVLW
MOVWF
COMF
CALL
BRA
TRISB
Ox55
PORTB
PORTB,F
QDELAY
L3
;WREG
55h
;-----------1/4 SECOND DELAY
ORG 128FOH
QDELAY
MOVLW D'2'
MOVWF R1
MOVLW D' 250 I
D1
MOVWF R2
MOVLW D'250 I
D2
MOVWF R3
D3
NOP
NOP
DECF R3, F
BNZ
D3
DECF R2, F
BNZ
D2
DECF R1, F
BNZ
D1
RETURN
END
Figure 8-14. List File for Test Program with INHX32 Option (Notice ORG address
for QDELAY. Some of the comments and lines are deleted for clarity.)
Intel hex split file of INHX8S
The INHX8S option is called the Intel split hex format. When we choose
the INHX8S option in the LIST directive, we get two files: .hxl for the low byte
and and .hxh for the high byte. Because the PIC 18 ROM is 16 bits wide, we have
even addresses for the low byte and odd addresses for the high byte, as shown in
Figure 8-15. The MPLAB assembler gives us this option because in many PICI8
chips with external memory we need to split the memory into odd and even banks
322
to create a 16-bit wide ROM space. Note that ROM chips have pins DO-D7; therefore, their organization is NkxS (e.g., 64kxS). That means we must burn the hex
file into the even-bank ROM and the .hxh file into the ROM with odd addresses.
Note that the .hxl and .hxh formats are the same as the INHXSM with the address
space limited to 64K for each bank. That means that with split ROM, we can have
a maximum of 12SK of ROM with 64K for each bank.
015
08
07
1
3
5
DO
o
2
4
Figure 8-15. The Odd and Even Banks for External Memory of PIC18
Review Questions
1. True or false. The Intel hex file does not use the checksum byte method to
ensure data integrity.
2. The first byte of a line in the Intel hex file represents _ _.
3. The last byte of a line in the Intel hex file represents _ _.
4. In the TT field of an Intel hex file, we have 00. What does it indicate?
5. Find the checksum byte for the following values: 22H, 76H, 5FH, SCH, 99H.
6. In Question 5, add all the values and the checksum byte. What do you get?
7. True or false. In the TT field of the INHX32 file, we have 04, indicating the
record is in the upper 16 bits of the 32-bit address.
SECTION 8.4: PIC18 TRAINER DESIGN AND LOADING
In this section, we discuss the connection for a simple PIC IS-based trainer. We also show various ways of loading a hex file into the PIC microcontroller.
Microchip has skillfully designed their microcontrollers for maximum flexibility
of loading programs. The three primary ways to load a program are:
I. A device burner loads the program into the microcontroller separate from the
system. This is useful on a manufacturing floor where a gang programmer is
used to program many chips at one time. Most mainstream device burners support the PIC families: Advin and EEToois are two of the more popular companies. Microchip supplies programmers for all their products; the PICkit 2 and
PIC START PLUS are just two examples. See Microchip's website for a complete list. You can also build your own device programmer. Doing this will
CHAPTER 8: PIC18F HARDWARE CONNECTION & ROM LOADERS
323
reduce the cost of purchasing a commercial programmer, which is usually
expensive. Building a programmer from scratch is beyond the scope of this
text; check the Internet for sites devoted to this.
The device programming method is straightforward: The chip is programmed before it is inserted into the circuit. Or, the chip can be removed and
reprogrammed if it is in a socket. A ZIF (zero insertion force) socket is even
quicker and less damaging than a standard socket. When removing and reinserting, we must observe ESD (electrostatic discharge) procedures. Although
PIC devices are rugged, there is always a risk when handling them. Using this
method allows all of the device's resources to be utilized in the design. No pins
are shared, nor are internal resources of the chip used as in the other two methods. This allows the embedded designer to use the minimum board space for
the design.
2. An in-circuit serial programmer (ICSP) allows the developer to program and
debug their microcontroller while it is in the system. This is done by two wires
with a system setup to accept this configuration. The Microchip ICD 2 is a
wonderful device for debugging programs. This method also allows the manufacturer to install the devices unprogrammed on the board. Before shipping to
customers, the microcontroller can be programmed with the most recent file.
In-circuit serial programming is excellent for designs that change or
require periodic updating. The ICSP uses two pins, RB7 and RB6. These pins
can be used as 110 after the device is programmed. The designer must make
sure that these pins do not conflict with the programmer. MCLR also needs a
10 kQ pull-up resistor for the ICSP. The ICD 2 also needs Vdd and Gnd. The
designer must bring the pins to a header on the board so that the programmer
can connect to it. Figure 8-16 shows the pin connections. The designer must
weigh the pros and cons of these methods.
Vdd
--
IC D2
CONN ECTION
Vdd
2
11
10K
<
1
1
PGD
5
40
4
39
3
12
PGC
Vss
-
7
Figure 8-16. ICSP Connections
Vdd
S
<
--
MCLR
324
PIC18 F458
(40 PIN DIP)
--
MCLR
RB7/P GD
RB6/PGC
Vss
3. A boot loader is a piece of code burned into the microcontroller's program
ROM. Its purpose is to communicate with the user's board to load the program.
A boot loader can be written to communicate via a serial port, CAN port, USB
port, or even a network connection. A boot loader can also be designed to
debug a system, similar to the ICD. This method of programming is excellent
for the developer who does not always have a device programmer or an ICD
available. Microchip has several application notes on writing boot loaders on
their website. The main drawback of the boot loader is that it does require a
communication port and program code space on the microcontroller. Also, the
boot loader has to be programmed into the device before it can be used, usually by one of the two previous ways.
The boot loader method is ideal for the developer who needs to quickly
program and test code. This method also allows the update of devices in the
field without the need of ICD tools. All one needs is a computer with a port
that is compatible with the board. (The serial port is one of the most commonly used and discussed, but a CAN or USB boot loader can also be written.) This
method also consumes the largest amount of resources. Code space must be
reserved and protected, and external devices are needed to connect and communicate with the PC. Developing projects using this method really helps programmers test their code. For mature designs that do not change, the other two
methods are better suited.
Next, we discuss the issues related to the ROM loader for PICISF-based
systems using chips such as the PICISF45S/45S0 and PICISF452/4520. We will
also provide guidelines for design ofa simple PICIS Trainer. If you decide to wirewrap one of these, make sure that you read Appendix B on wire wrapping.
PIC18F452/458-based Trainer
In systems based on a PIC IS-type microcontroller, you need a ROM burner to burn your program into the microcontroller. For the PIC I SF, the ROM burner can erase the Flash ROM in addition to burning a program into it. In the case of
the PICISC, you also need an EPROM erasure tool because it uses UV-EPROM.
Before burning the PIC ISC, you need to erase its contents, which takes approximately 20 minutes for UV-EPROM. For the PICISF, this is not required because
it has Flash ROM.
PIC18 Flash ROM size
While all PICIS chips share the same features, they come with different
amounts of on-chip ROM. Table 8-14 shows the on-chip ROM size for various
Table 8-14: PIC18 On-chip ROM Size and Address Space
On-chip Code ROM
Code Address Range
(Bytes)
(Hex)
OOOOO-OOFFF
PICI8F2220
4K
PICISF2410
16K
00000-03FFF
32K
00000-07FFF
PIC ISF45S/45S0
PICISF66S0
64K
OOOOO-OFFFF
PICISFS722
12SK
OOOOO-IFFFF
CHAPTER 8: PIC18F HARDWARE CONNECTION & ROM LOADERS
325
PICIS chips. Refer to the web site http://www.microchip.com for further information. Notice that while the PIC ISF2220 comes with 4K of on-chip ROM, and the
PIC ISF241 0 comes with 16K, the PIC ISF458 has 32K of on-chip ROM. Also
notice that the PICISF458 is a substitute for the PICISF452 with extra functions
such as controlled area network (CAN).
Example 8-6
Find the ROM memory address of each of the following PIC chips:
(a) PIC1SF2220 with 4 KB
(b) PICISF2410 with 16 KB
(c) PIC1SF45S/45S0 with 32 KB
Solution:
(a) With 4K of on-chip ROM memory space, we have 4096 bytes (4 x 1024 = 4096).
This maps to address locations of 0000 to OFFFH. Notice that 0 is always the first
location.
(b) With 16K of on-chip ROM memory space, we have 16,384 bytes (16 x 1024 =
16,3S4), which gives 0000--3FFFH.
(c) With 32K we have 32,76S bytes (32 x 1024 = 32,76S). Converting 32,768 to hex,
we get SOOOH; therefore, the memory space is 0000 to 7FFFH.
PIC18 Trainer connection
We selected the PIC1SF458 for a PIC IS-based Trainer because it allows
you to easily wirewrap an inexpensive but powerful trainer to be used at work and
home. Figure S-17 shows the connection for the PICl8F-based system to be used
with the PICkit 2 programmer.
PIC18F452/458
(40 Pin DIP)
1 Vpp
Vpp i·1-Vdd
Vss
PGD
PGC
AUX i..
11 Vdd
32 Vdd
12 Vss
L
31 Vss
40 PGD (RB7)
39 PGC (RB6)
Figure 8-17. PIC18F Connection to PICkit 2 with 6-Pin Header
Note: This connection using the PICkit 2 header applies to all families of PIC microcon-
trollers. The only differences are the pin number and designation.
326
The PlCkit 2 is an inexpensive programmer available from the Microchip
website. The www.MicroDigitaIEd.com web site shows the schematic for PICI8based Trainer connection.
Downloading to the PIC18 Trainer
After we build our PIC 18-based system, we can download the program
into the Trainer using the prCkit 2's programmer utility. See Figure 8-18.
Microchip is continuously updating MPLAB IDE to support PICkit 2 for programming of all PIC microcontrollers.
1;:1 ®
Qevic:e FnIy F'nJgiall',," Iooio !:feIp
PlC18F Device Configurotion- - - - - - - - - - - - - - ,
Configuration WOld
Device
Unsupported Device
PICkit 2 Micrncontrnlle< Programme<
fie
01FF FFFF FFFF FFFF
FFFF FFFF FFFF
User ID·s Ox7F7F7F7F
CheckSum OxFDFE
IUnsupported DeviCe DevID-I• .o
1C~";;(j]
Wr«e
I
Verly
p" P'DgI- _ory
0000
0010
0020
0030
0040
0050
0060
0070
0080
0090
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
OOAO FFFF
OOBO FFFF
ODeD FFFF
I~
Blank?
Ir
Vdd On
/5.D3
S....ce None (empty/era.edl
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
"I
p" Oala EEPROM 1010_,
000
008
010
018
020
028
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF A .
FF -I
FF FF
FF
FF ~I
~
MICROCHIP
Figure 8-18. PICkit 2 Programmer Utility
Test program for the PIC18 in Assembly and C
To test your PIC 18 hardware connection, we can run a simple test in which
all the bits of PORTB toggle continuously with some delay between the "on" and
"oft" states. See Programs 8-3 and 8-3C. Notice in these programs that the time
delay is based on a 10 MHz crystal. In developing your program, you can use the
program shells provided in Figures 8-19 and 8-20.
CHAPTER 8: PIC18F HARDWARE CONNECTION & ROM LOADERS
327
Trainer Test Program in Assembly
iProgram 8-3
LIST P=PIC18F458, F=INHX32, N=O, ST=OFF, R=HEX
#include P18F458.INC
CONFIG OSC = HS, OSCS = OFF
CONFIG WDT = OFF
CONFIG BORV = 45, PWRT = ON, BOR = ON
CONFIG DEBUG = OFF, LVP = OFF, STVR = OFF
R1
R2
R3
L3
EQU
EQU
EQU
Ox07
Ox08
OX09
ORG
CLRF
MOVLW
MOVWF
COMF
CALL
BRA
OOOOH
TRISB
ox55
PORTB
PORTB,F
QDELAY
L3
;note starting address
imake Port B an output port
;WREG = 55h
iPut 55h on port B pins
; toggle bits of Port B
;quarter of a second delay
; continue
;-----------1/4 SECOND DELAY
QDELAY
MOVLW D'2'
MOVWF R1
D1
MOVLW D'250'
MOVWF R2
D2
MOVLW n'250'
MOVWF R3
D3
NOP
NOP
DECF R3, F
BNZ
D3
DECP R2, F
BNZ
D2
DECF R1, F
BNZ
D1
RETURN
END
'#include P18F458.INC
CONFIG OSC = HS, OSCS = OFF
CONFIG WDT = OFF
CONFIG BORV = 45, PWRT = ON, BOR = ON
CONFIG DEBUG = OFF, LVP = OFF, STVR = OFF
ORG
OOOOH
;start of user code space
;begin user code
;end of user code
END
Figure 8-19: Shell of a Simple Assembly Language Program for MPLAB
Notice that the LIST directive is not used because it is one of the default settings in the
MPLAB IDE.
328
Trainer Test Program in C
;Test Program 8-3C: Toggling PORTB for the PIC18F458/4580
; (452/4520) with XTAL = 10 MHz
#pragma
#pragma
#pragma
#pragma
config
config
config
config
OSC = HS, OSCS = OFF
PWRT = OFF, BOR = ON, BORV
WDT = OFF, LVP = OFF
DEBUG = OFF, STVR = OFF
45
#include <PI8F458.h>
void msdelay(unsigned int ms);
void main (void)
TRISB = 0;
while (1)
//make Port B an output
{
PORTB = Ox55;
msdelay(500) ;
PORTB = OxAA;
msdelay(500) ;
}
//this is for a 10 MHz clock
void msdelay(unsigned int ms)
{
unsigned int Xi
unsigned char Zi
for{x=Oix<msix++)
for(z=Ojz<165jz++) i
#pragma
#pragma
#pragma
#pragma
config
config
config
config
OSC = HS, OSCS = OFF
PWRT = OFF, BOR = ON, BORV
WDT = OFF, LVP = OFF
DEBUG = OFF, STVR = OFF
45
#include <P18F458.h>
void main (void)
{
}
Figure 8-20: Shell of a Simple C Language Program for MPLAB
CHAPTER 8: PIC18F HARDWARE CONNECTION & ROM LOADERS
329
Some troubleshooting tips
Running the test program on your PIC ISF45S-based trainer (or PIC ISF452
system) should toggle all the I/O bits with some delay. If your wire-wrapped system does not work, follow these steps to find the problem:
I. With the power off, check your connection for all pins, especially Vdd and GND.
2. Check MCLR (pin I) using an oscilloscope. When the system is powered up,
pin I is HIGH. Upon pressing the momentary switch, it goes LOW. Make sure
the momentary switch is connected properly.
3. Observe the OSCI pin on the oscilloscope while the power is on. You should
see a crude sine wave. This indicates that the crystal oscillator is operating.
4. If all the above steps pass inspection, check the content of the on-chip ROM.
It must be the same as the opcodes provided by the .1st file. Your assembler
produces the .1st file, which lists the opcodes and operands on the left side of
the assembly instructions. This must match exactly the contents of your onchip ROM if the proper steps were taken in burning and loading the program
into the on-chip ROM.
Review Questions
1. Which method(s) to program the PIC microcontroller is/are the best for manfacturing oflarge-scale boards?
2. Which method(s) allow(s) for debugging a system?
3. Which method(s) would allow a small company to develop a prototype and test
an embedded system for a variety of customers?
4. True or false. The PICISC has Flash program ROM.
5. Which pin is used for reset in the PICI8F45S/45S0?
6. What is the status of the reset pin when it is not activated?
7. What kind of ROM is used in the PIC18F45S/45S0 chip?
S. True or false. The PIC IS can download the file into its ROM only if it is in
Intel hex file format.
9. Give two reasons that the PICISF is preferable over PICISC chips.
See the following website for the PIC18 Trainer:
http://www.MicroDigitaIEd.com
330
SUMMARY
This chapter began by describing the function of each pin of the
PIC18F458. The CONFIG registers of the PICI8F458 were discussed. These
CONFIG registers are located at address 30000lH and beyond, which is out of the
program ROM address range. They are burned into the PIC chip along with the
application. We use CONFIG registers to enable features such as low power frequency and watchdog timer. We also explained the Intel hex file formats INHX8M
and INHX32. We examined how the INHX32 format uses the 32-bit address of
ROM while INHX8M files are used for 16-bit addresses. Then the design of the
PICI8-based trainer was shown.
PROBLEMS
SECTION 8.1: PICI8F458/452 PI)',' CONNECTION
1.
2.
3.
4.
5.
The PICI8F458 DIP package is a(n) __-pin package.
Which pins are assigned to Vee and GND?
In the PIC 18F458, how many pins are designated as 110 port pins?
The crystal oscillator is connected to pins __ and __ .
IfPICI8F458 is rated as 40 MHz, what is the maximum frequency that can be
connected to it?
6. Indicate the pin number assigned to MCLR in the DIP package.
7. MCLR stands for _ __
8. The MCLR pin is normally
(LOW, HIGH) and needs a _ __
(LOW, HIGH) signal to be activated.
9. What are the contents of the PC (program counter) upon reset of the
PIC18F458?
10. What are the contents of the SP register upon reset of the PIC 18F458?
II. What are the contents of the WREG register upon reset of the PIC 18F458?
12. What are the contents of the TRIS registers upon reset of the PICl&F458?
13. In PIC18F458, how many pins are set aside for the Vdd?
14. In PIC18F458, how many pins are set aside for the Vss (Gnd)?
15. Which of the OSC pins are shared with the PORTA bit?
16. OSC I and OSC2 are
(input, output) pins.
17. MCLR is an
(input, output) pin.
18. How many pins are designated as PORTA and what are those in the DIP
package?
19. How many pins are designated as PO RTB and what are those in the DIP
package?
20. How many pins are designated as PORTC and what are those in the DIP
package?
21. How many pins are designated as PORTD and what are those in the DIP
package?
CHAPTER 8: PIC18F HARDWARE CONNECTION & ROM LOADERS
331
22. Upon reset, all the bits of ports are configured as _ _ (input, output).
23. In the PICISF45S, which port has only 3 pins?
24. Which I/O pin of the PICISF45S does not have an alternate function and can
be used solely for I/O?
SECTION S.2: PICIS CONFIGURATION REGISTERS
25. True or false. For the PICISF in reset state, the CPU does not execute any
code.
26. True or false. When the system is powered up, the power-up timer (PWRT) and
oscillator start-up timer (OST) keep the PICIS in the reset state until the voltage and frequency are stable.
27. True or false. The power-up timer (PWRT) and oscillator start-up timer (OST)
are components that we must add to the PIC IS externally.
2S. True or false. The watchdog timer is a component that we must add to the
PIC IS externally.
29. True or false. Ifwe do not provide CONFIG values in our source code, PICIS
uses the default values for them.
30. True or false. The CONFIG registers use the same address space as program
ROM.
31. Give the ROM address locations for CONFIG lH, CONFIG2L, CONFlG2H,
and CONFIG4L.
32. The CONFIG registers are
bits wide.
33. Which CONFIG register is used to set the clock frequency for the PICISF45S?
34. Which CONFIG register is used to set the brown-out reset voltage for the
PICISF45S?
35. Which CONFIG register is used to disble the watchdog timer for the
PIClSF45S?
36. If the brown-out reset voltage is set to 4.2 V, what does it mean to the system?
37. Show the CONFIG directive for a PIClSF45S system with the following
options:
(a) OSCI-OSC2 is connected to 20 MHz and it is the only source of the clock
for the system.
(b) The brown-out voltage is set for 4.2 V and the power-up timer is enabled.
(c) No watchdog timer
(d) No overflow on stack, no background debugger, and no LVP
3S. For CONFIG I H, which option for the OSC frequency provides the lowest
power dissipation?
39. Which CONFIG register is used to set the clock source for the PICISF45S?
40. Find the instruction cycle for the following crystal frequencies connected to
OSC I and OSC2. Assume that the HS option is chosen for all of them.
(a) 12 MHz (b) 20 MHz (c) 25 MHz (d) 30 MHz
SECTION S.3: EXPLAINING THE INTEL HEX FILE FOR PICIS
41. True or false. The INHX32 option can be set by MPLAB without using the
LIST directive.
332
42. True or false. The INHX32 option can be used for ROM sizes of more than 64
kilobytes.
43. True or false. The INHX8M option can be used for ROM sizes of more than
64 kilobytes.
44. True or false. The INHX8M option can be used for ROM sizes ofless than 64
kilobytes.
45. True or false. The INHX32 option can be used for ROM of any size.
46. Analyze the six parts ofline I of Figure 8-10.
47. Verify the checksum byte for line I of Figure 8-10. Verify also that the information is not corrupted.
48. Verify the checksum byte for line 2 of Figure 8-13. Verify also that the information is not corrupted.
49. What is the difference between the INHX8M and INHX32 hex files?
50. Analyze the INHX32 Intel hex file in Figure 8-13.
SECTION 8.4: PICI8 TRAINER DESIGN AND LOADING OPTIONS
51. True or false. Using the PICkit2, we must remove the PICI8F chip from the
system and place it into the programmer.
52. True or false. The PICkit2 can only work with Flash chips.
53. Which of the following choices is the cheapest?
(a) MPLAB IC02 (b) PICkit2
54. Write a program to get 8-bit data from PORTB and send it to ports PORTC and
PORTO.
55. Write a program to get 8-bit data from PORTO and send it to ports PORTB and
PORTC.
56. Which pins ofPORTB are PGD (program data) and PGC (program clock)?
57. At what program memory location does the PIC 18F458 wake up upon reset?
What is the implication of that?
58. Write a program to toggle all the bits of PORTB continuously
(a) using AAH and 55H (b) using the COMF instruction.
59. What is the address of the last location of program ROM for the PIC18F458?
60. What is the address of the last location of program ROM for the PIC 18F8722?
61. What is the address of the last location of program ROM for the PIC18F452?
ANSWERS TO REVIEW QUESTIONS
SECTION 8.1: PIC I 8F458/452 PIN CONNECTION
l.
I
2.
000000
000000
LOW
Two pins for Vdd and 2 pins for Gnd
3.
4.
5.
SECTION 8.2: PICI8 CONFIGURATION REGISTERS
l.
2.
16 MHz/4 ~ 4 MHz and 1/4 MHz ~ 250 ns
30000 I hex
CHAPTER 8: PIC18F HARDWARE CONNECTION & ROM LOADERS
333
3.
4.
5.
6.
7.
S.
9.
10.
False
0,200
CONFIG2H, 300003H
True
False
True
False
4.2 V
SECTION S.3: EXPLAINING THE INTEL HEX FILE FOR PICIS
I.
2.
3.
4.
5.
6.
False
The number of bytes of data in the line
The checksum byte of all the bytes in that line
00 means this is not the last line and that more lines of data follow.
22H + 76H + 5FH + SCH + 99H ~ 2ICH. Dropping the carries we have ICH and its 2's complement, which is E4H.
22H + 76H + 5FH + 8CH + 99H + E4H ~ 300H. Dropping the carries we have 00, which
means that the data is not corrupted.
7.
True
SECTION 8.4: PICI8 TRAINER DESIGN AND LOADING OPTIONS
Device burner
2.
3.
4.
5.
6.
7.
S.
9.
In-circuit serial debugger
ICSP
False
Pin I
HIGH
Flash
True
It can be used with ICSP and has a faster development time.
334
CHAPTER 9
PIC18 TIMER
PROGRAMMING
IN ASSEMBLY AND C
OBJECTIVES
Upon completion of this chapter, you will be able to:
»
»
»
»
List the timers of the PIC18 and their associated registers
Describe the various modes of the PIC18 timers
Program the PIC18 timers in Assembly and C to generate time delays
Program the PIC18 counters in Assembly and C as event counters
335
The PICI8 has two to five timers depending on the family member. They
are referred to as Timers 0, I, 2, 3, and 4. They can be used either as timers to generate a time delay or as counters to count events happening outside the microcontroller. In Section 9.1 we see how Timers 0 and I are used to generate time delays.
In Section 9.2 we show how they are used as event counters. In Section 9.3 we use
C language to program the PIC 18 timers. Timers 2 and 3 are discussed in Section
9.4.
SECTION 9.1: PROGRAMMING TIMERS 0 AND 1
Every timer needs a clock pulse to tick. The clock source can be internal or
external. If we use the internal clock source, then 1I4th of the frequency of the
crystal oscillator on the OSCI and OSC2 pins (Fosc/4) is fed into the timer.
Therefore, it is used for time delay generation and for that reason is called a timer.
By choosing the external clock option, we feed pulses through one of the PICI8's
pins: this is called a counter. In this section we discuss the PIC 18 timer and in the
next section we program the timer as a counter.
Basic registers of the timer
Many of the PIC 18 timers are 16 bits wide. Because the PIC 18 has an 8bit architecture, each 16-bit timer is accessed as two separate registers of low byte
(TMRxL) and high byte (TMRxH). Each timer also has the TCON (timer control)
register for setting modes of operation. Next, we discuss each timer separately.
TimerO registers and programming
TimerO can be used as an 8-bit or a 16-bit timer. The 16-bit register of
TimerO is accessed as low byte and high byte, as shown in Figure 9-1. The
low-byte register is called TMROL (TimerO low byte) and the high-byte register is
referred to as TMROH (TimerO high byte). These registers can be accessed like any
other special function registers. For example, the instruction "MOVWF TMROL"
moves the value in WREG into TMROL, the low byte of TimerO. These registers
can also be read like any other register. For example, "MOVFF TMROL, PORTB"
copies TMROL (low byte of TimerO) to PORTB.
r
TMROH
TMROL
__-------JI'~--------~ _--------~I'~--------~
V
Figure 9-1. Timer 0 High and Low Registers
TOCON (TimerO control) register
Each timer has a control register, called TCON, to set the various timer
operation modes. TOCON is an 8-bit register used for control of TimerO. The bits
for TOCON are shown in Figure 9-2.
336
~
II
TMROON
I
T08BIT
I
Toes
I
TOSE
I
PSA
I
TOPS2
I
TOPS1
I
TOPSO
I
TimerO ON and OFF control bit
I = Enable (start) TimerO
o= Stop TimerO
TimerO 8-bit/16-bit selector bit
T08BIT
D6
I = TimerO is configured as an 8-bit timer/counter.
0= TimerO is configured as a 16-bit timer/counter.
TOCS
D5
TimerO clock source select bit
I = External clock from RA4/TOCKI pin
0= Internal clock (Fosc/4 from XTAL oscillator)
TOSE
D4
TimerO source edge select bit
I = Increment on H-to-L transition on TOCKI pin
o = Increment on L-to-H transition on TOCK! pin
PSA
D3
TimerO prescaler assignment bit
I = TimerO clock input bypasses prescaler.
o = TimerO clock input comes from prescaler output.
TOPS2:TOPSO D2DIDO
TimerO prescaler selector
o 0 0 = 1:2 Prescale value (Fosc / 4 / 2)
00 1 = 1:4
Prescale value (Fosc / 4 / 4)
o 1 0 = 1:8 Prescale value (Fosc /4/ 8)
o I 1=1:16 Prescale value (Fosc /4/16)
I 0 0 = 1:32
Prescale value (Fosc /4/ 32)
I 0 I = 1:64
Prescale value (Fosc / 4 / 64)
I 1 0 = 1: 128 Prescale value (Fosc /4/128)
I I I = 1:256 Prescale value (Fosc / 4 / 256)
TMROON
D7
Figure 9-2. TOCON (TimerO Control) Register
Toes (TimerO clock source)
This bit in the TOCON register is used to decide whether the clock source
is internal (Fosc/4) or external. If TOCS = 0, then the Fosc/4 is used as clock
source. In this case, the timers are often used for time delay generation. See
Example 9-1. If TOCS = I, the clock source is external and comes from the
RA4/TOCKl, which is pin 6 on the DIP package ofPIC18l8F4580/4520. When the
clock source comes from an external source, the timer is used as an event counter.
We will discuss that option in the next section. See Example 9-2.
Example 9-1
Find the value for TOCON if we want to program TimerO in 16-bit mode, no prescaler.
Use PICI8's Fosc/4 crystal oscillator for the clock source, increment on positive-edge.
Solution:
TOCON = 0000 1000
16-bit, Fosc/4 clock source, no prescaler, TimerO off
CHAPTER 9: PICIS TIMER PROGRAMMING IN ASSEMBLY AND C
337
Example 9-2
Find the timer's clock frequency and its period for various PICl8-based systems, with
the following crystal frequencies. Assume that no prescaler is used.
(a) 10 MHz
(b) 16 MHz
(c) 4 MHz
Solution:
(a) 1/4 x 10 MHz = 2.5 MHz and
(b) 1/4 x 16 MHz = 4 MHz and T
(c) 1/4 x 4 MHz = 1 MHz and T
1 o~~~~or 1 -I
= 1/2.5 MHz = 0.4
= 1/4 MHz = 0.25 ~s
= 1/1 MHz = 1 ~s
T
~s
+4
NOTE: ]>ICIS TIMERS USE 1/4 OF THE CRYSTAL FREQUENCY, IN ADDITION TO PRESCALER.
TMROIFflag bit
Notice that the TMROIF bit (TimerO interrupt flag) is part of the INTCON
(interrupt control) register. See Figure 9-3. The other options of the INTCON register are discussed in Chapter 11. As we will see, when the timer reaches its maximum value of FFFFH, it rolls over to 0000, and TMROIF is set to I (see Figure
9-4). Chapter 11 shows how we can use TMROIF to cause an interrupt. Next, we
describe the 16-bit mode operation for TimerO.
I
TMROIF
D2
o=
I
=
TMROIF
I
TimerO interrupt overflow flag bit
TimerO did not overflow.
TimerO has overflowed (FFFF to 0000, or FF to 00 in 8-bit mode).
The importance of TMROIF: In 16-bit mode, when TMROH:TMROL overflows from
FFFF to 0000 this flag is raised. In 8-bit, it is raised when the timer goes from FF to 00.
We monitor this flag bit before we reload the TMROH:TMROL registers.
The other bits of this register are discussed in Chapter II.
Figure 9-3. INTCON (Interrupt Control Register) has the TMROIF Flag
XTAL
osdllator
.4
TMROIF goes high
\f1A1en FFFF --'0
TOCT = 0
TMROON
Figure 9-4. TimerO Overflow Flag
338
overflow
I.g
16-bit timer programming
The following are the characteristics and operations of 16-bit mode:
I. It is a 16-bit timer; therefore, it allows values of 0000 to FFFFH to be loaded
into the registers TMROH and TMROL.
2. After TMROH and TMROL are loaded with a 16-bit initial value, the timer
must be started. This is done by "BSF T OCON, TMROON" for TimerO.
3. After the timer is started, it starts to count up. It counts up until it reaches its
limit of FFFFH. When it rolls over from FFFFH to 0000, it sets HIGH a flag
bit called TMROIF (timer interrupt flag, which is part of the INTCON register). This timer flag can be monitored. When this timer flag is raised, one
option would be to stop the timer.
4. After the timer reaches its limit and rolls over, in order to repeat the process,
the registers TMROH and TMROL must be reloaded with the original value,
and the TMROIF flag must be reset to 0 for the next round.
Steps to program TimerO in 16-bit mode
To generate a time delay using the TimerO mode 16, the following steps are
taken:
l. Load the value into the TOCON register indicating which mode (8-bit or 16bit) is to be used and the selected prescaler option.
2. Load register TMROH followed by register TMROL with initial count values.
3. Start the timer with the instruction "BSF T OCON, TMROON".
4. Keep monitoring the timer flag (TMROIF) to see if it is raised. Get out of the
loop when TMROIF becomes high .
5. Stop the timer with the instruction "BCF TOCON, TMR OON".
6. Clear the TMROIF flag for the next round.
7. Go back to Step 2 to load TMROH and TMROL again.
To clarify the above steps, see Example 9-3. To calculate the exact time
delay and the square wave frequency generated on pin PBS, we need to know the
XTAL frequency. See Example 9-4 and Example 9-5.
Notice in Figure 9-5 that we should load TMROH first, and then load
TMROL, because the value for TMROH is kept in a temporary register and written to TMROH when TMROL is loaded. This will prevent any error in counting if
the TMROON flag is set HIGH.
FOSCl4
0
T~
--
TO&
~3
-.
Syncwith
1(2 rcY delay)
PSA
TOPS2:TOPSO
TIlCS
Hobo 1: TOCS, rOSE, PSA, TOPS2:TOPSO (TOCON<5:0».
2: Upon reset, r.:ner 0 II en.tlIed In 8-bII mode, with dock ~ from TOCKJ. mh o P!ftC811.
~
"'ROt.
0-
I
"'RO
I
TMROH
I-- SoI_
ff~~
li;.
I
--"-'.---~--o.ta Bus<1:0>
Figure 9-5. TimerO 16-bit Block Diagram
CHAPTER 9: PICIS TIMER PROGRAMMING IN ASSEMBLY AND C
339
Example 9-3
In the following program, we are creating a square wave of 50% duty cycle (with equal
portions high and low) on the PORTB.S bit. TimerO is used to generate the time delay.
Analyze the program.
BCF
MOVLW
MOVWF
HERE MOVLW
MOVWF
MOVLW
MOVWF
BCF
BTG
BSF
AGAIN BTFSS
BRA
BCF
BRA
TRISB,S
Oxos
TOCON
OxFF
TMROH
OxF2
TMROL
INTCON, TMROIF
PORTB,S
TOCON, TMROON
INTCON, TMROIF
AGAIN
TOCON, TMROON
HERE
as an output
jTimerO,16-bit,int elk/no prescale
iPB5
; load TOCON reg.
,TMROH = FFH, the high byte
,load TimerO high byte
,TMROL = F2H, the low byte
iload TimerO low byte
jclear timer interrupt flag bit
,toggle PBS
jstart TirnerO
jtnonitor TimerO flag until
;it rolls over
; stop TimerO
i10ad TH, TL again
Solution:
In the above program notice the following steps:
I.
2.
3.
4.
5.
6.
TOCON is loaded.
FFF2H is loaded into TMROH-TMROL.
The TimerO interrupt flag is cleared by the "BCF INTCON, TMROIF" instruction.
PORTB.S is toggled for the high and low portions of the pulse.
TimerO is started by the "BSF TOCON, TMROON" instruction.
TimerO counts up with the passing of each clock, which is provided by the crystal
oscillator. As the timer counts up, it goes through the states of FFF3, FFF4, FFFS,
FFF6, FFF7, FFF8, FFF9, FFFA, FFFB, and so on until it reaches FFFFH. One more
clock rolls it to 0, raising the TimerO flag (TMROIF = I). At that point, the
"BTFSS INTCON, TMROIF" instruction bypasses the "BRA AGAIN" instruction.
7. TimerO is stopped by the instruction "BCF TOCON, TMROON", and the process is
repeated.
Notice that to repeat the process, we must reload the TMROL and TMROH registers, and
start the timer again.
8-8-8·······························~8--c5
TMROIF=O
340
TMROIF=O
TMROIF=O
TMROIF=O
TMROIF=j
Example 9-4
In Example 9-3, calculate the amount of time delay generated by the timer. Assume that
XTAL = 10 MHz.
Solution:
The timer works with the Fosc/4 clock; therefore, we have 10 MHz 1 4 = 2.5 MHz as
the timer frequency. As a result, each clock has a period of T = I 12.5 MHz = 0.4 lis. In
other words, TimerO counts up each 0.4 liS resulting in delay = number of counts x 0.4
liS.
The number of counts for the rollover is FFFFH - FFF2H = ODH (13 decimal).
However, we add one to 13 because of the extra clock needed when it rolls over from
FFFF to 0 and raises the TMROIF flag. This gives 14 x 0.4 liS = 5.6 liS for half the pulse.
For the entire period the time delay generated by the timer is T = 2 x 5.6 liS = 11.2 lis.
Example 9-5
Calculate the frequency of the square wave generated on pin PORTB.5.
Solution:
To get a more accurate timing, we need to add clock cycles due to the instructions in the
loop.
Cycles
BCF
MOVLW
MOVWF
BCF
HERE
;
DELAY
AGAIN
TRISB,5
Ox08
TOCON
INTCON, TMROIF
MOVLW OxFF
MOVWF TMROH
MOVLW -D' 48'
MOVWF TMROL
CALL DELAY
PORTB,5
BTG
BRA
HERE
delay using TimerO
TOCON, TMROON
BSF
BTFSS INTCON, TMROIF
BRA
AGAIN
BCF
TOCON, TMROON
INTCON, TMROIF
BCF
RETURN
1
1
1
1
1
1
1
1
1
1
1
1
-..l
13
T = 2 x (48 + 13) x 0.4 liS
=
48.8 liS and F = 20.491 kHz.
CHAPTER 9: PICIS TIMER PROGRAMMING IN ASSEMBLY AND C
341
We can develop a formula for delay calculations using l6-bit mode of the
timer for a crystal frequency of XTAL = 10 MHz. This is given in Figure 9-6. The
scientific calculator in the Accessory directory of Microsoft Windows can help you
to find the TMROH, TMROL values. This calculator supports decimal, hex, and
binary calculations. See Examples 9-6 and 9-7.
(a)
(b)
in hex
(FFFF - YYXX + 1) X 0.4 ~s
where YYXX are the TMROH,
TMROL initial values respectively. Notice that YYXX values are in hex.
in decimal
Convert YYXX values of the
TMROH, TMROL register to decimal to get a NNNNN decimal
number, then (65536 - NNNNN)
x O. 4
~s
Figure 9-6. Timer Delay Calculation for XTAL = 10 MHz with No Prescaler
Example 9-6
Find the delay generated by TimerO in the following code, using both of the methods of
Figure 9-6. Do not include the overhead due to instructions.
BCF
MOVLW
MOVWF
BCF
HERE MOVLW
MOVWF
MOVLW
MOVWF
BSF
AGAIN BTFSS
BRA
BCF
BCF
BTG
BRA
TRISB,S
Ox80
TOCON
INTCON,TMROIF
OxB8
TMROH
Ox3E
TMROL
TOCON, TMROON
INTCON, TMROIF
AGAIN
TOCON, TMROON
INTCON, TMROIF
PORTB,S
HERE
;PBS as an output
i TimerO,16-bit,int elk, no prescale
iclear TimerO interrupt
B8, the high byte
;TMROH
;TMROL
3E, the low byte
istart TimerO
;monitor TirnerO flag until
;it rolls over
istoP TimerO
iclear TimerO interrupt
; toggle PBS
iload TH, TL again
Solution:
(a) (FFFF - B83E + 1) = 47C2H = 18,370 in decimal and 18,370 x 0.4 ~s = 7.348 ms.
(b) Because TMROH: TMROL= B83EH = 47166 (in decimal) we have 65,536 -47,166
= 18,370. This means that the timer counts from B83EH to FFFFH. This plus rolling
over to 0 goes through a total of 18,370 clock cycles, where each clock is 0.4 ~s in
duration. Therefore, we have 18,370 x 0.4 ~s = 7.348 ms as the width of the pulse.
342
Example 9-7
Find the frequency of the square wave generated by the following program ifXTAL =
10 MHz. In your calculation do not include the overhead due to instructions in the loop.
BCF
TRISB,S
MOVLW Ox08
MOVWF TOCON
HERE MOVLW Ox76
MOVWF TMROH
MOVLW Ox34
MOVWF TMROL
BCF
INTCON,TMROIF
CALL DELAY
BTG
PORTB,S
BRA
HERE
----delay using TimerO
DELAY BSF
TOCON,TMROON
AGAIN BTFSS INTCON,TMROIF
BRA
AGAIN
BCF
TOCON,TMROON
RETURN
as an output
jTimerO,16-bit,int elk/no prescale
; load TOCON reg.
;TMROH = 76H, the high byte
;load TimerO high byte
;TMROL = 34H, the low byte
jload TimerO low byte
jclear timer interrupt flag bit
jPBS
;toggle PBS
iload TH, TL again
;start TimerO
;monitor TimerO flag until
jit rolls over
; stop TimerO
Solution:
Because FFFFH - 7634H = 89CBH + I = 89CCH and 89CCH = 35,276 clock count,
35,276 x 0.4 !is = 14.11 ms and frequency = 1/(14.11 ms x 2) = 35.434 Hz. In this calculation, the overhead due to all the instructions in the loop is not included.
Finding values to be loaded into the timer
Assuming that we know the amount of timer delay we need, the question
is how to find the values needed for the TMROH and TMROL registers. To calculate the values to be loaded into the TMROL and TMROH registers, look at
Examples 9-8 and 9-9, where we use a crystal frequency of 10 MHz for the PICI8
system.
Assuming XTAL = 10 MHz and no prescaler we can use the following
steps for finding the TMROH and TMROL registers' values:
I. Divide the desired time delay by 0.4 !is.
2. Perform 65,536 - n, where n is the decimal value we got in Step 1.
3. Convert the result of Step 2 to hex, where yyxx is the initial hex value to be
loaded into the timer's registers.
4. Set TMROL = xx and TMROH = yy.
CHAPTER 9: PICIS TIMER PROGRAMMING IN ASSEMBLY AND C
343
Example 9-8
Assuming that XTAL = 10 MHz, write a program to generate a square wave with a period of 10 ms on pin PORTB.3.
Solution:
For a square wave with T = 10 ms we must have a time delay of 5 ms. Because XTAL
= 10 MHz, the counter counts up every 0.4 ~s. This means that we need 5 ms I 0.4 ~s =
12,500 clocks. 65,536 - 12,500 = 53,036 = CF2CH. Therefore, we have TMROH = CF
and TMROL = 2C.
BCF
TRISB,3
MOVLW OX08
MOVWF TOCON
HERE MOVLW OxCF
MOVWF TMROH
MOVLW Ox2C
MOVWF TMROL
INTCON,TMROIF
BCF
CALL DELAY
PORTB,3
BTG
BRA
HERE
delay using TimerO
DELAY BSF
TOCON,TMROON
AGAIN BTFSS INTCON,TMROIF
AGAIN
BRA
TOCON,TMROON
BCF
RETURN
;PB3 as an output
jTimerO,16-bit,int clk,no prescale
; load TOCON reg
;TMROH = CFH, the high byte
;load TimerO high byte
;TMROL = 2CH, the low byte
iload TimerO low byte
;clear timer interrupt flag bit
;toggle PB3
iload TH, TL again
istart TimerO
;monitor TimerO flag until
jit rolls over
;stop TimerO
Example 9-9
Assuming that XTAL = 10 MHz, modify the program in Example 9-8 to generate a
square wave of2 kHz frequency on pin PORTB.3.
Solution:
Look at the following steps.
(a) T = I IF = I 12kHz = 500 ~s the period of the square wave.
(b) 1/2 of it for the high and low portions ofthe pulse is 250 ~s.
(c) 250 ~s I 0.4 ~s = 625 and 65,536 - 625 = 64,911, which in hex is FD8FH.
(d) TMROL = 8FH and TMROH = FDH, all in hex.
344
Example 9-10
Modify TMROL and TMROH in Example 9-8 to get the largest time delay possible. Find
the delay in ms. In your calculation, exclude the overhead due to the instructions in the
loop.
Solution:
To get the largest delay we make TL and TH both O. This will count up from 0000 to
FFFFH and then rol1 over to zero.
BCF
MOVLW
MOVWF
CLRF
CLRF
BCF
CALL
BTG
BRA
TRISB,3
Ox80
TOCON
HERE
TMROH
TMROL
INTCON,TMROIF
DELAY
PORTB,3
HERE
------~delay using TimerO
DELAY BSF
TOCON,TMROON
AGAIN BTFSS INTCON,TMROIF
BRA
AGAIN
BCF
TOCON,TMROON
RETURN
jPB3 as an output
;TimerO,16-bit,int elk,no prescale
;load TOCON reg.
;TH = TL = 0
iclear timer interrupt flag bit
;toggle PB3
iload TH, TL again
;start TimerO
;monitor TimerO flag until
jit rolls over
istoP TimerO
Making TMROH and TMROL both zero means that the timer will count from 0000 to
FFFFH, and then rol1 over to raise the TMROIF flag. As a result, it goes through a
total of 65,536 states. Therefore, we have delay = (65,536 - 0) x 0.4 IlS = 26.214 ms.
That gives us the smal1est frequency of 1 / (2 x 26.214 ms) = 1 / (52.428 ms) =
19.073 Hz.
Using the Windows calculator to find TH, TL
The scientific calculator in Microsoft Windows is a handy and easy-to-use
tool to find the TMROH, TMROL values. Assume that we would like to find the
TMROH, TMROL values for a time delay that uses 35,000 clocks of 0.4 IlS. The
following steps show the calculation:
I.
2.
3.
4.
5.
Bring up the scientific calculator in MS Windows and select decimal.
Enter 35,000.
Select hex. This converts 35,000 to hex, which is 88B8H.
Select +/- to give -35,000 decimal (7748H).
The lowest two digits (48) of this hex value are for TMROL and the next two
(77) are for TMROH. We ignore all the Fs on the left because our number is
16-bit data.
CHAPTER 9: PIC18 TIMER PROGRAMMING IN ASSEMBLY AND C
345
Prescaler and generating a large time delay
As we have seen in the examples so far, the size of the time delay depends
on two factors, (a) the crystal frequency, and (b) the timer's l6-bit register. Both
of these factors are beyond the control of the PIC 18 programmer. We saw in
Example 9-10 that the largest time delay is achieved by making both TMROH and
TMROL zero. What if that is not enough? We can use the prescaler option in the
TOCON register to increase the delay by reducing the period. The prescaler option
of TOCON allows us to divide the instruction clock by a factor of 2 to 256 as was
shown in Figure 9-2.
As we have seen so far, with no prescaler enabled, the crystal oscillator frequency is divided by 4 (Fosc/4) and then fed into TimerO. If we enable the
prescaler bit in the TOCON register, however, then we can divide the instruction
clock (Fosc/4) further before it is fed into TimerO. The lower 3 bits of the TOCON
register give the options of the number we can divide by. As shown in Figure 9-2,
this number can be 2, 4, 8, 16, 32, 64, and so on. Notice that the lowest number is
2 and the highest number is 256. Examine Examples 9-11 through 9-15 to see how
the prescaler options are programmed.
Example 9-11
Find the value for TOCON if we want to program TimerO in 16-bit mode with a prescaler
of 64 and use internal clock (Fosc/4) for the clock source, positive-edge.
Solution:
From Figure 9-2 we have TOCON
prescaler of 64.
=
0000 0101; 16-bit mode, XTAL clock source,
Example 9-12
Find the timer's clock frequency and its period for various PICl8-based systems, with
the following crystal frequencies. Assume that a prescaler of 1:64 is used.
(a) 10 MHz
(b) 16 MHz
Solution:
XTAL
oscillator
-I
+4
1
-I
+64
-8
(a) 114 x 10 MHz = 2.5 MHz and 1164 x 2.5 MHz = 39062.5 Hz due to 1:64 prescaler
and T = 1I39062.5Hz = 25.6 Ils
(b) 114 x 16 MHz = 4 MHz and 1164 x 4 MHz
1162500 Hz = 16 Ils
346
= 62500 Hz due to prescaler and T =
Example 9-13
Examine the following program and find the time delay in seconds. Exclude the overhead due to the instructions in the loop. Assume XTAL = 10 MHz.
HERE
BCF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
CALL
BTG
TRISB,2
Oxos
TOCON
OxOl
TMROH
OxOS
TMROL
INTCON,TMROIF
DELAY
PORTB,2
BRA
HERE
--------delay using TimerO
DELAY BSF
TOCON,TMROON
AGAIN BTFSS INTCON,TMROIF
BRA
AGAIN
BCF
TOCON,TMROON
RETURN
iPB2
as an output
iTirnerO,16-bit,int clk,prescaler 64
; load TOCON reg.
;TMROH = OlH, the high byte
;load TimerO high byte
;TMROL = OSH, the low byte
i10ad TimerO low byte
iclear timer interrupt flag bit
;toggle PB2
;load THI TL again
;start TimerO
jmonitor TimerO flag until
;it rolls over
; stop TirnerO
Solution:
TMROH:TMROL = 0108H = 264 in decimal and 65,536 - 264 = 65,272. Now 65,272 x
64 x 0.4 ~s = 1.671 seconds, or from Example 9-12, we have 65,272 x 25.6 ~s = 1.671
seconds.
Example 9-14
Assume XTAL= 10 MHz. (a) Find the clock period fed into TimerO if a prescaleroption
of256 is chosen. (b) Show what is the largest time delay we can get using this prescaler
option.
Solution:
(a) 1/4 x 10 MHz ~ 2.5 MHz and 1/256 x 2.5 MHz=9765.625 Hz
due to 1:256 prescaler and T ~ 1/9765.625 Hz ~ 1024 ~s
= 1.024 ros
(b) To get the largest delay, we make TMROL and TMROH both O. Making TMROH and
TMROL both zero means that the timer will count from 0000 to FFFFH, and then
roll over to raise the TMROIF flag. As a result, it goes through a total of 65,536
states. Therefore, we have delay = (65,536 - 0) x 1024 ~s = 67,108,864 ~s =
67.1 08864 seconds.
CHAPTER 9: PIC18 TIMER PROGRAMMING IN ASSEMBLY AND C
347
Example 9-15
Assuming XTAL = 10 MHz, write a program to generate a square wave of 50 Hz frequency on pin PORTB.7. Use TimerO, 16-bit mode, with prescaler = 128.
Solution:
Look at the following steps:
(a) T = I / 50 Hz = 20 ms, the period of the square wave.
(b) 112 of it for the high and low portions of the pulse = 10 ms
(c) 10 ms / O.4l1s / 128 = 195 and 65,536 - 195 = 65,341 in decimal, and in hex it is
FF3DH.
(d) TL = 3D and TH = FF (hex)
BCF
MOVLW
MOVWF
HERE MOVLW
MOVWF
MOVLW
MOVWF
BCF
BTG
BSF
AGAIN BTFSS
BRA
BCF
BRA
TRISB,7
Ox06
TOCON
OxFF
TMROH
Ox3D
TMROL
INTCON, TMROIF
PORTB,7
TOCON, TMROON
INTCON, TMROIF
AGAIN
TOCON, TMROON
HERE
iPS? as an output
;TimerO, 16-bit,int clk,128 prescale
; load TOCON reg.
;TMROH = FF, the high byte
;load Timer O high byte
;TMROL = 3DH, the low byte
;load TimerO low byte
;clear timer interrupt flag bit
;toggle PB7
istart TimerO
jmonitor TimerO flag until
;it rolls over
;stap TimerO
iload TH, TL again
8-bit mode programming of TimerO
TimerO can also be used in 8-bit mode. The 8-bit mode allows only values
of 00 to FFH to be loaded into the timer's register TMRLO. After the timer is started, it starts to count up by incrementing the TMROL register. It counts up until it
reaches its limit of FFH. When it rolls over from FFH to 00, it sets HIGH the
TMROIF. See Figure 9-7.
Data Bus
FOSCJ4
~
lOCKI pin
0
0
~
~ .
POUT
Sync with
Internal
dock.
Programmable
(2 ICY delay)
Prescaler
TOSE
t
3
from lOCK! max.
348
1
nag bit TOIF
TOPS2:TOPSO
Figure 9-7. TimerO 8-bit Block Diagram
IPSOUT I
Set interrupt
PSA
on overflow
TOCS
Note1: TOCS. lOSE. PSA, TOPS2:TOPSO (TOCON<5:0» .
2: U
reset , TImer 0 is enabled in 6-bit mode, with clock in
,/
TMRO
escale.
Steps to program 8-bit mode of TimerO
To generate a time delay using TimerO in 8-bit mode, take the following
steps:
Load the TOCON value register indicating 8-bit mode is selected.
Load the TMROL registers with the initial count value.
Start the timer.
Keep monitoring the timer flag (TMROIF) to see if it is raised. Get out of the
loop when TMROIF becomes HIGH.
5. Stop the timer with the instruction "BCF TDCON, TMRDON".
6. Clear the TMROIF flag for the next round.
7. Go back to Step 2 to load TMROL again.
I.
2.
3.
4.
Notice that when we choose the 8-bit option, only the TMROL register is
used and the TMROH has a zero value during the count up. To clarify the above
steps, see Examples 9-16 and 9-17.
Example 9-16
Assuming that XTAL = 10 MHz, find (a) the frequency of the square wave generated
on pin PORTB.O in the following program, and (b) the smallest frequency achievable in
this program, and the TH value to do that.
BCF
TRISB,D
MOVLW Dx48
MOVWF TOCON
BCF
INTCON,TMRDIF
HERE MOVLW Dx5
MOVWF TMRDL
CALL DELAY
BTG
PORTB,D
BRA
HERE
--------delay using TimerD
DELAY BSF
TDCON,TMRDON
AGAIN BTFSS INTCON,TMRDIF
BRA
AGAIN
BCF
TDCON,TMRDON
BCF
INTCON,TMRDIF
RETURN
iPBO as an output
;TimerO,8-bit,int elk/no prescaler
;load TDCON reg.
iclear timer interrupt flag bit
iTMROL = 5, the low byte
iload TimerO byte
;toggle PBD
;load TL again
jstart TirnerO
;monitor TimerO flag until
;it rolls over
i stop TimerO
jclear TimerO interrupt flag bit
Solution:
(a) Now (256 - 05) = 251 x 0.4 ~s = 100.4 ~s is the high portion of the pulse. Because
it is a 50% duty cycle square wave, the period T is twice that; as a result T = 2 x
100.4 ~s = 200.8 ~s, and the frequency = 4.98 kHz.
(b) To get the smallest frequency, we need the largest T, and that is achieved when
TMROH = 00. In that case, we have T = 2 x 256 x 0.4 ~s = 204.8 ~s and the frequency = 1 / 204.8 ~s = 4,882.8 Hz.
CHAPTER 9: PIClS TIMER PROGRAMMING IN ASSEMBLY AND C
349
Example 9-17
Assume XTAL = 10 MHz. (a) Find the clock period fed into TimerO if the prescaler
option of 256 is chosen. (b) Show what is the largest time delay we can get using this
prescaler option.
Solutiou:
(a) 1/4 X 10 MHz = 2.5 MHz and 1/256 X 2.5 MHz = 9765.625 Hz due
to 1:256 prescaler and T = 1/9765.625 Hz = 1024 ~s
(b) To get the largest delay, we make TMROL = O. Making TMROL zero means that the
timer will count from 00 to FFH, and then roll over to raise the TMROIFF flag. As
a result, it goes through a total of 256 states. Therefore, we have delay = (256 0) x 1024 IlS = 262,144 IlS = 0.262144 second.
Assemblers and negative values
Because the timer is in 8-bit mode, we can let the assembler calculate the
value for TMROH. For example, in "MOVLW, -D' 100''', the assembler will calculate the -100 = 9C and make WREG = 9C in hex. This makes our job easier. See
Examples 9-18 and 9-19.
Example 9-18
Assuming that we are programming the timers for 8-bit mode, find the value (in hex)
loaded into TMROL for each of the following cases.
(a)
MOVLW -D'200'
(b)
MOVLW -D'60'
(c)
MOVLW -D'12'
MovwF TMROL
MOVWF TMROL
MOVWF TMROL
Solution:
You can use the Windows scientific calculator to verify the results provided by the
assembler. In the Windows calculator, select decimal and enter 200. Then select hex,
then +/- to get the negative value. The following is what we get.
350
Decimal
2's complement (TMROL value)
-200
-60
-12
38H
C4H
F4H
Example 9-19
Find (a) the frequency of the square wave generated in the following code, and (b) the
duty cycle of this wave. Assume XTAL = 10 MHz
BCF
TRISB,3
INTCON,TMROIF
BCF
MOVLW Ox48
MOVWF TOCON
HERE MOVLW -D'150'
MOVWF TMROL
BSF
PORTB,3
CALL DELAY
MOVWF TMROL
CALL DELAY
BCF
PORTB, 3
MOVWF TMROL
CALL DELAY
BRA
HERE
-delay using TimerO
DELAY BSF TOCON,TMROON
AGAIN BTFSS INTCON,TMROIF
BRA
AGAIN
BCF
TOCON,TMROON
BCF
INTCON,TMROIF
RETURN
;PB3 as an output
iclear timer interrupt flag bit
;TimerO,S-bit,int clk,no prescaler
; load TOCON reg.
;loading negative value
;load TimerO byte
; PB3 = 1
;reload TimerO byte
; PB3 = 0
jreload TimerO byte
;load TH, TL again
start TimerO
jffionitor TimerD flag until
;it rolls over
istop TimerO
;clear timer interrupt flag bit
i
Solution:
For the TMROL value in 8-bit mode, the conversion is done by the assembler as long as
we enter a negative number. This also makes the calculation easy. Because we are using
150 clocks, we have time for the DELAY subroutine = 150 x 0.4 IlS = 60 IlS. The high
portion of the pulse is twice the size of the low portion (66% duty cycle). Therefore, we
have: T = high portion + low portion = 2 x 60 IlS + 60 IlS = 180 IlS and frequency =
5.555555 kHz.
Another version of this program could be as follows:
BCF
TRISB,3
BCF
INTCON,TMROIF
MOVLW Ox48
MOVWF TOCON
PORTB,3
HERE BSF
CALL DELAY
CALL DELAY
BCF
PORTB,3
CALL DELAY
BRA
HERE
delay using TimerO
DELAY MOVLW -D'150'
MOVWF TMROL
BSF
TOCON,TMROON
AGAIN BTFSS INTCON,TMROIF
AGAIN
BRA
BCF
TOCON,TMROON
BCF
INTCON,TMROIF
RETURN
;PB3 as an output
iclear timer interrupt flag bit
;TimerO,B-bit,int elk/no prescaler
;load TOCON reg.
; PB3 = 1
; PB3 = 0
;load TH, TL again
iloading negative value
;load TimerO byte
istart TimerO
;monitor TimerO flag until
i it rolls over
;stop TimerO
jclear timer interrupt flag bit
CHAPTER 9: PIC18 TIMER PROGRAMMING IN ASSEMBLY AND C
351
Timer1 programming
Timer! is a 16-bit timer, and its 16-bit register is split into two bytes,
referred to as TMRIL (Timerl low byte) and TMRlH (Timerl high byte). See
Figure 9-8. Timerl can be programmed in 16-bit mode only and unlike TimerO, it
does not support 8-bit mode. Timer! also has the Tl CON (Timer I control) register in addition to the TMR!IF (Timerl interrupt flag). The TMR!IF flag bit goes
HIGH when TMRIH:TMRIL overflows from FFFF to 0000. Timerl also has the
prescaler option, but it only supports factors of I: I, I :2, I :4, and I :8. See Figure
9-9 for the Timerl block diagram and Figure 9-10 for Tl CON register options.
The PIRI register contains the TMRlIF flags. See Figure 9-11.
TMR1H
TMR1L
1\
r
1\
V
015 014\ 013\ 012 011 010 \ 09\ 08
07
06\05\04
"
03
02\ 01 \ 00
Figure 9-8. Timerl High and Low Registers
Set TMR 11F flag bit
on Overflow
Y
CCP Special Event Trigger
TMRl
TMR1H
I
GLR
TMR1L
TMR1DN
on/off
T10se
T1SYNC
T10S0fT1CKI
Tl0S1
Tl0SCEN
Enable (1)
Oscillator
Prescaler
1,2,4,8
o
Foscf4
Internal
Clock TMR 1CS
}
.-r
I
T1CKPS1:T1CKPSO
Figure 9-9. Timerl Block Diagram
Examples 9-20 and 9-21 show how to program Timer!. Notice that in
many of the time delay calculations, we have ignored the clocks caused by the
overhead instructions in the loop. To get a more accurate time delay, and hence frequency, you need to include them. If you use a digital scope and you don't get
exactly the same frequency as we have calculated, it is because of the overhead
associated with those instructions.
In this section, we used the PICI8 timer for time delay generation.
However, a more powerful and creative way to use these timers is as event counters. We discuss this use of the counter next.
352
RD16
D7
16-bit read/write enable bit
I = Timer! 16-bit is accessible in one 16-bit operation.
o = Timer! 16-bit is accessible in two 8-bit operations.
D6
Not used
TtCKPS2:TtCKPSO D5 D4 Timer!
o 0 = I: I
o I = 1:2
I 0 = 1:4
I I = 1:8
prescaler selector
Prescale value
Prescale value
Prescale value
Prescale value
TtoSCEN
D3
Timer! oscillator enable bit
I = Timer! oscillator is enabled.
o = Timer! oscillator is shutoff.
TtSYNC
D2
Timer! synchronization (used only when TMR I CS = I for
counter mode to synchronize external clock input)
If TMR I CS = 0 this bit is not used.
TMRICS
DI
Timer! clock source select bit
I = External clock from pin RCO/TI CKI
0= Internal clock (Fosc/4 from XTAL)
TMRtoN
DO
Timerl ON and OFF control bit
I = Enable (start) Timer!
o = Stop Timer!
Figure 9-10. Tt CON (Timer 1 Control) Register
I TMR11F I
TMRlIF
DI
o=
I
=
Timer! Interrupt overflow flag bit
Timer! did not overflow.
Timer! has overflowed (FFFF to 0000).
The importance ofTMRlIF: When TMRIH:TMRIL overflows from FFFF to 0000,
this flag is raised. We monitor this flag hit before we reload the TMRIH:TMRIL registers.
The other bits of this register are discussed in Chapter II.
Figure 9-11. PIRI (Interrupt Control Register 1) Contains the TMRlIF Flag
CHAPTER 9: PIC1S TIMER PROGRAMMING IN ASSEMBLY AND C
353
Example 9-20
Find the frequency of the square wave generated by the following program if XTAL =
10 MHz. In your calculation do not include the overhead due to instructions in the loop.
HERE
;
BCF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
CALL
BTG
BRA
TRISB,S
OxO
T1CON
Ox76
TMR1H
Ox34
TMRlL
PIR1,TMRlIF
DELAY
PORTB,RBS
HERE
;make PBS an output
;Timerl,16-bit,int clk,no prescale
;load TOCON reg
;TMR1H = 76H, the high byte
;load Timerl high byte
;TMR1L = 34H, the low byte
;load Timerl low byte
iclear timer interrupt flag bit
;toggle PBS
iload TH, TL again
delay using Timerl
T1CON,TMR1ON
DELAY BSF
AGAIN BTFSS PIR1, TMRlIF
BRA
AGAIN
PIR1,TMR10N
BCF
RETURN
;start Timerl
;monitor Timerl flag until
i it rolls over
; stop Timerl
Solution:
Because FFFFH - 7634H = 89CBH + I = 89CCH and 89CCH = 35276 clock count
35276 x 0.4 ~s = 14.11 ms and frequency = 1/ (14.11 ms x 2) = 35.434 Hz. In this calculation, the overhead due to all the instructions in the loop is not included. Calculation
is the same as Example 9-7.
Example 9-21
Assuming XTAL = 10 MHz, write a program to generate a square wave of 50 Hz frequency on pin PORTB.5. Use Timer! in 16-bit mode with the maximum prescaler
allowed.
Solution:
Because FFFFH - F3CBH = C34H + 1 = C35H and C35H = 3125 clock count 3125 x
8 x 0.4 ~s = 10 ms and frequency = 1 / (2 x 10 ms) = 50 Hz. In this calculation, the overhead due to all the instructions in the loop is not included.
HERE
i
BCF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
CALL
BTG
BRA
TRISB, S
Ox30
T1CON
OxF3
TMR1H
OxCB
TMR1L
PIR1,TMR1IF
DELAY
PORTB,RBS
HERE
;toggle PBS
;load TH, TL again
delay using Timerl
DELAY BSF
T1CON,TMR10N
AGAIN BTFSS PIR1,TMR1IF
BRA
AGAIN
BCF
PIR1,TMR10N
RETURN
354
;make PBS an output
;Timerl,16-bit,int clk,prescale 1:8
;load T1CON reg
;TMR1H = F3H, the high byte
;load Timerl high byte
;TMR1L = CBH, the low byte
;load Timerl low byte
;clear timer interrupt flag bit
;start Timer1
;monitor Timer1 flag until
;it rolls over
jstop Timerl
Review Questions
I. How many timers do we have in the PIC18F458/4580?
2.
3.
4.
5.
6.
True or false. TimerO can be used only as a 16-bit timer.
True or false. Timer! can be used only as a 16-bit timer.
True or false. The TOCON register is a bit-addressable register.
Indicate the selection made in the instruction "MOV TOCON, oxos".
In 16-bit mode, the counter rolls over when the counter goes from
to
7. In 8-bit mode, the counter rolls over when the counter goes from __ to
8. In the instruction "MOVLW -D' 200' ", find the hex value for WREG.
9. To get a 2-ms delay, what numbers should be loaded into TMROH and TMROL
using 16-bit mode? Assume that XTAL = 10 MHz.
10. To get a 100-)1s delay, what number should be loaded into the TMROL register
using 8-bit mode? Assume that XTAL = 10 MHz.
SECTION 9.2: COUNTER PROGRAMMING
In the last section, we used the timers of the PICI8 to generate time delays.
These timers can also be used as counters to count events happening outside the
PIC 18. The use of the timer as an event counter is covered in this section. When
the timer is used as a timer, the PICI8's crystal is used as the source of the frequency. When it is used as a counter, however, it is a pulse outside the PIC 18 that
increments the TH, TL registers. In counter mode, notice that registers such as
TOCON, TMROH, and TMROL are the same as for the timer discussed in the last
section; they even have the same names.
TOCS bit in TOCON register
Recall from the last section that the TOCS bit (TimerO clock source) in the
TOCON register decides the source of the clock for the timer. If TOCS = 0, the
timer gets pulses from the crystal oscillator connected to the OSC I and OSC2 pins
(Fosc/4). In contrast, when TOCS = I, the timer is used as a counter and gets its
pulses from outside the PIC 18. Therefore, when TOCS = I, the counter counts up
as pulses are fed from pin RA4 (PORTA.4). The pin is called TOCKI (TimerO clock
input). Notice that the pin belongs to Port A. In the case ofTimerO, when TOCS =
I, pin RA4 (PORTA.4) provides the clock pulse and the counter counts up for each
clock pulse coming from that pin. Similarly, for Timer I, when TMRI CS = I, each
clock pulse coming in from pin RCO (PORTC.O) makes the counter count up. See
Example 9-22.
In Example 9-23, we are using Timer! as an event counter that counts up
as clock pulses are fed into pin 3.5. These clock pulses could represent the number of people passing through an entrance, or the number of wheel rotations, or any
other event that can be converted to pulses.
CHAPTER 9: PIC18 TIMER PROGRAMMING IN ASSEMBLY AND C
355
In Example 9-23, the TL data was displayed in binary. In Example 9-24,
the TL registers are converted to ASCII to be displayed on an LCD.
As another example of the application of the timer with CIT = I, we can
feed an external square wave of 60 Hz frequency into the timer. The program will
generate the second, the minute, and the hour out of this input frequency and display the result on an LCD. This will be a nice digital clock, but not a very accurate one.
Example 9-22
Find the value for TOCON if we want to program TimerO as an 8-bit mode counter, no
prescaler. Use an external clock for the clock source and increment on the positive edge.
Solution:
TOCON
= 0 II 0 1000
8-bit, external clock source, no prescaler.
Example 9-23
Assuming that clock pulses are fed into pin TOCK!, write a program for counter 0 in 8bit mode to count the pulses and display the state of the TMROL count on PORTB.
Solution:
BSF
TRISA, RA4
CLRF TRISB
MOVLW Ox68
MOVWF TOCON
HERE MOVLW OxO
MOVWF TMROL
BCF
INTCON,TMROIF
TOCON, TMROON
BSF
AGAIN MOVFF TMROL, PORTB
BTFSSINTCON,TMROIF
BRA AGAIN
BCF
TOCON, TMROON
GOTO HERE
;PORTA.4 as an input for clock
;PORTB as an output
;TimerO, 8-bit,ext clk,no prescale
;load TOCON reg
;TMROL = 0
;load TimerO
;clear timer interrupt flag bit
;start TimerO
;display the count on PORTB
;monitor TimerO flag until
;it rolls over
;stop TimerO
PIC18F458
rPORTBI=
PORTB is connected to 8 LEDs
and input TOCK! to pulse.
356
~RA4
TOCK!
1=
1=
r-
.....
to
LEDs
Using external crystal for Timer1 clock
Timer! has two options when it comes to using the external clock source.
It uses either the clock fed into the Tl CKI pin or the clock from a crystal con-
nected to the TlaSI and Tlasa pins, as shown in Figure 9-9. Generally, a 32-kHz
crystal is connected to the Tl aSI and Tl asa pins and is used for saving power
during SLEEP mode because the SLEEP instruction does not disable Timeri.
Notice that this 32-kHz crystal connected to the Tl aSCI and Tl asa pins is in
addition to the main crystal connected to the aSCI and aSC2 pins. The PICI8
uses the main crystal to execute CPU instruction clock cycles among other things,
and when the CPU goes into SLEEP mode, the main crystal is shut down to save
power. The alternate 32-kHz crystal connected to pins Tl asa and Tl aSI provides clock to TimerI during SLEEP mode, while the main crystal is shut down.
This allows the use of the timer to implement an on-chip RTC (real-time clock).
Chapter 16 shows how to connect an external RTC to the PIC 18. Notice that in
order to use the alternate external clock source for Timer!, we must choose the
external clock source option of TMRI CS = I, in addition to enabling the
TlaSCEN bit (TlaSCEN = 1) in the TlCaN register, as shown in Figure 9-10.
Study Examples 9-23 through 9-27 to see how timers are used as counters.
Before we finish this section, we need to state an important point. You
might think monitoring the TMROIF and TMRI IF flags is a waste of the microcontroller's time. You are right. There is a solution to this: the use of interrupts.
Using interrupts enables us to do other things with the microcontroller. When a
timer Interrupt flag such as TMROIF is raised it will inform us. This important and
powerful feature of the PICI8 is discussed in Chapter II.
CHAPTER 9: PIC18 TIMER PROGRAMMING IN ASSEMBLY AND C
357
Example 9-24
Assume that a I-Hz frequency pulse is connected to input for TimerO (pin TOCKJ).
Write a program to display counter 0 on PORTB, PORTC, and PORTD in decimal. Set
the initial value of TMROL to -60.
Solution:
To display the TMROL count on an LCD, we must convert 8-bit binary data to ASCII.
See Chapter 5 for data conversion.
NUME
EQU
OxOO
QU
EQU
Ox20
RMND L
EQU
Ox30
RMND M
EQU
Ox31
RMND H
EQU
Ox32
MYDEN
EQU D' 10'
BSF
TRISA,RA4
MOVLW Ox68
MOVWF TOCON
HERE MOVLW OxO
MOVWF TMROL
BCF
INTCON,TMROIF
TOCON, TMROON
BSF
AGAIN MOVF TMROL, W
CALL BIN- ASC- CON
BTFSS INTCON,TMROIF
BRA AGAIN
BCF
TOCON, TMROON
GOTO HERE
;RAM loc for NUME
;RAM loc for quotient
;the least significant digit loc
;the middle significant digit lac
;the most significant digit loc
;value for divide by 10
;RA4 as an input
;TimerO,8-bit, ext clk,no prescale
; load TOCON reg
;TMROL = 0
;load TimerO
;clear timer interrupt flag bit
;start TimerO
;save the count in WREG
;monitor TimerO flag until
i it rolls over
;stop TimerO
;converting 8-bit binary to decimal
BIN DEC CON
- MOVFF PORTB, WREG
MOVWF NUME
;load numerator
MOVLWMYDEN
;WREG = 10, the denominator
;clear quotient
CLRF QU
D 1
INCF QU
;inc quotient for every subtract
SUBWFNUME
;subtract WREG from NUME value
BC
D 1
;if positive go back
ADDWFNUME
;once too many, first digit
DECF QU
;once too many for quotient
MOVFF NUME , RMND _ L
;save the first digit
MOVFF QU, NUME
;repeat the process one more time
CLRF QU
;clear QU
D 2
INCF QU
SUBWF NUME
;subtract WREG from NUME value
BC
D- 2
PIC18
ADDWFNUME
ionce too many
DECF QU
PBf-- "
MOVFF NUME, RMND M
;2nd digit
PC=
MOVFF QU, RMND_H;3rd digit
RETURN
PO=
~RA4
I Hz clock
TOCKI
=
-
In order to display the data on LCD, the decimal number must be converted to ASCII.
See Chapter 6.
358
Example 9-25
Assume that a l6-Hz frequency pulse is connected to input for TimerO (pin TOCKI).
Write a program to display the counter values ofTMROH and TMROL on ports Band
D. Set the initial values to O. Use TimerO, l6-bit mode, and positive-edge clock. Show
the program for (a) no prescaler, (b) prescaler of 1:16.
Solution:
(a)
BSF
CLRF
CLRF
MOVLW
MOVWF
HERE MOVLW
MOVWF
MOVLW
MOVWF
BCF
BSF
AGAIN MOVFF
MOVFF
BTFSS
BRA
BCF
GOTO
(b)
BSF
CLRF
CLRF
MOVLW
MOVWF
HERE MOVLW
MOVWF
MOVLW
MOVWF
BCF
BSF
AGAIN MOVFF
MOVFF
BTFSS
BRA
BCF
GOTO
TRISA,RA4
TRISB
TRISD
Ox28
TOCON
OxO
TMROH
OxO
TMROL
INTCON,TMROIF
TOCON,TMROON
TMROH,PORTD
TMROL,PORTB
INTCON,TMROIF
AGAIN
TOCON,TMROON
HERE
TRISA,RA4
TRISB
TRISD
Ox23
TOCON
OxO
TMROH
OxO
TMROL
INTCON,TMROIF
TOCON,TMROON
TMROH,PORTD
TMROL,PORTB
INTCON,TMROIF
AGAIN
TOCON,TMROON
HERE
iRA4 as an input
iPORTB as an output
;PORTD as an output
iTimer O,16-bit,ext elk/no prescale
;load TOCON reg
;TMROH = 0
;load TimerO high byte
;TMROL = 0
iload TirnerO low byte
jclear timer interrupt flag bit
; start TimerO
;display high byte count
;display low byte count
jmonitor TimerO flag until
jit rolls over
iStop TimerO
;RA4 as an input
jPORTB as an output
;PORTD as an output
iTO,16-bit,ext clk,prescale of 1:16
; load TOCON reg
;TMROH = 0
;load TimerO High byte
;TMROL = 0
;load TimerO low byte
jclear timer interrupt flag bit
jstart TimerO
;display high byte count
;display low byte count
;monitor TimerO flag until
;it rolls over
;stop TimerO
PIC18
"
PB-
JLfL.- RA4
16 Hz clock TOCK!
--
=
=
to
LEDs
PO-/
'----'
CHAPTER 9: PIC18 TIMER PROGRAMMING IN ASSEMBLY AND C
359
Example 9-26
Assuming that clock pulses are fed into pin TOCKI and a buzzer is connected to pin
PORTB.I, write a program for counter 0 in 8-bit mode to sound the buzzer every 100
pulses.
Solution:
To sound the buzzer every 100 pulses, we set the initial counter value to -100 (9C in
hex), then the counter counts up until it reaches FE Upon overflow, we can count the
buzzer by toggling the PORTB.1 pin.
BCF
TRISB,l
BSF
TRISA,4
MOVLW Ox68
MOVWF TOCON
MOVLW -D' 100 '
MOVWF TMROL
BCF
INTCON,TMROIF
BSF
TOCON,TMROON
AGAIN BTFSS INTCON, TMROIF
BRA
AGAIN
TOCON,TMROON
BCF
OVER BTG
PORTB,l
CALL DELAY
GOTO OVER
;RB1 as an output
;RA4 as an input for clock-in
;TimerO,8-bit,ext clk,no prescale
; load TOCON reg
;TMROL = 0
;load TimerO
;clear timer interrupt flag bit
;start TimerO
;monitor TimerO flag until
; it rolls over
;stop TimerO
;sound the buzzer
;quarter second delay
; forever
Bit 1 of PORTB is connected to a buzzer and input TOCKI to a pulse.
PIC18F458
PORTB. I 1----1
~RA4
100 Hz TOCKI
360
Buzzer
Example 9-27
Assume that a I-Hz frequency pulse is connected to input for Timer! (pin PORTC.D).
Write a program to display the counter values ofTMRIH and TMRIL on ports Band
D. Set the initial values to D. Use Timer!, 16-bit mode, no prescaler, and positive-edge
clock.
Solution:
BSF
TRISC, RCa
CLRF TRISB
CLRF TRISD
MOVLW Ox02
MOVWF TICON
HERE MOVLW OxO
MOVWF TMRIH
MOVLW OxO
MOVWF TMRIL
BCF
PIRl, TMRlIF
BSF
TICON, TMRION
AGAIN MOVFF TMRIH, PORTD
MOVFF TMRIL, PORTB
BTFSS PIRl, TMRlIF
BRA
AGAIN
BCF
PIRl, TMRION
GOTO HERE
;PCO as an input
;PORTB as an output
;PORTD as an output
;Timerl,16-bit,ext clk,no prescale
;load TOCON reg
;TMRIH = 0, the low byte
;load Timerl high byte
;TMRIL = 0, the low byte
;load Timerl low byte
;clear timer interrupt flag bit
; start Timerl
;display high byte count
;display low byte count
;monitor Timerl flag until
;it rolls over
;stop Timerl
PICIS
-'
rI
rI
L....J
I..--
--.J
I Hz clock TlCKI RCO
PB=
PO=
=
-
to
LEOs
CHAPTER 9: PIC18 TIMER PROGRAMMING IN ASSEMBLY AND C
361
Review Questions
I.
2.
3.
4.
What provides the clock pulses to PICI8 timers ifTOCS = O?
What provides the clock pulses to PICI8 timers ifTOCS = I?
Does the discussion in Section 9.1 apply to timers ifTOCS = I?
To allow RCO to be used as an input for the Timer! clock, what must be done,
and why?
5. Do we have a choice of counting up on the positive or negative edge of the
clock?
SECTION 9.3: PROGRAMMING TIMERS 0 AND 1 IN C
In Chapter 7 we showed some examples ofC programming for the PICI8.
In this section we show C programming for the PICI8 timers. As we saw in the
examples in Chapter 7, the general-purpose registers of the PICI8 are under the
control of the C compiler and are not accessed directly by C statements. All of the
SFRs, however, are accessible directly using C statements. As an example of
accessing the SFRs directly, we saw how to access ports PORTB-PORTD in
Chapter 7. Next, we discuss how to access the PICI8 timers directly using the C 18
C compiler.
Accessing timer registers in C
In CI8 we can access timer registers such as TMROH, TMROL, and
TOCON directly using the PICIBFxxx. h header file. This is shown in Example
9-28. Example 9-28 also shows how to access the TMROON and TMROIF flag
bits. Notice that all the SFR registers are bit-accessible.
Calculating delay length using timers
As we saw in the last two sections, the delay length depends on two factors: (a) the crystal frequency, (b) the prescaler factor. The third factor in the delay
size is the C compiler because various C compilers generate different hex code
sizes. Study Examples 9-28 through 9-33 and verify them using an oscilloscope.
362
Example 9-28
Write a CI8 program to toggle all the bits ofPORTB continuously with some delay. Use
TimerO, 16-bit mode, and no prescaler options to generate the delay.
Solution:
#include <plSf45S0.h>
void TODelay(void) ;
void main (void)
{
TRISB=O;
while (1)
//PORTB output port
//repeat forever
(
PORTB=Ox55;
TODelay();
PORTB=OxAA;
TODelay();
//toggle all bits of Port B
//delay size unknown
//toggle all bits of Port B
void TODelay ()
TOCON=OxOS;
//TimerO, l6-bit mode, no prescaler
TMROH=Ox35 ;
//load THO
//load TLO
TMROL=OxOO;
TOCONbits.TMROON=l;
/ /turn on TO
while(INTCONbits.TMROIF==O);
//wait for TFO to rollover
TOCONbits.TMROON=O;
//turn off TO
INTCONbits.TMROIF=O;
/ /clear TFO
CHAPTER 9: PIC18 TIMER PROGRAMMING IN ASSEMBLY AND C
363
Example 9-29
Write a C18 program to toggle only the PORTB.4 bit continuously every 50 ms. Use
TimerO, 16-bit mode, the 1:4 prescaler to create the delay. Assume XTAL = 10 MHz.
Solution:
#include <p1Bf45BO.h>
void TODelay(void);
#define mybit PORTBbits.RB4
void main(void}
{
TRISBbits.TRISB4~O;
while (1)
{
mybitA=l;
TODelay () ;
//toggle PORTB.4
//TimerO, mode 1 (16-bit)
void TODelay ()
//TimerO, 16-bit mode, 1:4 prescaler
//load THO
TMROL~OxEE;
//load TLO
TOCONbits.TMROON~l;
//turn on TimerO
//wait for TFO to rollover
while(INTCONbits.TMROIF~~O);
TOCONbits.TMROON~O;
//turn off TimerO
INTCONbits.TMROIF~O;
//clear TFO
TOCON~Ox01;
TMROH~OxB5;
FFFFh-85EEH = 7AllH = 31249 + 1 = 31250
Timer delay = 31250 x 4 x 0.4 I!S = 50 ms
364
Example 9-30
Write a CI8 program to generate a frequency of 2 Hz only on pin PORTB.5. Use
TimerO, 8-bit mode to create the delay.
Solution:
#include <p18f4580.h>
void TOM8Delay(void);
#define mybit PORTBbits.RB5
void main(void)
{
unsigned char X,Yi
TRISBbits.TRISB5 = 0;
while (1)
{
A
mybit =l;
for(x=0;x<250;x++)
for(y=0;y<35;y++)
TOM8Delay() ;
//toggle PortB.5
//due to for loop overhead
//we put 35 and not 39
}
void TOM8Delay ()
{
TOCON=Ox45;
//TimerO, 16-bit mode, prescaler 1:64
TMROL=-l;
//load TLO
TOCONbits.TMROON=l;
//turn on TO
while(INTCONbits.TMROIF==O); //wait for TFO to rollover
TOCONbits.TMROON=O;
//turn off TO
INTCONbits.TMROIF=O;
//clear TFO
256 - 255
I
X
=I
64 X 0.4 Ils
25.6 Ils
X
F = I I (2
=
25.6 Ils
250 X 39 = 0.2496 by calculation.
X
0.2496 s) = 1/0.4992 s = 2 Hz
The scope output, however, does not give us this result. This is due to overhead of the
for loop in C. To correct this problem, we put 35 instead of 39.
CHAPTER 9: PICI8 TIMER PROGRAMMING IN ASSEMBLY AND C
365
Example 9-31
Write a CI8 program to generate a frequency of 250 Hz on all bits of PORTC. Use
TimerO, 16-bit mode, and no prescaler to create the frequency. Assume XTAL = 10
MHz.
Solution:
#include <p18f4580.h>
void TODelay(void);
void main (void)
{
unsigned char X;
TRISC=O;
PORTC=Ox55;
while (1)
{
PORTC=-PORTC;
for(x=0;x<20;x++)
TODelay() ;
}
//PORTC output port
//toggle all bits of Port C
}
void TODelay ()
{
TOCON=OxO;
//Timer 0, 16-bit mode, no prescaler
TMROH=OxFF;
//load THO
TMROL=Ox06;
//load TLO
TOCONbits.TMROON=l;
//turn on TO
while (INTCONbits.TMROIF==O) ; //wait for TFO to rollover
TOCONbits.TMROON=O;
//turn off TO
INTCONbits.TMROIF=O;
//clear TFO
FF06H = 65286 in decimal
65536 - 65286 = 250
250 x 0.4 /-IS = 0.1 ms and 20 x 0.1 ms = 2 ms
T = 1 / (2 x 2 ms) = 1 /4 ms = 250 Hz
Another way is:
T = I / 250 Hz = 0.004 second and one half is 0.002 second
0.002 second / 0.4 /-IS = 5000
5000 / 20
366
=
250 because the for loop is set to 20.
Example 9-32
A switch is connected to pin PORTB.7. Write a C18 program to monitor SW and create
the following frequencies on pin PORTB.O:
SW= 0:
500 Hz
SW= 1:
750 Hz
Use TimerO with prescaler for both of them.
Solution:
#include <plBf4580.h>
#define mybit PORTBbits.RBO
#define SW PORTBbits.RB7
void TOPSDelay(unsigned char);
void main(void)
{
TRISBbits.TRISB7=1;//make PB.7 an input
TRISBbits.TRISBO=O;//make PB.O an output
SW=li
while (1)
(
A
mybit =l;
if(SW==O)
TOPSDelay(O)
else
TOPSDelay(l)
//toggle PB.O
//check switch
;
;
void TOPSDelay(unsigned char c)
TOCON=Ox05;
i f (c==O)
//Timer 0, 16-bit mode, prescaler 1:64
{
TMROH=OxFF;
TMROL=OxD9;
//load THO
//load TLO
}
else
TMROH=OxFF;
TMROL=OxE6;
/ /load THO
//load TLO
TOCONbits.TMROON=l;
while(INTCONbits.TMROIF==O);
TOCONbits.TMROON=O;
INTCONbits.TMROIF=O;
FFD9H = 65497
65536-65497 = 39
39 X 64 X 0.4 J.lS = 998 J.ls
1 / (998 J.ls X 2) = 501Hz
//turn on TO
//wait for TFO to rollover
//turn off TO
/ /clear TFO
FFE6H = 65510
65536-65510 = 26
26 X 64 X 0.4 J.ls = 666 J.lS
1/ (666 J.lS X 2) = 751 Hz
Use the scope and modifY TH:TL to get an exact frequency.
CHAPTER 9: PICI8 TIMER PROGRAMMING IN ASSEMBLY AND C
367
Example 9-33
Write a C18 program to create a frequency of2500 Hz on pin PORTB.I. Use Timer! to
create the delay.
Solution:
#include <p18f4580.h>
void T1Delay(void);
#define mybit PORTBbits.RBl
void main(void)
{
TRISBbits.TRISB1
while (1)
O',
{
mybit .... =li
T1Delay() ;
//toggle PB.1
void T1Delay ()
{
T1CON=OxO;
//Timer1, 16-bit mode, no prescaler
TMR1H=OxFE;
//load TH1
TMRIL=OxOC;
//load TL1
T1CONbits.TMR10N=1;
/ /turn on T1
while (PIR1bits.TMR1IF==O) ;
//wait for TFl to rollover
T1CONbits.TMR10N=O;
/ /turn off T1
PIR1bits.TMR1IF=O;
//clear TF1
}
1 / 2500 Hz = 400
400
~s
/ 2 = 200
200
~s
/ 0.4
~s =
~s
~s
500
65536 - 500 = 65036 = FEOCH
C programming of Timers 0 and 1 as counters
In Section 9.2 we showed how to use Timers 0 and 1 as event counters.
Timers can be used as counters if we provide pulses from outside the chip instead
of using the frequency of the crystal oscillator as the clock source. By feeding
pulses to the TOCKI (RA4) and TICKI (RCO) pins, we tum TimerO and Timer!
into Counter 0 and Counter 1, respectively. Study Examples 9-34 through 9-37 to
see how Timers 0 and 1 are programmed as counters using C language.
368
Example 9-34
Assume that a I-Hz external clock is being fed into pin TOCK! (RA4). Write a CI8 program for CounterO in 8-bit mode to count up and display the state of the TMROL count
on PORTB. Start the count at OH.
Solution:
#include <p18f4580.h>
void main (void)
{
TRISAbits.TRISA4=1;//make RA4/TOCKI an input
TRISB=O;
TOCON=Ox68;
//Counter 0, 8-bit mode, no prescaler
TMROL=O;
//set count to 0
while (1)
//repeat forever
{
do
{
TOCONbits.TMROON=l;
PORTB=TMROL;
/ /turn on TO
//place value on pins
}
while(INTCONbits.TMROIF==O);
TOCONbits.TMROON=O;
INTCONbits.TMROIF=O;
//wait for TFO to rollover
//turn off TO
//clear TFO
PIC18
PORTB is connected to 8 LEDs.
TOCK! (RA4) is connected to a
I-Hz external clock.
"
PB=
~LrLRA4
=
to
LEDs
L..-_....J=/
1 Hz
TOCKI
CHAPTER 9: PIC18 TIMER PROGRAMMING IN ASSEMBLY AND C
369
Example 9-35
Assume that a I-Hz external clock is being fed into pin TOCKI (RA4). Write a C program for Counter 0 in mode 1 (16-bit) to count the pulses and display the TMROH and
TMROL registers on PORTD and PORTB, respectively.
Solution:
#include <p18f4580.h>
void main(void)
{
TRISAbits.TRISA4=1;
//make RA4 an input for TOCKI
TRISB=O;
//PORTB output port
TRISD=O;
//PORTD output port
TOCON=Ox25;
/ /TimerO, 16-bit mode, prescaler 1:64
TMROH=O;
//set count to 0
TMROL=O;
//set count to 0
while (1)
//repeat forever
{
do
{
TOCONbits.TMROON=l;
PORTB=TMROL;
PORTD=TMROH;
//turn on TO
//
//place value on pins
}
while (INTCONbits.TMROIF==O) ii/wait for rollover
TOCONbits.TMROON=O;
INTCONbits.TMROIF=O;
//turn off TO
/ /clear TFO
}
PICIS
f=
PB and
POlo
LEOs
I-I--
f=
~
1 Hz clock
370
TOCKI
RA4
f=
/'
Example 9-36
Assume that a 64-Hz external clock is being fed into pin TOCKl (RA4). Write a C program for Counter 0 in 8-bit mode to display the count in ASCII. The 8-bit binary count
must be converted to ASCII. Display the ASCII digits (in binary) on PORTB, PORTC,
and PORTD, where PORTB has the least significant digit. Set the initial value of
TMROLto O.
Solution:
To display the TMROL count, we must convert 8-bit binary data to ASCII. See Chapter
7 for data conversion. The ASCII values will be shown in binary. For example, '9' will
show as 00 III 00 I on the ports.
#include <p18f4580.h>
void BinToASCII(unsigned char);
void main ()
{
unsigned char value;
TRISAbits.TRISA4=1;
//make RA4 an input
TRISB=O;
//make PORTB an output
//make PORTC an output
TRISC=O;
//make PORTD an output
TRISD=O;
TMROL=O;
TOCON=Ox65;
//Counter 0, 8-bit mode, prescaler 1:64
while (1)
{
do
(
TOCONbits.TMROON=l;
value=TMROL;
BinToASCII(value) ;
//turn on TO
}
while(INTCONbits.TMROIF==O); //wait for TFO to rollover
TOCONbits.TMROON=O;
//turn off TO
INTCONbits.TMROIF=O;
//clear TFO
}
void BinToASCII(unsigned char value)
//see Chapter 7
{
unsigned char x,dl,d2,d3;
x=value/l0;
dl=value%lO;
d2=x%10;
d3=x/l0;
PORTB=Ox30
dl;
PORTC=Ox30
d2;
PORTD= Ox3 0
d3 ;
CHAPTER 9: PIC18 TIMER PROGRAMMING IN ASSEMBLY AND C
371
Example 9-37
Assume that a 60-Hz external clock is being fed into pin TOCKI (RA4). Write a C program for Counter 0 in 8-bit mode to display the seconds and minutes on PORTB and
PORTO, respectively.
Solution:
#include <p18f4580.h>
void ToTime(unsigned char);
void main ()
{
unsigned char seCi
TRISB=TRISD=O;
TOCON=Ox68;
TMROL=-60;
while (1)
//PORTB,D outputs
//Timer 0, no prescaler
//sec = 60 pulses
{
do
{
TOCONbits.TMROON=l;
sec=TMROL;
ToTime(sec) ;
//turn on TO
}
while (INTCONbits.TMROIF==O) ; //wait for TFO to rollover
TOCONbits.TMROON=O;
//turn off TO
INTCONbits.TMROIF=O;
//clear TFO
}
}
void ToTime(unsigned char value)
{
unsigned char sec, min;
min = value / 60;
sec = value % 60;
PORTB = sec;
PORTD = min;
PIC18
I--
JL..rl- RA4
60 Hz clock
To
PB~
~
~
PB and
PO to
LEOs
PO I--
By using 60 Hz, we can generate seconds, minutes, and hours.
372
SECTION 9.4: PROGRAMMING TIMERS 2 AND 3
In this section we examine Timers 2 and 3 of the PIC 18 family and show
how to program them in both Assembly and C.
Timer2 programming
Timer2 is an 8-bit timer. The 8-bit register of Timer2 is called TMR2.
Timer2 also has an 8-bit register called the period register (PR2). We can set the
PR2 register to a fixed value and Timer2 will increment from 00 until it matches
the value in PR2. At that point, the equal signal will raise the TMR2IF flag and
reset TMR2 to 00. The clock source for Timer2 is Fosc/4 with the options of both
prescaler and postscaler, as shown in Figure 9-12. Notice from Figure 9-12 that
there is no external clock source for Timer2. In other words, it cannot be used as
a counter. Examine the next few examples to learn the programming syntax for
Timer2. See Figures 9-12 and 9-13.
Sets flag
bitTMR21F
TMR2 1
output ( )
Fosc/4
--1
Prescaler
1:1,1:4,1:16
H
}2
T2CKPS 1:T2CKPSO
I
TMR2 reg
~
Comparator
A
L
Reset
I
I
I
Postscaler
EQ
II
I
PR2 reg
I
1:1 to 1:16
r--
}4
TOUTPS3:TOUTPSO
Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock.
Figure 9-12 Timer2 Block Diagram
I TMR2IF I TMRllF I
TMR2IF
Timer2 Interrupt overflow flag bit
o = TMR2 value is not equal to PR2 register.
I
=
TMR2 value is equal to PR2 register.
The other bits of this register are discussed in Chapter II.
The location of TMRxlF in the PlR register can vary in future products.
Figure 9-13. PIRI (Peripheral Interrupt Flag Register 1) Contains TMR2IF Flag
CHAPTER 9: PIC18 TIMER PROGRAMMING IN ASSEMBLY AND C
373
I TOUTPS31 TOUTPS21 TOUTPSII TOUTPSO I TMR20N I T2CKPSIIT2CKPSOI
D7
TOUTPS3:TOUTPSO D6--D3
00 0 0 = I: I
00 0 I = 1:2
00 I 0 = 1:3
00 I I = 1:4
II I 0 = I: 15
II I I = I: 16
TMR20N
Not used
Timer2 Output Postcale Select bits
Postscale value
Postscale value
Postscale value
Postscale value
Postscale value
Postscale value
D2
Timer2 ON and OFF Control bit
I = Enable (Start) Timer2
o = Stop Timer2
T2CKPS1:T2CKPSO D I-DO Timer2 Clock Prescale Select bits
o 0 = Prescale is I
o I = Prescale is 4
I x = Prescale is 16
Figure 9-14. T2CON (Timer2 Control) Register
Example 9-38
Assuming that XTAL = 10 MHz, write a program to turn on pin PORTB4 when TMR2
reaches value 100 (decimal).
Solution:
Because XTAL = 10 MHz, TMR2 counts up every 0.4 !is. Therefore, when you have
TMR2H = PR2 = 100, PORTB4 will be turned on.
BCF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BSF
AGAIN BTFSS
BRA
BSF
BCF
HERE BRA
374
TRISB,4
PORTB,4
OxO
T2CON
OxO
TMR2
DIlDO'
PR2
PIR1,TMR2IF
T2CON,TMR20N
PIR1,TMR2IF
AGAIN
PORTB,4
T2CON,TMR20N
HERE
imake PORTB4 an output
;turn off PORTB4
iTimer2, no prescale or postscale
;load T2CON reg
;TMR2 = 0
;load Timer2
;PR2 = 100, the period register
;load PR2
iclear timer interrupt flag
istart Timer2
;monitor Timer2 flag
; turn on PORTB4
;stop Timer2
Example 9-39
Using the prescaler and postscaler, find the longest time delay that we can create using
Timer2. Assume that XTAL = 10 MHz.
Solution:
We can create the longest time delay by making PR2 = 255. When TMR2 reaches value
255 (decimal), it toggles a pin.
BCF
TRISB,4
BCF
PORTB,4
MOVLW B' 01111011'
MOVWF T2CON
MOVLW OxO
MOVWF TMR2
HERE MOVLW D' 255'
MOVWF PR2
BCF
PIR1,TMR2IF
BSF
T2CON, TMR20N
AGAIN BTFSS PIR1, TMR2IF
BRA AGAIN
BTG
PORTB,4
BCF
T2CON, TMR20N
BRA HERE
;make PORTB4 an output
;turn off PORTB4
; Timer2, prescale = 16,postscale = 16
;load T2CON reg
;TMR2 = 0
;load Timer2
;PR2 = 255, the period register
;load PR2
;clear timer interrupt flag bit
i start Timer2
;monitor Timer2 flag
; turn on PORTB4
; stop Timer2
Because XTAL = 10 MHz, TMR2 counts up every 0.4 I1S. Therefore, when you have
TMR2H = PR2 = 255, RB4 will be turned on and off every 52 ms because 255 x 0.4 I1S
x 16 x 16 = 26.112 ms.
Example 9-40
Assuming that XTAL = 10 MHz, write a CI8 program to turn on pin PORTB4 when
TMR2 reaches value 100. This is a repeat of Example 9-13 in C18.
Solution:
#include <p18f4580.h>
#define mybit PORTBbits.RB4
void main (void)
(
TRISBbits.TRISB4=0;
//PORTB4 as output
T2CON=OxO;
//Timer2, no prescaler/postscaler
TMR2=OxOO;
//TMR2 = 0
mybit=O;
/ /PB.4 = 0
PR2=100;
//load period register 2
T2CONbits.TMR20N=1;
//turn on TO
while(PIR1bits.TMR2IF==0); //wait for TMR2IF to be raised
mybit=l;
//PB.4 = 0
T2CONbits.TMR20N=0;
//turn off T2
PIR1bits.TMR2IF=0;
//clear TFO
while (1) ;
//stay here
}
CHAPTER 9: PIC18 TIMER PROGRAMMING IN ASSEMBLY AND C
375
Example 9-41
Using the prescaler and postscaler, find the longest time delay that we can create using
Timer2. Assume that XTAL = 10 MHz. This is a repeat of Example 9-39 in C18.
Solution:
#include <p1Bf45BO.h>
#define mybit PORTBbits.RB4
void main (void)
{
TRISBbits.TRISB4=O;
T2CON=Ox7B;
//Timer2, prescaler = 16,postscaler
TMR2=OxOO;
/ /TMR2 = 0
while (1)
16
{
PR2=255;
T2CONbits.TMR20N=1;
while (PIR1bits.TMR2IF==O) ;
mybit=-mybit;
T2CONbits.TMR20N=O;
PIR1bits.TMR2IF=O;
//load period register 2
/ /turn on T2
//wait for TMR2IF to be raised
//toggle PORTB4
/ /turn off T2
//clear TFO
}
Because XTAL = 10 MHz, TMR2 counts up every 0.4 ~s. Therefore, when TMR2H =
PR2 = 255, PORTB4 will be turned on and off every 52 ms because 255 x 0.4 ~s x 16
x 16 = 26.112 ms.
Timer3 Programming
Timer3 is a 16-bit timer that can be used as a timer or counter. Its 16-bit
register is split into two bytes referred to as TMR3L and TMR3H. (See Figure
9-17.) Timer3 can be programmed in 16-bit mode only and does not support 8-bit
mode. We select various options of Timer3 using the T3CON (Timer3 Control)
register, as shown in Figure 9-15. Timer3 has the prescaler options of I: I, I :2, 1:4,
and 1:8, as shown in Figure 9-15. Figure 9-15 also shows the bits related to the
CCP (compare/capture pulse-width-modulation) feature of the PIC 18. CCP is a
widely used feature of the PIC 18, and we will discuss it in Chapters IS and 17. In
Chapter IS, we will see how to use the CCP feature along with the interrupt to
measure the pulse width. Pulse width modulation (PWM) is an important concept
used in DC motor control. We will examine it in detail in Chapter 17. Because
Timer3 is a 16-bit timer, the TMR3IF flag bit goes HIGH when TMR3H:TMR3L
overflows from FFFF to 0000. Tbe TMR3IF (Timer3 Interrupt flag) is part of the
PIR2 register, as shown in Figure 9-16.
Examine the next few examples to learn the programming syntax for
Timer3.
376
IRD161 T3CCP21 T3CKPSll T3CKPSO I T3CCPl IT3SYNC I TMR3CS ITMR30N I
RD16
D7
16-bit read/write enable bit
1= Timer3 16-bit is accessible in one 16-bit operation.
o = Timer3 16-bit is accessible in two 8-bit operations.
T3CCP2:T3CCPl
06 03 Timer3 and Timer! to CPPx Enable bits
o 0 Timer! is the clock source for compare/capture of the CCP module.
o I Timer3 is the clock source for compare/capture of the CCP2.
Timer! is the clock source for compare/capture of the CCPI.
I x
Timer3 is the clock source for compare/capture of the CCP module.
T3CKPS1:T3CKPSO 0504 Timer3 Input Clock Prescaler Selector
o 0 = I: I
Prescale value
o I = 1:2 Prescale value
o = 1:4
Prescale value
I I = 1:8
Prescale value
TtSYNC
02
TMR3CS
01
TMR30N
00
Timer3 external clock input synchronization control bit
Used only when TMR3CS = I and clock comes from an
external source. IfTMR3CS = 0, this bit is not used.
I = 00 not synchronize external clock input
o = Synchronize external clock input
Timer3 clock source select bit
I = External clock from pin Tl OSI or Tl CKI
0= Internal clock (Fosc/4)
Timer3 On and Off control bit
I = Enable (start) Timer!
o = Stop Timer!
Figure 9-15. T3CON (Timer3 Control) Register
I TMR3IF I
TMR3IF
Timer3 interrupt overflow flag bit
o = Timer3 did not overflow.
I = Timer3 has overflowed (FFFF to 0000).
The importance ofTMR3IF: In 16-bit mode, when TMR3H:TMR3L overflows from
FFFF to 0000, this flag is raised.
The location of TMRxIF in the PIR register can vary in future products.
Figure 9-16. PIR2 (Peripheral Interrupt Flag Register 2) Contains the TMR3IF
Flag
CHAPTER 9: PIC18 TIMER PROGRAMMING IN ASSEMBLY AND C
377
Set TMR31F flag bit
on Overflow
Y
CCP Special Trigger
'----.J-- T3CCPx
o
TMR3
TMR3H
I
CLR
TMR3L
TMR30N
on/off
TT1p----i
Fosc/4
Internal
Clock
Prescaler
1,2,4,8
o
,h
J'
I
T3CKPS1:T3CKPSO
TMR3CS
Figure 9-17. Timer3 Block Diagram
Example 9-42
Find the frequency of the square wave generated by the following program if XTAL =
10 MHz, In your calculation do not include overhead due to instructions in the loop.
BCF
TRISB, S
; PBS as an output
MOVLW OxO
;Timer3, 16-bit, int clk,no prescale
MOVWF T3CON
; load T3CON reg
HERE MOVLW Ox76
;TMR3H = 76H, the high byte
MOVWF TMR3H
; load Timer3 high byte
MOVLW Ox34
;TMR3L = 34H, the low byte
MOVWF TMR3L
; load Timer3 low byte
BCF
PIR2,TMR3IF
;clear timer interrupt flag bit
CALL DELAY
PORTB, RBS
;toggle PBS
BTG
BRA
HERE
;load TH, TL again
- - - - - - d e l a y using Timer3
DELAY BSF
T3CON, TMR30N
; start Timer3
AGAIN BTFSS PIR2, TMR3 IF
;monitor Timer3 flag until
BRA
AGAIN
iit rolls over
BCF
T3 CON, TMR30N
;stop Timer3
RETURN
Solution:
Because FFFFH - 7634H = 89CBH + I = 89CCH and 89CCH = 35276 clock count,
35276 x 0.4 j.lS= 14.11 ms and frequency = 1/(2 x 14.11 ms)= I 128.22 ms = 35.434
Hz, In this calculation, the overhead due to all the instructions in the loop is not included. Notice that the calculation is the same as in Example 9-20.
378
Example 9-43
Assume XTAL = 10 MHz, write a program to generate a square wave of 50 Hz frequency on pin PORTB5. Use Timer3, 16-bit mode, with the maximum prescaler
allowed.
Solution:
Because FFFFH - 9E58H = 61A7H + I = 61A8H and 61A8H = 25,000 clock count,
25000 x 0.4 liS = I ms and frequency = 112 (I ms) = 50 Hz. In this calculation, the overhead due to all the instructions in the loop is not included.
BCF
TRISB, 5
; PB5 as an output
MOVLWOxO
;Timer3,16-bit,int clk,no prescale
MOVWF T3CON
; load T3CON reg.
HERE MOVLW Ox9E
;TMR3H = 9EH, the high byte
MOVWF TMR3H
;load Timer3 high byte
MOVLW Ox58
;TMR3L = 58H, the low byte
MOVWF TMR3L
;load Timer3 low byte
PIR2, TMR3IF
;clear Timer3 interrupt flag bit
BCF
CALL DELAY
BTG
PORTB, RB5
;toggle PB5
BRA
HERE
---------delay using Timer3
DELAY BSF
T3CON, TMR30N
; start Timer3
AGAINBTFSS PIR2,TMR3IF
;monitor timer flag until
BRA
AGAIN
; it rolls over
BCF
T3CON, TMR30N
;stop timer
RETURN
T = I I 50 Hz = 2 ms
1/2x2ms=lms
for high and low portions
I ms I 0.4 liS = 25000
number of clock counts
65536 - 25000 = 40536 = 9E58H
CHAPTER 9: PIC18 TIMER PROGRAMMING IN ASSEMBLY AND C
379
Example 9-44
Assume that a I-Hz frequency pulse is connected to the input for Timer3 (pin RCO).
Write a program to display the counter values TMR3H and TMR3L on ports Band D.
Set the initial values of to o. Use no prescaler.
Solution:
BSF
CLRF
CLRF
MOVLW
MOVWF
HERE MOVLW
MOVWF
MOVLW
MOVWF
BCF
BSF
AGAIN MOVFF
MOVFF
BTFSS
BRA
BCF
GOTO
TRISC, a
TRISB
TRISD
Ox02
T3CON
OxO
TMR3H
OxO
TMR3L
PIR2,TMR3IF
T3CON,TMR30N
TMR3L,PORTB
TMR3H,PORTD
PIR2,TMR3IF
AGAIN
T3CON,TMR30N
HERE
;PORTC.O as input T1CLKI
;PORTB as an output
;PORTD as an output
;Timer3,16-bit,ext elk/no prescale
; load TOCON reg
;TMR3H = 0, the low byte
;load Timer3 high byte
;TMRIL = 0, the low byte
;load Timer3 low byte
iclear timer interrupt flag bit
istart timer
;display low byte count
;display high byte count
;monitor Timer3 flag until
;it rolls over
istOP Timer3
PIC18
~
1 Hz clock TlCKI RCO
380
to
LEDs
Example 9-45
Write a CIS program to create a frequency of2500 Hz on pin PORTB.1. Use Timer3 to
create the delay.
Solution:
#include <p18f4580.h>
void T3Delay(void);
#define mybit PORTBbits.RBl
void main (void)
{
TRISBbits.TRISB1=O;
T3CON=OxOO;
while (1)
//PB1 as an output
//Timer3, 16-bit mode, no prescaler
{
mybit=-mybit;
T3Delay() ;
//toggle PB.l
}
void T3Delay ()
TMR3H=OxFE;
TMR3L=OxOC;
T3CONbits.TMR30N=1;
while (PIR2bits.TMR3IF==O) ;
T3CONbits.TMR30N=O;
PIR2bits.TMR3IF=O;
//load TH3
//load TL3
/ /turn on T3
//wait for TF3 to rollover
//turn off T3
//clear TF3
1 I 2500 Hz = 400 lIS
400 lIS I 2 = 200 lIS
200 lIS I 0.4 lIS = 500
65536 - 500 = 65036 = FEOCH
CHAPTER 9: PIC18 TIMER PROGRAMMING IN ASSEMBLY AND C
381
Example 9-46
Assume that a I-Hz external clock is being fed into pin T3 (RCO). Write a CI8 program
for Timer3 to be used as a counter. It should count the pulses and display the TMR3H
and TMR3L registers on PORTD and PORTB, respectively.
Solution:
#include <p18f4580.h>
void main(void)
{
TRISCbits.TRISCO=l;
TRISB = 0;
TRISD = 0;
T3CON=Ox02;
IITimerl,
TMR3H=0;
TMR3L=0;
while (1)
Ilmake RCO an input for TICKI
Ilmake PORTB an output
limake PORTD an output
16-bit mode, no prescaler
Iiset count to 0
Iiset count to 0
Ilrepeat forever
{
do
{
Iiturn on T3
Ilplace value on pins
II
T3CONbits.TMR30N=I;
PORTB=TMR3L;
PORTD=TMR3H;
}
while (PIR2bits.TMR3IF==0) ;
T3CONbits.TMR30N=0;
PIR2bits.TMR3IF=0;
Ilwait for TF3 to rollover
Iiturn off T3
Ilclear TF3
}
}
PIC18
=
-
~
1 Hz clock
382
TOCKI
RCO
f=
~
r-
PB and
PD to
LEDs
Review Questions
I.
2.
3.
4.
5.
6.
What provides the clock pulses to Timer2?
Indicate the selection made if T2CON = OxO 0 .
True or false. Timer2 cannot be used for a counter.
In Timer3, the counter rolls over when it goes from __ to __ .
Ifwe set PR2 = 200, state when TMR2IF is raised.
TMR2IF and TMR3IF are part of registers __ .
SUMMARY
The PIC IS can have up to four or more timers/counters, depending on the
family member. When used as timers, they can generate time delays. When used
as counters, they can serve as event counters. This chapter showed how to program
the timers/counters for various modes.
Generally, the timers are accessed as two S-bit registers, TMRLx and
TMRHx. They can be used as a 16-bit timer, or as an S-bit timer.
Each timer has its own TCON (Timer Control) register, allowing us to
choose various operational modes. Among the modes are the prescaler and
timer/counter options. When the timer is used as a timer, the PICIS's crystal is
used as the source of the frequency (Fosc/4); however, when it is used as a counter, it is a pulse outside of the PICIS that increments the TMRxH, TMRxL registers.
PROBLEMS
SECTION 9.1: PROGRAMMING TIMERS 0 AND I
How many timers are in the PIC ISF45S?
TimerO of the PICIS is __-bit, accessed as
and _ _ _.
Timer! of the PICIS is __-bit, accessed as
and _ __
TimerO supports the highest prescaler value of _ __
Timer! supports the highest prescaler value of _ __
The TOCON register is a(n)
-bit register.
What is the job of the TOCON register?
True or false. nCON is a bit-addressable register.
Find the nCON value for 16-bit mode, no prescaler, timer oscillator off, with
the clock coming from the PICIS's crystal.
10. Find the frequency and period used by the timer if the crystal attached to the
PIC IS has the following values:
(a) XTAL = 10 MHz
(b) XTAL = 20 MHz
(c) XTAL = 24 MHz
(d) XTAL = 30 MHz
II. Indicate which register holds the TMRxIF (Timer Interrupt Flag) bit for each
of the following timers:
(a) TimerO
(b) Timer!
1.
2.
3.
4.
5.
6.
7.
S.
9.
CHAPTER 9: PIC18 TIMERS PROGRAMMING IN ASSEMBLY AND C
383
12. Indicate the rollover value (in hex and decimal) of the timer for each of the following modes:
(a) 16-bit
(b) 8-bit
13. Indicate when the TMROIF flag is raised for each of the following modes:
(a) 16-bit
(b) 8-bit
14. True or false. Both TimerO and Timer! have their own timer interrupt flags.
15. True or false. Both TimerO and Timer! have their own timer start flags.
16. Assume that XTAL = 10 MHz. Find the TMROH, TMROL value needed to generate a time delay of2 ms. Use 16-bit mode, no prescaler mode.
17. Assume that XTAL= 10 MHz. Find the TMROH,TMROL value needed to generate a time delay of 5 ms. Use 16-bit mode, and the largest prescaler possible.
18. Assume that XTAL = 10 MHz. Find the TMRIH,TMRIL value needed to generate a time delay of2.5 ms. Use the largest prescaler possible.
19. Assume that XTAL= 10 MHz. Find the TMRIH,TMRIL value needed to generate a time delay of 0.2 ms. Use 16-bit mode, no prescaler mode.
20. Assume that XTAL = 20 MHz. Find the TMRIH,TMRIL value needed to generate a time delay of2 ms. Use 16-bit mode, and the largest prescaler possible.
21. Assuming that XTAL = 10 MHz, and we are generating a square wave on pin
RB7, find the lowest square wave frequency that we can generate using TimerO
in 16-bit mode.
22. Assuming that XTAL = 10 MHz, and we are generating a square wave on pin
RB2, find the highest square wave frequency that we can generate using
TimerO in 16-bit mode.
23. Repeat Problems 21 and 22 for 8-bit mode.
24. In 8-bit mode, assuming that TMROL = FI H, indicate which states TimerO
goes through until TMROIF is raised. How many states is that?
25. Program TimerO to generate a square wave of I kHz. Assume that XTAL = 10
MHz.
26. Program Timerl to generate a square wave of 3 kHz. Assume that XTAL = 10
MHz. Use the largest prescaler possible.
27. State the differences between TimerO and Timerl.
28. Find the value (in hex) loaded into WREG in each of the following:
(b)
MOVLW -0'22'
(a)
MOVLW -0'12'
(c)
MOVLW -0'34'
(d)
MOVLW -0'92'
(e)
MOVLW -0'120'
(t)
MOVLW -0'104'
SECTION 9.2: COUNTER PROGRAMMING
29. To use a timer as an event counter we must set the
bit in the TOCON
register to
(LOW, HIGH).
30. Can we use both TimerO and Timerl as event counters?
31. For Counter 0, which pin is used for the input clock?
32. For Counter I, which pin is used for the input clock?
33. Program Timer! to be an event counter. Use 16-bit mode, and display the binary count on PORTB and PORTO continuously. Set the initial count to 20,000.
34. Program TimerO to be an event counter. Use 8-bit mode and display the binary count on PORTB continuously. Set the initial count to 20.
384
35. The TlCON register is a(n) _ _-bit register.
36. True or false. The Tl CON register is not a bit-addressable register.
SECTION 9.3: PROGRAMMING TIMERS 0 AND I IN C
37. Program TimerO in C to generate a square wave of I kHz. Assume that XTAL
= 10 MHz.
38. Program Timer! in C to generate a square wave of 1 kHz. Assume that XTAL
= 10 MHz.
39. Program TimerO in C to generate a square wave of3 kHz. Assume that XTAL
= 10 MHz.
40. Program Timer! in C to generate a square wave of 3 kHz. Assume that XTAL
= 10 MHz.
41. Program Timerl in C to be an event counter. Use 16-bit mode and display the
binary count on PORTB and PORTO continuously. Set the initial count to
20,000.
42. Program TimerO in C to be an event counter. Use 8-bit mode and display the
binary count on PORTO continuously. Set the initial count to 20.
SECTION 9.4: PROGRAMMING TIMERS 2 AND 3
43. Indicate the highest size of the prescaler supported for each of the following
timers:
(a) Timer2
(b) Timer3
44. Indicate the rollover value (in hex and decimal) ofTimer3.
45. Indicate when the timer flag is raised for each of the following:
(a) Timer2
(b) Timer3
46. True or false. The PR2 register of Timer2 is an 8-bit register.
47. True or false. Both Timer2 and Timer3 are l6-bit timers.
48. Assume that XTAL= 10 MHz. Find the TMR3H,TMR3L value needed to generate a time delay of2 ms. Use no prescaler.
49. Assume that XTAL = 10 MHz. Find the TMR3H,TMR3L value needed to generate a time delay of 5 ms. Use the highest prescaler allowed.
50. Program Timer3 to be an event counter. Use 16-bit mode and display the binary count on PORTB and PORTO continuously. Set the initial count to 20,000.
51. Program Timer2 in Assembly to toggle pin RB3 when it counts up from 0 to
200. Assume that XTAL = 10 MHz.
52. Program Timer3 in C to generate a square wave of 3 kHz. Assume that XTAL
= 10 MHz.
53. Program Timer2 in C to toggle pin RB3 when it counts up from 0 to 200.
Assume that XTAL = 10 MHz.
54. Program Timer3 in C to generate a square wave of 1 kHz. Assume that XTAL
= 10 MHz.
CHAPTER 9: PIC18 TIMER PROGRAMMING IN ASSEMBLY AND C
385
ANSWERS TO REVIEW QUESTIONS
SECTION 9.1: PROGRAMMING TIMERS
1.
2.
3.
4.
5.
6.
7.
S.
a AND
I
4
False
True
True
0000 1000 indicates 16-bit mode, no prescaler. and using XTAL for frequency.
FFFFH, 0000
FFH, 00
-200 is 3SH; therefore, WREG ~ 3SH
9. 2 ms / 0.4 us ~ 5000, 65536 - 5000 ~ 60536 ~ EC7SH, TMROH ~ ECH and TMROL ~ 7SH.
10. 100 us / 0.4 us ~ 250, 256 - 250 ~ 06; therefore TMROL ~ 06H.
SECTION 9.2: COUNTER PROGRAMMING
1.
2.
3.
4.
5.
The crystal attached to the PIC IS
The clock source for the timer comes from pin RA4 (PORTA4) .
Yes
We must configure the pin as input to allow the clocks to come in from an external source.
Yes
SECTION 9.4: PROGRAMMING TIMERS 2 AND 3
1.
2.
3.
4.
5.
6.
386
The crystal attached to the PICIS (Fosc/4)
Prescale of I, postscale of I, and stop Timer2
True
FFFFH,O
TMR2 counts up until it matches PR2. At that time TMR2IF is raised.
PIR I and PIR2 respectively.
CHAPTER 10
PIC18 SERIAL PORT
PROGRAMMING IN
ASSEMBLY AND C
OBJECTIVES
Upon completion of this chapter, you will be able to:
»
»
»
»
»
»
»
»
»
»
»
»
»
»
Contrast and compare serial versus parallel communication
List the advantages of serial communication over parallel
Explain serial communication protocol
Contrast synchronous versus asynchronous communication
Contrast half- versus full-duplex transmission
Explain the process of data framing
Describe data transfer rate and bps rate
Define the RS232 standard
Explain the use of the MAX232 and MAX233 chips
Interface the PICl8 with an RS232 connector
Discuss the baud rate of the PICl8
Describe serial communication features of the PICl8
Describe the main registers used by serial communication ofthe PICl8
Program the PICl8 serial port in Assembly and C
387
Computers transfer data in two ways: parallel and serial. In parallel data
transfers, often eight or more lines (wire conductors) are used to transfer data to a
device that is only a few feet away. Devices that use parallel transfers include
printers and hard disks; each uses cables with many wire strips. Although a lot of
data can be transferred in a short amount of time by using many wires in parallel,
the distance cannot be great. To transfer to a device located many meters away, the
serial method is used. In serial communication, the data is sent one bit at a time,
in contrast to parallel communication, in which the data is sent a byte or more at a
time. Serial communication of the PICI8 is the topic of this chapter. The PICI8
has serial communication capability built into it, thereby making possible fast data
transfer using only a few wires.
In this chapter we first discuss the basics of serial communication. In
Section 10.2, PICI8 interfacing to RS232 connectors via MAX232 line drivers is
discussed. Serial port programming of the PICl8 is discussed in Section 10.3.
Section lOA covers PIC I 8 C programming for the serial port using the C 18 compiler.
SECTION 10.1: BASICS OF SERIAL COMMUNICATION
When a microprocessor communicates with the outside world, it provides
the data in byte-sized chunks. In some cases, such as printers, the information is
simply grabbed from the 8-bit data bus and presented to the 8-bit data bus of the
printer. This can work only if the cable is not too long, because long cables diminish and even distort signals. Furthermore, an 8-bit data path is expensive. For these
reasons, serial communication is used for transferring data between two systems
located at distances of hundreds offeet to millions of miles apart. Figure 10-1 diagrams serial versus parallel data transfers.
Serial Transfer
Sender
• IReceiver I
Parallel Transfer
Sender
DO
Receiver
07
Figure 10-1. Serial versus Parallel Data Transfer
The fact that in a single data line is used in serial communication instead
of the 8-bit data line of parallel communication makes serial transfer not only
much cheaper but also enables two computers located in two different cities to
communicate over the telephone.
For serial data communication to work, the byte of data must be converted
to serial bits using a parallel-in-serial-out shift register; then it can be transmitted
388
over a single data line. This also means that at the receiving end there must be a
serial-in-parallel-out shift register to receive the serial data and pack them into a
byte. Of course, if data is to be transferred on the telephone line, it must be converted from Os and I s to audio tones, which are sinusoidal signals. This conversion
is performed by a peripheral device called a modem, which stands for "modulator/demodulator."
When the distance is short, the digital signal can be transferred as it is on
a simple wire and requires no modulation. This is how IBM PC keyboards transfer data to the motherboard. For long-distance data transfers using communication
lines such as a telephone, however, serial data communication requires a modem
to modulate (convert from Os and I s to audio tones) and demodulate (convert from
audio tones to Os and Is).
Serial data communication uses two methods, asynchronous and synchronous. The synchronous method transfers a block of data (characters) at a time
whereas the asynchronous method ransfers a single byte at a time. It is possible to
write software to use either of these methods, but the programs can be tedious and
long. For this reason, special IC chips are made by many manufacturers for serial
data communications. These chips are commonly referred to as UART (universal
asynchronous receiver-transmitter) and USART (universal synchronous-asynchronous receiver-transmitter). The PIC 18 chip has a built-in USART, which is discussed in detail in Section 10.3.
•I
Simplex
Transmitter
Half Duplex
Transmitter ' " i
Receiver
Full Duplex
Transmitter
Receiver
Receiver
,~Receiver
I
V-----I"-i Transmitter I
__
• I Receiver
Ir.--------LI~T~ra~n2:s~m~itt~e~rI
I
Figure 10-2. Simplex, Half-, and Full-Duplex Transfers
Half- and full-duplex transmission
In data transmission, if the data can be both transmitted and received, it is
a duplex transmission. This is in contrast to simplex transmissions such as with
printers, in which the computer only sends data. Duplex transmissions can be half
or full duplex, depending on whether or not the data transfer can be simultaneous.
If data is transmitted one way at a time, it is referred to as half duplex. If the data
CHAPTER 10: PIC18 SERIAL PORT PROGRAMMING IN ASSEMBLY AND C 389
can go both ways at the same time, it is filiI duplex. Of course, full duplex requires
two wire conductors for the data lines (in addition to the signal ground), one for
transmission and one for reception, in order to transfer and receive data simultaneously. See Figure 10-2.
Asynchronous serial communication and data framing
The data coming in at the receiving end of the data line in a serial data
transfer is all Os and I s; it is difficult to make sense of the data unless the sender
and receiver agree on a set of rules, a protocol, on how the data is packed, how
many bits constitute a character, and when the data begins and ends.
Start and stop bits
Asynchronous serial data communication is widely used for character-oriented transmissions, while block-oriented data transfers use the synchronous
method. In the asynchronous method, each character is placed between start and
stop bits. This is called framing. In data framing for asynchronous communications, the data, such as ASCII characters, are packed between a start bit and a stop
bit. The start bit is always one bit but the stop bit can be one or two bits. The start
bit is always a 0 (low) and the stop bites) is I (high). For example, look at Figure
10-3 in which the ASCII character "A" (8-bit binary 0 I 00000 I) is framed between
the start bit and a single stop bit. Notice that the LSB is sent out first.
.
space
-.
.
stop
bit
:t
goes out last
.
.
1
0
.
.
0
.
d7
.
0
.. 0
0
..
.
1
0
.
dO
•
.
.
start mark:
bit
t:
goes out first
Figure 10-3. Framing ASCII 'A' (41H)
Notice in Figure 10-3 that when there is no transfer, the signal is I (high),
which is referred to as mark. The 0 (low) is referred to as space. Notice that the
transmission begins with a start bit followed by DO, the LSB, then the rest of the
bits until the MSB (D7), and finally, the one stop bit indicating the end ofthe character "A".
In asynchronous serial communications, peripheral chips and modems can
be programmed for data that is 7 or 8 bits wide. This is in addition to the number
of stop bits, I or 2. While in older systems ASCII characters were 7-bit, in recent
years, 8-bit data has become common due to the extended ASCII characters. In
some older systems, due to the slowness of the receiving mechanical device, two
stop bits were used to give the device sufficient time to organize itself before transmission of the next byte. In modern PCs, however, the use of one stop bit is standard. Assuming that we are transferring a text file of ASCII characters using I stop
bit, we have a total of 10 bits for each character: 8 bits for the ASCII code, and I
bit each for the start and stop bits. Therefore, each 8-bit character has an extra 2
bits, which gives 25% overhead.
390
In some systems, the parity bit of the character byte is included in the data
frame in order to maintain data integrity. This means that for each character (7 - or
8-bit, depending on the system) we have a single parity bit in addition to start and
stop bits. The parity bit is odd or even. In the case of an odd parity bit the number
of I s in the data bits, including the parity bit, is odd. Similarly, in an even parity
bit system the total number of bits, including the parity bit, is even. For example,
the ASCII character "A", binary 0100 0001, has 0 for the even parity bit. UART
chips allow programming of the parity bit for odd-, even-, and no-parity options.
Data transfer rate
The rate of data transfer in serial data communication is stated in bps (bits
per second). Another widely used terminology for bps is baud rate. However, the
baud and bps rates are not necessarily equal. This is because baud rate is the
modem terminology and is defined as the number of signal changes per second. In
modems, sometimes a single change of signal transfers several bits of data. As far
as the conductor wire is concerned, the baud rate and bps are the same, and for this
reason in this book we use the terms bps and baud interchangeably.
The data transfer rate of a given computer system depends on communication ports incorporated into that system. For example, the early IBM PC/XT could
transfer data at the rate of 100 to 9600 bps. In recent years, however, Pentiumbased PCs transfer data at rates as high as 56K. Note that in asynchronous serial
data communication, the baud rate is generally limited to 100,000 bps.
RS232 standards
To allow compatibility among data communication equipment made by
various manufacturers, an interfacing standard called RS232 was set by the
Electronics Industries Association (EIA) in 1960. In 1963 it was modified and
called RS232A. RS232B and RS232C were issued in 1965 and 1969, respectively. In this book we refer to it simply as RS232. Today, RS232 is the most widely
used serial I/O interfacing standard. This standard is used in PCs and numerous
types of equipment. Because the standard was set long before the advent of the
TTL logic family, however, its input and output voltage levels are not TTL compatible. In RS232, a 1 is represented by -3 to -25 V, while a 0 bit is +3 to +25 V,
making -3 to +3 undefined. For this reason, to connect any RS232 to a microcontroller system we must use voltage converters such as MAX232 to convert the
TTL logic levels to the RS232 voltage level, and vice versa. MAX232 IC chips are
commonly referred to as line drivers. RS232 connection to MAX232 is discussed
in Section 10.2.
RS232 pins
Table 10-1 provides the pins and their labels for the RS232 cable, commonly referred to as the DB-25 connector. In labeling, DB-25P refers to the plug
connector (male) and DB-25S is for the socket connector (female). See Figure
10-4.
CHAPTER 10: PIC18 SERIAL PORT PROGRAMMING IN ASSEMBLY AND C 391
o
14
Figure 10-4. RS232 Connector DB-25
Because not all the pins are used in PC cables, IBM introduced the DB-9
version of the serial I/O standard, which uses only 9 pins, as shown in Table 10-2.
The DB-9 pins are shown in Figure 10-5.
Data communication classification
Current terminology classifies data communication equipment as DTE
(data terminal equipment) or DCE (data communication equipment). DTE refers
to terminals and computers that send and receive data, while DCE refers to communication equipment, such as
modems, that are responsible for trans- Table 10-1: RS232 Pins (DB-25)
ferring the data. Notice that all the
Descri~tion
RS232 pin function definitions of Pin
Protective ground
Tables 10-1 and 10-2 are from the DTE I
2
Transmitted
data ~TxDl
point of view.
Received data (RxDl
The
simplest
connection 3
Reguest to send (RTS)
4
between a PC and a microcontroller
Clear to send (CTS)
requires a minimum of three pins, TX, 5
6
Data
set readJ: (DSR1
RX, and ground, as shown in Figure
Signal ground ~GNDl
10-6. Notice in that figure that the RX 7
8
Data
carrier detect (Om1
and TX pins are interchanged.
9110 Reserved for data testing
Examining RS232 handUnassigned
11
12
Secondan: data carrier detect
shaking signals
13
Secondary clear to send
To ensure fast and reliable data 14
Secondan: transmitted data
transmission between two devices, the 15
Transmit signal element timing
data transfer must be coordinated. Just 16
Secondary received data
as in the case ofthe printer, because the 17
Receive signal element timing
receiving device may have no room for 18
Unassigned
the data in serial data communication, 19
Secondan: reguest to send
there must be a way to inform the 20
Data terminal readJ: ( DTR1
sender to stop sending data. Many of 21
Signal guali!J: detector
the pins of the RS-232 connector are 22
Ring indicator
used for handshaking signals. Their 23
Data signal rate select
description is provided below only as a 24
Transmit signal element timing
reference, and they can be bypassed 25
Unassigned
because they are not supported by the
PICI8 UART chip.
392
I. DTR (data terminal ready). When
5
the terminal (or a PC COM port) is
turned on, after going through a
self-test, it sends out signal DTR to
indicate that it is ready for communication. If there is something
wrong with the COM port, this sig6
9
nal will not be activated. This is an
active-LOW signal and can be used
to inform the modem that the com- Figure 10-5. DB-9 9-Piu Couuector
puter is alive and kicking. This is
an output pin from DTE (PC COM Table 10-2: IBM PC DB-9 Signals
Pin
Description
port) and an input to the modem.
DSR (data set ready). When the I
Data carrier detect (urn)
DCE (modem) is turned on and has 2
Received data (RxD)
gone through the self-test, it asserts :;:.3--...:T,::r:.:an:.:s:..m=it:..;te:::d::.:d::.a"'t:.:a::.:(T~xD=)--DSR to indicate that it is ready to 4
Data terminal ready (DTR)
communicate. Thus, it is an output 5
Signal ground (GND)
from the modem (DCE) and an 6
Data set ready (psID
input to the PC (DTE). This is an 7
active-LOW signal. If for any reaRequest to send (!ITS)
son the modem cannot make a con- ~8_ _...:C:::I;::e::;ar~t:::;0:...:s::.:e::;n:.:;d...:(ITS)==,-_ _ __
nection to the telephone, this signal "-9_ _..:R..:;i;:;n..
g..:i;;:nd,;;;i;.:c,;;;at.:..;0;.;.r...l(.:,RI=)'--_ _ __
remains inactive, indicating to the
PC (or terminal) that it cannot
OTE
OTE
accept or send data.
RTS (request to send). When the
TxD
TxD
DTE device (such as a PC) has a
RxD
byte to transmit, it asserts RTS to
RxD
signal the modem that it has a byte
of data to transmit. RTS is an
ground
active-LOW output from the DTE
Figure 10-6. Null Modem Connection
and an input to the modem.
CTS (clear to send). In response to
RTS, when the modem has room to store the data it is to receive, it sends out
signal CTS to the DTE (PC) to indicate that it can receive the data now. This
input signal to the DTE is used by the DTE to start transmission.
DCO (data carrier detect). The modem asserts signal DCD to inform the DTE
(PC) that a valid carrier has been detected and that contact between it and the
other modem is established. Therefore, OCD is an output from the modem and
an input to the PC (OTE).
RI (ring indicator). An output from the modem (OCE) and an input to a PC
(OTE) indicates that the telephone is ringing. RI goes on and off in synchronization with the ringing sound. Of the six handshake signals, this is the least
often used because modems take care of answering the phone. If in a given system the PC is in charge of answering the phone, however, this signal can be
used.
o
2.
3.
4.
5.
6.
o
CHAPTER 10: PIC18 SERIAL PORT PROGRAMMING IN ASSEMBLY AND C 393
From the above description, PC and modem communication can be summarized as follows: While signals DTR and DSR are used by the PC and modem,
respectively, to indicate that they are alive and well, it is RTS and CTS that actually control the flow of data. When the PC wants to send data it asserts RTS, and
in response, the modem, if it is ready (has room) to accept the data, sends back
CTS. If, for lack of room, the modem does not activate CTS, the PC will deassert
DTR and try again. RTS and CTS are also referred to as hardware control flow signals.
This concludes the description of the most important pins of the RS232
handshake signals plus TX, RX, and ground. Ground is also referred to as SG (signal ground).
IBM PC/compatible COM ports
IBM PC/compatible computers based on x86 (8086, 286, 386, 486, and all
Pentiums) microprocessors used to have two COM ports. Both COM ports were
RS232-type connectors. Many PCs used one each of the DB-25 and DB-9 RS232
connectors. The COM ports were designated as COM I and COM 2. In recent
years, one of these has been replaced with the USB port, and COM I is the only
serial port available, if any. We can connect the PIC 18 serial port to the COM I
port of a PC for serial communication experiments. In the absence of a COM port,
we can use a COM-to-USB converter module.
With this background in serial communication, we are ready to look at the
PIC 18. In the next section we discuss the physical connection of the PIC 18 and
RS232 connector, and in Section 10.3 we see how to program the PICI8 serial
communication port.
Review Questions
1. The transfer of data using parallel lines is
(faster, slower) but
_ _ _ _ _ _ _ (more expensive, less expensive).
2. True or false. Sending data to a printer is duplex.
3. True or false. In full duplex we must have two data lines, one for transfer and
one for receive.
4. The start and stop bits are used in the
(synchronous, asynchronous) method.
5. Assuming that we are transmitting the ASCII letter "E" (0100 0101 in binary)
with no parity bit and one stop bit, show the sequence of bits transferred serially.
6. In Question 5, find the overhead due to framing.
7. Calculate the time it takes to transfer 10,000 characters as in Question 5 if we
use 9600 bps. What percentage of time is wasted due to overhead?
8. True or false. RS232 is not TTL compatible.
9. What voltage levels are used for binary 0 in RS232?
10. True or false. The PICI8 has a built-in UART.
II. On the back of x86 PCs, we normally have _ _ COM port connectors.
12. The PC COM ports are designated by DOS and Windows as
and
394
SECTION 10.2: PIC18 CONNECTION TO RS232
In this section, the details of the physical connections of the PIC 18 to
RS232 connectors are given. As stated in Section 10.1, the RS232 standard is not
TTL compatible; therefore, a line driver such as the MAX232 chip is required to
convert RS232 voltage levels to TTL levels, and vice versa. The interfacing of
PIC 18 with RS232 connectors via the MAX232 chip is the main topic of this section.
RX and TX pins in the PIC18
The PIC 18 has two pins that are used specifically for transferring and
receiving data serially. These two pins are called TX and RX and are part of the
PORTC group (RC6 and RC7) of the 40-pin package. Pin 25 of the PICI8 (RC7)
is assigned to TX and pin 26 (RC6) is designated as RX. These pins are TTL compatible; therefore, they require a line driver to make them RS232 compatible. One
such line driver is the MAX232 chip. This is discussed next.
MAX232
Because the RS232 is not compatible with today's microprocessors and
microcontrollers, we need a line driver (voltage converter) to convert the RS232's
signals to TTL voltage levels that will be acceptable to the PICI8's TX and RX
pins. One example of such a converter is MAX232 from Maxim Corp.
(www.maxim-ic.com). The MAX232 converts from RS232 voltage levels to TTL
voltage levels, and vice versa. One advantage of the MAX232 chip is that it uses
a +5 V power source, which is the same as the source voltage for the PIC 18. In
other words, with a single +5 V power supply we can power both the PIC 18 and
MAX232, with no need for the dual power supplies that are common in many
older systems.
Vee
lC3
16
+
2
1
3 MAX232 6
4
5
T10uT
T11N
C1
+
C2
11
T ;:4
14
13
T20uT
T21N
10
PlC18
R11N
R10UT
12
+
7
MAX232
PORTC.6 25
(RC6)TxD
11
PORTC.? 26
(RC?)RxD
12
R21N
R20UT
9
/"'"'
14
2
13
3
5
~
'-'
DB-9
8
TTL side
15
RS232 side
40-Pin DIP Package PIelS
-
Figure 10-7. (a) Inside MAX232 and (b) its Connection to the PIC18 (Null Modem)
The MAX232 has two sets of line drivers for transferring and receiving
data, as shown in Figure 10-7. The line drivers used for TX are called TI and T2,
CHAPTER 10: PIC18 SERIAL PORT PROGRAMMING IN ASSEMBLY AND C 395
while the line drivers for RX are designated as Rl and R2. In many applications
only one of each is used. For example, Tl and RI are used together for TX and RX
of the PICI8, and the second set is left unused. Notice in MAX232 that the Tlline
driver has a designation ofTlin and Tlout on pin numbers II and 14, respectively. The Tl in pin is the TTL side and is connected to TX of the microcontroller,
while Tlout is the RS232 side that is connected to the RX pin of the RS232 DB
connector. The RI line driver has a designation ofRlin and Rlout on pin numbers
13 and 12, respectively. The Rlin (pin 13) is the RS232 side that is connected to
the TX pin of the RS232 DB connector, and Rlout (pin 12) is the TTL side that is
connected to the RX pin of the microcontroller. See Figure 10-7. Notice the null
modem connection where RX for one is TX for the other.
MAX232 requires four capacitors ranging from I to 22 IlF. The most widely used value for these capacitors is 22 1lF.
MAX233
To save board space, some designers use the MAX233 chip from Maxim.
The MAX233 performs the same job as the MAX232 but eliminates the need for
capacitors. However, the MAX233 chip is much more expensive than the
MAX232. Notice that MAX233 and MAX232 are not pin compatible. You cannot
take a MAX232 out of a board and replace it with a MAX233. See Figure 10-8 for
MAX233 with no capacitor used.
Vee
13
14
12
7
17
2
3
T11N
MAX233
5
4
T20UT
18
PORTC.6 25
(RC6)TxD
2
PORTC.? 26
(RC7)RxD
3
R21N
R20UT
9
RS233 side
,....,
5
2 5-:::h-
4
3
'--"
DB-9
19
6
TTL side
PIC18
R11N
R10UT
T21N
20
11
15
16
10
T10UT
MAX233
40-Pin DIP Package PIelS
Figure 10-8. (a) Inside MAX233 and (b) Its Connection to the PIe18 (Null Modem)
Review Questions
I. True or false. The PC COM port connector is the RS232 type.
2. Which pins of the PIC 18 are set aside for serial communication, and what are
their functions?
3. What are line drivers such as MAX 232 used for?
4. MAX232 can support __ lines for TX and __ lines for RX.
5. What is the advantage of the MAX233 over the MAX232 chip?
396
SECTION 10.3: PIC18 SERIAL PORT PROGRAMMING IN
ASSEMBLY
In this section we discuss the serial communication registers of the PIC IS
and show how to program them to transfer and receive data using asynchronous
mode. The USART (universal synchronous asynchronous receiver) in the PIC IS
has both the synchronous and asynchronous features. The synchronous mode can
be used to transfer data between the PIC and external peripherals such as ADC and
EEPROMs. The asynchronous mode is the one we will use to connect the PIC ISbased system to the IBM PC serial port for the purpose of full-duplex serial data
transfer. In this section we examine the asynchronous mode only. In the PIC
microcontroller six major registers are associated with the UART that we deal with
in this chapter. They are (a) SPBGR (serial port baud rate generator), (b) TXREG
(Transfer register), (c) RCREG (Receive register), (d) TXSTA (transmit status and
control register), (e) RCSTA (receive status and control register), and (f) PIRI
(peripheral interrupt request register!). We examine each of them and show how
they are used in full-duplex serial data communication.
SPBRG register and baud rate in the PIC18 Table 10-3: Some
PC Baud Rates in
Because IBM PC/compatible computers are so widely used to communicate with PICIS-based systems, we will HyperTerminal
1,200
emphasize serial communications of the PICIS with the --7~:----COM port of the PC. Some of the baud rates supported by _ _....:2::2,..:.4°::..:°'--__
4,SOO
PC HyperTerminal are listed in Table 10-3. You can examine ----'-'.::..::..:'---these baud rates by going to the Microsoft Windows ----'i~9::::,~2°::..:0°::,.0-
HyperTerminal program and clicking on the Communication
Settings option. The PIC IS transfers and receives data seri- _ _-=:3",S"",4-,,0.::,0_ _
ally at many different baud rates. The baud rate in the PICIS
57,600
115,200 _
is programmable. This is done with the help of the S-bit reg- _ _':":":2::..::"::"'-_
ister called SPBRG. For a given crystal frequency, the value
loaded into the SPBRG decides the baud rate. The relation between the value
loaded into SPBRG and the Fosc (frequency of oscillator connected to the OSC I
and OSC2 pins) is dictated by the following formula:
---=-=-=-.::.-----
Desired Baud Rate = Fosc/(64X + 64) = Fosc/64(X + I)
=
where X is the value we load into the SPBGR register. Assuming that Fosc
10 MHz, we have the following:
Desired Baud Rate = Fosc/64(X + I) = 10 MHz/64(X + I) = 6250 HZ/(X + I)
To get the X value for different baud rates we can solve the equation as fol-
lows:
X = (1 56250IDesired Baud Rate) - I
Table 10-4 shows the X values for the different baud rates if Fosc = 10
MHz. Another way to understand the SPBRG values in Table 10-4 is to look at
CHAPTER 10: PIC18 SERIAL PORT PROGRAMMING IN ASSEMBLY AND C 397
them from the perspective of the instruction cycle time. As we discussed in previous chapters, the PIC18 divides the crystal frequency (Fosc) by 4 to get the instruction cycle time frequency. In the case of XTAL = 10 MHz, the instruction cycle
frequency is 2.5 MHz. The PIC 18's UART circuitry divides the instruction cycle
frequency by 16 once more before it is used by an internal timer to set the baud
rate. Therefore, 2.5 MHz divided by 16 gives 156,250 Hz. This is the number we
use to find the SPBRG value shown in Table 10-4. Example 10-1 shows how to
verify the data in Table 10-4. Table 10-5 shows the SPBRG values with the crystal frequency of 4 MHz (Fosc = 4 MHz).
Example 10-1
With Fosc = 10 MHz, find the BGRP value needed to have the following baud rates:
(a) 9600
(b) 4800
(c) 2400
(d) 1200
Solution:
Because Fosc = 10 MHz, we have 10 MHzl4 = 2.5 MHz for the instruction cycle frequency. This is divided by 16 once more before it is used by UART. Therefore, we have
2.5 MHzlI6= 156250 Hz and X = (156250 HzlDesired Baud Rate) -1:
(a) (156250/9600) - 1 = 16.27 - 1 = 15.27 = 15 = F (hex) is loaded into SPBRG
(b) (156250/4800) -1 = 32.55 -1 = 31.55 = 32 = 20 (hex) is loaded into SPBRG
(c) (156250/2400) -1 = 65.1-1 = 64.1 = 64 = 40 (hex) is loaded into SPBRG
(d) (15625011200) - 1 = 130.2 - 1 = 129.2 = 129 = 81 (hex) is loaded into SPBRG
Notice that dividing the instruction cycle frequency by 16 is the setting upon Reset. We
can get a higher baud rate with the same crystal by changing this default setting. This is
done by making bit BRGH = 1 in the TXSTA register. This is explained at the end of
this section.
10 MHz
Instruction cycle freq
XTAL
+4
2.5 MHz
oscillator
156,250 Hz
+ 16
byUART
L -_ _ _- '
Table 10-4: SPBRG Values for Various Baud Rates (Fosc = 10 MHz,
BRGH=O)
SPBRG (Decimal Value)
Baud Rate
38400
19200
9600
4800
2400
1200
Note: For Fosc
398
~
SPBRG (Hex Value)
3
3
7
15
32
64
129
7
F
20
40
81
10 MHz we have SPBRG
~
(I 56,250/BaudRate) - 1
ToUART
to set the
baud rate
Table 10-5: SPBRG Values for Various Baud Rates (Fosc
=
4 MHz, BRGH
= 0)
Baud Rate
SPBRG (Decimal Value)
19200
9600
4800
2400
1200
Note: For Fosc
2
5
12
25
51
=
2
5
OC
19
33
4 MHz we have 4 MHz/4
used by the UART is 1 MHzll6
SPBRG (Hex Value)
~
=
1 MHz for instruction cycle freq. The frequency
~ (62500/Baud Rate) ~ 1
62,500 Hz. That means SPBRG
TXREG register
TXREG is another 8-bit register used for serial communication in the
PICI8. For a byte of data to be transferred via the TX pin, it must be placed in the
TXREG register. TXREG is a special function register (SFR) and can be accessed
like any other register in the PIC 18. Look at the following examples of how this
register is accessed:
MOVLW Ox41
MOVWF TXREG
;WREG=41H, ASCII for letter 'A'
;copy WREG into TXREG
MOVFF PORTB,TXREG ;copy PORTB contents into TXREG
The moment a byte is written into TXREG, it is fetched into a register
called TSR (transmit shift register). The TSR frames the 8-bit data with the start
and stop bits and the IO-bit data is transferred serially via the TX pin. Notice that
while TXREG is accessible by the programmer, TSR is not accessible and is strictly for internal use.
RCREG register
Similarly, when the bits are received serially via the RX pin, the PIC 18
deframes them by eliminating the stop and start bits, making a byte out of the data
received, and then placing it in the RCREG register. The following code will dump
the received byte into PORTB:
MOVFF RCREG,PORTB ;copy RXREG to PORTB
TXSTA (transmit status and control register)
The TXSTA register is an 8-bit register used to select the
synchronous/asynchronous modes and data framing size, among other things.
Figure 10-9 describes various bits of the TXSTA register. In this textbook we use
the asynchronous mode with a data size of 8 bits. The BRGH bit is used to select
a higher speed for transmission. The default is lower baud rate transmission. We
will examine the higher transmission rate at the end of this chapter. Notice that D6
of the TXSTA register determines the framing of data by specifying the number of
bits per character. We use an 8-bit data size. There are some applications for the
9-bit in which the ninth bit can be used as an address.
CHAPTER 10: PIC18 SERIAL PORT PROGRAMMING IN ASSEMBLY AND C 399
CSRC
CSRC D7
TX9 D6
TXEN D5
SYNC D4
o
TX9
TXEN
SYNC
o
I BRGH I TRMT I TX9D
Clock Source Select (not used in asynchronous mode, therefore D7 = 0.)
9-bit Transmit Enable
I = Select 9-bit transmission
0= Select 8-bit transmission (We use this option, therefore D6 = 0.)
Transmit Enable
I = Transmit Enabled
o = Transmit Disabled
We turn "on" and "off" this bit in order to start or stop data transfer.
USART mode Select (We use asynchronous mode, therefore D4 = 0.)
I = Synchronous
o = Asynchronous
D3
BRGH D2
High Baud Rate Select
Low Speed (Default)
I = High Speed
We can double the baud rate with the same Fosc. See the end of this
section for further discussion on this bit.
TRMTDI
Transmit Shift Register (TSR) Status
1= TSR empty
0= TSR full
The importance of the TSR register. To transfer a byte of data serially, we write it
into TXREG. The TSR (transmit shift register) is an internal register whose job is to
get the data from the TXREG, frame it with the start and stop bits, and send it out one
bit at a time via the TX pin. When the last bit, which is the stop bit, is transmitted, the
TRMT flag is raised to indicate that it is empty and ready for the next byte. When
TSR fetches the data from TXREG, it clears the TRMT flag to indicate it is full.
Notice that TSR is a parallel-in-serial-out shift register and is not accessible to the programmer. We can only write to TXREG. Whenever the TSR is empty, it gets its data
from TXREG and clears the TXREG register immediately, so it does not send out the
same data twice.
o=
TXD9 DO
9th bit of Transmit Data (Because we use the 8-bit option, we make
DO = 0)
Can be used as an address/data or a parity bit in some applications
Figure 10-9. TXSTA: Transmit Status and Control Register
RCSTA (receive status and control register)
The RCSTA register is an 8-bit register used to enable the serial port to
receive data, among other things. Figure 10-10 describes various bits of the
RCSTA register. In this section we use the 8-bit data frame.
400
SPEN
SPEN D7
RX9
D6
SREN D5
CREN D4
ADDEN D3
FERR D2
OERR Dl
TXD9 DO
RX9
SREN
CREN
I ADDE I FERR
OERR
RX9D
Serial port enable bit
1 ~ Serial port enabled, which makes TX and RX pins as serial port pins
o~ Serial port disabled
9-bit Receive enable bit
I ~ Select 9-bit reception
o ~ Select 8-bit reception (We use this option; therefore, D6 ~ 0.)
Single receive enable bit (not used in asynchronous mode D5 ~ 0)
Continuous receive enable bit
1 ~ Enable continuous Receive (in asynchronous mode)
o~ Disable continuous Receive (in asynchronous mode)
Address delete enable bit (Because used with the 9-bit data frame D3 ~ 0)
Framing error bit
1 ~ Framing error
o ~ No Framing error
Overrun error bit
1 ~ Overrun error
o ~ No overrun error
9th bit of Receive data (Because we use the 8-bit option, we make DO ~ 0)
Can be used as an address/data or a parity bit in some applications.
Figure 10-10. RCSTA: Receive Status and Control Register
RCIF
RCIF
TXIF
TXIF
Receive interrupt flag bit
1 ~ The UART has received a byte of data and it is sitting in the
RCREG register (receive buffer), waiting to be picked up.
Upon reading the RCREG register, the RCIF is cleared to allow the
next byte to be received.
o~ The RCREG is empty.
Transmit interrupt flag bit
o ~ The TXREG register is full.
I
~
The TXREG (transmit buffer) register is empty.
The importance of TXIF: To transmit a byte of data, we write it into TXREG. Upon
writing a byte into TXREG, the TXIF flag is cleared. When the entire byte is transmitted via the TX pin, the TXIF flag bit is raised to indicate that it is ready for the next
byte. So, we must monitor this flag before we write a new byte into TXREG, otherwise,
we wipe out the last byte before it is transmitted.
Several bits of this register are used by the timer flag, as we saw in Chapter 9. The
location of the flag bits in the PIR 1 register is not fixed and can vary in future PIC 18
products.
Figure 10-11. PIRI (Peripheral Interrupt Register 1)
CHAPTER 10: PIC18 SERIAL PORT PROGRAMMING IN ASSEMBLY AND C 401
PIR1 (peripheral interrupt request register 1)
In Chapter 9, we saw how some of the bits ofPIRI are used by the timers.
Two of the PIRI register bits are used by the UART. They are TXIF (transmit
interrupt flag) and RCIF (receive interrupt flag). See Figure 10-11. We monitor
(poll) the TXIF flag bit to make sure that all the bits of the last byte are transmitted before we write another byte into the TXREG. By the same logic, we monitor
the RCIF flag to see if a byte of data has come in yet. In Chapter II we will see
how these flags are used with interrupts instead of polling. Next we will examine
how TXIF flags are used in serial data transfer.
Programming the PIC18 to transfer data serially
In programming the PIC 18 to transfer character bytes serially, the following steps must be taken:
1. The TXSTA register is loaded with the value 20H, indicating asynchronous
mode with 8-bit data frame, low baud rate, and transmit enabled.
2. Make TX pin ofPORTC (RC6) an output for data to come out of the PIC.
3. The SPBRG is loaded with one of the values in Table 10-4 (or Table 10-5 if
Fosc = 4 MHz) to set the baud rate for serial data transfer.
4. SPEN bit in the RCSTA register is set HIGH to enable the serial port of the
PICI8.
5. The character byte to be transmitted serially is written into the TXREG register.
6. Monitor the TXIF bit ofthe PIRI register to make sure UART is ready for next
byte.
7. To transfer the next character, go to Step 5.
Example 10-2 shows the program to transfer data serially at 9600 baud.
Example 10-3 shows how to transfer "YES" continuously.
Example 10-2
Write a program for the PICI8 to transfer the letter 'G' serially at 9600 baud, continuously. Assume XTAL = 10 MHz.
Solntion:
MOVLW B'00100000'
MOVWF TXSTA
OVER
81
402
MOVLW D'15'
MOVWF SPBRG
BCF TRISC, TX
BSF RCSTA, SPEN
MOVLW AlGI
BTFSS PIR1, TXIF
BRA Sl
MOVWF TXREG
BRA OVER
;enable transmit and choose low baud rate
iwrite to reg
;9600 bps (Fose ! (64 * Speed) - 1)
;write to reg
;make TX pin of PORTC an output pin
;enable the entire serial port of PICIS
iASCII letter 'G' to be transferred
;wait until the last bit is gone
;stay in loop
;load the value to be transferred
ikeep sending letter 'G'
Example 10-3
Write a program to transmit the message "YES" serially at 9600 baud, 8-bit data, and I
stop bit. Do this forever.
Solution:
OVER
MOVLW B'00100000'
MOVWF TXSTA
MOVLW D'15'
MOVWF SPBRG
BCF TRISC, TX
BSF RCSTA, SPEN
MOVLW A'Y'
CALL TRANS
MOVLW A'E'
CALL
;enable transmit and choose low baud
;write to reg
; 9600 bps (Fosc /
(64
*
Speed)
- 1)
;write to reg
;make TX pin of PORTC an output pin
ienable the serial port
iASCII letter 'y' to be transferred
iASCII letter
'E'
to be transferred
;ASCII letter'S'
to be transferred
TRANS
MOVLW A'S'
CALL TRANS
MOVLW OxO
CALL TRANS
BRA
OVER
;NULL to purge the buffer
; keep doing it
TRANS ;----serial data transfer subroutine
Sl
BTFSS PIR1, TXIF
;wait until the last bit is gone
BRA Sl
;stay in loop
MOVWF TXREG
iload the value to be transmitted
RETURN
ireturn to caller
Importance of the TXIF flag
To understand the importance of the role of TXIF, look at the following
sequence of steps that the PICI8 goes through in transmitting a character via TX:
I. The byte character to be transmitted is written into the TXREG register.
2. The TXIF flag is set to I internally to indicate that TXREG has a byte and will
not accept another byte until this one is transmitted.
3. The TSR (Transmit Shift Register) reads the byte from TXREG and begins to
transfer the byte starting with the start bit.
4. The TXIF is cleared to indicate that the last byte is being transmitted and
TXREG is ready to accept another byte.
s. The 8-bit character is transferred one bit at a time.
6. By monitoring the TXIF flag, we make sure that we are not overloading the
TXREG register. If we write another byte into the TXREG register before the
TSR has fetched the last one, the old byte could be lost before it is transmitted.
From the above discussion we conclude that by checking the TXIF flag bit,
we know whether or not the PIC 18 is ready to transfer another byte. The TXIF flag
bit can be checked by the instruction "BTFSS PIR1, TXIF" or we can use an interrupt, as we will see in Chapter II. In Chapter II we will show how to use interrupts to transfer data serially, and avoid tying down the microcontroller with
instructions such as "BTFSS PIR1, TXIF".
CHAPTER 10: PIC18 SERIAL PORT PROGRAMMING IN ASSEMBLY AND C 403
Programming the PIC18 to receive data serially
In programming the PIC 18 to receive character bytes serially, the following steps must be taken:
I. The RCSTA register is loaded with the value 90H, to enable the continuous
receive in addition to the 8-bit data size option.
2. The TXSTA register is loaded with the value OOH to choose the low baud rate
option.
3. SPBRG is loaded with one of the values in Table 10-4 to set the baud rate
(assuming XTAL = 10 MHz).
4. Make the RX pin ofPORTC (RC7) an input for data to come into the PICI8.
5. The RCIF flag bit of the PlRI register is monitored for a HIGH to see if an
entire character has been received yet.
6. When RClF is raised, the RCREG register has the byte. Its contents are moved
into a safe place.
7. To receive the next character, go to Step 5.
Example 10-4 shows the coding of the above steps.
Example 10-4
Program the PICI8 to receive bytes of data serially and put them on PORTB. Set the
baud rate at 9600, 8-bit data, and I stop bit.
Solution:
MOVLW
MOVWF
MOVLW
MOVWF
BSF
CLRF
B'10010000'
RCSTA
jenable receive and serial port itself
;write to reg
D'lS'
; 9600 bps (Fosc / (64 * Speed) - 1}
jwrite to reg
SPBRG
TRISC, RX
;make RX pin of PORTC an input pin
jmake port B an output port
TRISB
ig et a byte from serial port and place it on PORTB
BTFSS PIR1, RCIF
icheck for ready
R1
jstay in loop
BRA
R1
MOVFF RCREG, PORTB
isave value into PORTB
BRA
R1
;keep doing that
Importance of the RCIF flag bit
In receiving bits via its RX pin, the prCI8 goes through the following
steps:
I. It receives the start bit indicating that the next bit is the first bit of the character byte it is about to receive.
2. The 8-bit character is received one bit at time. When the last bit is received, a
byte is formed and placed in RCREG
3. The stop bit is received. It is during receiving the stop bit that the PICI8 makes
RCIF = I, indicating that an entire character byte has been received and must
404
be picked up before it gets overwritten by another incoming character.
4. By checking the RCIF flag bit when it is raised, we know that a character has
been received and is sitting in the RCREG register. We copy the RCREG contents to a safe place in some other register or memory before it is lost.
5. After the RCREG contents are read (copied) into a safe place, the RCIF flag
bit is forced to 0 by the UART itself This allows the next received character
byte to be placed in RCREG, and also prevents the same byte from being
picked up multiple times.
From the above discussion we conclude that by checking the RCIFI flag bit
we know whether or not the PICl8 has received a character byte. Ifwe fail to copy
RCREG into a safe place, we risk the loss of the received byte. More importantly,
note that the RCIF flag bit is raised by the PIC 18, and it is also cleared by the CPU
when the data in the RCREG is picked up. Note also that if we copy RCREG into
a safe place before the RCIF flag bit is raised, we risk copying garbage. The RCIF
flag bit can be checked by the instruction "BTFSS PIRl, RCIF" or by using an
interrupt, as we will see in Chapter II.
Quadrupling the baud rate in the PIC18
There are two ways to increase the baud rate of data transfer in the PICI8:
1. Use a higher-frequency crystal.
2. Change a bit in the TXSTA register, as shown below.
Option I is not feasible in many situations because the system crystal is
fixed. Therefore, we will explore option 2. There is a software way to quadruple
the baud rate of the PIC 18 while the crystal frequency stays the same. This is done
with the BRGH bit of the TXSTA register. When the PIC 18 is powered up, D2
(BRGH bit) of the TXSTA register is zero. We can set it to high by software and
thereby quadruple the baud rate.
To see how the baud rate is quadrupled with this method, we show the
role of the BRGH bit (D2 bit of the TXSTA register), which can be 0 or I. We
discuss each case.
Baud rates for BRGH
=0
When BRGH = 0, the PICIS divides Fosc/4 (crystal frequency) by 16 once
more and uses that frequency for UART to set the baud rate. In the case of XTAL
= 10 MHz we have:
Instruction cycle freq. = 10 MHz / 4 = 2.5 kHz
and
2.5 MHz / 16 = 156,250 Hz because BRGH = 0
This is the frequency used by UART to set the baud rate. This has been the
basis of all the examples so far because it is the default when the PIC 18 is powered up. The baud rate for BRGH = 0 was listed in Table 10-4 and Table 10-5.
CHAPTER 10: PIC1S SERIAL PORT PROGRAMMING IN ASSEMBLY AND C 405
Baud rates for BRGH
=1
With the fixed crystal frequency, we can quadruple the baud rate by making BRGH = I. When the BRGH bit (D2 of the TXSTA register) is set to I, Fosc/4
of XTAL is divided by 4 (instead of 16) once more, and that is the frequency used
by UART to set the baud rate. In the case of XTAL = 10 MHz, we have:
Instruction cycle freq. = 10 MHz / 4
2.5 MHz
and
2.5 MHz / 4 = 625000 Hz because BHRG = 1
This is the frequency used by UART to set the baud rate if BHRH = I.
Table 10-8 shows that the values loaded into SPBREG are the same for
both cases; however, the baud rates are quadrupled when BRGH = I. Look at
Examples 10-5 through 10-7 to clarify the data given in Tables 10-6 and 10-7.
Table 10-6: SPBRG Values for Various Baud Rates (Fosc = 10MHz and
BRGH= 1)
Baud Rate
57600
38400
19200
9600
4800
SPBRG (Decimal Value)
10
15
32
64
129
SPBRG (Hex Value)
OA
OF
20
40
81
Note: For Fasc = 10 MHz we have SPBRG = (625000!Baud Rate) - I
IExample 10-5
Find the SPBRG value (in both decimal and hex) to set the baud rate to each of the following:
(b) 4800 ifBRGH = 1
(a) 9600 ifBRGH = 1
Assume that XTAL = 10 MHz.
Solution:
With XTAL = 10 MHz, Fosc/4 = 2.5 MHz. Because BRGH = 1, we have UART frequency = 2.5 MHz/4 = 625,000 Hz.
(a) (625,500 19600) - I = 64; therefore, SPBRG = 64 or SPBRG = 40H (in hex).
(b) (625,500 14800) - I = 129; therefore, SPBRG = 129 or SPBRG = 81H (in hex).
BRGH= 1
10 MHz
XTAL
oscillator
_
[J
+4
---l
Instruct. cycle freq.
2.5 MHz
+ 4 1625000 Hz To
IL~.J----" UART
to set
I.
1156250 Hz baud
'---II ~ 16 I
rate
BRGH=O
406
Table 10-7: SPBRG Values for Various Baud Rates (XTAL = 10 MHz)
BRGH=O
Baud Rate
SPBRG (Decimal)
57600
2
38400
3
19200
7
15
9,600
4,800
32
SPBRG = (1 56250/Baud rate) - 1
BRGH= 1
SPBRG (Decimal)
10
15
32
64
129
SPBRG = (625000/Baud rate) - 1
Table 10-8: SPBRG Values vs. Baud Rates for BRGH = 0 and BRGH = 1
(XTAL = 10 MHz)
SPBRG (Decimal)
15
32
64
BRGH=O
BRGH= 1
Baud Rate
9600
4800
2400
Baud Rate
38400
19200
9600
Table 10-9: SPBRG Values for Various Baud Rates (XTAL = 4 MHz)
BRGH = 0
Baud Rate
SPBRG (Decimal)
19200
3
9,600
6
4,800
12
2,400
25
SPBRG = (62500/Baud rate) - 1
BRGH = 1
SPBRG (Decimal)
12
25
51
103
SPBRG = (250000/Baud rate) - 1
Example 10-6
Write a program for the PIel8 to transfer the letter 'G' serially at 57600 baud, continuously. Assume XTAL = 10 MHz. Use the BRGH = 1 mode
Solution:
OVER
81
MOVLW B'00100100' ienable transmit and choose high baud rate
MOVWF TXSTA
iwrite to reg
MOVLW D'10'
;57600 bps (Fose / (16 * Speed) - 1)
MOVWF SPBRG
;write to reg
BCF TRISC, TX
;make TX pin of PORTC an output pin
BSF RC8TA, 8PEN
ienable the entire Serial port of PIel8
MOVLW A'G'
jASCII letter 'G' to be transferred
BTF88 PIR1, TXIF ;wait until the last bit is gone
BRA 81
jstay in loop
MOVWF TXREG
;load the value to be transferred
BRA OVER
jkeep sending letter 'G'
CHAPTER 10: PIC18 SERIAL PORT PROGRAMMING IN ASSEMBLY AND C 407
Baud rate error calculation
In calculating the baud rate we have used the integer number for the
SPBRG register values because PIC microcontrollers can only use integer values.
By dropping the decimal portion of the calculated values we run the risk of introducing error into the baud rate. There are several ways to calculate this error. One
way would be to use the following formula.
Error = (Calculated value for the SPBRG - Integer part )/Integer part
For example, with the XTAL = \0 MHz and BRGH
lowing for the 9600 baud rate:
=
0 we have the fol-
SPBRG value = (156250/9600) -I = 16.27 -I = 15.27 = 15
and the error is
(15.27 - 15)/16 = 1.7%
Another way to calculate the the error rate is as follows:
Error = (calculated baud rate - desired baud rate) / desired baud rate
Example 10-7
Assuming XTAL = 10 MHz, calculate the baud rate error for the following:
(a) 2400
(b) 1200
(c) 19200
(d) 57600
Use the BRGH = 0 mode.
Solution:
(a) SPBRG Value = (15625012400) - 1 = 65.1-1 = 64.1 = 64
Error = (64.1 - 64)/ 65 = 0.15%
(b) SPBRG Value (156250/1200) - 1 = 130.2 - 1 = 129.2 = 129
Error = (129.2 - 129)/130 = 0.15%
(c) SPBRG Value (156250/19200) - 1 = 8.138 - 1 = 7.138 = 7
Error = (7.138 - 7)/8 = 1.7%
(d) SPBRG Value (156250/57600) - 1 = 2.71 - 1 = 1.71 = 1
Error = (1.71 - 1)12 = 35%
Such an error rate is too high. Let's round up the number to see what happens.
Error = (3 - 2.7)/3 = 10% This means we use SPBRG = 2 instead of SPBRG = 1.
408
where the desired baud rate is calculated using X = «Fosc/Desired Baud
rate)64) - I and then the integer X (value loaded into SPBRG reg) is used for the
calculated baud rate as follows:
calculated baud rate = Fosc!(64(X + I)) (for BRGH = 0)
For XTAL = 10 MHz and 9600 baud rate, we got X = 15. Therefore, we
get the calculated baud rate of 10 MHz/(64(l5 + I)) = 9765. Now the error is calculated as follows:
Error = (9765 - 9600)/9600= 1.7%
which is the same as what we got earlier using the other method.
Tables 10-10 and 10-11 provide the error rates for SPBRG values of 10 MHz and
4 MHz crystal frequencies, respectively. Compare Examples 10-7 and 10-8 to see
how to calculate the error rates two different ways.
Example 10-8
Assuming XTAL = 10 MHz, calculate the baud rate error for the following:
(a) 2400
(b) 1200
Assume BRGH = 0
Solution:
(a) SPBRG Value = (156250/2400) -1 = 65.1 -I = 64.1 = 64
and calculated baud rate is 156250/(64 + 1) = 2403
Error = (2403 - 2400)12400 = 0.12%
(b) SPBRG Value (15625011200) - 1 = 130.2 - 1 = 129.2 = 129
where the calculated baud rate is 156250/(129 + 1) = 1202
Error = (1202 - 1200)/1200 = 0.16%
Table 10-10: SPBRG Values for Various Baud Rates (XTAL = 10 MHz)
BRGH= 1
BRGH=O
Baud Rate
38400
19200
9,600
4,800
SPBRG
3
7
15
32
Error
1.5%
1.7%
1.7%
1.3%
SPBRG = (1 56250/Baud rate) - 1
SPBRG
15
32
64
129
Error
1.7%
1.3%
0.15%
0.15%
SPBRG = (6250001Baud rate) - 1
Table 10-11: SPBRG Values for Various Baud Rates (XTAL = 4 MHz)
BRGH= 1
BRGH=O
Baud Rate
19200
9,600
4,800
2,400
SPBRG
2
6
12
25
Error
8.3%
8%
0.15%
0.16%
SPBRG = (62500/Baud rate) - 1
SPBRG
12
25
51
103
Error
0.15%
0.15%
0.15%
0.16%
SPBRG = (250000/Baud rate) - 1
CHAPTER 10: PIC18 SERIAL PORT PROGRAMMING IN ASSEMBLY AND C 409
Examine the next few examples to master the topic of PIC 18 serial port
programmmg.
Example 10-9
Assume a switch is connected to pin RD7. Write a program to monitor its status and
send two messages to the serial port continuously as follows:
SW = 0 send "NO"
SW = 1 send "YES"
Assume XTAL = 10 MHz, and set the baud rate to 9,600.
Solution:
OVER
FN
NEXT
LN
EXIT
BSF TRISD,7
MOVLW Ox20
MOVWF TXSTA
MOVLW D'lS'
MOVWF SPBRG
TRISC, TX
BCF
BSF
RCSTA, SPEN
BTFSS PORTD, 7
BRA
NEXT
MOVLW high(MESS1)
MOVWF TBLPTRH
MOVLW low(MESS1)
MOVWF TBLPTRL
;PORTD.7 as in input for SW
jenable transmit and choose low baud rate
iwrite to reg
;9600 bps (Fosc / (64 * Speed) - 1)
jwrite to reg
;make TX pin of PORTC an output pin
ienable the entire serial port of PIelS
TBLRD*+
iread the character
MOVF TABLAT,W
BZ
EXIT
CALL SEND COM
BRA
FN
MOVLW high (MESS2)
MOVWF TBLPTRH
MOVLW low(MESS2)
MOVWF TBLPTRL
TBLRD*+
MOVF TABLAT,W
BZ
EXIT
CALL SEND COM
BRA
LN
MOVLW Ox20
CALL SENDCOM
GOTO OVER
;if SW
o display "NOli
jcheck for end of line
;send character to serial port
; repeat
iif SW = 1 display "YES!!
jread the character
; Z = 1 if NULL
;check for end of line
jsend character to serial port
jrepeat
isend space
;-------------
SEND COM
Sl
BTFSS PIR1, TXIF
BRA
Sl
MOVWF TXREG
RETURN
;-----------------MESS1 DB
MESS2 DB
410
"NOII,a
IIYES",O
iwait until the last bit is gone
jstay in loop
iload the value to be transferred
ireturn to caller
Example 10-10
Write a program to send the message "The Earth is but One Country" to the serial port
continuously. Assume a SW is connected to pin RBO. Monitor its status and set the baud
rate as follows:
SW = 0 9600 baud rate
SW = I 38400 baud rate
Assume XTAL = 10 MHz.
Solution:
As shown in Table 10-8, we can quadruple the baud rate by changing the BRGH bit of
the TXSTA register.
BSF
BCF
BSF
TRISB,O
;PORTB.O as in input for SW
TRISC, TX
;make TX pin of PORTC an output pin
RCSTA, SPEN ;enable the entire serial port of PIC18
MOVLW ox20
OVER
NEXT
;transmit at low baud rate
MOVWF TXSTA
; wri te to reg
MOVLW D'15'
;9600 bps (Fose / (64 * Speed) - 1)
MOVWF SPBRG
;write to reg
BTFSC PORTB,O
;test bit PORTB.O and skip if LOW
BSF
TXSTA,BRGH ;transmit at high rate by making BRGH
MOVLW upper(MESSAGE)
MOVWF TBLPTRU
MOVLW high (MESSAGE)
MOVWF TBLPTRH
MOVLW low (MESSAGE)
MOVWF TBLPTRL
TBLRD*+
iread the character
MOVF TABLAT, W
iplace it in WREG
BZ
OVER
i i f end of line, start over
CALL SENDCOM
isend char to serial port
BRA
NEXT
jrepeat for the next character
1
i------------SEND COM
Sl
BTFSS PIR1, TXIF
BRA
Sl
MOVWF TXREG
RETURN
;wait until the last bit is gone
;stay in loop
;load the value to be transmitted
ireturn to caller
j-----------------MESSAGE DB
"The Earth is but One Country",
°
CHAPTER 10: PIC18 SERIAL PORT PROGRAMMING IN ASSEMBLY AND C 411
Transmit and receive
Assume that the PICI8 serial port is connected to the COM port ofthe IBM
PC, and we are using the HyperTerminal program on the PC to send and receive
data serially. The ports PORTB and PORTD of the PICI8 are connected to LEDs
and switches, respectively. Program 10-1 shows a PIC 18 program with the following parts: (a) sends the message "YES" once to the PC screen, (b) gets data on
switches and transmits it via the serial port to the PC's screen, and (c) receives any
key press sent by HyperTerminal and puts it on LEDs. The program performs part
(a) once, but parts (b) and (c) continuously. It uses the 9600 baud rate for XTAL =
10 MHz.
,Program 10-1 Transmit and Receive
ORG 0
;initialize the serial ports for both transmit and receive
ienable transmit, choose high baud
MOvLW B'00100100'
MOVWF
MOVLW
MOVWF
MOvLW
MOVWF
BSF
BCF
BSF
CLRF
SETF
TXSTA
B'10010000'
RCSTA
D'15'
SPBRG
RCSTA, SPEN
TRISC, TX
TRISC, RX
TRISB
TRISD
;write to reg
;enable receive, serial port itself
;write to reg
;9600 bps (FOSC ! (64 * Speed) - 1)
;write to reg
ienable the serial port itself
imake TX pin of PORTe an output
imake RX pin of PORTe an input
imake port B an output port
imake port D an input port
;send the message "YES"
MOVLW
CALL
MQVLW
'Y'
iASCII letter ryr
to be transferred
jASCII letter rEr
to be transferred
TRANS
'E'
CALL TRANS
MOVLW IS'
jASCII letter rsr to be transferred
CALL TRANS
iget a byte from switches and transmit data to PC screen
OVER MOVF PORTD,W
;get a byte from SW of PORTD
CALL TRANS
itransmit it via serial port
ias keys are pressed on PC receive data and put it on LEDs
jreceive the byte from serial port
CALL RECv
;display it on LEDS of PORTB
MOVWF PORTB
OVER
;keep doing it
BRA
;--serial transfer (WREG needs the byte to be transmitted)
TRANS
BTFSS PIR1, TXIF
iwait until the last bit is gone
Sl
BRA
Sl
;load the value to be transferred
MOVWF TXREG
RETURN
;return to caller
;----serial data receive subroutine (WREG = received byte)
412
RECV
BTFSS PIR1, RCIF
BRA
RECV
MOVF RCREG,W
RETURN
;check for ready
jstay in loop
isave value in WREG
"
8
TXIE
I
TXIF
J
H
~
Data Bus
TXREG register
MSb
~~
Pin Buffer
and Control
1(7)1
TSR Register
i
Interrupt
SPEN
Baud Rate Clock
I SPBRG I
Baud Rate Generator
Figure 10-12. Simplified USART Transmit Block Diagram
Interrupt-based data transfer
By now you might have noticed that it is a waste of the microcontroller's
time to poll the TXIF and RXIF flags. In order to avoid wasting the microcontroller's time we use interrupts instead of polling. In Chapter 11, we will show
how to use interrupts to program the PICIS's serial communication port.
Review Questions
1. Which register of the PICIS is used to set the baud rate?
2. IfXTAL = 10 MHz, what frequency is used by the UART to set the baud rate
(assuming default mode)?
3. Which bit of the TXSTA register is used to set the low or high baud rate?
4. With XTAL = 10 MHz, what value should be loaded into SPBRG to have a
9600 baud rate? Give the answer in both decimal and hex.
5. To transmit a byte of data serially, it must be placed in register _ _ _ .
6. TXSTA stands for
and it is a(n) __-bit register.
7. Which register is used to set the data frame size?
S. True or false. TXSTA is a bit-addressable register.
9. When is TXIF raised? When is it cleared?
10. Which register has the BRGH bit, and what is its status when the PIC IS is
powered up?
CHAPTER 10: PIC18 SERIAL PORT PROGRAMMING IN ASSEMBLY AND C 413
SECTION 10.4: PIC18 SERIAL PORT PROGRAMMING IN C
This section shows C programming of the serial ports for the PICI8 chip.
Transmitting and receiving data in PIC18 C
As we saw in Chapter 7, all the special function registers (SFRs) of the
PIC 18 are accessible directly in C 18 compilers by using the appropriate header
file. Examples 10-11 through 10-15 show how to program the serial port in PICI8
C. Connect your PICI8 Trainer to the PC's COM port and use HyperTerminal to
test the operation of these examples. Notice that Examples 10-11 through 10-15
are C versions of the Assembly programs in the last section.
Example 10-11
Write a C program for the PIC 18 to transfer the letter 'G' serially at 9600 baud, continuously. Use 8-bit data and I stop bit. Assume XTAL = 10 MHz.
Solution:
#include <P18F4580.h>
void main (void)
{
TXSTA= Ox2 0 ;
SPBRG=15;
TXSTAbits.TXEN=I;
RCSTAbits.SPEN=l;
//choose low baud rate,8-bit
//9600 baud rate/ XTAL = 10 MHz
while (1)
(
TXREG=' G' ;
/ /place value in buffer
while (PIRlbits.TXIF==O) ;
//wait until all gone
}
}
Review Questions
I. True or false. All the SFR registers of PIC 18 are accessible in the C 18 C compiler.
2. True or false. C 18 compilers support the bit-addressable registers ofthe PIC 18.
3. True or false. The TXIF flag is cleared the moment we write a character to the
TXREG register.
4. Which register is used to set the baud rate?
5. To which register does the BRGH bit belong, and what is its role?
414
Example 10-12
Write a PIC 18 C program to transfer the message "YES" serially at 9600 baud, 8-bit
data, and I stop bit. Do this continuously.
Solution:
#include <P18F458.h>
void SerTx(unsigned char) ;
void main (void)
{
TXSTA=Ox20;
SPBRG=15;
TXSTAbits.TXEN=l;
RCSTAbits.SPEN=l;
while (1)
//choose low baud rate,8-bit
//9600 baud rate/ XTAL = 10 MHz
{
SerTx ( 'Y' ) ;
SerTx ( , E ' ) ;
SerTx ( , S ' ) ;
}
void SerTx(unsigned char c)
{
while (PIRlbits.TXIF==O) ;
TXREG=c;
//wait until transmitted
//place character in buffer
}
Example 10-13
Program the PIC 18 in C to receive bytes of data serially and put them on PORTB. Set
the baud rate at 9600, 8-bit data, and I stop bit.
Solution:
#include <PI8F458.h>
void main (void)
{
TRISB = 0;
RCSTA=Ox90;
SPBRG=15;
while (1)
{
while(PIRlbits.RCIF==O);
PORTB=RCREG;
//PORTB an output
lienable serial port and receiver
//9600 baud rate/ XTAL = 10 MHz
//repeat forever
Ilwait to receive
//save value
CHAPTER 10: PIC18 SERIAL PORT PROGRAMMING IN ASSEMBLY AND C 415
IExample 10-14
Write an C 18 program to send two different strings to the serial port. Assuming that SW
is connected to pin PORTB.5, monitor its status and make a decision as follows:
SW = 0: send your first name
SW = 1: send your last name
Assume XTAL = 10 MHz, baud rate of 9600, and 8-bit data.
Solution:
#include <P18F4S8.h>
#define MYSW PORTBbits.RBS
void main (void)
//INPUT SWITCH
{
unsigned char Zi
unsigned char fname[]="ALI";
unsigned char lname[]="SMITH";
TRISBbits.TRISBS = 1; //an input
TXSTA=Ox20;
//choose low baud rate, 8-bit
SPBRG=lS;
//9600 baud rate/ XTAL = 10 MHz
TXSTAbits.TXEN=l;
RCSTAbits.SPEN=l;
i f (MYSW==O)
//check switch
(
for(z=0;z<3;z++)
//write name
{
while(PIR1bits.TXIF==O); //wait for transmit
TXREG=fname[z];
//place char in buffer
}
}
else
(
for(z=O;z<S;z++)
//write name
while (PIR1bits.TXIF==O) ; //wait for transmit
TXREG=lname[z] ;
//place value in buffer
while (1) ;
}
416
Example 10-15
Write a PICI8 C program to send the two messages "Normal Speed" and "High Speed"
to the serial port. Assuming that SW is connected to pin PORTB.O, monitor its status
and set the baud rate as follows:
SW = 0 9600 baud rate
SW = I 38400 baud rate
Assume that XTAL = 10 MHz for both cases.
Solution:
#include <P18F458.h>
#define MYSW PORTBbits.RB5
void main (void)
//INPUT SWITCH
{
unsigned char z;
unsigned char Messl[)="Normal Speed";
unsigned char Mess2[)="High Speed";
TRISBbits.TRISB5 = 1; //an input
TXSTA=Ox20;
//choose low baud rate, 8-bit
SPBRG=15;
//9600 baud rate/ XTAL = 10 MHz
TXSTAbits.TXEN=l;
RCSTAbits.SPEN=l;
i f (MYSW==O)
(
for(z=0;z<12;z++)
(
while (PIRlbits.TXIF==O) ; //wait for transmit
TXREG=Messl[z);
//place value in buffer
}
}
else
(
TXSTA=TXSTA[Ox4;
//for high speed
for(z=0;z<10;z++)
(
while (PIRlbits.TXIF==O) ; //wait for transmit
TXREG=Mess2[z);
//place value in buffer
}
while (1) ;
CHAPTER 10: PIC18 SERIAL PORT PROGRAMMING IN ASSEMBLY AND C 417
SUMMARY
This chapter began with an introduction to the fundamentals of serial communication. Serial communication, in which data is sent one bit a time, is used in
situations where data is sent over significant distances because in parallel communication, where data is sent a byte or more a time, great distances can cause distortion of the data. Serial communication has the additional advantage of allowing
transmission over phone lines. Serial communication uses two methods: synchronous and asynchronous. In synchronous communication, data is sent in blocks of
bytes; in asynchronous, data is sent one byte at a time. Data communication can
be simplex (can send but cannot receive), half duplex (can send and receive, but
not at the same time), or full duplex (can send and receive at the same time).
RS232 is a standard for serial communication connectors.
The PICI8's UARTwas discussed. We showed how to interface the PICI8
with an RS232 connector and change the baud rate of the PIC 18. In addition, we
described the serial communication features of the PIC 18, and programmed the
PIC 18 for serial data communication. We also showed how to program the serial
port of the PIC 18 chip in Assembly and C.
PROBLEMS
SECTION 10.1: BASICS OF SERIAL COMMUNICATION
I. Which is more expensive, parallel or serial data transfer?
2. True or false. 0- and 5-V digital pulses can be transferred on the telephone
without being converted (modulated).
3. Show the framing of the letter ASCII 'Z' (0101 1010), no parity, I stop bit.
4. If there is no data transfer and the line is high, it is called
(mark,
space).
5. True or false. The stop bit can be I, 2, or none at all.
6. Calculate the overhead percentage if the data size is 7, I stop bit, no parity.
7. True or false. RS232 voltage specification is TTL compatible.
8. What is the function of the MAX 232 chip?
9. True or false. DB-25 and DB-9 are pin compatible for the first 9 pins.
10. How many pins of the RS232 are used by the IBM serial cable, and why?
II. True or false. The longer the cable, the higher the data transfer baud rate.
12. State the absolute minimum number of signals needed to transfer data between
two PCs connected serially. What are those?
13. If two PCs are connected through the RS232 without the modem, both are configured as a
(DTE, DC E) -to(DTE, DCE) connection.
14. State the nine most important signals of the RS232.
15. Calculate the total number of bits transferred if 200 pages of ASCII data are
sent using asynchronous serial data transfer. Assume a data size of 8 bits, I
stop bit, and no parity. Assume each page has 80x25 of text characters.
16. In Problem 15, how long will the data transfer take if the baud rate is 9,600?
418
SECTION 10.2: PIC18 CONNECTION TO RS232
17. The MAX232 DIP package has _ _ pins.
18. For the MAX232, indicate the Vee and GND pins.
19. The MAX233 DIP package has __ pins.
20. For the MAX233, indicate the Vee and GND pins.
2l. Is the MAX232 pin compatible with the MAX233?
22. State the advantages and disadvantages of the MAX232 and MAX233.
23. MAX232/233 has
line driver(s) for the RX wire.
24. MAX232/233 has
line driver(s) for the TX wire.
25. Show the connection of pins TX and RX of the PIC18 to a DB-9 RS232 connector via the second set ofline drivers of MAX232.
26. Show the connection of the TX and RX pins of the PIC18 to a DB-9 RS232
connector via the second set ofline drivers ofMAX233.
27. What is the advantage of the MAX233 over the MAX232 chip?
28. Which pins of the PIC 18 are set aside for serial communication, and what are
their functions?
SECTION 10.3: PIC18 SERIAL PORT PROGRAMMING IN ASSEMBLY
29. Which of the following baud rates are supported by the HyperTerminal program in PC?
(a) 4,800
(b) 3,600
(c) 9,600
(d) 1,800
(e) 1,200
(f) 19,200
30. Which timer of the PIC 18 is used for baud rate programming?
3l. Which bit of the TXSTA is used for baud rate speed?
32. What is the role of the TXREG register in serial data transfer?
33. TXREG is a(n) __-bit register.
34. What is the role of the TXSTA register in serial data transfer?
35. TXSTA is a(n) __-bit register.
36. For XTAL = 10 MHz, find the SPBRG value (in both decimal and hex) for
each of the following baud rates.
(a) 9,600
(b) 4,800
(c) 1,200
37. What is the baud rate if we use SPBRG = 15 to program the baud rate? Assume
XTAL = 10 MHz.
38. Write a PIC18 program to transfer serially the letter 'z' continuously at 1,200
baud rate. Assume XTAL = 10 MHz.
39. Write a PIC18 program to transfer serially the message "The earth is but one
country and mankind its citizens" continuously at 57,600 baud rate. Assume
XTAL = 10 MHz.
40. When is the TXIF flag bit raised or cleared?
41. When is the RCIF flag bit raised or cleared?
42. To which register do RCIF and TXIF belong? Is that register bit-addressable?
43. What is the role of the SPEN bit in the RCSTA register?
44. In a given situation we cannot accept reception of any serial data. How do you
block such a reception with a single instruction?
CHAPTER 10: PIC1S SERIAL PORT PROGRAMMING IN ASSEMBLY AND C 419
45. To which register does the BRGH bit belong? State its role in rate of data transfer.
46. Is the BRGH bit HIGH or LOW when the PICl8 is powered up?
47. Find the SPBRG for the following baud rates if XTAL = 16 MHz and
BRGH=O.
(a) 9600
(b) 19200
(c) 38400
(d) 57600
48. Find the SPBRG for the following baud rates if XTAL = 16 MHz and
BRGH= 1.
(a) 9600
(b) 19200
(c) 38400
(d) 57600
49. Find the SPBRG for the following baud rates if XTAL = 20 MHz and
BRGH=O.
(b) 19200
(al 9600
(c) 38400
(d) 57600
50. Find the SPBRG for the following baud rates if XTAL = 20 MHz and
BRGH = 1.
(a) 9600
(b) 19200
(c) 38400
(d) 57600
51. Find the baud rate error for Problem 47.
52. Find the baud rate error for Problem 48.
SECTION 10.4: PICI8 SERIAL PORT PROGRAMMING IN C
53. Write an PICI8 C program to transfer serially the letter 'z' continuously at
1,200 baud rate.
54. Write an PICl8 C program to transfer serially the message 'The earth is but
one country and mankind its citizens" continuously at 57,600 baud rate.
ANSWERS TO REVIEW QUESTIONS
SECTION 10.1: BASICS OF SERIAL COMMUNICATION
1.
2.
3.
4.
5.
Faster, more expensive
False; it is simplex.
True
Asynchronous
With 0100 0101 binary the bits are transmitted in the sequence:
(a) 0 (start bit) (b) 1 (c) 0 (d) 1 (e) 0 (I) 0 (g) 0 (h) I (i) 0 (j) I (stop bit)
6. 2 bits (one for the start bit and one for the stop bit). Therefore, for each 8-bit character, a total
of 10 bits is transferred.
7. 10000 x 10 = 100000 total bits transmitted. 100000/9600 = lOA seconds; 2 / 10 = 20%.
8. True
9. +3 to +25 V
10. True
II. One
12. COM I. COM 2
420
SECTION 10.2: PICI8 CONNECTION TO RS232
1.
2.
3.
4.
5.
True
Pins RC6 and RC7. Pin RC6 is for TX and pin RC7 for RX.
They are used for converting from RS232 voltage levels to TTL voltage levels and vice versa.
Two, two
It does not need the four capacitors that MAX232 must have.
SECTION 10.3: PICI8 SERIAL PORT PROGRAMMING IN ASSEMBLY
SPBRG
156,250 Hz
BRGH
15 in decimal (or F in hex) because 156,250/9600 - 1 = 15
TXREG
Transmit Status and Control Register, 8
TXSTA
True
It is raised during transfer of the stop bit. It is cleared when we write a byte to TXREG to be
transmitted.
10. TXSTA; it is low upon power-on reset.
1.
2.
3.
4.
5.
6.
7.
8.
9.
SECTION 10.4: PIC18 SERIAL PORT PROGRAMMING IN C
1.
2.
3.
4.
5.
True
True
True
SPBRG
TXSTA. It allows us to quadruple the baud rate with the sarne crystal frequency.
CHAPTER 10: PIC1S SERIAL PORT PROGRAMMING IN ASSEMBLY AND C 421
CHAPTER 11
INTERRUPT
PROGRAMMING IN
ASSEMBLY AND C
OBJECTIVES
Upon completion ofthis chapter, you will be able to:
»
»
»
»
»
»
»
»
»
»
Contrast and compare interrupts versus polling
Explain the purpose ofthe ISR (interrupt service routine)
List all the major interrupts ofthe PIC18
Explain the purpose of the interrupt vector table
Enable or disable PIC18 interrupts
Program the PIC18 timers using interrupts
Describe the external hardware interrupts of the PIC18
Program the PIC18 for interrupt-based serial communication
Define the interrupt priority of the PIC18
Program PIC interrupts in C
423
In this chapter we explore the concept of the interrupt and interrupt programming. In Section 11.1, the basics of PIC 18 interrupts are discussed. In Section
11.2, interrupts belonging to timers are discussed. External hardware interrupts are
discussed in Section 11.3, while the interrupt related to serial communication is
presented in Section 11.4. In Section 11.5, we cover the interrupt associated with
PORTB. In Section 11.6, we cover interrupt priority. Throughout this chapter, we
provide examples in both Assembly and C.
SECTION 11.1: PIC18 INTERRUPTS
In this section, first we examine the difference between polling and interrupts and then describe the various interrupts of the PICI8.
Interrupts vs. polling
A single microcontroller can serve several devices. There are two methods
by which devices receive service from the microcontroller: interrupts or polling.
In the interrupt method, whenever any device needs the microcontroller's service,
the device notifies it by sending an interrupt signal. Upon receiving an interrupt
signal, the microcontroller stops whatever it is doing and serves the device. The
program associated with the interrupt is called the interrupt service routine (ISR)
or interrupt handler. In polling, the microcontroller continuously monitors the status of a given device; when the status condition is met, it performs the service.
After that, it moves on to monitor the next device until each one is serviced.
Although polling can monitor the status of several devices and serve each of them
as certain conditions are met, it is not an efficient use of the microcontroller. The
advantage of interrupts is that the microcontroller can serve many devices (not all
at the same time, of course); each device can get the attention of the microcontroller based on the priority assigned to it. The polling method cannot assign priority because it checks all devices in a round-robin fashion. More importantly, in
the interrupt method the microcontroller can also ignore (mask) a device request
for service. This also is not possible with the polling method. The most important
reason that the interrupt method is preferable is that the polling method wastes
much of the microcontroller's time by polling devices that do not need service. So
interrupts are used to avoid tying down the microcontroller. For example, in discussing timers in Chapter 9 we used the bit test instruction "BTFSS TMRO IF"
and waited until the timer rolled over, and while we were waiting we could not do
anything else. That is a waste of microcontroller time that could have been used to
perform some useful tasks. In the case of the timer, if we use the interrupt method,
the microcontroller can go about doing other tasks, and when the TMROIF flag is
raised, the timer will interrupt the microcontroller in whatever it is doing.
Interrupt service routine
For every interrupt, there must be an interrupt service routine (ISR), or
interrupt handler. When an interrupt is invoked, the microcontroller runs the interrupt service routine. Generally, in most microprocessors, for every interrupt there
is a fixed location in memory that holds the address of its ISR. The group of memory locations set aside to hold the addresses of ISRs is called the interrupt vector
424
table. In the case of the PIC 18, there are only two locations for the interrupt vector table, locations 0008 and 0018, as shown in Table II-I. We will discuss the difference between these two in Section 11.6 when we cover interrupt priority.
Table 11-1: Interrupt Vector Table for the PIC18
Interrupt
Power-on Reset
High Priority Interrupt
Low Priority Interrupt
ROM Location (Hex)
0000
0008 (Default upon power-on reset)
0018 (See Section 11.6)
Steps in executing an interrupt
Upon activation of an interrupt, the microcontroller goes through the following steps:
I. It finishes the instruction it is executing and saves the address of the next
instruction (program counter) on the stack.
2. It jumps to a fixed location in memory called the interrupt vector table. The
interrupt vector table directs the microcontroller to the address of the interrupt
service routine (ISR).
3. The microcontroller gets the address of the ISR from the interrupt vector table
and jumps to it. It starts to execute the interrupt service subroutine until it
reaches the last instruction of the subroutine, which is RETFIE (return from
interrupt exit).
4. Upon executing the RETFIE instruction, the microcontroller returns to the
place where it was interrupted. First, it gets the program counter (PC) address
from the stack by popping the top bytes of the stack into the PC. Then it starts
to execute from that address.
Notice from Step 4 the critical role of the stack. For this reason, we must
be careful in manipulating the stack contents in the ISR. Specifically, in the ISR,
just as in any CALL subroutine, the number of pushes and pops must be equal.
Sources of interrupts in the PIC18
There are many sources of interrupts in the PIC 18, depending on which
peripheral is incorporated into the chip. The following are some of the most widely used sources of interrupts in the PIC 18:
I. There is an interrupt set aside for each of the timers, Timers 0, 1,2, and so on.
See Section 11.2.
2. Three interrupts are set aside for external hardware interrupts. Pins RBO
(PORTB.O), RBI (PORTB.I), and RB2 (PORTB.2) are for the external hardware interrupts INTO, INTI, and INT2, respectively. See Section 11.3.
3. Serial communication's USART has two interrupts, one for receive and another for transmit. See Section 11.4.
4. The PORTB-Change interrupt. See Section ll.S.
5. The ADC (analog-to-digital converter). See Chapter 13.
6. The CCP (compare capture pulse-width-modulation). See Chapters 15 and 17.
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
425
The PIC I 8 has many more interrupts than the above list shows. We will
cover them throughout the book as we study the peripherals of the PICI8. Notice
in Table I I - I that a limited number of bytes is set aside for high-priority interrupts.
For example, a total of 8 bytes, from location 0008 to 00001 7H, are set aside for
high-priority interrupts. Normally, the service routine for an interrupt is too long
to fit in the memory space allocated. For that reason, a GOTO instruction is placed
in the vector table to point to the address ofthe rSR. The rest of the bytes allocated to the interrupt are unused. In upcoming sections of this chapter, we will see
many examples of interrupt programming that clarify these concepts.
From Table II - I, also notice that only 8 bytes of ROM space are assigned
to the reset pin. They are ROM address locations 0-7. For this reason, in our program we put the GOTO as the first instruction and redirect the processor away
from the interrupt vector table, as shown in Figure I I - I. In the next section we will
see how this works in the context of some examples.
ORG 0
;wake-up ROM reset location
GOTO MAIN ;bypass interrupt vector table
;---- the wake-up program
ORG lOOH
MAIN:
;enable interrupt flags
END
Figure 11-1. Redirecting the PIeIS from the Interrupt Vector Table at Power-Up
TMR11F
TMR21F
TXIF
RXIF
vector
location
OxOOOB
Other
Peripheral
Interrupts
PEIE
(PEripheral
Interrupt Enable)
GIE
(Global Interrupt
Enable)
Figure 11-2. Simplified View ofInterrupts (default for power-on reset)
Enabling and disabling an interrupt
Upon reset, all interrupts are disabled (masked), meaning that none will be
responded to by the microcontroller if they are activated. The interrupts must be
enabled (unmasked) by software in order for the microcontroller to respond to
them. The D7 bit of the INTCON (Interrupt Control) register is responsible for
426
enabling and disabling the interrupts globally. Figure 11-3 shows the INTCON
register. The GIE bit makes the job of disabling all the interrupts easy. With a single instruction (BCF INTCON,GIE), we can make GIE = 0 during the operation
of a critical task. See Figure 11-2.
Steps in enabling an interrupt
To enable anyone of the interrupts, we take the following steps:
I. Bit D7 (GIE) of the INTCON register must be set to HIGH to allow the interrupts to happen. This is done with the "BSF INTCON, GIE" instruction.
2. If GIE = I, each interrupt is enabled by setting to HIGH the interrupt enable
(IE) flag bit for that interrupt. Because there are a large number of interrupts
in the PICI8, we have many registers holding the interrupt enable bit. Figure
11-2 shows that the INTCON has interrupt enable bits for TimerO (TMROIE)
and external interrupt 0 (INTOIE). As we study each of peripherals throughout
the book we will examine the registers holding the interrupt enable bits. It must
be noted that if GIE = 0, no interrupt will be responded to, even if the corresponding interrupt enable bit is high. To understand this important point look
at Example 11-1.
3. As shown in Figures 11-2 and 11-3, for some of the peripheral interrupts such
as TMRlIF, TMR2IF, and TXIF, we have to enable the PEIE flag in addition
to the GIE bit.
D7
OlE
DO
ITMROIE I INTOIE I
GIE (Global Interrupt Enable)
GIE = 0 Disables all interrupts. If GIE = 0, no interrupt is ackoowledged, even if
they are enabled individually.
If OlE = I, interrupts are allowed to happen. Each interrupt source is enabled by setting the corresponding interrupt enable bit.
TMROIE
TimerO interrupt enable
= 0 Disables TimerO overflow interrupt
= I Enables TimerO overflow interrupt
INTOIE
Enables or disables external interrupt 0
= 0 Disables external interrupt 0
= I Enables external interrupt 0
These bits, along with the OlE, must be set high for an interrupt to be responded to.
Upon activation of the interrupt, the GIE bit is cleared by the Plel8 itself to make sure
another interrupt cannot interrupt the microcontroller while it is servicing the current
one. At the end of the ISR, the RETFIE instruction will make OlE = I to allow another
interrupt to come in.
PEIE (PEripheral Interrupt Enable)
For many of the peripherals, such as Timers I, 2, .. and the serial port, we must enable
this bit in addition to the OlE bit (See Figure 11-2.)
Figure 11-3. INTCON (Interrupt Control) Register
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
427
Example 11-1
Show the instructions to (a) enable (unmask) the TimerO interrupt and external hardware
interrupt 0 (INTO), and (b) disable (mask) the TimerO interrupt, then (c) show how to
disable (mask) all the interrupts with a single instruction.
Solution:
(~
BSF INTCON,TMROIE
; enable (unmask) TimerO interrupt
BSF INTCON,INTOIE ;enable external interrupt 1(INTO)
BSF INTCON,GIE ;allow interrupts to come in
We can perform the above actions with the following two instructions:
MOVLW B'10110000'
MOVWF INTCON
;GIE = 1, TMROIF = 1,INTIFO = 1
;load the INTCON reg
~)
BCF INTCON,TMROIE ;mask (disable) TimerO interrupt
(c)
BCF INTCON,GIE
;mask all interrupts globally
Review Questions
1. Ofthe interrupt and polling methods, which one avoids tying down the microcontroller?
2. Give the name of the interrupts in the INTCON register.
3. Upon power-on reset of the PICI8, what memory area is assigned to the interrupt vector table? Can the programmer change the memory space assigned to
the table?
4. What is the content ofD7 (GIE) of the INTCON register upon reset, and what
does it mean?
5. Show the instruction needed to enable the TMRO interrupt.
6. What address in the interrupt vector table is assigned to high-priority and lowpriority interrupts?
428
SECTION 11.2: PROGRAMMING TIMER INTERRUPTS
In Chapter 9 we discussed how to use Timers 0, I, 2, and 3 with the polling
method, In this section we use interrupts to program the PIC 18 timers. Please
review Chapter 9 before you study this section.
Rollover timer flag and interrupt
In Chapter 9 we stated that the timer flag is raised when the timer rolls
over. In that chapter, we also showed how to monitor the timer flag with the
instruction "BTFSS TMROIF". In polling TMROIF, we have to wait until
TMROIF is raised. The problem with this method is that the microcontroller is tied
down waiting for TMROIF to be raised, and cannot do anything else. Using interrupts avoids tying down the controller. If the timer interrupt in the interrupt register is enabled, TMROIF is raised whenever the timer rolls over and the microcontroller jumps to the interrupt vector table to service the ISR. In this way, the microcontroller can do other things until it is notified that the timer has rolled over. To
use an interrupt in place of polling, first we must enable the interrupt because all
the interrupts are masked upon power-on reset. The TMRxIE bit enables the interrupt for a given timer. TMRxIE bits are held by various registers as shown in Table
11-2. In the case of TimerO, the INTCON register (Figure 11-4) contains the
TMROIE bit, and PIE I (peripheral interrupt enable) holds the TMRIIE bit. See
Figure 11-5 and Program 11-1.
Table 11-2: Timer Interrupt Flag Bits and Associated Registers
Interrupt Flag Bit Register
Enable Bit Register
TimerO TMROIF INTCON
TMROIE
INTCON
TMRIIE
PIEI
Timerl
TMRIIF PIRI
Timer2 TMR2IF PIRI
TMR2IE
PIE I
Timer3 TMR3IF PIR3
TMR3IE
PIE2
I TMROIE I
I TMROlF I
Figure 11-4. INTCON Register with TimerO Interrupt Enable and Interrupt Flag
TMR11F
TMR11E
TMROIF
TMROIE
vector
location
OxOO08
TMR21F
TMR21E
GIE
PEIE
(PEripheral Interrupt
Enable)
Figure 11-5. The Role of Timer Interrupt Enable Flag (TMRxIE)
Note: The TMRxlP (timer interrupt priority) flag is not shown. TMRxIP is used to force
the interrupt to land at vector location OxOOI8. See Section 11.6.
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
429
Notice the following points about Program II-I:
I. We must avoid using the memory space allocated to the interrupt vector table.
Therefore, we place all the initialization codes in memory starting at an
address such as 100H. The GOTO instruction is the first instruction that the
PICI8 executes when it is awakened at address 00000 upon power-on reset
(POR). The GOTO instruction at address 00000 redirects the controller away
from the interrupt vector table.
2. In the MAIN program, we enable (unmask) the TimerO interrupt with instruction "BSF INTCON, TMROIE" followed by the instruction "BSF INTCON, GI E" to enable all interrupts globally.
3. In the MAIN program, we initialize the TimerO register and then enter an infinite loop to keep the CPU busy. This could be a real-world application being
executed by the CPU. In this case, the loop gets data from PORTC and sends
it to PORTD. While the PORTC data is brought in and issued to PORTD continuously, the TMROIF flag is raised as soon as TimerO rolls over, and the
microcontroller gets out of the loop and goes to 00008H to execute the ISR
associated with TimerO. At this point, the PICI8 clears the GIE bit (D7 of
INTCON) to indicate that it is currently serving an interrupt and cannot be
interrupted again; in other words, no interrupt inside the interrupt. In Section
11.6, we show how to allow an interrupt inside an interrupt.
4. The ISR for TimerO is located starting at memory location 00200H because it
is too large to fit into address space 08-17H, the address allocated to high-priority interrupts.
5. In the ISR for TimerO, notice that the "BCF INTCON, TMROIF" instruction
is needed before the RETFIE instruction. This will ensure that a single interrupt is serviced once and is not recognized as multiple interrupts.
6. RETFIE must be the last instruction of the ISR. Upon execution of the RETFIE instruction, the PICI8 automatically enables the GIE (D7 of the INTCON
register) to indicate that it can accept new interrupts.
Program II-I: For this program, we assume that PORTC is connected to 8 switches and PORTO to 8 LEOs. This program uses TimerO to generate a square wave on pin
PORTB.5, while at the same time data is being transferred from PORTC to PORTO.
;Program 11-1
ORG
OOOOH
GOTO MAIN
;bypass interrupt vector table
;--on default all interrupts land at address 00008
ORG
0008H
; interrupt vector table
BTFSS INTCON,TMROIF
;TimerO interrupt?
RETFIE
;No. Then return to main
GOTO TO ISR
;Yes. Then go TimerO ISR
;--main program for initialization and keeping CPU busy
ORG
00100H
;after vector table space
;PB5 as an output
MAIN BCF TRISB,5
CLRF TRISD
;make PORTD output
;make PORTC input
SETF TRISC
430
MOVLW Ox08
;TimerO,16-bit,
;no preseale,internal elk
MOVWF TOCON
;load TOCON reg
MOVLW OxFF
;TMROH = FFH, the high byte
MOVWF TMROH
;load TimerO high byte
MOVLW OxF2
;TMROL = F2H, the low byte
MOVWF TMROL
;load TimerO low byte
BCF INTCON,TMROIF;elear timer interrupt flag bit
BSF TOCON,TMROON
;start TimerO
BSF INTCON,TMROIE
;enable Timer 0 interrupt
BSF INTCON,GIE
;enable interrupts globally
;--keeping CPU busy waiting for interrupt
OVER MOVFF PORTC,PORTD ;send data from PORTC to PORTD
BRA OVER
;stay in this loop forever
;--------------------------ISR for Timer 0
TO ISR
ORG 200H
MOVLW OxFF
; TMROH = FFH, the high byte
MOVWF TMROH
; load TimerO high byte
MOVLW OxF2
; TMROL = F2H, the low byte
MOVWF TMROL
;load TimerO low byte
BTG
PORTB,S
;toggle RBS
BCF INTCON,TMROIF ;elear timer interrupt flag bit
EXIT RETFIE ;return from interrupt (See Example 11-2)
END
Example 11-2
What is the difference between the RETURN and RETFIE instructions? Explain why
we cannot use RETURN instead of RETFIE as the last instruction of an ISR.
Solution:
Both perform the same actions of popping off the top bytes of the stack into the program
counter, and making the PIC18 return to where it left off. However, RETFIE also performs the additional task of clearing the GIE flag, indicating that the servicing of the
interrupt is over and the PIC18 now can accept a new interrupt. If you use RETURN
instead of RETFIE as the last instruction of the interrupt service routine, you simply
block any new interrupt after the first interrupt, because the GIE would indicate that the
interrupt is still being serviced.
In Program 11-1, the TimerO ISR (interrupt service routine) was too long
to be placed in memory locations allocated to the high interrupt (addresses of
0008-00017H). There was enough space, however, to test to see which interrupt
was the cause of landing at the 0008 address. Very often, we go from address 0008
to another address with a larger space to check the source of the interrupt, given
the fact that the PIC 18 has so many interrupts and we have limited space at address
0008. See Program 11-2.
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
431
Program 11-2 uses TimerO and Timer! interrupts to generate square waves on pins
RB! and RB7 respectively, while data is being transferred from PORTe to PORTO.
;Program 11-2
ORG
OOOOH
GOTO MAIN
;bypass interrupt vector table
;--on default all interrupts land at address 00008
ORG
0008H
;interrupt vector table
GOTO CHK INT
;90 to an address with more space
;--check to see the source of interrupt
ORG
0040H
;we got here from 0008
CHK INT
BTFSC INTCON,TMROIF
iIs it TimerO interrupt?
BRA TO ISR
;Yes. Then branch to TO ISR
BTFSC PIRl,TMRlIF
;Is it Timerl interrupt?
BRA Tl ISR
; Yes. Then branch to Tl ISR
RETFIE
;No. Then return to main
;-main program for initialization and keeping CPU busy
ORG
OIOOH ;somewhere after vector table space
MAIN BCF TRISB, 1
; PBl as an output
BCF TRISB,7
;PB7 as an output
;make PORTD output
CLRF TRISD
;make PORTC input
SETF TRISC
;TimerO,16-bit,
MOVLW Ox08
;no prescale,internal clk
MOVWF TOCON
;load TOCON reg
MOVLW OxFF
;TMROH ~ FFH, the high byte
MOVWF TMROH
;load TimerO high byte
MOVLWOxF2
;TMROL ~ F2H, the low byte
MOVWF TMROL
;load TimerO low byte
BCF INTCON,TMROIF;clear TimerO interrupt flag bit
MOVLW OxO
;Timerl,16-bit,
ina prescale,internal
elk
MOVWF TICON
;load TICON reg
;TMRIH ~ FFH, the high byte
MOVLW OxFF
MOVWF TMRIH
;load TimerO high byte
;TMRIL ~ F2H, the low byte
MOVLW OxF2
MOVWF TMRIL
;load Timerl low byte
BCF PIRl,TMRlIF ;clear Timerl interrupt flag bit
BSF INTCON,TMROIE
;enable TimerO interrupt
BSF PIEl,TMRlIE
;enable Timerl interrupt
BSF INTCON,PEIE ;enable peripheral interrupts
BSF INTCON,GIE
;enable interrupts globally
BSF TOCON,TMROON
;start TimerO
BSF TlCON,TMRlON
;start Timerl
;--keeping CPU busy waiting for interrupt
OVER MOVFF PORTC,PORTD ;send data from PORTC to PORTD
BRA OVER
;stay in this loop forever
;--------------------------ISR for Timer 0
TO ISR
ORG 200H
432
MOVLW OxFF
;TMROH = FFH, the high byte
;load TimerO high byte
MOVWF TMROH
;TMROL = F2H, the low byte
MOVLW OxF2
;load TimerO low byte
MOVWF TMROL
BTG
PORTB,l
;toggle PB1
BCF INTCON,TMROIF ;clear timer interrupt flag bit
GOTO CHK INT
;--------------------------ISR for Timer1
T1 ISR
ORG 300H
;TMR1H = FFH, the high byte
MOVLW OxFF
;load TimerO high byte
MOVWF TMR1H
;TMR1L = F2H, the low byte
MOVLW OxF2
MOVWF TMR1L
;load Timer1 low byte
BTG PORTB,?
BCF PIR1,TMR1IF ;clear Timer1 interrupt flag bit
GOTO CHK INT
END
Notice that the addresses 0040H
LED
OIOOH, 00200H, and 0300H that we used in'J1..f"L
PORTB.6
T1CKI (RCO)
Program 11-2 are all arbitrary and can be
(PORTC.O)
changed to any addresses we want. The only
addresses that we have no choice on are the
power-on reset location of 0000 and highpriority address of 0008 because they were
fixed at the time of the PIel8 design.
FIgure 11-6. For Program 11-3
Program 11-3 has two interrupts: (I) PORTO counts up everytime TimerO overflows. It uses 16-bit mode of TimerO with the largest prescale possible; (2) I-Hz pulse is
fed into Timer! where Timer! is used as counter and counts up. Whenever the count
reaches 200, it will toggle the pin PORTB.6.
;Program 11-3
ORG
OOOOH
GOTO MAIN
;bypass interrupt vector table
;--on default all interrupts land at address 00008
ORG
0008H
GOTO CHK INT
;-----------------find the interrupt source
ORG
0040H
CHK INT
iIS it TimerO interrupt?
BTFSC INTCON,TMROIF
;Yes. Then branch to TO ISR
BRA
TO ISR
BTFSC PIR1,TMR1IF
iIs it Timerl interrupt?
BRA
T1 ISR
;Yes. Then branch to T1 ISR
RETFIE
iNa. Then return to main
;--the main program for initialization
ORG
00100H
; after vector table space
MAIN BSF TRISC, T13CKI
; PORTC. 0 as an input
CLRF TRISD
;make PORTD output
BCF TRISB,6
;make RB6 output
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
433
;16-bit, prescale
256,
;internal clk
MOVWF TOCON
;load TOCON reg
MOVLW OxOO
;TMROH = OOH, the high byte
MOVWF TMROH
; load TimerO high byte
MOVLW OxOO
; TMROL = 0, the low byte
MOVWF TMROL
;load TimerO low byte
BCF INTCON,TMROIF ;clear timer interrupt flag bit
MOVLW Ox6
;Timerl, no prescale,
;ext. clock
; load TICON reg
MOVWF TlCON
MOVLW D'255'
;TMRIH = 255
;load Timerl high byte
MOVWF TMRIH
;TMRIL = 0
MOVLW -D'200'
;load Timerl low byte
MOVWF TMRIL
BCF PIRl,TMRlIF ;clear timer interrupt flag bit
BSF TOCON,TMROON
;start TimerO
BSF TICON,TMRION
;start Timerl
BSF INTCON,TMROIE
;enable TimerO interrupt
BSF PIEl,TMRlIE
;enable Timerl interrupt
BSF INTCON,PEIE ;enable peripheral interrupts
BSF INTCON,GIE
;enable interrupts globally
OVER BRA OVER
; stay in this loop forever
;--------------------------ISR for TimerO
TO ISR
ORG 200H
;increment PORTD
INCF PORTD
MOVLWOxOO
;TMROL = 0, the low byte
MOVWF TMROL
;load TimerO low byte
MOVLW OxO 0
; TMROH = 00, the high byte
MOVWF TMROH
; load TimerO high byte
BCF INTCON,TMROIF ;clear timer interrupt flag bit
GOTO CHK INT
;--------------------------ISR for Timer2
Tl ISR
ORG 300H
BTG PORTB,6
;toggle PORTC.6
;TMRIH = 255
MOVLW D' 255'
MOVWF TMRIH
;load Timerl high byte
; TMRIL = 0
MOVLW -D' 200'
;load Timerl low byte
MOVWF TMRIL
BCF PIRl,TMRlIF ;clear Timerl interrupt flag bit
GOTO CHK INT
END
MOVLW Ox08
Notice in Programs 11-2 and 11-3 that we use the "GOTO CHK_INT" instruction
instead of RETFIE as the last instruction of the ISR. This is because we are checking for activation of multiple interrupts.
434
PIC18 interrupt programming in C using C18 compiler
In Chapter 7, we discussed how the C 18 compiler uses "#pragma code" to
place code at a specific ROM address, Because the Cl8 does not place an ISR at
the interrupt vector table automatically, we must use Assembly language instruction GOTO at the interrupt vector to transfer control to the ISR. This is done as follows:
#pragma code high _vector =Ox0008 II High-priority interrupt location
void My_HiVecUnt (void)
{
asm
GOTOmy_isr
endasm
}
#pragma code
II End of code
Now we redirect it from address location 00008 to another program to find
the source of the interrupt and finally to the ISR. This is done with the help of the
keyword interrupt as follows:
#pragma interrupt my_isr
void my_isr (void)
{
Ilinterrupt is reserved keyword
Ilused for high-priority interrupt
//C18 places RETFIE here automatically due to
//interrupt keyword
}
Note that "pragma", "code", and "interrupts" are reserved keywords while
the choice of all other labels is up to us. Examine Programs 11-2C and 11-3C.
They are the C versions of Programs 11-2 and 11-3.
Program 11-2C uses TimerO and Timer! interrupts to generate square waves on
pins RBI and RB7, respectively, while data is being transferred from PORTC to PORTD.
This is a C version of Program 11-2.
//program 11-2C (C version of Program 11-2)
#include <p18F458.h>
#define myPB1bit PORTBbits.RB1
#define myPB7bit PORTBbits.RB7
void TO_ISR(void) ;
void T1_ISR(void);
#pragma interrupt chk_isr
//used for high-priority
//interrupt only
void chk isr (void)
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
435
if
(INTCONbits.TMROIF==l)
TO_ISR() ;
if (PIR1bits.TMR1IF==1)
T1ISR();
IITimerO causes interrupt?
IIYes. Execute TimerO ISR
IIOr was it Timer1?
II Yes. Execute Timer1 ISR
}
#pragma code My_HiPrio_Int=OxOBllhigh-priority interrupt
void My_HiPrio Int (void)
{
asm
GOTO chk isr
endasm
#pragma code
void main (void)
{
TRISBbits.TRISB1=0;
IIRB1 = OUTPUT
TRISBbits.TRISB?=O;
IIRB? = OUTPUT
TRISC = 255;
IlpORTC = INPUT
TRISD = 0;
IlpORTD = OUTPUT
TOCON=OxO;
IITimer 0, 16-bit mode, no prescaler
TMROH=Ox35;
Ilload THO
TMROL=OxOO;
Ilload TLO
T1CON=OxBB;
IITimer 1, 16-bit mode, no prescaler
TMR1H=Ox35;
Ilload TH1
TMR1L=OxOO;
Ilload TL1
INTCONbits.TMROIF=O;
Ilclear TFO
PIR1bits.TMR1IF=O;
Ilclear TF1
INTCONbits.TMROIE=l;
lienable TimerO interrupt
INTCONbits.TMROIE=l;
lienable Timer1 interrupt
TOCONbits.TMROON=l;
Iiturn on TimerO
T1CONbits.TMR10N=1;
Iiturn on Timer1
INTCONbits.PEIE=l;llenable all peripheral interrupts
INTCONbits.GIE=l; lienable all interrupts globally
while (1)
Ilkeep looping until interrupt comes
{
PORTD=PORTC;
Iisend data from PORTC to PORTD
void TO ISR(void)
{
myPB1bit=-myPB1bit;
TMROH=Ox35;
TMROL=OxOO;
INTCONbits.TMROIF=O;
Iitoggle PORTB.1
Ilload THO
Ilload TLO
Ilclear TFO
}
void T1 ISR(void)
myPB?bit=-myPB?bit;
436
Iitoggle PORTB.?
TMRIH=Ox35;
TMRIL=OxOO;
PIRlbits.TMRlIF=O;
((load THO
((load TLO
((clear TFl
Program 11-3C shows the C version of Program 11-3.
Program 11-3C has two interrupts: (I) PORTC counts up every time TimerO overflows. It uses the 16-bit mode of TimerO with the largest prescale possible; (2) a I-Hz
pulse is fed into Timer! where Timer! is used as a counter and counts up. Whenever the
count reaches 200, it will toggle pin RB6.
((Program 11-3C
#include <plBF45B.h>
#define myPB6bit PORTBbits.RB6
void chk_isr(void);
void TO ISR(void);
void Tl ISR(void);
#pragma interrupt chk_isr ((for high-priority interrupt only
void chk_isr (void)
{
if (INTCONbits.TMROIF==l)
((TimerO causes interrupt?
TO_ISR( );
((Yes. Execute TimerO program
if (PIRlbits.TMRlIF==l) ((Or was it Timer2?
Tl ISR();
((Yes. Execute Timer2 program
)
#pragma code My_HiPrio Int=OxOOOB ((high-priority interrupt
void My_HiPrio_Int (void)
asm
GO TO chk isr
endasm
)
#pragma code
void main (void)
TRISBbits.TRISB6=O;
TRISCbits.TRISCO=l;
TRISD=O;
TOCON=OxOB;
TMROH=O;
TMROL=O;
TICON=Ox06;
TMRIH=255;
TMRIL=-200;
INTCONbits.TMROIF=O;
PIRlbits.TMRlIF=O;
((RB6 = OUTPUT
((PORTCO = INPUT
((TimerO, 16-bit mode,
((no prescaler
((load TimerO high byte
((load TimerO low byte
((Timer 2, no prescaler
((load Timerl high byte
((load Timerl low byte
((clear TFO
((clear TFl
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
437
INTCONbits.TMROIE=l; lienable TimerO interrupt
PIElbits.TMR1IE=1;
lienable Timerl interrupt
TOCONbits.TMROON=l;
Iiturn on TimerO
T1CONbits.TMR10N=1;
Iiturn on Timerl
INTCONbits.PEIE=l;llenable all peripheral interrupts
INTCONbits.GIE=l;
lienable all interrupts globally
while(l); Ilkeep looping until interrupt comes
}
void TO_ISR(void)
{
PORTD++;
TMROH=O;
TMROL=O;
INTCONbits.TMROIF=O;
Ilcount up PORTD
Ilload TimerO high byte
Ilload TimerO low byte
Ilclear TFO
}
void Tl ISR(void)
{
myPB6bit=-myPB6bit;
TMR1H=255;
TMR1L=-200;
PIRlbits.TMR2IF=O;
Iitoggle PB.6
Ilload Timerl high byte
Ilload Timerl low byte
Ilclear TFl
Review Questions
I. True or false. A unique address in the interrupt vector table is assigned to each
of TimerO-Timer3.
2. Upon power-on reset, what address in the interrupt vector table is assigned to
the high-priority interrupt?
3. Which register does TMRIIE belong to? Show how it is enabled.
4. Assume that Timer! is programmed in 8-bit mode, TMRIL = F5H, and the
TMRIIF bit is enabled. Explain how the interrupt for the timer works.
5. True or false. The last two instructions of the ISR for TimerO are:
BCF INTCON,TMROIF
RETFIE
438
SECTION 11.3: PROGRAMMING EXTERNAL HARDWARE
INTERRUPTS
The PIC 18 has three external hardware interrupts. Pins RBO (PORTB.O),
RBI (PORTB.I), and RB2 (PORTB.2), designated as INTO, INTI, and INT2
respectively, are used as external hardware interrupts. Upon activation of these
pins, the PIC 18 gets interrupted in whatever it is doing and jumps to the vector
table to perform the interrupt service routine. In this section we study these three
external hardware interrupts of the PICI8 with some examples in both Assembly
andC.
External interrupts INTO, INT1, and INT2
There are three external hardware interrupts in the Plel8: INTO, INTI, and INT2. They
are located on pins RBO, RBI, and RB2, respectively. See Figures 11-7 and 11-8. On
default, all three hardware interrupts are directed to vector table location 0008H, unless
we specify otherwise. They must be enabled before they can take effect. This is done
using the INTxIE bit. The registers associated with INTxIE bits are shown in Table 113. For example, the instruction "BSF INTCON, INTO IE" enables INTO. The INTO
is a positive-edge-triggered interrupt, which means, when a low-to-high signal is
applied to pin RBO (PORTB.O), the INTOIF is raised, causing the controller to be interrupted. The raising ofINTOIF forces the Plel8 to jump to location 0008H in the vector
table to service the ISR. In Table 11-3, notice the INTxlF bits and the registers they
belong to. Upon power-on reset, the Plel8 makes INTO, INTI, and INT2 rising (positive) edge-triggered interrupts. To make them falling (negative) edge-triggered interrupts, we must program the INTEDGx bits, as we will see shortly.
Examine Program 11-4 and its C version, Program 11-4C, to gain insight into
external hardware interrupts.
Table 11-3: Hardware Interrupt Flag Bits and Associated Registers
Interrupt (Pin) Flag bit
Register
Enable bit
Register
INTO (RBO)
INTI (RBI)
INT2 (RB2)
INTCON
INTCON3
INTCON3
INTOIE
INTlIE
INT2IE
INTCON
INTCON3
INTCON3
INTOIF
INTI IF
INT2IF
5
36
6
7
PIC18F452/458 35
(DIP)
8
33
34
-.....
INT2 (PORTB.2 or RB2)
INT1 (PORTB.1 orRB1)
INTO (PORTB.O or RBO)
Figure 11-7. PIC18 External Hardware Interrupt Pins
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
439
INTOIF
INTOIE
INT1IF
INT11E
INT21F
INT21E
vector
location
TMR11F
TMR21F
TXIF
RXIF
other
Peripheral
Interrupts
Ox0008
PEIE
(PEripheral Interrupt
Enable)
Figure 11-8. INTO--INT2 Hardware Interrupts
Program 11-4 connects a switch to INTO and
an LED to pin RB7. In this program, every time
INTO is activated, it toggles the LED, while at the
same time data is being transferred from PORTe to
PORTD.
Switch
INTO (RBO)
(PORTB.O)
LED
PORTB.7
Figure 11-9. For Program 11-4
;Program 11-4
ORG
OOOOH
;bypass interrupt vector table
GOTO MAIN
;--on default all interrupts go to to address 00008
ORG
0008H
;interrupt vector table
BTFSS INTCON,INTOIF
;Did we get here due to INTO?
iNa. Then return to main
RETFIE
GOTO INTO ISR
;Yes. Then go INTO ISR
;;--the main program for initialization
ORG
00100H
MAIN BCF TRISB,7
;PB7 as an output
BSF TRISB,INTO
;make INTO an input pin
CLRF TRISD
;make PORTD output
;make PORTC input
SETF TRISC
;enable INTO interrupt
BSF INTCON,INTOIE
;enable interrupts globally
BSF INTCON, GIE
OVER MOVFF PORTC, PORTD
;send data from PORTC to PORTD
BRA OVER
;stay in this loop forever
;--------------------------ISR for INTO
INTO ISR
ORG 200H
BTG PORTB,7
;toggle PB7
BCF INTCON,INTOIF
;clear INTO interrupt flag bit
;return from ISR
RETFIE
END
440
Look at Program 11-4. When a rising edge of the signal is applied to pin
INTO, the LED will toggle. In this example, to toggle the LED again, the INTO
pulse must be brought back LOW and then forced HIGH to create a rising edge to
activate the interrupt.
II Program 11-4C (This is the C version of Program 11-4)
#inc1ude <p18F4580.h>
#define mybit PORTBbits.RB7
void chk_isr(void);
void INTO_ISR(void);
#pragma interrupt chk_isrllused for high-priority int
void chk_isr (void)
(
if (INTCONbits.INTOIF==l)
INTOISR();
IIINTO caused interrupt?
IIYes. Execute INTO program
}
#pragma code My_HiPrio_Int=Ox08
Ilhigh-priority
Ilinterrupt location
asm
GOTO chk isr
endasm
#pragma code
void main (void)
(
TRISBbits.TRISB7=O;
IIRB7 = OUTPUT
TRISBbits.TRISBO=l;
IIINTO = INPUT
TRISC = OxFF;
IIPORTC = INPUT
TRISD = 0;
IlpORTD = OUTPUT
INTCONbits.INTOIF=O; Ilclear TFl
INTCONbits.INTOIE=l; lienable TimerO interrupt
INTCONbits.GIE=l;
lienable all interrupts
while (1)
Ilkeep looping until interrupt comes
{
PORTD=PORTC;
}
}
void INTO ISR(void)
{
mybit=-mybit;
INTCONbits.INTOIF=O;
Ilclear INTO flag
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
441
Negative edge-triggered interrupts
Upon power-on reset, the PICI8 makes INTO, INTI, and INT2 positive
(rising) edge-triggered interrupts. To make any of them a negative (falling) edgetriggered interrupt, we must program the corresponding bit called INTEDGx,
where x can be 0, I, or 2. The INTCON2 register holds, among other bits, the INTEDGO, INTEDGI, and INTEDG flag bits as shown in Figure 11-10. INTEDGO,
INTEDGl, and INTEDG2 are bits D4, D5, and D6 of the INTCON2 register,
respectively, as shown in Figure 11-10. The status of these bits determines the negative or positive edge-triggered mode of the hardware interrupts. Upon reset,
INTEDGx bits are all I s, meaning that the external hardware interrupts are positive edge-triggered. By making the INTEDGO bit LOW, the external hardware
interrupts of INTO become negative edge-triggered interrupts. For example, the
instruction "BSF INTCON2, INTEDG1" makes INTEDGI a negative edge-triggered interrupt, in which, when a high-to-Iow signal is applied to pin RB I
(PORTB.I), the controller will be interrupted and forced to jump to location
0008H in the vector table to service the ISR (assuming that the GlE and INTOIE
bits are enabled). This is shown in Program 11-5. Its C version is shown in
Program 1I-5C.
IINTEDGOIINTEDGq INTEDG21
INTEDGx
External Hardware Interrupt Edge trigger bit
o ~ Interrupt on negative (falling) edge
1 ~ Interrupt on positive (rising) edge (Default for power-on reset)
Figure 11-10. INTCON2 Register INTEDG Allows Positive or Negative Edge
Trigger
In Program 11-5 we assume that pin
RB I (INTI) is connected to a pulse generator
and the pin RB7 is connected to an LED. The
program will toggle the LED on the falling
edge of the pulse. In other words, the LED is
turned on and off at the same rate as the puis es are applied to the INTI pin.
J"1J"L
INT1 (RS1)
(PORTS.1)
LED
PORTS.7
Figure 11-11. For Program 11-5
;Program 11-5
ORG
OOOOH
GOTO MAIN
;bypass interrupt vector table
;--on default all interrupts go to to address 00008
ORG
0008H
; interrupt vector table
BTFSS INTCON3,INTIIF ;Did we get here due to
;INTI interrupt?
RETFIE
;No. Then return to main
;Yes. Then go INTI ISR
GOTO INTI ISR
;--the main program for initialization
ORG
00100H
MAIN BCF TRISB, 7
; PB7 as an output
BSF TRISB,INTI ;make INTI an input pin
442
BSF INTCON3,INT1IE
BCF INTCON2,INTEDG1
;enable INT1 interrupt
;make it negative
; edge-triggered
BSF INTCON,GIE
;enable interrupts globally
OVER BRA OVER
; stay in this loop forever
;--------------------------ISR for INT1
INT1 ISR
ORG 200H
;toggle on RB7
BTG PORTB,7
BCF INTCON3,INT1IF ;clear INT1 interrupt flag bit
RETFIE
END
IIProgram 11-5C (This is the C version of Program 11-5)
#include <p18F4580.h>
#define mybit PORTBbits.RB7
void chk_isr(void);
void INT1 ISR(void);
#pragma code MY_HiPrio_Int =Ox0008
interrupt location
void My_HiPrio_Int (void)
Ilhigh-priority
{
asm
GOTO chk isr
endasm
}
#pragma code
#pragma interrupt chk isr
Ilused for high-priority
Ilinterrupt only
void chk_isr (void)
{
if (INTCON3bits.INT1IF==1) IIINT1 causes interrupt?
INT1_ISR ( );
I IYes. Execute INT1 program
}
void main(void)
{
TRISBbits.TRISB7=O;
IIRB7 = OUTPUT
TRISBbits.TRISB1=1;
IIINT1 = INPUT
INTCON3bits.INT1IF=O; Ilclear INT1
INTCON3bits.INT1IE=1; lienable INT1 interrupt
INTCON2bits.INTEDG1=O;llmake it negative edge
INTCONbits.GIE=l;
lienable all interrupts
while(l); Ilkeep looping until interrupt comes
}
void INT1 ISR(void)
{
mybit=-mybit;
INTCON3bits.INT1IF=O;
Ilclear INT1 flag
}
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
443
Sampling the edge-triggered interrupt
Before ending this section, we need to answer the question of how often
the edge-triggered interrupt is sampled. In edge-triggered interrupts, the external
source must be held HIGH for at least two instruction cycles, and then held LOW
for at least two instruction cycles to ensure that the transition is seen by the microcontroller.
The rising edge (or the falling edge) is latched by the PIC 18 and is held by
the INTxIF bits. The INTOIF, INTI IF, and INTIF2 bits hold the latched rising (or
falling, depending on the INTEDGx bit) edge of pins RBO-RB2. The
INTOIF-INT2IF bits function as interrupt-in-service flags. When an interrupt-inservice flag is raised, it indicates to the external world that the interrupt is being
serviced and no new interrupt on this INTn pin will be responded to until this service is finished. This is just like the busy signal you get when calling a telephone
number that is in use. Regarding the INTOIF-INT2IF Qne more point must be
emphasized. The point is that before the ISRs are finished (that is, before execution of instruction RETFIE), these bits (INTOIF-INT2IF) must be cleared, indicating that the interrupt is finished and the PIC 18 is ready to respond to another
interrupt on that pin. For another interrupt to be recognized, the pin must go back
to a logic LOW state and be brought back HIGH to be considered a positive edgetriggered interrupt.
Minimum pulse duration to detect edge
2 Instr. Cycle
triggered interrupts ~ 2 instruction cycles •
•
0.8 Il S
For XTAL ~ 10 MHz, we have an
0.8 I l S '
•
instruction cycle time of 400 ns ~ 0.4 IlS
2 Instr. Cycle
Review Questions
I. True or false. Upon reset, all external hardware interrupts INTO-INT2 go to
the interrupt vector table address of 0008.
2. For PIC 18F458, what pins are assigned to INTO-INT2?
3. Show how to enable the INTI.
4. Assume that the INTOIE bit for the external hardware interrupt INTO is
enabled. Explain how this interrupt works when it is activated.
5. True or false. Upon reset, the external hardware interrupt is negative edge-triggered.
6. How do we make sure that a single interrupt is not recognized as multiple
interrupts?
7. True or false. The last two instructions of the ISR for INTO are:
BCF INTCON2,INTOIF
RETFIE
444
SECTION 11.4: PROGRAMMING THE SERIAL COMMUNICATION INTERRUPTS
In Chapter 10 we studied the serial communication ofthe PICI8. All examples in that chapter used the polling method. In this section we explore interruptbased serial communication, which allows the PICI8 to do many things, in addition to sending and receiving data from the serial communication port.
RCIF and TXIF flags and interrupts
As you may recall from Chapter 10, TXIF (transfer interrupt) is raised
when the last bit of the framed data, the stop bit, is transferred, indicating that the
TXREG register is ready to transfer the next byte. RCIF (received interrupt) is
raised when the entire frame of data, including the stop bit, is received. In other
words, when the RCREG register has a byte, RCIF is raised to indicate that the
received byte needs to be picked up before it is lost (overrun) by new incoming
serial data. As far as serial communication is concerned, all the above concepts
apply equally when using either polling or an interrupt. The only difference is in
how the serial communication needs are served. In the polling method, we wait for
the flag (TXIF or RCIF) to be raised; while we wait we cannot do anything else.
In the interrupt method, we are notified when the PICl8 has received a byte, or is
ready to send the next byte; we can do other things while the serial communication needs are served.
In the PIC 18 two interrupts are set aside for serial communication. One
interrupt is used for send and the other for receive. If the corresponding interrupt
bit ofTXIE or RCIE is enabled, when TXIF or RCIF is raised the PIC 18 gets interrupted and jumps to memory address location 0008H to execute the ISR.
Table 11-4: Serial Port Interrupt Flag Bits and their Associated Registers
Interrupt
Flag bit
TXIF (Transmit) TXIF
RCIF (Receive) RCIF
I
Register
PIRI
PIRI
ReIE
Enable bit
TXIE
RCIE
Register
PIEI
PIE I
TXIE
Figure 11-12. PIEl Register Bits Holding TXIE and RCIE
TMROIF
TMROIE
TXIF
TXIE
vector
location
RCIF
RCIE
Ox0008
GIE
Other Timers and
Peripheral
Interrupts
PEIE
(PEripheral Interrupt
Enable)
Figure 11-13: Serial Interrupt Enable Flags
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
445
Use of serial COM in the PIC18
In the vast majority of applications, the serial interrupt is used mainly for
receiving data and is seldom used for sending data serially. This is like receiving
a telephone call, where we need a ring to be notified of an incoming call. If we
need to make a phone call there are other ways to remind ourselves and so no need
for ringing. In receiving the phone call, however, we must respond immediately no
matter what we are doing or we will miss the call. Similarly, we use the serial interrupt to receive incoming data so that it is not lost. Look at Program 11-6. Notice
that the last instruction of the ISR is RETFIE and there is no clearing of the TXIF
flag, since it is done by writing a byte to TXREG
In Figure 11-13, notice the role ofPEIE (PEripheral Interrupt Enable) in
allowing serial communication interrupts and other interrupts to come in. This is
in addition to the GIE bit discussed in Section 11-\'
For Program 11-6 we assume an 8-bit switch is connected to PORTD. In this program, the PICl8 reads data from PORTD and writes it to TXREG continuously to
be transmitted serially. We assume that XTAL = 10 MHz. The baud rate is set at
9600.
;Program 11-6
ORG
OOOOH
GOTO MAIN
;bypass interrupt vector table
;--on default all interrupts go to to address 00008
ORG
0008H
; interrupt vector table
BTFSC PIR1,TXIF ;Is interrupt due to transmit?
BRA TX ISR
;Yes. Then go to ISR
RETFIE
;No. Then return
ORG 0040H
TX ISR
;service routine for TXIF
MOVWFF PORTD,TXREG;load new value, clear TXIF
RETFIE
;then return to main
i--the main program for initialization
ORG
00100H
MAIN SETF TRISD
MOVLW Ox20
MOVWF TXSTA
MOVLW D' 15'
;write to reg
MOVWF SPBRG
BCF TRISC, TX
;write to reg
BSF
BSF
BSF
BSF
OVER BRA
END
446
;make PORTD input
;enable transmit and choose
;low baud
; 9600 bps
; (Fosc / (64 * Speed)
- 1)
;make TX pin of PORTC an
;output pin
RCSTA, SPEN ;enable the serial port
PIE1,TXIE
;enable TX interrupt
INTCON,PEIE ;enab1e peripheral interrupts
INTCON,GIE
;enable interrupts globally
OVER
;stay in this loop forever
Program 11-7 is a modification of Program 11-6 with receive interrupt. In this program, the PICI8 gets data from PORTD and sends it to TXREG continuously
while incoming data from the serial port is sent to PORTB. We assume that XTAL
= 10 MHz and the baud rate = 9600. This program can be verified by connecting
your PICTrainer to the serial port of the x86 IBM PC and using HyperTerminal to
send and receive data between the PIC Trainer and the IBM Pc.
;Program 11-7
ORG
OOOOH
GOTO MAIN
;bypass interrupt vector table
;--on default all interrupts go to to address 00008
;interrupt vector table
ORG
0008H
lis it TX interrupt?
HI ISR BTFSC PIR1,TXIF
;Yes. Then branch to TX ISR
TX ISR
BRA
BTFSC PIR1,RCIF
;Is it RC interrupt?
BRA RC ISR
;Yes. Then branch to RC ISR
RETFIE
;No. Then return to main
;loading TXREG clears TXIF
TX ISR MOVFF PORTD,TXREG
GOTO HI ISR
RC ISR
;copy received data to PORTB
MOVFF RCREG,PORTB
GOTO HI ISR
;--the main program for initialization
ORG
00100H
;PORTB as an output
MAIN CLRF TRISB
;make PORTD input
SETF TRISD
MOVLW Ox20
;enable transmit and choose low baud
;write to reg
MOVWF TXSTA
MOVLW D'15'
; 9600 bps (Fosc / (64 * Speed) - 1)
MOVWF SPBRG
;write to reg
BCF TRISC,TX
;make TX pin of PORTC an output pin
BSF TRISC,RX
;make RCV pin of PORTC an input pin
MOVLW Ox90
;enable receive and serial port
MOVWF RCSTA
; wri te to reg
BSF PIE1,TXIE
;enable TX interrupt
BSF PIE1,RCIE
;enable receive interrupt
BSF INTCON,PEIE ;enable peripheral interrupts
BSF INTCON,GIE
;enable interrupts globally
OVER BRA OVER
;stay in this loop forever
END
//Program 11-7C (This is the C version of Program 11-7)
#include <p18F458.h>
void chk_isr(void);
void TX_ISR(void);
void RC_ISR(void);
#pragma code My_HiPrio_Int=Ox08 //high-priority interrupt
void My_HiPrio_Int (void)
{
asm
GOTO chk isr
endasm
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
447
}
#pragma code
#pragma interrupt chk_isr//used for high-priority interrupt
void chk_isr (void)
(
if
(PIR1bits.TXIF==1)
TX_ISR( );
if (PIR1bits.RCIF==1)
RC_ISR( );
//Transmit caused interrupt?
//Yes. Execute Transmit program
//Receive caused interrupt?
//Yes. Execute Receive program
}
void main (void)
TRISD = OxFF;
/ /PORTD = INPUT
//PORTB = OUTPUT
TRISB = 0;
TRISCbits.TRISC6=0;
//TX pin = OUTPUT
//RCV pin = INPUT
TRISCbits.TRISC7=1;
//choose low baud rate, 8-bit
TXSTA=Ox20;
//9600 baud rate/ XTAL = 10 MHz
SPBRG=15;
RCSTAbits.CREN=l;
RCSTAbits.SPEN=l;
TXSTAbits.TXEN=l;
PIE1bits.RCIE=1;
lienable RCV interrupt
PIE1bits.TXIE=1;
lienable TX interrupt
INTCONbits.PEIE=l;
lienable peripheral interrupts
INTCONbits.GIE=l;
lienable all interrupts globally
while(l);
//keep looping until interrupt comes
}
void TX_ISR(void)
(
TXREG=PORTD;
void RC_ISR(void)
PORTB=RCREG;
}
}
Review Questions
I. True or false. All interrupts, including the TXIF and RXIF, are directed to a
single location in the interrupt vector table.
2. What address in the interrupt vector table is assigned to the serial interrupt?
3. Which register do the TXIF and RXIF flags belong to? Show how they are
enabled.
4. Assume that the RCIF bit is enabled. Explain how this interrupt gets activated
and its actions upon activation.
5. True or false. Upon reset, the serial interrupts are active and ready to go.
6. True or false. The last two instructions of the ISR for the receive interrupt are:
BCF RIRI,RCIF
RETFIE
7. Answer Question 6 for the transmit interrupt.
448
SECTION 11.5: PORTB-CHANGE INTERRUPT
The four pins of the PORTB (RB4-RB7) can cause an interrupt when any
changes are detected on anyone ofthem. They are referred to as "PORTB-Change
interrupt" to distinguish them from the INTO-INT2 interrupts, which are also
located on PORTB (RBO-RB2). See Figure 11-15. The PORTB-Change interrupt
has a single interrupt flag called RBIF and is located in the INTCON register. This
is shown in Figure 11-14. In Figure 11-14, also notice the RBIE bit for enabling
the PORTB-Change interrupt. In Section 11.3 we discussed the external hardware
interrupts of INTO, INTI, and INT2. Notice the following differences between the
PORTB-Change interrupt and INTO-INT2 interrupts:
(a) Each of the INTO-INT2 interrupts has its own pin and is independent
of the others. These interrupts use pins PORTB.O (RBO), PORTB.I (RB I), and
PORTB.2 (RB2), respectively. The PORTB-change interrupt uses all four of the
PORTB pins RB4-PB7 and is considered to be a single interrupt even though it
can use up to four pins.
(b) While each of the INTO-INT2 interrupts has its own flag, and is independent of the others, there is only a single flag for the PORTB-Change interrupt.
(c) While each of the INTO-INT2 interrupts can be programmed to trigger
on the negative or positive edge, the PORTB-Change interrupt causes an interrupt
if any of its pins changes status from HIGH to LOW, or LOW to HIGH. See Figure
11-16.
PORTB-Change is widely used in keypad interfacing as we will see in
Chapter 12. Another way to use the PORTB-Change interrupt is shown in Program
11-8. In that program, we assume a door sensor is connected to pin RB4 and upon
opening or closing the door, the buzzer will sound. See Figure 11-17.
D7
GIE
DO
RBIE
RBIF
GIE (Global Interrupt Enable)
GIE = 0 Disables all interrupts. If GIE = 0, no interrupt is acknowledged, even if
they are enabled individually.
If GIE = I, interrupts are allowed to happen. Each interrupt source is enabled by setting the corresponding interrupt enable bit.
RBIE
PORTB-Change Interrupt Enable
= 0 Disables PORTB-Change interrupt
= I Enables PORTB-Change interrupt
RBIF
PORTB-Change Interrupt Flag.
= 0 None of the RB4-RB7 pins have changed state
= I At least one of the RB4-RB7 pins have changed state
The RBIE bit, along with the GIE, must be set high for any changes on the pins
RB4-RB7 to cause an interrupt. The RB4-RB7 pins must also have been configured as
input pins for this interrupt to work. In order to clear the RBIF flag we must read the
pins ofRB4-RB7 and use the instruction "BCF INTCON,RBIF".
Figure 11-14. INTCON (Interrupt Control) Register
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
449
1
40
2
3
PIC 18F452/458 39
(DIP)
38
4
37
.
RB7 (PORTB.7)
.-
..-
RB6 (PORTB.6)
RB5 (PORTB.5)
RB4 (PORTB.4)
Figure 11-15. PORTB-Change Interrupt Pms
INTOIF
INTOIE
INT11F
INT11E
RBIF
RBIE
vector
location
Ox0008
TMR11F
TMR21F
TXIF
RXIF
Other
Peripheral
Interrupts
PEIE
(PEripheral Interrupt
Enable)
Figure 11-16. PORTB-Change Interrupt (RBIF)
Sensor
(Switch)
RB4
(PORTB.4)
PIC18F
~
RC7
(PORTC.7)
Buzzer
/
-!.
Figure 11-17. PORTB-Change Interrupt for Program 11-8
450
For Program 11-8 we have connected a door sensor to pin RB4 and a buzzer to
pin RC7. In this program, every time the door is opened, it sounds the buzzer by sending
it a square wave frequency.
;Program 11-8
MYREG EQU
Ox20
;set aside a couple of registers
DELRG EQU Ox80
;for buzzer time delay
ORG
OOOOH
GOTO MAIN
;bypass interrupt vector table
;--on default all interrupts go to to address 00008
ORG
0008H
;interrupt vector table
BTFSS INTCON,RBIF
;Did we get here due to RBIF?
RETFIE
;No. Then return to main
GOTO PB ISR
;Yes. Then go ISR
;--the main program for initialization
ORG
00100H
MAIN BCF TRISC,7
; PORTC. 7 as an output for buzzer
BSF
TRISB,4
;PORTB.4 as an input for interrupt
BSF INTCON,RBIE ;enable PORTB-Change interrupt
BSF INTCON,GIE
;enable interrupts globally
OVER BRA OVER
;stay in this loop forever
;--------------------------ISR for PORTB-Change INT
PB ISR
ORG 200H
MOVF PORTB,W
;we must read PORTB
MOVLW D'250'
;for delay
MOVWF MYREG
BUZZ BTG PORTC, 7
;toggle PC7 for the buzzer
MOVLW D' 255'
;for delay
MOVWF DELRG
DELAY DECF DELRG, F
BNZ DELAY
;keep sounding the buzzer
DECF MYREG,F
BNZ BUZZ
BCF INTCON,RBIF ;and clear RBIF interrupt flag bit
RETFIE
END
Notice for the PORTB-Change interrupt, there is no need to enable the PEIE;
however, we still need to enable the GIE bit.
It must be noted again that, while the INTO-INT2 interrupts each have
their own interrupt flags, there is only a single interrupt flag (RBIF) for all the four
pins of the RB4--RB7. Examine Program 11-9. For this program, we assume that
each ofthe pins RB4 and RB5 is connected to an external switch. Upon activation
of the SW, an LED reflects the status. See Figure 11-18.
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
451
(SW1) RB4
(PORTB.4)
(SW2) RB5
(PORTB.5)
PIC18F
RC6 (LED1)
(PORTC.6)
RC? (LED2)
(PORTC.?)
Figure 11-18: PORTB-Change Interrupt for Program 11-9
For Program 11-9 we have connected SWI and SW2 to pins RB4 and RB5
respectively. In this program, the activation of SWI and SW2 will result in changing the
state of LED I and LED2 respectively.
;Program 11-9
ORG
OOOOH
GOTO MAIN ;bypass interrupt vector table
;--on default all interrupts go to to address 00008
ORG
0008H
; interrupt vector table
BTFSS INTCON,RBIF;Did we get here due to RBIF?
;No. Then return to main
RETFIE
GOTO PB ISR
;Yes. Then go ISR
;--the main program for initialization
ORG
0100H
MAIN BCF TRISC, 4
; PC4 as an output
BCF TRISC,S
;PCS as an output
BSF TRISB,4 ;PB4 as an input for the interrupt
BSF TRISB,S ;PBS as an input for the interrupt
BSF INTCON,RBIE ;enable PORTB interrupt
BSF INTCON,GIE
;enable interrupts globally
OVER BRA OVER
; stay in this loop forever
;--------------------------ISR for PORTB_Change
PB ISR
ORG 200H
MOVFF PORTB,W ;get the status of switches
ANDLW Ox30 ;mask unneeded bits
MOVFF W,PORTC ;update LEDs
BCF INTCON,RBIF ;clear RBIF interrupt flag bit
RETFIE
END
452
II Program 11-9C (This is the C version of Program 11-9)
#include <plBF45B.h>
#define LEDI PORTCbits.RC4
#define LED2 PORTCbits.RC5
void chk_isr(void) ;
void RBINT_ISR(void);
#pragma code My_HiPrio_Int =OxOOOB Ilhigh-priority int
void MY_HiPrio_Int (void)
asm
GOTO chk isr
endasm
#pragma code
#pragma interrupt chk isr
void chk_isr (void)
Ilused for high-priority int
{
if (INTCONbits.RBIF==I)
IIRBIF caused interrupt?
RBINT_ISR( );
IIYes. Execute ISR program
}
void main (void)
{
TRISCbits.TRISC4=O;
IIRC4
OUTPUT
TRISCbits.TRISC5=O;
IIRC5
OUTPUT
TRISBbits.TRISB4 = 1; IIRB4
INPUT for interrupt
TRISBbits.TRISB5 = 1; IIRB5
INPUT for interrupt
INTCONbits.RBIF=O;
Ilclear RBIF
INTCONbits.RBIE=I;
lienable RB interrupt
INTCONbits.GIE=I;
lienable all interrupts globally
while(I); Ilkeep looping until interrupt comes
void RBINT_ISR(void)
{
LEDl=PORTBbits.RB4;
LED2=PORTBbits.RB5;
INTCONbits.RBIF=O;
Ilclear RBIF flag
}
Review Questions
1. True or false. There is a single interrupt for each of the PORTB pins.
2. What address in the interrupt vector table is assigned to the PORTB-Change
interrupt?
3. Which register do the RBIF and RBIE flags belong to? Show how RBIE is
enabled.
4. Give the last two instructions of the ISR for the PORTB-Change interrupt.
5. True or false. Upon reset, the RBIF interrupt is active and ready to go.
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
453
SECTION 11.6: INTERRUPT PRIORITY IN THE PIC18
The next topic that we must deal with is what happens if two interrupts are
activated at the same time? Which of these two interrupts is responded to first?
Interrupt priority is the main topic of discussion in this section.
Setting interrupt priority
In the PIC 18 microcontroller, there are only two levels of interrupt priority: (a) low level, and (b) high level. While address 0008 is assigned to high-priority interrupts, the low-priority interrupts are directed to address 00018 in the interrupt vector table. See Table 11-5. Upon power-on reset, all interrupts are automatically designated as high priority and will go to address 00008H. This is done to
make the PIC 18 compatible with the earlier generation of PIC microcontrollers
such as PIC16xxx. We can make the PICI8 a two-level priority system by way of
programming the IPEN (interrupt priority enable) bit in the RCON register. Figure
11-19 shows the IPEN bit of the RCON register. Upon power-on reset, the IPEN
bit contains 0, making the PICI8 a single priority level chip, just like the
PIC 16xxx. To make the PIC 18 a two-level priority system, we must first set the
IPEN bit to HIGH. It is only after making IPEN = I that we can assign a low priority to any of the interrupts by programming the bits called IP (interrupt priority).
Figure 11-20 shows IPRI (interrupt priority register) with the IP bits for TXIP,
RCIP, TMR lIP, and TMR2IP. If IPEN = I, then the IP bit will take effect and will
assign a given interrupt a low priority. As a result of assigning a low priority to a
given interrupt, it will land at the address 00 I 8 instead of 0008 in the interrupt vector table. The IP (interrupt priority) bit along with the IF (interrupt flag) and IE
(interrupt enable) bits will complete all the flags needed to program the interrupts
for the PIC 18. Table 11-6 shows the three flags and the registers they belong to for
some of the interrupts used in this chapter. In Table I I -6, notice the absence of the
INTO priority flag. The INTO has only one priority and that is high priority. That
means all the PICI8 interrupts can be assigned a low or high priority level, except
the external hardware interrupt of INTO. Study Figures 11-22 through 11-25 very
carefully. When examining these figures, the following point must be noted. By
making IPEN = I, we enable the interrupt priority feature. Now we must also
enable two bits to enable the interrupts: (a) We must set GIEH = 1. The GIEH bit
is part of the INTCON register (Figure 11-21) and is the same as GIE, which we
have used in previous sections. In this regard there is no difference between the
priority and no-priority systems. (b) The second bit we must set high is GIEL (part
of INTCON). Making GIEL = I will enable all the interrupts whose IP = O. That
means all the interrupts that have been given the low priority will be forced to vector location 00018H.
Table 11-5: Interrupt Vector Table for the PIC18
Interrupt
Power-on-Reset
High-priority Interrupt
Low-priority Interrupt
454
ROM Location (Hex)
0000
0008 (Default upon power-on reset)
0018 (Selected with IP bit)
IPEN
I
/I
IPEN Interrupt Priority Enable bit
o ~ All the interrupts are directed to the vector location 0008 (default).
I ~ Interrupts can be assigned a low or high priority.
The importance ofIPEN: Upon power-on reset, all the interrupts ofPIC18 are directed to location 0008, making it a single-priority system, just like PIC 16xxx. To prioritize
the PICI8 interrupts into low- and high-level priorities, we must make IPEN ~ 1.
When IPEN ~ 1, we can assign either a low or a high priority to any of the interrupts by
manipulating the corresponding bit in the IPR (interrupt priority register) for that interrupt. When interrupt priority is enabled (IPEN ~ 1), we must set both the GIEH and
GIEL bits to high in order to enable the interrupts globally. Notice in Figure 11-21 that
GIE is the same as GIEH.
Figure 11-19. RCON Register. IPEN Allows Prioritizing the Interrupt into 2 Levels
I RCIP I TXIP I
I TMR2IP I TMRlIP I
RCIP USART (Serial COM) Receive Interrupt Priority bit
o~ Low priority
1 ~ High priority
TXIP USART (Serial COM) Transmit Interrupt Priority bit
o~ Low priority
I ~ High priority
TMR2IP Timer2 Interrupt Priority bit
o ~ Low priority
1 ~ High priority
TMRlIP Timer! Interrupt Priority bit
o~ Low priority
I ~ High priority
Figure 11-20. IPRI Peripheral Interrupt Priority Register 1
Table 11-6: Interrupt Flag Bits for PIC18 Timers
Interrupt Flag bit (Register)
TimerO TMROIF (INTCON)
Timer!
TMRlIF (PIR!)
Timer2 TMR2IF (PIR!)
Timer3
TMR3IF (PIR3)
INTI
INTlIF (PIRl)
INT2
INT2IF (PIR!)
TXIF
TXIF (PIR!)
RCIF
RCIF (PIR!)
RB INT RBIF (INTCON)
Enable bit (Register)
TMROIE (INTCON)
TMRlIE (PIE!)
TMR2IE (PIE!)
TMR3IE (PIE2)
INTlIE (PIEl)
INT2IE (PIEl)
TXIE (PIE!)
RCIE (PIEl)
RBIE (INTCON)
Priority (Register)
TMROIP (INTCON2)
TMRlIP (IPRl)
TMR2IP (lPRl)
TMR3IP (IPR2)
INTlIP (INTCON3)
INT2IP (INTCON)
TXIP (IPRl)
RCIP (IPRl)
RBIP (INTCON2)
Note: INTO has only the high-level priority.
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
455
DO
D7
1GIE(GIEH) I
IiL-__,IL-1_ ....1'-----'1"1_---"1_---'11'----'
GIEL
GIE (Global Interrupt Enable) This is also referred to as GIEH
GIE = 0 Disables all interrupts. If GIE = 0, no interrupt is acknowledged, even if
they are enabled individually.
If GIE = I, interrupts are allowed to happen. Each interrupt source is enabled by setting the corresponding interrupt enable bit.
GIEL (This is called Global Interrupt Enable Low to distinguish it from D7)
While GIH (D7) is used to enable or disable all the interrupts (both low and high priority), the GIEL (D6) is used to enable or disable only the low-priority interrupts. That
means GIEL works only when the IPEN (Interrupt Priority Enable) bit is enabled.
If IPEN = 0
GIEL = 0 Disables all peripheral interrupts (same as PEIE)
GIEL = I Enables all peripheral interrupts (same as PEIE)
If IPEN = I
GIEL = 0 Disables the Low-priority Interrupt
GIEL = 1 Enables the Low-priority Interrupt
Figure 11-21. INTCON (Interrupt Control) Register
INTOIF
INTOIE
INT11F
INT11E
INT11P
INT21F
INT21E
INT21P
GIE
RBIF
RBIE
RBIP
TMR11F
TMR11E
TMR11P
TMR21F
MR21E
TMR21P
TXIF
TXIE
TXIP
RCIF
RCIE
RCIP
PEIE
(PEripheral Interrupt
Enable)
Interrupt Priority (IP) = 1 is high priority (Ox0008)
Figure 11-22. Interrupts with High-Priority (IP) Flag
456
INT1IF
INT11E
INT11P
INT21F
INT21E
INT21P
TMROIF
TMROIE
TMROIP
INTOIF
INTOIE
Wake-up (if in SLEEP mode)
RBIF
RBIE
RBIP
Interrupt to CPU
Vector to Location
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
TXIF
TXIE
TXIP
SSPIF
SSPIE
0OOO8h
SSPI~
CCP11F
CCP11E
CCP11P
CCP21F
CCP21E
CCP21P
TMR11F
TMRllE
TMRllP
TMR21F
TMR21E
TMR21P
TMR31F
TMR31E
TMR31P
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
IPEN
PEIEfGIEL
To low-priority
interrupt logic
Figure 11-23. High-Priority Interrupts (Redrawn from PIC18 Manual)
TOlE
TOIF
TotP
R81F
RBIE
RBIP
INTOIF
INTOIE
INTllF
INT11E
3=2r=;==t'c---,
Wake-up if in SLEEP mode
1
I~lll~
INT21E
INT21P
GIEHIGIE
Additional Perip!1erallnterrupts
High_Priority Interrupt Inmalized
(disable tow-priority interrupts)
THigh-Priority Interrupt Generation
1
Law-PrIOrity Interrupt Generation
Penpherallnterrupt Enable bn
pe=~~~:~~~~~ ~~
TOIF
Additional Peripheral Interrupts
TOlE
il~
3=tr=;:==l)
Wake-up
(~in SLEEP made)
Interrupt to CPU
Vector to location 0018h
(Low-Pnority Interrupt
Vector Address)
GIELIPEIE
III
Figure 11-24. Low- and High-Priority Interrupt Selection (Redrawn from
PIC18 Manual)
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
457
~~~I~
~~I~
~~I~
~I~
~~~I~
~~~11~
~~~~I~
f~~ll~
f~~~1
High-priority interrupt initiated signal
(Disable Low-priority Interrupts)
Wake-up (if in SLEEP Mode)
IPEN
Interrupt to CPU
Vector to Location 00018h
(Low-Priority Interrupt
Vector Address)
f~~~IF
~~~I~
~~~I~
f~~~1
l~f~l~
I~fll~
l~f~l~
~~I~
Figure 11-25_ Low-Priority Interrupt Selection with IP Flag (Redrawn from
PIC18 Manual)
458
Program \1-10 uses TimerO and Timer! interrupts to generate square waves on
pins RB I and RB7 respectively, while data is being transferred from PORTe to PORTO.
This is a repeat of Program 11-2, except Timer! has been assigned to low priority.
;Program 11-10
ORG
OOOOH
GOTO MAIN
;bypass interrupt vector table
;--high-priority interrupts go to address 00008
ORG
0008H
;high-priority interrupt vector table
BTFSC INTCON,TMROIF
;Is it TimerO interrupt?
BRA TO ISR
;Yes. Then branch to TO_ISR
RETFIE OxOl
;No. Then fast return to main
;--low-priority interrupts go to address 00018
ORG
0018H
;low-priority interrupt vector table
BTFSC PIR1,TMRlIF
;Is it Timerl interrupt?
BRA Tl ISR
;Yes. Then branch to Tl ISR
RETFIE
;No. Then return to main
i-main program for initialization and keeping CPU busy
ORG
0100H ; somewhere after vector table space
MAIN BCF TRISB, 1
; PBl as an output
BCF TRISB,7
;PB7 as an output
CLRF TRISD
;make PORTD output
SETF TRISC
;make PORTC input
MOVLW Ox08
;TimerO, 16-bit, no prescale,
;internal clk
MOVWF TOCON
;load TOCON reg
MOVLW OxFF
; TMROH = FFH, the high byte
MOVWF TMROH
; load TimerO high byte
MOVLW OxOO
; TMROL = OOH, the low byte
MOVWF TMROL
;load TimerO low byte
BCF INTCON,TMROIF ;clear TimerO interrupt flag bit
BSF INTCON,TMROIE ;enable TimerO interrupt
MOVLW OxO
;Timerl, 16-bit, no prescale,
;internal clk
MOVWF TICON
;load T1CON reg
MOVLW OxFF
;TMR1H = FFH, the high byte
MOVWF TMR1H
;load TimerO high byte
MOVLW OxOO
;TMR1L = OOH, the low byte
MOVWF TMR1L
;load Timerl low byte
BCF PIR1, TMRlIF ;clear Timerl interrupt flag bit
BSF PIE1, TMRlIE ;enable Timerl interrupt
BCF IPR1, TMRlIP ;make Timerl low-priority interrupt
BSF RCON, IPEN ;enable priority levels
BSF INTCON,GIEL
BSF INTCON,GIEH ;enable interrupts globally
BSF T1CON,TMR10N;start Timerl
BSF TOCON,TMROON;start TimerO
;--keeping CPU busy waiting for interrupt
OVER MOVFF PORTC,PORTD ;send data from PORTC to PORTD
BRA OVER
; stay in this loop forever
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
459
;--------------------------ISR for TimerO
TO ISR
ORG 200H
MOVLW OxFF
;TMROH = FFH, the high byte
MOVWF TMROH
;load TimerO high byte
MOVLW OxOO
;TMROL = OOH, the low byte
MOVWF TMROL
;load TimerO low byte
BTG
PORTB,1
;toggle RBI
BCF INTCON,TMROIF ;clear timer interrupt flag bit
RETFIE OxOl
;--------------------------ISR for Timer1
T1 ISR
ORG 300H
MOVLW OxFF
;TMR1H = FFH, the high byte
MOVWF TMR1H
;load TimerO high byte
MOVLW OxOO
;TMRIL = OOH, the low byte
MOVWF TMR1L
;load Timer1 low byte
BTG PORTB,7
BCF PIR1,TMR1IF ;clear Timer1 interrupt flag bit
RETFIE
END
Program II-II has four interrupts. It uses TimerO and Timer I interrupts to
generate square waves on pins RCO and RC I respectively. It also uses the transmit
and receive interrupts to send and receive data serially. Data from PORTD is transmitted and the received byte is placed on PORTB. TimerO and receive ISRs have
the high priority while Timerl and send ISRs are assigned a low priority level.
;Program 11-11
ORG
OOOOH
GOTO MAIN
;bypass interrupt vector table
;--high-priority interrupts go to address 00008
ORG
0008H
;need to redirect because not
ienough space
GOTO CHK HI PRIO
;--no need to redirect because we have plenty of space
ORG
00018
;low-priority interrupt vector table
BTFSC PIR1,TMR1IF
lis it Timer1 interrupt?
BRA T1 ISR
;Yes. Then branch to T1 ISR
BTFSC PIR1,TXIF ;Did we get here due to TxD?
BRA TX ISR
;Yes. Then branch to TX_ISR
RETFIE
iNc. Then return to main
,
0
______
----------
CHK HI PRIO
ORG
Ox50
;Is it TimerO interrupt?
BTFSC INTCON,TMROIF
BRA TO ISR
;Yes. Then branch to TO ISR
BTFSC PIR1,RCIF ;Did we get here due to RCV int?
BRA RC ISR
;Yes. Then branch to RC_ISR
iNa. Then return to main
RETFIE Ox01
460
i-main program for initialization and keeping CPU busy
ORG
OIOOH
;somewhere after vector table space
MAIN BCF
TRISC,RCO
TRISC,RCI
BCF
CLRF TRISB
;make PORTB output
SETF TRISD
;make PORTD input
MOVLW Ox08
;TimerO, 16-bit, no prescale,
;internal elk
MOVWF TOCON
;load TOCON reg
MOVLW OxFF
;TMROH = FFH, the high byte
MOVWF TMROH
; load TimerO high byte
MOVLWOxOO
;TMROL = OOH, the low byte
MOVWF TMROL
;load TimerO low byte
BCF INTCON,TMROIF ;clear TimerO interrupt flag bit
MOVLW OxO
;Timerl, 16-bit, no prescale,
;internal clk
MOVWF TICON
; load TICON reg
MOVLW OxFF
;TMRIH = FFH, the high byte
;load TimerO high byte
MOVWF TMRIH
MOVLW OxOO
;TMRIL = OOH, the low byte
MOVWF TMRIL
;load Timerl low byte
BCF PIRl, TMRlI F ;clear Timerl interrupt flag bit
MOVLW Ox20
;enable transmit and choose low baud
MOVWF TXSTA
;write to reg
MOVLW Dr 15 r
; 9600 bps (Fosc I (64 * Speed) - 1)
MOVWF SPBRG
;write to reg
ienable receive and serial port
MOVLW Ox90
MOVWF RCSTA
;write to reg
BCF TRISC, TX
;make TX pin of PORTC an output pin
BSF TRISC, RX
;make RCV pin of PORTC an input pin
BSF
RCON,IPEN
BSF
PIEl, RCIE
BSF PIEl,TXIE
;enable TX interrupt
BSF INTCON,TMROIE
;enable TimerO interrupt
BSF PIEl,TMRlIE ;enable Timerl interrupt
BCF IPRl,TMRlIP ;make Timerl a low-priority interrupt
BCF IPRl,TXIP ;make Transmit a low-priority interrupt
BSF TOCON, TMROON
; start TimerO
BSF TICON,TMRION
;start Timerl
BSF INTCON,GIEL
;enable low-priority interrupts
BSF INTCON,GIEH
;enable high-priority interrupts
;--keeping CPU busy waiting for interrupt
OVER BRA
OVER
;stay in this loop forever
;--------------------------ISR for TimerO
TO ISR
ORG 200H
MOVLW OxFF
;TMROH = FFH, the high byte
MOVWF TMROH
;load TimerO high byte
MOVLW OxOO
;TMROL = OOH, the low byte
;load TimerO low byte
MOVWF TMROL
BTG
PORTC, 0
;toggle RBI
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
461
BCF INTCON,TMROIF ;clear timer interrupt flag bit
RETFIE OxOl
;--------------------------ISR for Timerl
Tl ISR
ORG 300H
MOVLW OxFF
;TMRIH = FFH, the high byte
MOVWF TMRIH
;load TimerO high byte
MOVLW OxOO
;TMRIL = OOH, the low byte
MOVWF TMRIL
;load Timerl low byte
BTG PORTC,l
BCF PIRl,TMRlIF ;clear Timerl interrupt flag bit
RETFIE
;----------------Transmit ISR
TX ISR
BCF PIRl,TXIF ;clear TX interrupt flag bit
MOVFF PORTD,TXREG
RETFIE
;------------
RC ISR
MOVFF RCREG,PORTB
BCF
PIRl, RCIF
RETFIE 1
END
;copy received data to PORTD
; clear RCIF
Example 11-3
For Program 11-11 (or Program 11-11C), discuss what happens: (a) if interrupt RCIF is
activated when the PIC18 is serving the Timerl interrupt, (b) Timer 1 is activated when
TimerO is being served, (c) RCIF and TMROIF and TMRlIF are activated at the same
time.
Solution:
In Program II-II, notice that the Receive (RCIF) and TimerO (TMROIF) interrupts are
assigned to high priority while the Transmit (TXIF) and Timerl (TMRlIF) interrupts
have low priority. As a result we have the following:
(a) if the RCIF is activated during the execution of the Timerl ISR, the Receive interrupt comes in and its ISR is executed first because it has a higher priority. After it is finished, the PIC18 goes back and finishes the Timerl ISR.
(b) if the TMRIIF is activated during the execution of the TimerO ISR, it is ignored
because it has lower priority. After the TimerO ISR is finished, the PIC 18 will execute
the Timerl ISR.
(c) If all three, RCIF, TMROIF, and TMRIIF, are activated at the same time, the
Received ISR and and TimerO ISR are taken care of first because they are assigned to
high priority. Between the Receive and TimerO interrupts, the TimerO ISR is served first
due to the programming sequence we have set in the interrupt vector table for the highpriority interrupts. That means if these three interrupts are activated at the same time,
they are executed in the following sequence: TimerO ISR, Receive ISR, and Timerl ISR.
462
Low-priority interrupt programming in C
As we saw in the last four sections, the C 18 compiler uses the reserved
keyword interrupt to designate an interrupt as high priority. To assign low priority level to a given interrupt, it uses the keyword interruptlow. See Table 11-7.
This is shown in Program 11-11 C, which is a repeat of Program 11-11 in C.
Table 11-7: Interrupt Vector Table for the PICIS using CIS Syntax
Interrupt
High-priority Interrupt
Low-priority Interrupt
ROM Location
Ox0008 (Default)
OxOO 18 (Selected with IP bit)
CIS keyword
interrupt
interruptlow
Program II-II C has four interrupts. It uses TimerO and Timer I interrupts to generate square waves on pins RCI and RC7, respectively. It also uses the transmit and
receive interrupts to send and receive data serially. Data from PORTB is transmitted and
the received byte is placed on PORTO. TimerO and receive ISRs have the high priority
while Timer I and transmit ISRs are assigned low priority level.
//Program 11-11C (This is the C version of Program 11-11)
#include <p18F458.h>
#define myPCObit PORTCbits.RCO
#define myPC1bit PORTCbits.RC1
void
void
void
void
void
void
chk_isr(void);
chk_low_isr(void);
TO lSR(void);
T1 lSR(void);
TX_lSR(void);
RC_lSR(void);
#pragma code My_HiPrio_lnt =Ox0008 //high-priority int
void My_HiPrio_lnt (void)
asm
GOTO chk isr
endasm
#pragma code My_Lo_Prio lnt =Ox00018 //low-priority int
void My_LO Prio lnt (void)
{
asm
GOTO chk low isr
endasm
}
#pragma interruptlow chk_low_isr//used for low-priority
void chk low_isr (void)
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
463
if(PIR1bits.TMR1IF==1)//Timer1 causes interrupt?
T1ISR();
//Yes. Execute Timer1 ISR
if (PIR1bits.TXIF==1) //Transmit causes interrupt?
TX_ISR( );
//Yes. Execute Transmit ISR
#pragma interrupt chk_isr//used for high-priority interrupt
void chk_isr (void)
if
if
(PIR1bits.TMR1IF==1)//TimerO causes interrupt?
TO ISR ( );
/ /Yes. Execute TimerO ISR
(PIR1bits.RCIF==1) //Receiver causes interrupt?
RC_ISR( );
//Yes. Execute Receiver ISR
void main (void)
TRISCbits.TRISCO=O;
TRISCbits.TRISC1=0;
TRISD = 255;
TRISB = 0;
TOCON=Ox08;
//RCO = OUTPUT
//RC1 = OUTPUT
//PORTD
INPUT
//PORTB = OUTPUT
//TimerO, 16-bit mode,
fino prescaler
//load THO
TMROH=OxFF;
TMROL=OxOO;
//load TLO
INTCONbits.TMROIF=O; //clear TF1
T1CON=OxO; //Timer 1, 16-bit mode, no prescaler
TMR1H=OxFF;
//load TH1
//load TL1
TMR1L=OxOO;
PIR1bits.TMR1IF=0;
//clear TF1
//choose low baud rate,8-bit
TXSTA=Ox20;
//9600 baud rate/ XTAL = 10 MHz
SPBRG=15;
RCSTAbits.CREN=l;
RCSTAbits.SPEN=l;
TRISCbits.TRISC6=0;
//TX pin = OUTPUT
//RCV pin = INPUT
TRISCbits.TRISC7=1;
RCONbits. IPEN=l;
PIE1bits.RCIE=1;
PIE1bits.TXIE=1;
lienable TX interrupt
INTCONbits.TMROIE=l;
PIE1bits.TMR1IE=1;
IPR1bits.TMR1IP=0;
//make Timer1 a low-priority
IPR1bits.TXIP=0;
//make TX a low-priority
TOCONbits.TMROON=l;
//turn on TO
T1CONbits.TMR10N=1;
//turn on T1
INTCONbits.GIEL=l;
lienable low-priority interrupts
INTCONbits.GIEH=l;//enable high-priority interrupts
while(l);
//keep looping until interrupt comes
464
//-------------ISR for TimerO
void TO ISR(void)
TMROH=OxFF;
TMROL=OxOO;
myPCObit=-myPCObit;
INTCONbits.TMROIF=O;
//load THO
//load TLO
//toggle RBl
/ /clear TFO
}
//-------------ISR for Timerl
void Tl ISR(void)
TMR1H=OxFF;
TMR1L=OxOO;
PIRlbits.TMR1IF=O;
myPClbit=-myPClbit;
//load THO
//load TLO
//clear TFl
//toggle RBl
}
//-------------ISR for Transmit
void TX_ISR(void)
{
TXREG=PORTD;
//clear Tx Interrupt flag
}
//-------------ISR for Receive
void RC ISR(void)
{
PORTB=RCREG;
RCSTAbits.CREN=O;//clear CREN to clear any error
RCSTAbits.CREN=l;//set CREN for continuous reception
Interrupt inside an interrupt
What happens if the PICIS is executing an ISR belonging to an interrupt
and another interrupt is activated? In such cases, a high-priority interrupt can interrupt a low-priority interrupt. This is an interrupt inside an interrupt. In the PIC IS
a low-priority interrupt can be interrupted by a higher-priority interrupt, but not by
another low-priority interrupt. Although all the interrupts are latched and kept
internally, no low-priority interrupt can get the immediate attention of the CPU
until the PIC IS has finished servicing all the high-priority interrupts. The GIE
(which is also called GIEH) and GIEL bits play an important role in the process of
the interrupt inside the interrupt. Regarding the interrupt inside an interrupt concept, the following points must be emphasized:
I. When a high-priority interrupt is vectored into address OOOSH, the GIE bit is
disabled (GIEH = 0), thereby blocking another interrupt (low or high) from
coming in. The RETFIE instruction at the end of the lSR will enable the GIE
(GIE = I) automatically, which allows interrupts to come in again. If we want
to allow another high-priority interrupt to come in during the execution of the
current ISR, then we must make GIE = I at the beginning of the current ISR.
2. When a low-priority interrupt is vectored into address 00 ISH, the GIEL bit is
disabled (GIEL = 0), thereby blocking another low-priority interrupt from
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
465
coming in. The RETFIE instruction at the end of the ISR will enable the GIEL
(GIEL = I) automatically, which allows low-priority interrupts to come in
again. Notice that the low-priority interrupt cannot block a high-priority interrupt from coming in during the execution of the current low-priority ISR
because GIEH is still set to one (GIEH = I).
3. When two or more interrupts have the same priority level. In this case, they are
serviced according to the sequence by which the program checks them in the
interrupt vector table. We saw many examples of that in this chapter. See
Example 11-3.
Fast context saving in task switching
In many applications, such as multitasking real-time operating systems
(RTOS), the CPU brings in one task (job or process) at a time and executes it
before it moves to the next one. In executing each task, which is often organized
as the interrupt service routine, access to all the resources of the CPU is critical in
performing the task in a timely manner. In early CPUs, the limited number of registers forced programmers to save the entire contents of the CPU on the stack
before execution of the new task. This saving of the CPU contents before switching to a new task is called context saving (or context switching). The use of the
stack as a place to save the CPU's contents is tedious, time consuming, and slow.
For this reason some CPU s such as x86 microprocessors have instructions such as
PUSHA (Push All) and POPA (Pop All), which will push and pop all the main registers onto the stack with a single instruction. Because the PIC 18 has numerous
general purpose registers, there is no need for using the stack to save the CPU's
general purpose registers. However, each task generally needs the key registers of
WREG, BSR, and STATUS. For that reason the PICl8 automatically saves these
three registers internally in shadow registers when a high-priority interrupt is activated. This way, the three key registers of the main task are saved internally. To
restore the original contents of these three key registers, one must use instruction
"RETFIE OxOl" instead of "RETFIE" at the end of the high-priority ISR. The
"RETFIE OxOI" is called fast context saving in PICI8 literature. Regarding fast
context saving in the PICI8, two important points must be noted:
1. It is not available for the low-priority interrupts, and works only for high-priority interrupts. That means that when a low-priority interrupt is activated,
there is no fast context saving and we must save these three registers at the
beginning of the low-priority ISR, if they are being used by the low-priority
ISR.
2. The shadow registers keeping these three key registers have a depth of one,
meaning that there is only one of them. For that reason, the fast context saving
works only when a high-priority ISR is activated during the main subroutine.
If two or three high-priority interrupts are activated at the same time, only the
first ISR can use the fast context saving because the depth of shadow registers
is only one. In that case, the second and third ISRs must save these key registers at the beginning of the body of their ISRs. This should not be difficult
because we know the sequence by which the ISRs are executed, as we saw in
many examples in this chapter.
466
Interrupt latency
The time from the moment an interrupt is activated to the moment the CPU
starts to execute the code at the vector address of 0008H (or OxOO 18H) is called
the interrupt latency. This latency can be anywhere from 2 to 4 instruction cycle
times depending on whether the source of the interrupt is an internal (e.g., timers)
or external hardware (e.g., hardware INTx and PORTB-Change) interrupt. The
duration of an interrupt latency can also be affected by the type of the instruction
in which the CPU was executing when the interrupt comes in. It takes slightly
longer in cases where the instruction being executed lasts for two instruction
cycles (e.g., MOVFF reg,reg) compared to the instructions that last for only one
instruction cycle time (e.g., ADDWL). See PICl8 for the timing data sheet.
Triggering the interrupt by software
Sometimes when we need to test an ISR by way of simulation. This can be
done with simple instructions to set the interrupts HIGH and thereby cause the
PICI8 to jump to the interrupt vector table. For example, if the TMRIIE bit for
Timer I is set, an instruction such as "BSF INTCON, TMR1IF" will interrupt the
PIC 18 in whatever it is doing and force it to jump to the interrupt vector table. In
other words, we do not need to wait for Timer I to roll over to have an interrupt.
We can cause an interrupt with an instruction that raises the interrupt flag.
Review Questions
I. True or false. Upon reset, all interrupts have the same priority.
2. Which bit of what register is used to enable the interrupt priority option in the
PIC 18? Is it a bit-addressable register?
3. Which register has the TXIP bit? Show how to assign it low priority.
4. Assume that INTO and INTI have the same low priority. Explain what happens
if both INTO and INTI are activated at the same time. Also assume that INTO
is checked first in the program for the interrupt vector table.
5. Explain what happens if a higher-priority interrupt is activated while the PICI8
is serving a lower-priority interrupt (i.e., executing a lower-priority ISR).
SUMMARY
An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service. Every interrupt has a program
associated with it called the ISR, or interrupt service routine. The PIC 18 has many
sources of interrupts, depending on the family members. Some of the most widely used interrupts are for the timers, external hardware interrupts, and serial communication. When an interrupt is activated, the IF (Interrupt flag) bit is raised.
The PICI8 can be programmed to enable (unmask) or disable (mask) an
interrupt, which is done with the help of the GIE (global interrupt enable) and IE
(interrupt enable) bits. The PICI8 has two levels of priority, low and high. Upon
power-on reset, all the interrupts are designated as high priority and are directed to
address 0008 in the interrupt vector table. This default setting can be altered with
the help ofthe IP (interrupt priority) bits. By programming the IP bit, we can make
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
467
an interrupt a low priority and force it to land at address OxOOO 18 in the interrupt
vector table. This chapter also showed how to program PIC 18 interrupts in both
Assembly and C languages.
PROBLEMS
SECTION 11.1: PICI8 INTERRUPTS
I.
2.
3.
4.
Which technique, interrupt or polling, avoids tying down the microcontroller?
List some of the interrupt sources in the PICI8.
In the PICI8 what memory area is assigned to the interrupt vector table?
True or false. The PIC 18 programmer cannot change the memory address location assigned to the interrupt vector table.
5. What memory address in the interrupt vector table is assigned to low-priority
interrupts?
6. What memory address in the interrupt vector table is assigned to high-priority
interrupts?
7. Do we have a memory address in the interrupt vector table assigned to the
TimerO interrupt?
8. Do we have a memory address in the interrupt vector table assigned to the
INTI interrupt?
9. To which register does the GIE bit belong?
10. Why do we put a GOTO instruction at address O?
II. What is the state of the GIE bit upon power-on reset, and what does it mean?
12. Show the instruction to enable the INTO interrupt.
13. Show the instruction to enable the TimerO interrupt.
14. The TMROIE bit belongs to register~~_.
IS. How many bytes of address space in the interrupt vector table are assigned to
the high-priority interrupt?
16. How many bytes of address space in the interrupt vector table are assigned to
the low-priority interrupt?
17. To put the entire interrupt service routine in the interrupt vector table for high
priority, it must be no more than _ _ bytes in size.
18. True or false. The INTCON register is not a bit-addressable register.
19. With a single instruction, show how to disable all the interrupts.
20. With a single instruction, show how to disable the INTO interrupt.
21. True or false. Upon reset, all interrupts are enabled by the PICI8.
22. In the PIC 18, how many bytes of ROM space are assigned to the reset?
SECTION 11.2: PROGRAMMING TIMER INTERRUPTS
23. True or false. For each of Timer 0 and Timer!, there is a unique address in the
interrupt vector table.
24. What address in the interrupt vector table is assigned to Timer!?
25. Show how to enable the TimerO interrupt.
26. Which bit of INTCON belongs to the TimerO interrupt? Show how it is
enabled.
468
27. Assume that TimerO is programmed in 8-bit mode, TMROH = FOH, and the
TMROIE bit is enabled. Explain how the interrupt for the timer works.
28. True or false. The last two instructions of the ISR for Timerl are:
BCF PIR1,TMR1IF
RETFIE
29. Assume that Timer! is programmed for 16-bit mode, TMRIH = FFH, TMRIL
= F8H, and the TMRIIE bit is enabled. Explain how the interrupt is activated.
30. If Timer I is programmed for interrupts in 8-bit mode, explain when the interrupt is activated.
31. Write a program using the TimerO interrupt to create a square wave of I Hz on
pin RB7 while data from PORTC is being sent to PORTD. Assume XTAL = 10
MHz.
32. Write a program using the Timer! interrupt to create a square wave of 3 kHz
on pin RB7 while data from PORTC is being sent to PORTD. Assume XTAL
= 10 MHz.
SECTION 11.3: PROGRAMMING EXTERNAL HARDWARE INTERRUPTS
33. True or false. An address location is assigned to each of the external hardware
interrupts INTO, INTI, and INT2.
34. What address in the interrupt vector table is assigned to INTO, INTI and
INT2? How about the pin numbers on PORTB?
35. To which register does the INTOIE bit belong? Show how it is enabled.
36. To which register does the INTI IE bit belong? Show how it is enabled.
37. Show how to enable all three external hardware interrupts.
38. Assume that the INTOIE bit for external hardware interrupt INTO is enabled
and is negative edge-triggered. Explain how this interrupt works when it is
activated.
39. True or false. Upon reset, all the external hardware interrupts are negative
edge-triggered.
40. In Question 38, how do we make sure that a single interrupt is not recognized
as multiple interrupts?
41. The INTOIF bit belongs to the
register.
register.
42. The INTI IF bit belongs to the
43. True or false. The last two instructions of the ISR for INTI are:
BCF INTCON3,INT1IF
RETFIE
44. Explain the role ofINTOIF and INTOIE in the execution of external interrupt O.
45. Explain the role of INTI IF and INTlIE in the execution of external interrupt I.
46. Assume that the INTI IE bit for external hardware interrupt INTI is enabled
and is positive edge-triggered. Explain how this interrupt works when it is activated. How can we make sure that a single interrupt is not interpreted as multiple interrupts?
47. True or false. INT()""INT2 are part of the PEIE group.
48. True or false. Upon power-on reset, all of INT()""INT2 are positive edge-triggered.
49. Explain the difference between positive and negative edge-triggered interrupts.
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
469
50. How do we make the hardware interrupt negative edge-triggered?
51. True or false. INTO-INT2 must be configured as an input pin for a hardware
interrupt to come in.
52. Which register holds the INTEDGx bits?
SECTION 11.4: PROGRAMMING THE SERIAL COMMUNICATION INTERRUPTS
and
SECTION 11.5: PORTB-CHANGE INTERRUPT
53. True or false. Two separate interrupts are assigned to each of the interrupts,
TXIF and RCIF.
54. Upon power-on reset, what address in the interrupt vector table is assigned to
the serial interrupt? How many bytes are assigned to it?
55. To which register does the TXIF belong? Show how it is enabled.
56. Assume that the TXIE bit for the serial interrupt is enabled. Explain how this
interrupt gets activated and also explain its working upon activation.
57. True or false. Upon reset, serial interrupts are blocked.
58. True or false. The last two instructions of the ISR for the transmit interrupt are:
BCF PIRl,TXIF
RETFIE
59. State how the RCIF is cleared.
60. Assuming that the TXIE bit is set when TXIF is raised, what happens subsequently?
61. Assuming that the RCIE bit is set when RCIF is raised, what happens subsequently?
62. Write a program using interrupts to get data serially and send it to PORTD
while at the same time any changes on PORTB.4 will cause the LED connected to PORTC.7 to toggle.
63. Provide the following information for the PORTB-Change interrupt.
(a) the flag associated with the PORTB-Change interrupt
(b) the register to which these flag belong
(c) the difference between the PORTB-Change and INTO-INT2 interrupts
(d) the pins that are part of the PORTB-Change interrupt
SECTION 11.6: INTERRUPT PRIORITY IN THE PICI8
64.
65.
66.
67.
68.
69.
True or false. Upon reset, all interrupts have high priority.
What register enables the interrupt priority in the PICI8 ? Explain its role.
Which register has the INTOIP bit? Show how to assign it low priority.
Which register has TMRlIP bit? Show how to assign it low priority.
Which register has the INTlIP bit? Show how to assign it low priority.
Assume that INTlIP and INT2IP are both Os. Explain what happens if both
INT lIF and INT2IF are activated at the same time.
70. Assume that TMROIP and TMRlIP are both Os. Explain what happens if both
TMROIF and TMR I IF are activated at the same time.
71. If both TMROIP and TMRlIP are set to HIGH, what happens if both are activated at the same time?
470
72. Ifboth INTlIP and INT2IP in the IP are set to HIGH, what happens if both are
activated at the same time?
73. Explain what happens if a low-priority interrupt is activated while the PICI8
is serving a high-priority interrupt.
74. Explain what happens if a high-priority interrupt is activated while the PIC 18
is serving a low-priority interrupt.
75. Explain the role of the GIEH bit in masking and unmasking the interrupts.
76. True or false. In PIC 18, an interrupt inside an interrupt is not allowed.
77. Explain the role of the GIEL bit in masking and unmasking interrupts.
78. Explain the role of RETFIE in enabling the GIEL bit.
79. Explain the difference between the "RETFIE" and "RETFIE I" instructions.
80. Explain the concept of fast context saving in PIC.
ANSWERS TO REVIEW QUESTIONS
SECTION 11.1: PICI8 INTERRUPTS
1.
2.
3.
4.
5.
6.
Interrupts
INTO and TMRO
Address locations Ox0008 to OxOOOI7. No. It is set when the processor is designed.
GIE ~ 0 means that all interrupts are masked, and as a result no interrupts will be responded
to by the PICI8.
Assuming GIE ~ I, we need "BSF INTCON, TMROIE" .
0008 for the high-priority interrupts and OxOOl8 for the low-priority interrupts.
SECTION 11.2: PROGRAMMING TIMER INTERRUPTS
1.
2.
3.
4.
5.
False. There is a single address for all the timers, TimerO, Timer I , and so on.
0008H
PIEI and "BSF PIE1, TMRlIE" will enable the Timer! interrupt.
After Timerl is started, the timer will count up from F5H to FFH on its own while the PICI8
is executing other tasks. Upon rolling over from FFH to 00, the TMRlIF flag is raised, which
will interrupt the PIel8 in whatever it is doing and forces it to jump to memory location 0008
to execute the ISR belonging to this interrupt.
True
SECTION 11.3: PROGRAMMING EXTERNAL HARDWARE INTERRUPTS
1.
2.
3
4.
5.
6.
7.
True
Bits RBO (PORTB.O), RB I (PORTB.I), and RB2 (PORTB.2)
BSF INTCON3,INTlIE
Upon application ofa low-to-high pulse to pin RBO, the PICI8 is interrupted in whatever it is
doing and jumps to ROM location 0008H to execute the ISR.
False
When the CPU jumps to ROM location 0008 to execute the ISR, the GIE becomes 0, effectively blocking another interrupt from the same source. The last two instructions of the ISR are
"BCF INCON, INTO IF" followed by "RETFIE". While the first instruction will clear the
previous request for interrupt, the second one will make GIE = 1, allowing a new interrupt to
come in from the same source. That can happen only if a new low-to-high pulse is applied to
the pin.
True
CHAPTER 11: INTERRUPT PROGRAMMING IN ASSEMBLY AND C
471
SECTION 11.4: PROGRAMMING THE SERIAL COMMUNICATION INTERRUPTS
1.
2.
3.
True. There is only one interrupt for all all interrupts including the transfer and receive.
Ox0008 for high-priority interrupts and OxOO 18 for low-priority interrupts.
"BSF PIE1, TXIE" will enable the send interrupt and "BSF PIE1, RCIE" will enable the
receive interrupt.
4.
5.
6.
7.
The RCIF (received interrupt flag) is raised when the entire frame of data, including the stop
bit, is received. As a result the received byte is delivered to the RCREG register and the PIC 18
jumps to memory location 0008H to execute the ISR belonging to this interrupt. In the serial
COM interrupt service routine, we must save the RCREG content before it is lost by the
incoming data.
False
True
BCF RIRl, TXIF
RETFIE
SECTION 11.5: PORTB-CHANGE INTERRUPT
1.
2.
3.
False
All interrupts, including the PORTB-Change interrupt, go to location 0008 on default.
INTCON, and we enable it with the instruction "BSF INTCON, RBIF"
4.
BCF INTCON, RBIF
RETFIE
5.
False
SECTION 11.6: INTERRUPT PRIORITY IN THE PICI8
1.
2.
3.
4.
True
IPEN bit of the RCON register. Yes, it is bit-addressable.
IPRI and the instruction "BCF IPR1, TXIP" will do it.
If both are activated at the same time, INTO is serviced first because it is checked tirst. After
INTO is serviced, INTI is serviced.
5.
We have an interrupt inside an interrupt, meaning that the lower-priority interrupt is put on
hold and the higher one is serviced. After servicing this higher-priority interrupt, the PICI8
resumes servicing the lower-priority ISR.
472
CHAPTER 12
LCD AND KEYBOARD
INTERFACING
OBJECTIVES
.'
Upon completion of this chapter,YOIi will be able"~,:"
,
»
»
»
»
»
»
»
,
Describe the funCtions of the pins ofa~ I;CD·
List Instruction eommandeodes forptiJgr~ing anl£J>··
Interface an Len t"thePICI8
.
Program an LCD in ~ssembly aiul C
."
Explain the basic: tPeration of a keybQard
Describe the key press and deteetionnieeftanisms • .
Interface a 4x4.keypad toth.e PIC18~~C BocfAssembly
473
This chapter explores some real-world applications of the PIC 18. We
explain how to interface the PICI8 to devices such as an LCD and a keyboard. In
Section 12.1, we show LCD interfacing with the PICI8. In Section 12.2, keyboard
interfacing with the PIC 18 is shown. We use C and Assembly for both sections.
SECTION 12.1: LCD INTERFACING
This section describes the operation modes of LCOs, then describes how to
program and interface an LCD to a PIC 18 using Assembly and C.
LCD operation
In recent years the LCD has been finding widespread use replacing LEOs
(seven-segment LEOs or other multisegment LEOs). This is due to the following
reasons:
I. The declining prices of LCOs.
2. The ability to display numbers, characters, and graphics. This is in contrast to
LEOs, which are limited to numbers and a few characters.
3. Incorporation of a refreshing controller into the LCD, thereby relieving the
CPU ofthe task of refreshing the LCD. In contrast, the LED must be refreshed
by the CPU (or in some other way) to keep displaying the data.
4. Ease of programming for characters and graphics.
LCD pin descriptions
The LCD discussed in this section has
Table 12-1: Pin Descriptions for LCD
14 pins. The function of each pin is given in
Table 12-1. Figure 12-1 shows the pin positions Pin Srmbol I/O
Descri)!tion
for various LCOs.
Ground
I
Vss
2
+5 V power supply
Vee
Vee, Vss, and VEE
3
Power supply
VEE
While Vee and V ss provide +5 V and
to control contrast
ground, respectively, VEE is used for control4
RS
RS - 0 to select
ling LCD contrast.
command register,
RS, register select
There are two very important registers
inside the LCD. The RS pin is used for their
selection as follows. If RS = 0, the instruction
command code register is selected, allowing the
user to send a command such as clear display,
cursor at home, and so on. If RS = I the data
register is selected, allowing the user to send
data to be displayed on the LCD.
RJW; read/write
RIW input allows the user to write information to the LCD or read information from it.
RIW = I when reading; RlW = 0 when writing.
474
5
RIW
I
6
7
8
9
10
II
12
E
OBO
OBI
OB2
OB3
OB4
OB5
OB6
OB7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
13
14
RS = I to select
data register
RIW = 0 for write,
RIW = I for read
Enable
The 8-bit data bus
The 8-bit data bus
The 8-bit data bus
The 8-bit data bus
The 8-bit data bus
The 8-bit data bus
The 8-bit data bus
The 8-bit data bus
E, enable
The enable pin is used by the LCD to latch information presented to its data
pins. When data is supplied to data pins, a high-to-low pulse must be applied to the
En pin in order for the LCD to latch in the data present at the data pins. This pulse
must be a minimum of 450 ns wide. In this book we call this delay the SDELAY
(short delay) to distinguish it from other delays.
00-07
The 8-bit data pins, DO-D7, are used to send information to the LCD or
read the contents of the LCD's
Table 12-2: LCD Command Codes
internal registers.
code
command to tcb Instruction
To display letters and
Register
numbers, we send ASCII codes
Clear dIsplay screen
for the letters A-Z, a-z, and
Return
home
2
numbers 0-9 to these pins
Decrement cursor (shift cursor to left)
4
while making RS = 1.
Increment cursor (shift cursor to right)
6
There are also instrucShift display right
tion command codes that can 5
Shift display left
be sent to the LCD to clear the 7
Display off, cursor off
display or force the cursor to 8
Display off, cursor on
the home position or blink the A
Display on, cursor off
cursor. Table 12-2 lists the C
Display on, cursor blinking
instruction command codes. To E
Display
on, cursor blinking
F
send any of the commands listShift cursor position to left
ed in Table 12-2 to the LCD, 10
cursor position to right
Shift
14
make pin RS = O. For data,
Shift the entire display to the left
make RS = 1. Then send a 18
high-to-low pulse to the E pin
to enable the internal latch of
the LCD. There are two ways
to send characters (command/data) to the LCD: (1) use
a delay before sending the next
one, (2) use the busy flag to see
12
.;;l~C~~S~h~ift~thc!::e:..:e~n!::tJ.~·re~d!::is:J::p!::.la!J:y,,!t~o..!:th!!:e~rifl.g7:ht~_
:;8;;0:-----:F~0:::r.:::ce=c~ur!.:s:::0:!.r.:to~b.:::egfl.l~·n~n~in~go...:::of~l::::st--:17in~e::....-_
CO
Force cursor to beginning of 2nd line
:;.3:::.8---,,,,..:2~li:.:ne:::s~a:::n;:;:d::..:::.5x:.:.7~m::=a:::t!..!ri:::x...,...,.-:-:,...,.._ _ __
Note: This table is extracted from Table 12-4.
if the LCD is ready for the next one.
14
000000000000000
0
II
14
II
0
o
nnnnnnnlIllllllllllll
14
DMCl610A
DMCl606C
DMC16117
DMC16128
DMC16129
DMC1616433
2
DMC16106B
DMC16207
DMC16230
DMC20215
DMC32216
2 1
0
00
13
HI0 I
00
1
DMC20261
DMC24227
DMC24138
DMC32132
DMC32239
DMC40131
..
FIgure 12-1. Pm PosItIons for VarIous LCDs from Optrex
CHAPTER 12: LCD AND KEYBOARD INTERFACING
475
Sending commands and data to LeOs with a time delay
Program 12-1 shows how to send characters (command/data) to the LCD
without checking the busy flag. Notice that we need to wait 5-10 ms (DELAY)
between issuing each character to the LCD. We call this delay simply DELAY. In
programming an LCD, we also need a long delay for the power-up process. We
call it LDELAY (long delay). SDELAY (short delay) is used to make the En signal wide enough for the LCD's enable input. See Chapter 3 for delays.
Figure 12-2 shows the LCD connections to the microcontroller.
PIC18
RDO
LCD
;:::-,:----""7,"", +5V
DO
Vee
10K
D7
RD7
POT
RBOI----'
RBI 1-----'
RB21-_ _ _---1
Figure 12-2. LCD Connections
Using delay before sending data/command
EQU PORTD
iLCD data pins RDO-RD7
EQU PORTB
iLCD control pins
RBO
EQU
iRS pin of LCD
EQU RBI
;R/W pin of LCD
EQU RB2
;E pin of LCD
TRISD
;PORTD = Output
CLRF
CLRF
TRISB
;PORTB = Output
BCF
LCD- CTRL,EN jenable idle low
CALL
LDELAY
;wait for initialization
MOVLW
Ox38
;init. LCD 2 lines, 5x7 matrix
CALL
COMNWRT
;call command subroutine
LDELAY
;initialization hold
CALL
MOVLW
OxOE
;display on, cursor on
CALL
COMNWRT
;call command subroutine
CALL
DELAY
;give LCD some time
MOVLW
OxOl
iclear LCD
jcall command subroutine
CALL
COMNWRT
CALL
DELAY
;give LCD some time
Ox06
MOVLW
; shift cursor right
jcall command subroutine
CALL
COMNWRT
DELAY
CALL
igive LCD some time
MOVLW
Ox84
icursor at line 1, pos. 4
COMNWRT
CALL
icall command subroutine
CALL
DELAY
;give LCD some time
MOVLW
A'N'
; display letter 'N'
DATAWRT
CALL
icall display subroutine
CALL
DELAY
;give LCD some time
A'OI
MOVLW
;display letter '0'
iPrograrn 12-10
LCD DATA
LCD CTRL
RS
RW
EN
476
AGAIN
jcall display subroutine
CALL
BTG
BRA
DATAWRT
LCD_CTRL,O
AGAIN
MOVWF
BCF
BCF
BSF
CALL
BCF
RETURN
LCD DATA
LCD_CTRL,RS
LCD_CTRL,RW
LCD_CTRL,EN
SDELAY
LCD_CTRL,EN
iRS = 0 for command
;R/W = 0 for write
;E = 1 for high pulse
jmake a wide En pulse
;E = 0 for H-to-L pulse
MOVWF
BSF
BCF
BSF
CALL
BCF
RETURN
LCD DATA
LCD_CTRL,RS
LCD_CTRL,RW
LCD_CTRL,EN
SDELAY
LCD_CTRL,EN
;write data to LCD
;copy WREG to LCD DATA pin
iRS = 1 for data
;R/W = 0 for write
;E = 1 for high pulse
irnake a wide En pulse
;E = 0 for H-to-L pulse
COMNWRT
DATAWRT
jstay here
jsend command to LCD
jCoPY WREG to LCD DATA pin
jlook in previous chapters for delay routines
END
Sending command or data to the LCD using busy flag
We use RS = 0 to read the busy flag bit to see if the LCO is ready to receive
information. The busy flag is 07, and can be read when RIW = 1 and RS = 0, as
follows: ifRIW = 1, RS = O. When 07 = 1 (busy flag = 1), the LCO is busy taking care of internal operations and will not accept any new information. When 07
= 0, the LCO is ready to receive new information.
This is shown in Program 12-2.
;Program 12-2: Check busy flag before sending
;data or command to LCD (See Fig. 12-2)
LCD_DATA
EQU PORTD
;LCD data pins RDO-RD7
EQU PORTB
LCD CTRL
iLCD control pins
;RS pin of LCD
EQU RBO
RS
RW
EQU RBI
; R/W pin of LCD
EQU RB2
EN
jE pin of LCD
CLRF
; PORTD = Output
TRISD
CLRF
;PORTB = Output
TRISB
BCF
LCD_CTRL,EN jenable idle low
CALL
LDELAY
;long delay (250 ms) for power-up
;init. LCD 2 lines, 5x7 char
MOVLW
Ox38
CALL
COMMAND
iissue command
CALL
LDELAY
jinitialization hold
MOVLW
OxOE
iLCD on, cursor on
CALL
COMMAND
;issue command
CALL
READY
; I s LCD ready?
MOVLW
jclear LCD command
OxOl
CALL
COMMAND
iissue command
CALL
READY
; I s LCD ready?
MOVLW
ishift cursor right
Ox06
CHAPTER 12: LCD AND KEYBOARD INTERFACING
477
HERE
CALL
CALL
MOVLW
CALL
CALL
MOVLW
CALL
CALL
MOVLW
CALL
BRA
COMMAND
READY
Ox86
COMMAND
READY
A'N'
iissue command
iIs LCD ready?
iCUrSQr: line 1, pos. 6
jcommand subroutine
iIs LCD ready?
;display letter 'N'
DATA DISPLAY
jIs LCD ready?
READY
AIO'
; display letter '0'
DATA DISPLAY
HERE
;STAY HERE
i----------------------------------------------
COMMAND
MOVWF
BCF
BCF
BSF
CALL
BCF
RETURN
LCD DATA
LCD_CTRL,RS
LCD_CTRL,RW
LCD_CTRL,EN
SDELAY
LCD_CTRL,EN
;issue command code
iRS = 0 for command
;R/W = 0 for write
;E = 1 for high pulse
imake a wide En pulse
;E = 0 for H-to-L pulse
j----------------------------------------------
DATA DISPLAY MOVWF LCD DATA
LCD_CTRL,RS
BSF
LCD_CTRL,RW
BCF
LCD_CTRL,EN
BSF
CALL
SDELAY
BCF
LCD_CTRL,EN
RETURN
;copy WREG to LCD DATA pin
;RS = 1 for data
;R/W = a for write
;E = 1 for high pulse
imake a wide En pulse
;E = 0 for H-to-L pulse
i----------------------------------------------
READY
SETF
BCF
BSF
jread command reg
BACK
BSF
CALL
BCF
BTFSC
BRA
CLRF
RETURN
TRISD
imake PORTD input port for LCD data
LCD_CTRL,RS iRS = 0 access command reg
LCD_CTRL,RW ;R/W = 1 read command reg
and check busy flag
LCD_CTRL,EN ;E = 0 for L-to-H pulse
SDELAY
imake a wide En pulse
LCD_CTRL,EN ;E = 1 L-to-H pulse
LCD_DATA, 7
;stay until busy flag = 0
BACK
TRISD ;make PORTD output port for LCD data
;look in previous chapters for delay routines
END
Notice in Program 12-2 that the busy flag is D7 of the command register.
To read the command register, we make RIW = I and RS = 0, and a L-to-H pulse
for the E pin will provide us the command register. After reading the command
register, if bit D7 (the busy flag) is HIGH, the LCD is busy and no information
(command or data) should be issued to it. Only when D7 = 0 can we send data or
commands to the LCD. Notice that no time delays are used in this method because
we are checking the busy flag before issuing commands or data to the LCD.
Contrast the read and write timing for the LCD in Figures 12-3 and 12-4. Note that
the E line is negative edge-triggered for the write while it is positive edge-triggered for the read.
478
DO-D7-----------·--t-D--,~K~____D
__am
_____J)
I
E
R/W
~L------
RS
to == Data output delay time
tAS
Setup time prior to E (going high) for both RS and RIW = 140 ns (minimum)
=
tAH = Hold time after E has come down for both RS and R/W = 10 os (minimum)
Note: Read requires an L-to-H pulse for the E pin.
Figure 12-3. LCD Timing for Read ( L-to-H for Eline)
---------------<\
Data
..
E
R/W
RS~
,----+-------------~~
tpWH =
Enable pulse width = 450 os (minimum)
tosw = Data setup time
=
195 os (minimum)
tH = Data hold time = 10 os (minimum)
tAS =
Setup time prior to E (going high) for both RS and RJW = 140 os (minimum)
tAH = Hold time after E has come down for both RS and RIW = 10 os (minimum)
Figure 12-4. LCD Timing for Write (H-to-L for Eline)
CHAPTER 12: LCD AND KEYBOARD INTERFACING
479
LCD data sheet
In the LCD, one can put data at any location. The following shows address
locations and how they are accessed.
RS
RlW
DB7
00
DB6
DBS
DB4
DB3
DB2
OBI
DBO
A
A
A
A
A
A
A
where AAAAAAA = 0000000 to 0100111 forline I and AAAAAAA = 1000000
to 1100111 for line 2. See Table 12-3.
The upper address range can go as high as 0100111 for the 40-character-wide LCD, while for the 20-character-wide LCD it goes up to 010011 (19 decimal = 10011 binary). Notice that the upper-range 0100111 (binary) = 39 decimal,
which corresponds to locations 0 to 39 for the LCDs of 40x2 size.
From the above discussion we can get the addresses of cursor positions for
various sizes ofLCDs. See Figure 12-5 for the cursor addresses for common types
ofLCDs. Note that all the addresses are in hex. Table 12-4 provides a detailed list
of LCD commands and instructions. (Table 12-2 is extracted from this table.)
Table 12-3: LCD Addressing
Line I {min}
Line 1 {max}
Line 2 {min}
Line 2 {max}
16 x 2 LCD
20 x 1 LCD
20 x 2 LCD
20 x 4 LCD
40 x 2 LCD
DB7
1
1
DB6
0
0
1
1
DBS
0
1
0
1
DB4
0
0
0
0
DB3
0
0
0
0
80
CO
80
80
CO
80
CO
94
D4
80
CO
81
C1
81
81
C1
81
C1
95
D5
81
C1
82
C2
82
82
C2
82
C2
83
C3
83
83
C3
83
C3
97
D7
83
C3
84
85
C4
C5
through
through
through
through
through
through
through
through
through
96
D6
82
C2
Note: All data is in hex.
Figure 12-S. Cursor Addresses for Some LCDs
480
DB2
0
1
0
DBl
0
1
0
DBO
0
1
0
86 through 8F
C6 through CF
93
93
D3
93
D3
A7
E7
A7
E7
Table 12-4: List of LCD Instructions
Instruction
Description
Clear Display
000 0 0 0 0 001
Return Home
o
0 0 0 0 0 001
Entry Mode
Set
o
0 0 0 0 0 0 1 liD S
Display Oll!
Off Control
o
0 0 0 0 OlD C B
Cursor or
Display Shift
Function Set
o
0 0 0 0 1 SiC R/L -
o
0 0 0 1 DL N F - -
Set CG RAM o
Address
Set DD RAM 0
Address
Read Busy
0
Flag & Address
Wnte Data
CGorDDRAM
Read Data
CGorDDRAM
0
0 1
AGC
0 1
ADD
1 BF
AC
1 0
1 1
Write Data
Read Data
Execution
Time
(Max)
Clears entire display and sets DD
RAM address 0 in address counter
Sets DD RAM address 0 as address
counter. Also returns display being
shifted to original position. DD RAM
contents remain unchanged.
Sets cursor move difectlOn and specifies
shift of display. These operations are
performed during data write and read.
Sets OllIOft of entire display (D),
cursor On/Off (C), and blink of cursor
position character (B).
Moves cursor and shifts display wlthout changing DD RAM contents.
Sets interface data length (DL), number of display lines (L), and character
font (F).
Sets CG RAM address. CG RAM data
is sent and received after this setting.
Sets DD RAM address. DD RAM data
is sent and received after this setting.
Reads busy flag (BF) mdlcatmg mternal operation is being performed and
reads address counter contents.
Wntes data into DD or CG RAM.
40 JlS
Reads data from DD or CG RAM.
40 JlS
1.64 ms
1.64 ms
40 JlS
40 JlS
4U JlS
40 JlS
40 JlS
40 JlS
40 JlS
Notes:
1. Execution times are maximum times when fep or fose is 250 kHz.
2. Execution time changes when frequency changes.
(e.g., when fcp or fosc is 270 kHz: 40 ~ x 250 I 270 ~ 37 ~s.)
3. Abbreviations:
DDRAM
Display data RAM
CGRAM
Character generator RAM
ACC
CG RAM address
DD RAM address, corresponds to cursor address
ADD
AC
Address counter used for both DD and CG RAM addresses.
I/D~ I
lID ~ 0 Decrement
Increment
S~l
Accompanies display shift
S/C~ I
SIC ~ 0 Cursor move
Display shift;
RIL~ I
RIL ~ 0 Shift to the left
Shift to the right;
DL~ I
8 bits, DL ~ 0: 4 bits
N~ I
I line, N ~ 0: I line
F~ I
5X lOdots,F~0:5X7dots
BF~ I
Internal operation;
BF ~ 0 Can accept instruction
CHAPTER 12: LCD AND KEYBOARD INTERFACING
481
Optrex is one of the largest
manufacturers of LCOs. You can obtain
datasheets from their Web site,
http://www.optrex.com.
The LCOs can be purchased from the
following Web sites:
http://www.digikey.com
http://www.jameco.com
http://www.elexp.com
http://www.bgmicro.com
Sending information to LCD using the TBLRD instruction
Program 12-3 shows how to use the TBLRD instruction to send data and
commands to an LCD.
For a PICI8 C version of LCD programming see Program 12-IC and
Program 12-2C.
;Program 12-3: Using TableRead
;PORTD = DO-D7, RBO = RS, RBI = R/W, RB2 = E pins
LCD DATA
LCD CTRL
RS
RW
EN
EQU PORTD
;LCD data pins RDO-RD7
EQU PORTB
jLCD control pins
EQU RBO
;RS pin of LCD
EQU RBI
;R/W pin of LCD
EQU RB2
;E pin of LCD
CLRF
TRISD
; PORTD = Output
CLRF
TRISB
;PORTB = Output
BCF
LCD_CTRL,EN ;enable idle low
CALL
LDELAY
;long delay (250 ms) for power-up
MOVLW upper (MYCOM)
MOVWF TBLPTRU
MOVLW high (MYCOM)
MOVWF TBLPTRH
MOVLW low (MYCOM)
MOVWF TBLPTRL
CI
TBLRD*+
MOVF TABLAT,W
482
;give it to WREG
IORLW OxO
iIs it the end of command?
BZ
SEND DAT
;if yes then go to display data
CALL
COMNWRT
CALL
BRA
DELAY
CI
icall command subroutine
igive LCD some time
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
DT1
upper (MYDATA)
TBLPTRU
high (MYDATA)
TBLPTRH
low (MYDATA)
TBLPTRL
TBLRD*+
OVER
COMNWRT
MOVF TABLAT,W
IORLW OxO
BZ
OVER
CALL
DATAWRT
CALL
DELAY
BRA
DT1
BRA
OVER
MOVWF
BCF
BCF
BSF
CALL
BCF
RETURN
DATAWRT
MYCOM
igive it to WREG
iIs it the end of data string?
iif yes then exit
icall DATA subroutine
igive LCD some time
LCD DATA
LCD_CTRL,RS
LCD_CTRL,RW
LCD_CTRL,EN
SDELAY
LCD_CTRL,EN
;stay here
isend command to LCD
jCopy WREG to LCD DATA pin
iRS = 0 for command
;R/W = 0 for write
;E
=
1 for high pulse
imake a wide En pulse
;E
=
0 for H-to-L pulse
;write data to LCD
MOVWF LCD DATA
;copy WREG to LCD DATA pin
BSF
LCD_CTRL,RS
iRS = 1 for data
LCD_CTRL,RW
BCF
;R/W = 0 for write
LCD_CTRL,EN
BSF
;E = 1 for high pulse
jmake a wide En pulse
CALL
SDELAY
BCF
LCD_CTRL,EN
;E = 0 for H-to-L pulse
RETURN
500H
ORG
DB Ox3B,OxOE,Ox01,Ox06,OxB4,O;commands and null
MYDATA
DB IIHELLO",O
;data and null
ilook in previous chapters for delay routines
END
This CI8 program sends letters 'M', 'D', and 'E' to the LCD using delays.
j/Program 12-1C: This is the C version of Program 12-1.
#include <P1BF45BO.h>
#define ldata PORTD
#define rs PORTBbits.RBO
#define rw PORTBbits.RB1
#define en PORTBbits.RB2
//PORTD = LCD data pins
/ Irs
PORTB. 0
/ /rw
PORTB.1
PORTB. 2
/ len
(Fig. 12-2)
void main()
TRISD = 0;
TRISB = 0;
en = 0 ;
MSDelay(250)
lcdcmd (Ox3B)
MSDelay(250)
lcdcmd (OxOE)
//both ports Band D as output
lienable idle low
;
;
;
;
//init. LCD 2 lines, 5x7 matrix
//displayon, cursor on
CHAPTER 12: LCD AND KEYBOARD INTERFACING
483
MSDelay (15) ;
lcdcmd (OxOl) ;
MSDelay(15) ;
lcdcmd(Ox06);
MSDelay(15) ;
lcdcmd(Ox86) ;
MSDelay (15) ;
lcddata ('M') ;
MSDelay (15) ;
//clear LCD
/ /shift cursor right
//line 1, position 6
//display letter 'M'
lcddata('D')i
//display letter 'D'
MSDelay (15) ;
lcddata( 'E');
/ /display letter 'E'
void lcdcmd(unsigned char value)
Idata = value;
rs
0;
rw = 0;
en = 1;
MSDelay(l) ;
en = 0;
//put the value on the pins
//strobe the enable pin
void lcddata(unsigned char value)
Idata = value;
rs
1;
rw = OJ
en = Ii
//put the value on the pins
//strobe the enable pin
MSDelay (1) ;
en =
0;
void MSDelay(unsigned int itime)
j;
for(i=Oii<itimeii++)
for(j=0;j<l35;j++) ;
unsigned int i ,
The following is the eversion of Program 12-2, using the busy flag method.
//Program 12-2C. C version of Program 12-2
#include <P18F458.h>
#define ldata PORTD
//PORTD = LCD data pins
#define rs PORTBbits.RBO
Ilrs
PORTB.O
#define rw PORTBbits.RB1
Ilrw = PORTB.1
#define en PORTBbits.RB2
lien = PORTB.2
#define busy PORTDbits.RD7 //busy = PORTD.7
(Fig.
12-2)
void main()
{
TRISD = 0;
484
//both ports Band D as output
TRISB = 0;
en = 0;
MSDelay(250) ;
lcdcmd (Ox3 8) ;
MSDelay(250) ;
lcdcmd (OxOE) ;
lcdready () ;
lcdcmd (Ox01) ;
1cdready() ;
lcdcmd (Ox06) ;
lcdready () ;
lcdcmd (Ox86) ;
lcdready () ;
lcddata ('M') ;
lcdready() ;
lcddata( 'D');
lcdready() ;
lcddata( 'E');
lienable idle low
/ /long delay
//long delay
//check the LCD busy flag
//check the LCD busy flag
//check the LCD busy flag
//line 1, position 6
//check the LCD busy flag
//check the LCD busy flag
//check the LCD busy flag
}
void lcdcmd(unsigned char value)
(
//put the value on the pins
Idata = value;
rs = OJ
rw = 0 i
en = Ii
MSDelay(l) ;
en =
//strobe the enable pin
OJ
}
void lcddata(unsigned char value)
(
//put the value on the pins
Idata = value;
rs = 1;
rw = 0;
en = 1;
MSDelay(l) ;
en = OJ
//strobe the enable pin
void lcdready ()
{
//make PORTD an input
TRISD = OxFF;
rs = 0 i
rw = 1;
do
//wait here for busy flag
(
en = Ii
MSDelay(l) ;
en = 0;
}while(busy==l) ;
TRISD = 0;
//strobe the enable pin
void MSDelay(unsigned int itime)
{
unsigned int i,
j;
for(i=O;i<itimeji++)
for(j=O;j<135;j++) ;
}
CHAPTER 12: LCD AND KEYBOARD INTERFACING
485
//Program 12-3C: C version of Program 12-3 Displaying Data in ROM
#include <P18F4S8.h>
#define ldata PORTD
IlpORTD
#define rs PORTBbits.RBO
#define rw PORTBbits.RB1
#define en PORTBbits.RB2
LCD data pins (Fig. 12-2)
PORTB.O
Ilrs
PORTB.l
Ilrw
PORTB.2
lien
#pragma romdata mycom = Ox300
Ilcommand at ROM addr Ox300
far rom const char mycom[] = (OxOE,OX01,Ox06,Ox84j;
#pragma romdata mydata = Ox320
far rom const char mydata []
=
Iidata at ROM addr Ox320
"HELLOIl i
void main()
unsigned char z=O;
TRISD = 0;
TRISB = 0;
Ilboth ports Band D as output
en
lienable idle low
OJ
=
MSDelay(2S0) ;
lcdcmd(Ox38);
MSDelay(2S0) ;
Iisend out the commands
for(jz<4jz++)
lcdcmd(mycom[z]);
MSDelay(lS) ;
Iisend out the data
for{z=Ojz<Sjz++)
lcddata(mydata[z]) ;
MSDelay(lS) ;
while(l); Ilinfinite loop
void lcdcmd(unsigned char value)
Idata = value;
rs
OJ
rw = OJ
Ilput the value on the pins
en = 1;
Iistrobe the enable pin
MSDelay(l) ;
en = OJ
void lcddata(unsigned char value)
Idata
rs
rw
486
=
1;
=
OJ
value;
Ilput the value on the pins
en
=
1;
//strobe the enable pin
MSDelay (1) ;
en
=
0;
void MSDelay(unsigned int itime)
{
unsigned int i, j;
for(i=O;i<itimeji++)
for(j=O;j<l35;j++) ;
Review Questions
I. The RS pin is an _ _ _ (input, output) pin for the LCD.
2. The E pin is an
(input, output) pin for the LCD.
3. The E pin requires an
(H-to-L, L-to-H) pulse to latch in infonnation
at the data pins of the LCD.
4. For the LCD to recognize infonnation at the data pins as data, RS must be set
to
(HIGH, LOW).
5. Give the command codes for line I, first character, and line 2, first character.
SECTION 12.2: KEYBOARD INTERFACING
Keyboards and LCDs are the most widely used input/output devices and a
basic understanding of them is essential. In this section, we first discuss keyboard
fundamentals, along with key press detection and key identification mechanisms.
Then we show how a keyboard is interfaced to a PICI8.
Interfacing the keyboard to the PIC18
At the lowest level, keyboards are organized in a matrix of rows and
columns. The CPU accesses both rows and columns through ports; therefore, with
two 8-bit ports, an 8 x 8 matrix of keys can be connected to a microprocessor.
When a key is pressed, a row and a column make a contact; otherwise, there is no
connection between rows and columns. In IBM PC keyboards, a single microcontroller takes care of hardware and software interfacing of the keyboard. In such
systems, programs stored in the ROM of the microcontroller scan the keys continuously, identify which one has been activated, and present it to the motherboard.
See Example 12-3. In programming for keypad interfacing we must have two
processes: (a) key press detection, and (b) key identification. There are two ways
by which the PICI8 can perfonn key press detection: (I) the interrupt method, and
(2) the scanning method. In the PIC 18, the PORTB-Change interrupt can be used
to implement the interrupt-based key press detection. Next we explain the interrupt method.
Interrupt method of key press detection
Figure 12-6 shows a 4 x 4 matrix keypad connected to PORTB. The rows
are connected to PORTB.Low (RB3-RBO) and the columns are connected to
PORTB.High (RB7-RB4), which is the PORTB-Change interrupt. As we dis-
CHAPTER 12: LCD AND KEYBOARD INTERFACING
487
Example 12-3
From Figure 12-6, identify the row and column of the pressed key for the following:
RB3- RBO = 1110 for the row, RB7-RB4 = 1011 for the column
Solution:
From Figure 12-6, the row and column can be used to identify the key. The row belongs
to RBO and the column belongs to RB6; therefore, key number 2 was pressed.
3
2
~d
RBO
7
B
A
F
RB3
PORTB
(Out)
'>;ad
4
9
'>;ad
'>;ad
8
'>pd
D
E
'>;ad
'>pd
'>;ad
'>pd
">Pd
RB2
0
'>pd
5
6
'>;ad
RB1
1
'>pd
'>;ad
C
'>;ad
'>;ad
RB7 RB6
RB5 RB4
Using PORTB-Change
interrupt
PORTB
(In)
Figure 12-6. Matrix Keyboard Connection to Ports
cussed in Chapter 11, any changes on the RB7-RB4 pins will cause an interrupt
indicating a key press. Examine Program 12-4, which goes through the following
stages:
I. To make sure that the preceeding key has been released, Os are output to all
rows at once, and the columns are read and checked repeatedly until all the
columns are HIGH. When all columns are found to be HIGH, the program
waits for a short amount of time before it goes to the next stage of waiting for
a key to be pressed.
2. To see if any key is pressed, the columns are connected to the PORTB-Change
interrupt. Therefore, any key press will cause an interrupt and the microcontroller will execute the ISR. The ISR must do two things: (a) ensure that the
first key press detection was not erroneous due to spike noise, and (b) wait 20
ms to prevent the same key press from being interpreted as multiple key presses. See Figure 12-8 for keyboard debounce.
3. To detect which row the key press belongs to, the microcontroller grounds one
row at a time, reading the columns each time. If it finds that all columns are
HIGH, this means that the key press cannot belong to that row; therefore, it
grounds the next row and continues until it finds the row the key press belongs
488
(
Start
)
I
Read all columns
no
I
!
Find which key
is pressed
L -_ _ (
Get scan code
from table
RBIF?
yes
Return
from interrupt
Wait for debounce
I
Read ali columns
I
~
Figure 12-7. Flowchart for Program 12-4
CHAPTER 12: LCD AND KEYBOARD INTERFACING
489
to. Upon finding the row that the key press belongs to, it sets up the starting
address for the look-up table holding the scan codes (or the ASCll value) for
that row and goes to the next stage to identify the key.
4. To identify the key press, the microcontroller rotates the column bits, one bit
at a time, into the carry flag and checks to see if it is LOW. Upon finding the
zero, it pulls out the ASCII code for that key from the look-up table; otherwise,
it increments the pointer to point to the next element of the look-up table.
Figure 12-7 flowcharts this process.
The look-up table method shown in Program 12-4 can be modified to work
with any matrix up to 8 x 4. Figure 12-7 provides the flowchart for Program 12-4
for scanning and identifying the pressed key.
vee - - - ,
GND
Unstable
Unstable
Figure 12-8. Keyboard Debounce
Examine Program 12-4. Notice in that program that the interrupt detects
the key press. Then it is the job of the ISR to identify to which key the key press
belongs (key identification). Program 12-4C is a CI8 version of Program 12-4. In
the Assembly version (12-4), the character is placed on PORTD, while in the C18
version (12-4C), it is sent to the serial port to be displayed on the monitor.
Program 12-4: This program waits for a key press on PORTB, then places the
character on PORTD. We assume the following for this program:
RB3~RBO connected to rows
RB7~RB4 connected to columns
D15mH
D15rnL
COL
DR15mH
DR15rnL
,
0
EQU
EQU
EQU
EQU
EQU
D'lOO'
D'255'
OxOB
Ox09
OxOA
;15 rns de lay high byte of value
; low byte of value
;holds the column found
;registers for 15 rns delay
___________________________________________
RESET ISR
HI ISR
~
ORG
OxOOOOOO
GOTO MAIN
OxOOOOOB
ORG
BTFSC INTCON,RBIF
BRA
RBIF ISR
RETFIE
~
490
_
ijump over interrupt table
jWas it a PORTB change?
iyes then go to ISR
ielse return
;------------program for initialization
MAIN
CLRF TRISD
;make PORTD output port
BCF
INTCON2,RBPU;enable PORTB pull-up resistors
MOVLW OxFO
imake PORTB high input ports
imake FORTB low output ports
MOVWF TRISB
MOVWF PORTB
;ground all rows
KEYOPEN
CPFSEQ PORTB
iare all keys open
GOTO KEYOPEN
iwait until keypad ready
MOVLW upper(KCODEO)
MOVWF TBLPTRU
;load upper byte of TBLPTR
MOVLW high(KCODEO)
MOVWF TBLPTRH
;load high byte of TBLPTR
BSF
INTCON,RBIE ;enable PORTB change interrupt
BSF
INTCON,GIE ;enable all interrupts globally
GOTO LOOP
iwait for key press
LOOP
;------------key identification ISR
iwait for debounce
RBIF ISR
CALL DELAY
MOVFF PORTB,COL
;get the column of key press
MOVLW OxFE
MOVWF PORTB
iground row 0
;Did PORTB change?
CPFSEQ PORTB
BRA
ROWO
i yes then row 0
MOVLW OxFC
iground row 1
MOVWF PORTB
CPFSEQ PORTB
;Did PORTB change?
BRA
ROWl
iyes then row 1
MOVLW OxFB
MOVWF PORTB
i ground row 2
CPFSEQ PORTB
;Did PORTB change?
BRA
ROW2
iyes then row 2
MOVLW OxF7
MOVWF PORTB
iground row 3
CPFSEQ PORTB
iDid PORTB change?
BRA
ROW3
iyes then row 3
GOTO BAD RBIF
i no then key press too short
ROWO
MOVLW low (KCODEO) iset TBLPTR = start of row 0
BRA
FIND
ifind the column
ROWl
MOVLW low (KCODE1) iset TBLPTR = start of row 1
;find the column
BRA
FIND
ROW2
MOVLW low (KCODE2 ) iset TBLPTR = start of row 2
BRA
FIND
ifind the column
ROW3
MOVLW low (KCODE3) iset TBLPTR = start of row 3
FIND
MOVWF TBLPTRL
;load low byte of TBLPTR
MOVLW OxFO
XORWF COL
;invert high nibble
;bring to low nibble
SWAPF COL,F
AGAIN
RRCF COL
irotate to find column
BC
MATCH
;column found, get the ASCII code
INCF TBLPTRL
ielse point to next col. address
CHAPTER 12: LCD AND KEYBOARD INTERFACING
491
BRA
AGAIN
; keep searching
TBLRD*+
;get ASCII code from table
MOVFF TABLAT,PORTD;display pressed key on PORTD
WAIT
MOVLW OxFO
MOVWF PORTB
;reset PORTB
CPFSEQ PORTB
;Did PORTB change?
BRA
WAIT
iyes then wait for key release
BCF
INTCON,RBIF ;clear PORTB, change flag
RETFIE
jreturn and wait for key press
BAD RBIF
MOVLW OxOO
jreturn null
GOTO WAIT
;wait for key release
;-------------delay
DELAY:
MOVLW D15mH
;high byte of delay
MOVWF DR15mH
istore in register
D2:
MOVLW D15mL
;low byte of delay
MOVWF DR15mL
istore in register
DL
DECF DR15mL,F
;stay until DR15mL becomes a
BNZ
Dl
DECF DR15mH,F
;loop until all DR15m = OxOOOO
BNZ
D2
RETURN
;-------------key scancode look-up table
ORG
300H
KCODEO:
DB
'0' '1' , '2' , r 3'
jROW 0
KCODE1:
DB
t 4
'5' , '6' '7 '
; ROW 1
KCODE2:
DB
'8 I , '9' 'A' 'B'
;ROW 2
KCODE3 :
Ie', 'Dr 'E' 'F'
DB
; ROW 3
END
MATCH
I
I
I
I
I
f
I
I
Program 12-4C shows keypad programming in PICI8 C.
Program 12-4C: This C 18 program reads the keypad and sends the result to the
serial port. We assume the following for this program.
RBO-RB3 connected to rows
RB4-RB7 connected to columns
Serial port is set for 9600 baud (10 MHz XTAL), 8-bit mode, and 1 stop bit.
#include <plBf458.h>
void SerTX(unsigned char
X)i
void RBIF_ISR{void) ;
void MSDelay(unsigned int millisecs) i
uns igned char keypad [4] [4] = {' 0 ' , '1'
I r 2 ' , '3 ' I
'4 I , t 5 1 I '6' , 17 r I
18', '9' / 'A', 'B',
'C','D','E','F'}i
#pragma code My_HiPrio_Int =OxOOOB //high-priority interrupt
void My HiPrio Int
{
-
asm
GOTO chk isr
endasm
492
(void)
#pragma code
#pragma interrupt chk isr
void chk_isr (void)
if (INTCONbits.RBIF==l)
RBIF _ISR ( );
//which ISR
//RBIF caused interrupt?
//yes go to RBIF_ISR
#pragma code
void main ()
{
TRISD=O;
INTCON2bits.RBPU=0;
TRISB=OxFO;
PORTB=OxFO;
while (PORTB!=OxFO) ;
TXSTA=Ox20;
SPBRG=15;
TXSTAbits.TXEN=l;
RCSTAbits.SPEN=l;
INTCONbits.RBIE=l;
INTCONbits.GIE=l;
while (1) ;
//make PORTD output port
lienable PORTB pull-up resistors
//PORTB low as output and high as input
//clear PORTB low
//wait until key not pressed
//choose low baud rate, 8-bit
//9600 baud rate, XTAL = 10 MHz
lienable transmit
lienable serial port
lienable PORTB interrupt on change
lienable interrupts globally
//wait until key press
}
void RBIF ISR(void)
//finds the key pressed
{
unsigned char temp,COL=O,ROW=4i
MSDelay (15) ;
temp = PORTB;
//get column
temp "'= OxFO i
//invert high nibble
if(!temp) return;
//if false alarm return
while (temp«=l) COL++i
//find the column
PORTB = OxFE;
//ground row 0
if(PORTB != OxFE)
//Did high nibble change?
//yes then row 0
ROW = 0;
/ /try next row
else {
PORTB = OxFD;
//ground row 1
if(PORTB != OxFD)
//Did high nibble change?
ROW = 1;
//yes then row 1
else {
//try next row
PORTB = OxFB;
/ /ground row 2
if(PORTB != OxFB)
//Did high nibble change?
//yes then row 2
ROW = 2;
//try last row
else {
PORTB = OxF7;
//ground row 3
if(PORTB != OxF7) //Did high nibble change?
ROW = 3;
//yes then row 3
}
if (ROW<4)
//Did we find a valid row?
SerTX (keypad [ROW] [COL] ); / /then send character
while (PORTB!=OxFO) PORTB=OxFO;
//wait for release
INTCONbits.RBIF=O;
//reset flag
void SerTX(unsigned char x)
//sends character
{
whi1e(PIR1bits.TXIF!=1) ;
TXREG=Xi
//wait until ready
//send character out serial port
CHAPTER 12: LCD AND KEYBOARD INTERFACING
493
void MSDelay(unsigned int millisecs)
{
unsigned int if ji
for(i=Oii<millisecsii++)
for(j=O;j<l35;j++) ;
Scanning method for key press detection
Another method for key press detection is by scanning. In this method, to
detect a pressed key, the microcontroller grounds all rows by providing 0 to the
output latch, then it reads the columns. If the data read from the columns are equal
to 1111, no key has been pressed and the process continues until a key press is
detected. If one of the column bits has a zero, however, this means that a key press
has occurred. After a key press is detected, the microcontroller will go through the
process of identifying the key. Starting with the top row, the microcontroller
grounds it by providing a LOW to the first row only; then it reads the columns. If
the data read is all 1s, no key in that row is activated and the process is moved to
the next row. It grounds the next row, reads the columns, and checks for any zero.
This process continues until the row is identified. After identification of the row in
which the key has been pressed, the next task is to find out which column the
pressed key belongs to. This should be easy since the microcontroller knows at any
time which row and column are being accessed. Figure 12-9 shows the flowchart
for this method. The program implementation is left to the reader.
Some IC chips, such as National Semiconductor's MM74C923, incorporate
keyboard scanning and decoding all in one chip. Such chips use combinations of
counters and logic gates (no microcontroller) to implement the underlying concepts presented in this section.
Review Questions
I. True or false. To see if any key is pressed, all rows are grounded.
2. IfRB7-RB4 = 0 III is the data read from the columns, which column does the
pressed key belong to?
3. True or false. Key press detection and key identification require two different
processes.
4. In Figure 12-6, if the rows are RB3-RBO = 1110 and the columns are
RB7-RB4 = III 0, which key is pressed?
5. True or false. To identify the pressed key, one row at a time is grounded.
494
I
Read all columns
I
!
no
Key.
'-____ < press
In
his row?
Find which key
is pressed
Get scan code
from table
no
L -_ _ (Anyke
down?
yes
(
Return )
Wait for debounce
I
Read all columns
I
no
Figure 12-9. Flowchart of Scanning Method for Key Press Detection
CHAPTER 12: LCD AND KEYBOARD INTERFACING
495
SUMMARY
This chapter showed how to interface real-world devices such as LCDs and
keypads to the PIC IS. First, we described the operation modes of LCDs, then
described how to program the LCD by sending data or commands to it via its interface to the PIC IS.
Keyboards are one of the most widely used input devices for PIC IS projects. This chapter also described the operation of keyboards, including key press
detection and key identification mechanisms. Then the PIC IS was shown interfacing with a keyboard. PIC IS programs were written to return the ASCII code for
the pressed key.
PROBLEMS
SECTION 12.1: LCD INTERFACING
1.
2.
3.
4.
5.
6.
7.
S.
9.
10.
II.
12.
13.
14.
15.
16.
496
The LCD discussed in this section has
(4, S) data pins.
Describe the function of pins E, R/W, and RS in the LCD.
What is the difference between the Vee and VEE pins on the LCD?
"Clear LCD" is a _____ (command code, data item) and its value is _
hex.
What is the hex value of the command code for "display on, cursor on"?
Give the state of RS, E, and R/W when sending a command code to the LCD.
Give the state of RS, E, and R/W when sending data character' Z' to the LCD.
Which of the following is needed on the E pin in order for a command code
(or data) to be latched in by the LCD?
(a) H-to-L pulse (b) L-to-H pulse
True or false. For the above to work, the value of the command code (data)
must already be at the 00-07 pins.
There are two methods of sending streams of characters to the LCD: (I) checking the busy flag, or (2) putting some time delay between sending each character without checking the busy flag. Explain the difference and the advantages and disadvantages of each method. Also explain how we monitor the
busy flag.
For a 16 x 2 LCD, the location of the last character of line I is SFH (its command code). Show how this value was calculated.
For a 16 x 2 LCD, the location of the first character of line 2 is COH (its command code). Show how this value was calculated.
For a 20 x 2 LCD, the location of the last character ofline 2 is 93H (its command code). Show how this value was calculated.
For a 20 x 2 LCD, the location of the third character ofline 2 is C2H (its command code). Show how this value was calculated.
For a 40 x 2 LCD, the location of the last character of line I is A7H (its command code). Show how this value was calculated.
For a 40 x 2 LCD, the location of the last character of line 2 is E7H (its command code). Show how this value was calculated.
17. Show the value (in hex) for the command code for the 10th location, line I on
a 20 x 2 LCD. Show calculations.
18. Show the value (in hex) for the command code for the 20th location, line 2 on
a 40 x 2 LCD. Show calculations.
19. Rewrite the COMNWRT subroutine. Assume connections RC4 = RS, RC5 =
R/W, RC6 = E.
20. Repeat Problem 19 for the data write subroutine. Send the string "Hello" to the
LCD by checking the busy flag. Use the instruction TBLRD.
SECTION 12.2: KEYBOARD INTERFACING
21. In reading the columns of a keyboard matrix, if no key is pressed we should
get all
(Is, Os).
22. In Program 12-4, to detect the key press, which of the following is performed?
(a) PORTB-Change interrupt
(b) grounding one row at time
23. In Figure 12-6, to identify the key pressed, which ofthe following is grounded?
(a) all rows
(b) one row at time
(c) both (a) and (b)
24. For Figure 12-6, indicate the key press for RB7~RB4 = 0111, RB3~RBO =
III O.
25. Indicate an advantage and a disadvantage of using an IC chip instead of a
microcontroller for keyboard scanning and decoding.
26. What is the best compromise for the answer to Problem 25?
ANSWERS TO REVIEW QUESTIONS
SECTION 12.1: LCD INTERFACING
l.
2.
3.
4.
5.
Input
Input
H-to-L
HIGH
80H and COH
SECTION 12.2: KEYBOARD INTERFACING
l.
True
2.
Column 3
3.
4.
5.
True
0
True
CHAPTER 12: LCD AND KEYBOARD INTERFACING
497
CHAPTER 13
ADC, DAC, AND SENSOR
INTERFACING
OBJECTIVES
Upon~mpletion
ofthis chapteJ:, you will be able to:
»
>i>
Discuss 'the ADC (analog-tQ-digital cOBverter) section ~f the PIC18 chip
jll~ ~~J:ature sensorS to tile PIC18
•,». . EXplaiit tim ~,s$~f data aequisitlOnusing ADC
»: •. Describe f,ct!I:B: tellOOsHierinStllectlng an ADC chip
»". :Pril1iOOri tne~Kil$'~ADCi~CanctAssembly
» .• :llescrlbe tbe:~~ ~ratj~.!)f a DAC(digitaHo-analog l!Q\lverter} chip
» : ;Iot'"",:aiJM,.{i:Ol1,to.thePIC18
.
.......
.
· :» .I'J:ogl'l!m.a D~~~i~tCI )!J:~uce a sine Wave on an oscilloscope
>;:.; ~'ldM.C iQ'i~:kt1tIC18 C and As.Sembly '. . .
· >>: .·hpbi&i t~ r~l!!ltioB9r~recmon OC:iemperatuJ;'e sensOrs.
· >>: .• ~ :Signal ~\ljtio$jBg ..it its role in data acquisition
"
"''''
'
499
This chapter explores more real-world devices such as ADCs (analog-todigital converters), DACs (digital-to-analog converters), and sensors. We will also
explain how to interface the PICI8 to these devices. In Section 13.1, we describe
analog-to-digital converter (ADC) chips. We will program the ADC portion of the
PIC 18 chip in Section 13.2. The characteristics of DAC chips are discussed in
Section 13.3. In Section 13.4, we show the interfacing of sensors and discuss the
issue of signal conditioning.
SECTION 13.1: ADC CHARACTERISTICS
This section will explore ADC programming in PIC 18 chips. First, we
describe some general aspects of the ADC itself, then show how to program the
ADC portion of the PIC 18 in both Assembly and C.
ADC devices
Analog-to-digital converters are among the most widely used devices for
data acquisition. Digital computers use binary (discrete) values, but in the physical world everything is analog (continuous). Temperature, pressure (wind or liquid), humidity, and velocity are a few examples of physical quantities that we deal
with every day. A physical quantity is converted to electrical (voltage, current) signals using a device called a transducer. Transducers are also referred to as sensors.
Sensors for temperature, velocity, pressure, light, and many other natural quantities produce an output that is voltage (or current). Therefore, we need an analogto-digital converter to translate the analog signals to digital numbers so that the
microcontroller can read and process them. See Figures 13-1 and 13-2.
Sensor
CPU
ADC
Display
FIgure 13-1. MlcrocontroIIer ConnectIOn to Sensor vIa ADC
Vref
I
Vin
DO
Binary
Data
Output
Analog Input
Start
Conversio~
07
.
.
-L
-
FIgure 13-2. An 8-bJt ADC Block DIagram
500
Table 13-1: Resolution versus Step Size for ADC (Vref= 5 V)
n-bit
8
10
12
16
Notes: Vee
=
Number of steps
256
1,024
4,096
65,536
5V
Step size (mV)
5/256 - 19.53
5/1,024 = 4.88
5/4,096 - 1.2
5/65,536 - 0.076
Step size (resolution) is the smallest change that can be discerned by an ADC.
Some of the major characteristics of the ADC are as follows:
Resolution
ADC has n-bit resolution, where n can be 8, 10, 12, 16, or even 24 bits. The
higher-resolution ADC provides a smaller step size, where step size is the smallest
change that can be discerned by an ADC. Some widely used resolutions for ADCs
are shown in Table 13-1. Although the resolution of an ADC chip is decided at the
time of its design and cannot be changed, we can control the step size with the help
of what is called Vref. This is discussed below.
Conversion time
In addition to resolution, conversion time is another major factor in judging an ADC. Conversion time is defined as the time it takes the ADC to convert
the analog input to a digital (binary) number. The conversion time is dictated by
the clock source connected to the ADC in addition to the method used for data conversion and technology used in the fabrication of the ADC chip such as MOS or
TTL technology.
Vref
V ref is an input voltage used for the reference voltage. The voltage connected to this pin, along with the resolution of the ADC chip, dictate the step size.
For an 8-bitADC, the step size is V re l256 because it is an 8-bitADC, and 2 to the
power of8 gives us 256 steps. See Table 13-1. For example, if the analog input
range needs to be 0 to 4 volts, V ref is connected to 4 volts. That gives 4 V/256 =
15.62 mV for the step size of an 8-bitADC. In another case, if we need a step size
of 10 mV for an 8-bitADC, then V ref = 2.56 V, because 2.56 V1256 = 10 mY. For
Table 13-2: V ref Relation to Yin Range for an 8-bit ADC
V ref (V)
5.00
4.0
3.0
2.56
2.0
1.28
1
Yin (V)
o to 5
o to 4
o to 3
oto 2.56
o to 2
o to 1.28
o to 1
CHAPTER 13: ADC, DAC, AND SENSOR INTERFACING
Step Size (mV)
5/256 - 19.53
4/256 = 15.62
3/256 = 11.71
2.56/256 - 10
2/256 = 7.81
1.281256 = 5
11256 = 3.90
501
Table 13-3: V ref Relation to Vin Range for an 10-bit ADC
V ref (V)
5.00
4.096
3.0
2.56
2.048
1.28
1.024
Step Size (mV)
5/1,024 - 4.88
4.096/1,024 = 4
3/1,024 = 2.93
2.5611 ,024 = 2.5
2.04811 ,024 = 2
111,024 - 1.25
1.024/1,024 = I
Yin (V)
o to 5
o to 4.096
o to 3
o to 2.56
o to 2.048
o to 1.28
o to 1.024
the 10-bit ADC, if the Vref = 5V, then the step size is 4.88 mV as shown in
Table 13-1. Tables 13-2 and 13-3 show the relationship between the Vrefand step
size for the 8- and 10-bit ADCs, respectively. In some applications, we need the
differential reference voltage where Vref= Vref(+) - Vref(-). Often the Vref() pin is connected to ground and the Vref (+) pin is used as the Vref.
Digital data output
In an 8-bitADC we have an 8-bit digital data output of DO-D7 while in the
IO-bit ADC the data output is DO--D9. To calculate the output voltage, we use the
following formula:
step size
where Dout = digital data output (in decimal), Yin = analog input voltage,
and step size (resolution) is the smallest change, which is Vref/256 for an 8-bit
ADC. See Example 13-1. This data is brought out of the ADC chip either one bit
at a time (serially), or in one chunk, using a parallel line of outputs. This is discussed next.
Example 13-1
For an 8-bit ADC, we have V ref = 2.56 V. Calculate the DO--D7 output if the analog
input is: (a) 1.7 V, and (b) 2.1 V.
Solution:
Because the step size is 2.561256 = 10 mV, we have the following:
(a) DOU! = 1.7 V/lO mV = 170 in decimal, which gives us 10101011 in binary for
D7-DO.
(b) DOU! = 2.1 V/IO mV = 210 in decimal, which gives us 11010010 in binary for
D7-DO.
Parallel versus serial ADC
The ADC chips are either parallel or serial. In parallel ADC, we have 8 or
more pins dedicated to bringing out the binary data, but in serial ADC we have
only one pin for data out. That means that inside the serial ADC, there is a paral502
CH1
I
I
GND
Vcc
ADC0848
DO/MAO
D 1/MA1
D2/MA2
D3/MA3
D4/MA4
CH8
AGND
Vref
D7
INTR
WR CS RD
t t t
Figure 13-3. ADC0848 Parallel ADC Block Diagram
~
CHO
~
CS
SCLK
I
VDD
MAX1112
CH7
REFIN
REFOUT
Din
DOUT
SHDN SSTRB
t t
t
FIgure 13-4. MAXl112 SerIal ADC Block DIagram
lel-in-serial-out shift register responsible for sending out the binary data one bit at
a time. The DO-D7 data pins of the 8-bit ADC provide an 8-bit parallel data path
between the ADC chip and the CPU. In the case of the 16-bit parallel ADC chip.
we need 16 pins for the data path. In order to save pins, many 12- and 16-bitADCs
use pins DO--D7 to send out the upper and lower bytes ofthe binary data. In recent
years, for many applications where space is a critical issue, using such a large
number of pins for data is not feasible. For this reason, serial devices such as the
serial ADC are becoming widely used. While the serial ADCs use fewer pins and
their smaller packages take much less space on the printed circuit board, more
CPU time is needed to get the converted data from the ADC because the CPU must
get data one bit at a time, instead of in one single read operation as with the parallel ADC. ADC848 is an example of a parallel ADC with 8 pins for the data output, while the MAXll12 is an example of a serial ADC with a single pin for Dout.
Figures 13-3 and 13-4 show the block diagram for ADC848 and MAXI112,
respectively.
CHAPTER 13: ADC, DAC, AND SENSOR INTERFACING
503
Analog input channels
Many data acquisition applications need more than one ADC. For this reason, we see ADC chips with 2, 4, 8, or even 16 channels on a single chip.
Multiplexing of analog inputs is widely used as shown in the ADC848 and
MAX 1112. In these chips, we have 8 channels of analog inputs, allowing us to
monitor multiple quantities such as temperature, pressure, heat, and so on. PIC 18
microcontroller chips come with 5 to 15 ADC channels, depending on the family
member. The PICI8 ADC feature is discussed in the next section.
Start conversion and end-of-conversion signals
The fact that we have multiple analog input channels and a single digital
output register makes it necessary for start conversion (SC) and end-of-conversion
(EOC) signals. When SC is activated, the ADC starts converting the analog input
value of Yin to an n-bit digital number. The amount of time it takes to convert
varies depending on the conversion method as was explained earlier. When the
data conversion is complete, the end-of-conversion signal notifies the CPU that the
converted data is ready to be picked up.
From the discussion we conclude that the following steps must be followed
for data conversion by an ADC chip:
I. Select a channel.
2. Activate the start conversion (SC) signal to start the conversion of analog
input.
3. Keep monitoring the end-of-conversion (EOC) signal.
4. After the EOC has been activated, we read data out of the ADC chip.
Review Questions
I. Give two factors that affect the step size calculation.
2. The ADC0848 is a(n)
-bit converter.
3. True or false. While the ADC0848 has 8 pins for DOUT' the MAX II 12 has only
one DOUT pin.
4. Indicate the number of analog input channels for each of the following ADC
chips.
(a) ADC0848
(b) MAX 111 2
5. Find the step size for an 8-bit ADC, if Vref = 1.28 V
6. For question 5, calculate the DO-D7 output if the analog input is: (a) 0.7 V,
and (b) I V.
504
SECTION 13.2: ADC PROGRAMMING IN THE PIC18
Because the ADC is widely used in data acquisition, in recent years an
increasing number of microcontrollers have an on-chip ADC peripheral, just like
timers and USART. An on-chip ADC eliminates the need for an external ADC connection, which leaves more pins for other 1/0 activities. The vast majority of the
PICl8 chips come with 8 channels ofADC, and some PICI8s have as many as 16
channels of ADCs. In this section we discuss the ADC feature of the
PICI8452/458 and show how it is programmed in both Assembly and C.
PIC18F452/458 ADC features programming
The ADC peripheral of the PIC 18 has the following characteristics:
(a) It is a lO-bit ADC.
(b) It can have 5 to IS channels of analog input channels, depending on the
family member. In PIC18452/458, pins RAO--RA7 of PORTA are used for the 8
analog channels. See Figures 13-5A and 13-5B.
(c) The converted output binary data is held by two special function registers called ADRESL (ND Result Low) and ADRESH (AID Result High).
MCLRNPP
40
RB7/PGD
RAO/ANO/CVREF
2
39
RB6/PGC
RA1/AN1
3
38
RB5/PGM
RA2/AN2NREF-
4
37
RB4
RA3/AN3NREF+
5
36
RB3/CANRX
RA4ITOCKI
6
35
RB2/CANTX/INT2
RA5/AN4/SS/LVDIN
7
34
RB1/INT1
REO/AN5/RD
8
33
RBO/INTO
RE 11AN6IWR/C 1OUT
9
32
VDD
RE2/AN7/CS/C20UT
10
31
VSS
VDD
11
30
RD7/PSP7/P1D
VSS
12
29
RD6/PSP6/P1 C
PIC18F458
OSC1/CLKI
13
28
RD5/PSP5/P1 B
OSC2/CLKO/RA6
14
27
RD4/PSP4/ECCP/P1 A
RCO/T1 OSO!T1 CKI
15
26
RC7/RXIDT
RC11T10S1
16
25
RC6ITX/CK
RC2/CCP1
17
24
RC5/SDO
RC3/SCK/SCL
18
23
RC4/SDI/SDA
RDO/PSPO/C1IN+
19
22
RD3/PSP3/C2IN-
20
21
RD2/PSP2/C2IN+
RD1/PSP1/C1IN-
Figure 13-5A: PIC18F458 Pins with ADC Channels Shown in Bold
CHAPTER 13: ADC, DAC, AND SENSOR INTERFACING
505
(Channel Select)
CHS2:CHSO
...........1.1.1..........,
-
•
10·bit
Converter AID
VAIN
(Analog Input Voltage)
Reference
Voltage
1.------------------
Vref+
0
110
1
~ClAN6
0
101
1
~ClAN5
0
JQQ
i
~ClAN4
~ClAN7
:
--
,.... ,....
o.A' N3
010
N2
,.... ,....
001
,,-uNl
.... .L ....
,.... ,....
000
.~ANO
--
--._--------.-------_._._-
PCFGO
··
···
··
··
111
011
~V~D
p---.- .. -_.- -._--_.
-
!
0
---
,....
Vref-
..>'
,
~
.......
AVss
.
FIgure 13-5B: PICIS ADC Channel and Reference SelectIOn
(d) Because the ADRESH:ADRESL registers give us 16 bits and the ADC
data out is only 10 bits wide, 6 bits of the 16 are unused. We have the option of
making either the upper 6 bits or the lower 6 bits unused.
(e) We have the option of using Vdd (Vcc), the voltage source of the PICI8
chip itself, as the Vref or connecting it to an external voltage source for the Vref.
(t) The conversion time is dictated by the F osc of crystal frequency con·
nected to the OSCs pins. While the Fosc for PICI8 can be as high as 40 MHz, the
conversion time can not be shorter than 1.6 ms.
(g) It allows the implementation of the differential Vref voltage using the
Vref(+) and Vref(-) pins, where Vref= Vref(+) - Vref(-).
Many of the above features can be programmed by way of ADCONO (ND
control register 0) and ADCON 1 (ND control register I), as we will see next.
506
ADCONO register
The ADCONO register is used to set the conversion time and select the analog input channel among other things. Figure 13-6 shows the ADCONO register. In
order to reduce the power consumption of the PIC 18, the ADC feature is turned
off when the microcontroller is powered up. We turn on the ADC with the ADON
bit of the ADCONO register, as shown in Figure 13-6. The other important bit is
the GO/DONE bit. We use this bit to start conversion and monitor it to see if conversion has ended. Notice in ADCCONO that not all family members have all the
8 analog input channels. The conversion time is set with the ADCS bits. While
ADCSI and ADCSO are held by the ADCONO register, ADCS2 is part of the
ADCON I register. This is discussed next.
IADCS 1 I ADCSO I CHS2 I CHS 1 I CHSO I GOIDONE I
ADCS2 (from ADCONl)
0
0
0
0
ADCSI
0
0
0
0
CHS2
0
0
0
0
CHSI CHSO
0
0
0
0
1
0
0
0
1
0
1
I ADON I
ADCSO
Conversion Clock Sonrce
FosC/2
0
1
Fosc/8
0
Fosc/32
1
Internal RC used for clock source
0
Fosc/4
Fosc/16
Fosc/64
0
Internal RC used for clock source
CHANNEL SELECTION
CHANO (ANO)
CHANI (ANI)
CHAN2 (AN2)
CHAN3 (AN3)
CHAN4 (AN4)
CHAN5 (AN5) not implemented on 28-pin PIC18
CHAN6 (AN6) not implemented on 28-pin PIC18
CHAN7 (AN7) not implemented on 28-pin PIC 18
GO/DONE AID conversion status bit.
1 = AID conversion is in progress. This is used as start conversion, which
means after the conversion is complete, it will go LOW to indicate the endof-conversion.
o = AID conversion is complete and digital data is available in registers
ADRESH and ADRESL.
ADON AID on bit
0= AID part of the PIC18 is off and consumes no power. This is the default
and we should leave it off for applications in which ADC is not used.
1 = AID feature is powered up.
Figure 13-6. ADCONO (AID Control Register 0)
CHAPTER 13: ADC, DAC, AND SENSOR INTERFACING
507
ADCON1 register
Another major register of the PICI8's ADC feature is ADCONI. The
ADCONI register is used to select the Vref voltage among other things. It is
shown in Figure 13-7. After the AID conversion is complete, the result sits in registers ADRESL (AID Result Low Byte) and ADRESH (AID Result High Byte).
The ADFM bit of the ADCONI is used for making it right-justified or left-justified because we need only 10 bits of the 16. See Figure 13-8.
I ADFM I ADCS21
I PCFG3 I PCFG21 PCFG I I PCFGO I
ADFM AID Result fonnat select bit
I ~ Right justified: The 10-bit result is in the ADRESL register and the lower
2 bits of ADRESH. That means the 6 most significant bits of the ADRESH
register are all Os.
o ~ Left justified: The 10-bit result is in the ADRESL register and the upper 2
bits of ADRESL. That means the 6 least significant bits of the ADRESL
register are all Os.
ADCS2 AID Clock Select bit 2. This bit along with the ADCS 1 and ADCSO bits of
the ADCONO register decide the conversion clock for the ADC. The default value for
ADCS2 is 0, which means setting the ADCSO and ADCS I values of ADCONO can
give us clock conversion of Fosc/2, Fosc/8, and Fosc/32. See the ADCONO register.
PCFGs: AID Port Configuration Control bits:
PCFGs
0000
000 I
001 0
00 I 1
01 00
oI 0 I
01 I x
I 000
100 I
I 0 10
I011
I I 00
1 10 I
I I I0
I I I I
AN7
A
A
D
D
D
D
D
A
D
D
D
D
D
D
D
AN6 AN5 AN4 AN3
A
A
A
A
A
Vref+
A
A
D
D
A
A
D
D
A Vref+
D
D
A
D
D
D
D
Vref+
D
D
D
D
A
A
A Vref+
D
A
A
A
D
A
A Vref+
D
A
A Vref+
D
D
A Vref+
D
D
D Vref+
D
D
D
D
Vref+
D
D
D
AN2 ANI
A
A
A
A
A
A
A
A
D
A
D
A
D
D
Vref- A
A
A
A
A
Vref- A
Vref- A
Vref- A
D
D
Vref- D
ANO
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
Vref+
Vdd
AN3
Vdd
AN3
Vdd
AN3
VrefVss
Vss
Vss
Vss
Vss
Vss
AN3 AN2
Vdd Vss
AN3
Vss
AN3 AN2
AN3 AN2
AN3 AN2
Vdd Vss
AN3 AN2
C/R
8/0
711
5/0
411
3/0
211
0/0
6/2
6/0
511
4/2
3/2
2/2
110
112
A ~ Analog input, D ~ Digital 1/0
C/R ~ # of analog input channels I # of pins used for AID voltage reference
The default is option 0000, which gives us 8 channels of analog input and uses the
Vdd ofPICI8 as Vref.
Figure 13-7. ADCONI (AID Control Register I)
508
ADRESH
Left-Justified
ADFM = 0
2
[9
ADFM = 1
[
Right-Justified
ADRESL
UNUSED
[ 9 8 [
[1 0 [
[7
UNUSED
o[
Figure 13-8. ADFM Bit and ADRESx Registers
The port configuration for AID channels is handled by the PCFG (AID port
configuration) bits. While in chips such as the PIC 18452/458, we can have up to
8 channels of analog input, not all applications need that many ADC inputs. The
PORTA pins ofRAO-RA3 and RA5 and REO-RE2 of PORTE are used for the analog input channels. With PCFG = 0110, we can use all the pins of the PORTA as
the digital I/O. The default is PCFG = 0000, which allows us to use all 8 pins for
analog inputs. In that case Vref= Vdd, the same voltage source used by the PICI8
chip itself In many applications we need Vref other than V dd. The AN3 pin can
be used as an external source of voltage for Vref. For example, option PCFG =
0101 allows us to use two channels for analog inputs, AN3 = Vref, and the other 5
pins for the digital 1/0. In this case the Vss (Gnd) pin of the PICI8 is used for the
Vref(-). See Examples 13-2 and 13-3.
Example 13-2
For a PIC I 8-based system, we have V ref = Vdd = 5 Y. Find (a) the step size, and (b) the
ADCONI value if we need 3 channels. Assume that the ADRESH:ADRESL registers
are right justified.
Solution:
(a) The step size is 511,024 = 4.8 mY.
(b) ADCONI = IxOOOIOO because option 100 gives us 3 analog input channels. The x
= ADCS2 is decided by the conversion speed.
Example 13-3
For a PICl8-based system, we have Vref = 2.56 V. Find (a) the step size, and (b) the
ADCONI value if we need 3 channels. Assume that the ADRESH:ADRESL registers
are right justified.
Solution:
(a) The step size is 2.56/1,024 = 2.5 mY.
(b) ADCONI = I xOOOO I I because option 0011 gives us 3 analog input channels where
x = ADCS2 is decided by the conversion speed.
CHAPTER 13: ADC, DAC, AND SENSOR INTERFACING
509
Calculating AID conversion time
By using the ADCS (ND clock source) bits of both the ADCONO and
ADCON I registers we can set the AID conversion time. The conversion time is
defined in terms of Tad, where Tad is the conversion time per bit. To calculate the
Tad, we can select a conversion clock source of Fosc/2, Fosc/4, Fosc/8, Fosc/16,
Fosc/32, or Fosc/64, where Fosc is the speed ofthe crystal frequency connected to
the PICI8 chip. For the PICI8, the conversion time is 12 times the Tad. Notice that
the Tad cannot be faster than 1.6 ms. Look at Examples 13-4 and 13-5 for clarification.
We can also use the the internal RC oscillator for the conversion clock
source, instead of the Fosc of the external crystal oscillator. In that case the Tad is
typically 4-6 IlS and conversion time is 12 x 6 IlS = 72 IlS.
Another timing factor that we must pay attention to is the acquisition time
(Tacq). After an ND channel is selected, we must allow some time for the sample
-and-hold capacitor (C hold) to charge fully to the input voltage level present at the
channel. It is only after the elapsing of this acquisition time that the AID conversion can be started. Although many factors (e.g., V dd and temperature) affect the
duration of Tacq, we can use a typical value of 15 IlS. In some newer generations
of the PIC 18, we have the option of controlling the exact time of Tacq by programming the internal register ADCON2. In the PIC 18F452/458, we have only the
ADCONO and ADCON 1 registers. See Example 13-6.
Example 13-4
A PICI8 is connected to the 10 MHz crystal oscillator. Calculate the conversion time
for all options of ADCS bits in both the ADCONO and ADCONI registers.
Solution:
The options for the conversion clock source for both ADCONO and ADCONI are as follows:
(a) For Fosc/2, we have 10 MHz 12 = 5 MHz.
Tad = I I 5 MHz = 200 ns. Invalid because it is faster than 1.6 IlS.
(b) For Fosc/4, we have 10 MHz 14 = 2.5 MHz.
Tad = I I 2.5 MHz = 400 ns. Invalid because it is faster than 1.6 IlS.
(c) For Fosc/8, we have 10 MHz 18 = 1.25 MHz.
Tad = I 12.5 MHz = 800 ns. Invalid because it is faster than 1.6 IlS.
(d) For Fosc/16, we have 10 MHz 116 = 625 kHz.
Tad =1/625 kHz = 1.6 IlS. The conversion time = 12 x 1.6 IlS = 19.2 IlS
(e) For Fosc/32, we have 10 MHz 132 = 312.5 kHz.
Tad = 1/312.5 kHz = 3.2 IlS. The conversion time = 12 x 3.2 IlS = 38.4 IlS
(f) For Fosc/64, we have 10 MHz 164 = 156.25 kHz.
Tad = I 1156.25 kHz = 6.4 IlS. The conversion time = 12 x 6.4 IlS = 76.8 IlS
Notice that for the Fosc/4, Fosc/16, and Fosc/64 selections, we must use the ADSC2 bit
in the ADCONI register, in addition to the ADCS bits in the ADCONO register.
510
Example 13-5
A PICI8 is connected to the 4 MHz crystal oscillator. Calculate the conversion time if
we want to use only the ADCS bits of the ADCONO register.
Solution:
The options for the conversion clock source available in the ADCONO register are as
follows:
(a) For Foscl2, we have 4 MHz / 2 = 2 MHz.
Tad = I / 2 MHz = 400 ns. Invalid because it is faster than 1.6 I1S.
(b) For Fosc/8, we have 4 MHz / 8 = 500 kHz.
Tad = I /500 kHz = 2 I1S. The conversion time = 12 x 2 I1S = 24 I1S
(c) For Fosc/32, we have 4 MHz / 32 = 125 kHz.
Tad = I / 125 kHz = 811s. The conversion time = 12 x 8 I1S = 96 I1S
Example 13-6
Find the values for the ADCONO and ADCONI registers for the following options: (a)
channel ANO as analog input, (b) Vref+ = Vdd, Vref- = Vss, (c) Fosc/64, (d) AID result
is right justified, and (e) AID module is on.
Solution:
From Figure 13-6, we have ADCONO
From Figure 13-7, we have ADCONI
= 10000xi. With x = 0 we have 10000001.
= llxxll10. With x = 0 we have 11001110.
Steps in programming the AID converter using polling
To program the AID converter of the PIC 18, the following steps must be
taken:
1. Turn on the ADC module of the PICI8 because it is disabled upon power-on
reset to save power. We can use the "BSF ADCONO, ADON" instruction.
2. Make the pin for the selected ADC channel an input pin. We use "BSF
TRISA, x." or "BSF TRISE, x" where x is the channel number.
3. Select voltage reference and AlC input channels. We use registers ADCONO
andADCONI.
4. Select the conversion speed. We use registers ADCONO and ADCONI.
5. Wait for the required acquisition time.
6. Activate the start conversion bit of GO/DONE.
7. Wait for the conversion to be completed by polling the end-of-conversion
(GO/DONE) bit.
8. After the GO/DONE bit has gone LOW, read the ADRESL and ADRESH registers to get the digital data output.
9. Go back to step 5.
CHAPTER 13: ADC, DAC, AND SENSOR INTERFACING
511
Programming PIC18F458 ADC in Assembly
The Assembly language Program 13-1 illustrates the steps for ADC conversion shown above. The C version of the program is shown in Program 13-1 C.
Program 13-1: This program gets data from channel 0 (RAO)
of ADC and displays the result on PORTC and PORTD. This is
done every quarter of second.
;Program 13-1
ORG
OOOOH
CLRF
TRISC
;make PORTC an output
CLRF
TRISD
;make PORTD an output
BSF
TRISA,O ;make RAO an input for analog input
MOVLW Ox81
;Fosc/64, channel 0, A/D is on
MOVWF ADCONO
MOVLW OxCE ; right justified, Fosc/64, ANO
analog
MOVWF ADCON1
OVER CALL
DELAY ;wait for Tacq (sample and hold time)
BSF ADCONO, GO
jstart conversion
BACK BTFSC ADCONO, DONE
;keep polling end-of-conversion
BRA BACK
;wait for end of conversion
MOVFF ADRESL, PORTC
;give the low byte to PORTC
MOVFF ADRESH, PORTD
;give the high byte to PORTD
CALL
QSEC_DELAY
BRA OVER
;keep repeating it
END
AV DD
PIC18F
PORTe
10k
POT
~----+I
RAO/ANO
PORTD
Figure 13-9. AID Connection for Program 13-1
512
Programming PIC18F458 AID in C
Program 13-1 C is the C version of the ADC conversion for Program 13-1.
Program 13-1C: This program gets data from channel 0 (RAO)
of ADC and displays the result on PORTC and PORTD. This is
done every quarter of second. This is the C version of
Program 13-l.
IIProgram 13-1C
void main (void)
{
TRISC=O;
Ilmake PORTC output port
TRISD=O;
Ilmake PORTD output port
TRISAbits.TRISAO=O;
llRAO = INPUT for analog input
ADCONO
Ox81;
IIFosc/64, channel 0, AID is on
ADCONl = OxCE;
Ilright justified, Fosc/64,
llANO = analog
while (1)
{
DELAY (1) ; Ilgive AID channel time to sample
ADCONObi ts. GO = 1;
I I start converting
while(ADCONObits.DONE == 1);
PORTC=ADRESL;
Iidisplay low byte on PORTC
PORTD=ADRESH;
Iidisplay high byte on PORTD
DELAY(250);
Ilwait for one quarter of a
Iisecond before trying again
}
}
Programming AID converter using interrupts
In Chapter II, we showed how to use interrupts instead of polling to avoid
tying down the microcontroller. To program the AID using the interrupt method,
we need to set HIGH the ADIE (AID interrupt enable) flag. If ADIE = I, then upon
the completion of the conversion, the ADIF (AID interrupt flag) becomes HIGH,
which will force the CPU to jump to read binary outputs. Table 13-4 shows to
which registers these two flags belong.
Table 13-4: AID Converter Interrupt Flag Bits and their Registers
Interrupt
ADIF (ADC)
Flag bit
ADIF
Register
PIRI
Enable bit
ADIE
Register
PIE I
Note: Upon power-on reset, the AID is assigned to high-priority interrupt (vector address
of 0008). We can use the ADIP bit of the IPR I register to assign low priority to it, which
will land at vector address 00018H. See Chapter II.
CHAPTER 13: ADC, DAC, AND SENSOR INTERFACING
513
;Program 13-2
ORG
OOOOH
GOTO MAIN
;bypass interrupt vector table
;--on default all interrupts go to to address 00008
ORG
0008H
;interrupt vector table
BTFSS PIR1,ADIF ;Did we get here due to A/D int?
RETFIE
;No. Then return to main
GOTO AD ISR
;Yes. Then go INTO ISR
;--the main program for initialization
ORG
00100H
MAIN CLRF TRISC
irnake PORTC an output
CLRF
TRISD
; make PORTD an output
BSF
TRISA,O imake RAO an input pin for analog input
MOVLW Ox81
;Fosc/64, channel 0, A/D is on
MOVWF ADCONO
MOVLW OxCE ; right justified, Fosc/64, ANO = analog
MOVWF ADCON1
BCF PIR1,ADIF
;clear ADIF for the first round
BSF PIE1,ADIE
;enable A/D interrupt
BSF INTCON,PEIE ;enable peripheral interrupts
BSF INTCON,GIE
;enable interrupts globally
OVER CALL DELAY
;wait for Tacq (sample and hold time)
BSF
ADCONO, GO ; start conversion
BRA OVER
;stay in this loop forever
;-----A/D Converter ISR
AD ISR
ORG 200H
MOVFF ADRESL,PORTC
;give the low byte to PORTC
MOVFF ADRESH,PORTD
;give the high byte to PORTD
CALL QSEC_DELAY
BCF PIR1,ADIF
;clear ADIF interrupt flag bit
RETFIE
END
//Program 13-2C (This is the C version of Program 13-2)
#include <PIC18F458.h>
#pragma code My_HiPrio_Int=Ox0008 //high-priority interrupt
void My_HiPrio_Int (void)
{
#pragma code
#pragma interrupt chk isr
void chk_isr (void)
//end high-priority interrupt
//Which interrupt?
(
if (PIR1bits.ADIF==1)
AD ISR( );
}
514
//A/D caused interrupt?
//Yes. Execute INTO program
void main (void)
{
TRISC=O;
//make PORTC output port
TRISD=O;
//make PORTD output port
TRISAbits.TRISAO=O;
//RAO = INPUT for analog input
ADCONO = Ox81;
//Fosc/64, channel 0, A/D is on
ADCONl = OxCE; //right justified, Fosc/64, ANO = analog
PIRlbits.ADIF=O;
//clear A/D interrupt flag
PIElbits.ADIE=l;
lienable A/D interrupt
INTCONbits.PEIE=l;
lienable peripheral interrupts
INTCONbits.GIE=l;
lienable all interrupts globally
while (l)
//keep looping until interrupt comes
{
DELAY (l) ;
ADCONObits.GO
l ',
//start converting
}
}
//----------A/D ISR
void AD_ISR(void}
{
PORTC=ADRESL;
PORTD=ADRESH;
DELAY (250) ;
PIRlbits.ADIF=O;
//display low byte on PORTC
//display high byte on
//wait for one quarter of a
//second before trying again
//clear A/D interrupt flag
}
Review Questions
Give the main factor affecting the step size of ND in PIC 18.
TheND ofPICI8 is a(n)
-bit converter.
True or false. The ND ofPICI8 has pins for Dour.
True or false. ND in the PICI8 is an off-chip module.
Find the step size for an PIC18 ADC, ifVref = 1.024 V.
For problem 5, calculate the DO-D9 output if the analog input is: (a) 0.7 V,
and (b) I V.
7. Indicate the number of available analog input channels for each of the following options in the ADCONO register:
(a) PCFG = 0100
(b) PCFG = IDOl
8. True or false. The conversion time is equal to 12 x Tad.
9. The minimum Tad allowed is
~s.
10. Which bit is used to poll for the end of conversion?
I.
2.
3.
4.
5.
6.
CHAPTER 13: ADC, DAC, AND SENSOR INTERFACING
515
SECTION 13.3: DAC INTERFACING
This section will show how to interface a DAC (digital·to·analog converter) to the PICI8. Then we demonstrate how to generate a sine wave on the scope
using the DAC.
Digital-to-analog converter (DAC)
The digital-to-analog converter (DAC) is a device widely used to convert
digital pulses to analog signals. In this section we discuss the basics of interfacing
a DAC to the PICI8.
Recall from your digital electronics course the two methods of creating a
DAC: binary weighted and Rl2R ladder. The vast majority of integrated circuit
DACs, including the MC I 408 (DAC0808) used in this section, use the Rl2R
method because it can achieve a much higher degree of precision. The first criterion for judging a DAC is its resolution, which is a function of the number of binary inputs. The common ones are 8, 10, and 12 bits. The number of data bit inputs
decides the resolution of the DAC because the number of analog output levels is
equal to 2 n, where n is the number of data bit inputs. Therefore, an 8-input DAC
such as the DAC0808 provides 256 discrete voltage (or current) levels of output.
See Figure 13-10. Similarly, the 12-bit DAC provides 4,096 discrete voltage levels. There are also 16-bit DACs, but they are more expensive.
Vref
I
DO
1-.
Analog Output
Digital Inputs
D7
WR
RD
I
I
Figure 13-10. DAC Block Diagram
MC1408 DAC (or DAC0808)
In the MC1408 (DAC0808), the digital inputs are converted to current
(lout), and by connecting a resistor to the lout pin, we convert the result to voltage.
The total current provided by the lout pin is a function of the binary numbers at the
DO-D7 inputs of the DAC0808 and the reference current (lref), and is as follows:
1
- 1
(
out - ref
D7
2
D6
D5
D4
D3
+ -:;- + -8- +
+
D2
16 32 + 6i
D1
DO)
+ 128 + 256
where DO is the LSB, D7 is the MSB for the inputs, and Iref is the input current
that must be applied to pin 14. The Iref current is generally set to 2.0 rnA. Figure
13-11 shows the generation of current reference (setting Iref = 2 rnA) by using the
516
+5V
+5V
RBD
(PORTB.D)
RB7
(PORTB.7)
T
T
DAC0808
PIC18
RO
vee
WR
Vref (+)
~ 5.
1
1 - -....
5'
-~-
_--1?>-.. . .-/~"~'V'- T.... ~~OP
........
1---+1 DO
01
02
03
0'
05
06
07
OUT
1.
.....
1 - - - - -..
O.1UF
Vref (-)
~
r
Vout=O
to 10V
=
VEE COMP
GND
U
D1UF
-'-
-12V
Figure 13-11. PIC18 Connection to DAC0808
standard 5 V power supply. Now assuming that Iref = 2 rnA, if all the inputs to the
DAC are high, the maximum output current is 1.99 rnA (verify this for yourself).
Converting
lout
to voltage in DAC0808
Ideally we connect the output pin lout to a resistor, convert this current to
voltage, and monitor the output on the scope. In real life, however, this can cause
inaccuracy because the input resistance of the load where it is connected will also
affect the output voltage. For this reason, the Irefcurrent output is isolated by connecting it to an op-amp such as the 741 with Rf = 5 kOhms for the feedback resistor. Assuming that R = 5 kOhms, by changing the binary input, the output voltage
changes as shown in Example 13-7.
Example 13-7
Assuming that R = 5 kOhms and Iref = 2 rnA, calculate V out for the following binary
inputs:
(b) 11001000 (C8H)
(a) 10011001 binary (99H)
Solution:
(a) lout = 2 rnA (153/256) = 1.195 rnA and V out = 1.195 rnA x 5K = 5.975 V
(b) lout = 2 rnA (200/256) = 1.562 rnA and V out = 1.562 rnA x 5K = 7.8125 V
Generating a sine wave
Example 13-8 shows how to generate a stair-step ramp. To generate a sine
wave, we first need a table whose values represent the magnitude of the sine of
angles between 0 and 360 degrees. The values for the sine function vary from -1.0
to +1.0 for 0- to 360-degree angles. Therefore, the table values are integer numCHAPTER 13: ADC, DAC, AND SENSOR INTERFACING
517
Example 13-8
In order to generate a stair-step ramp, set up the circuit in Figure 13-11 and connect the
output to an oscilloscope. Then write a program to send data to the DAC to generate a
stair-step ramp.
Solution:
AGAIN:
CLRF
CLRF
INCF
RCALL
BRA
TRISB
PORTB
PORTB,F
DELAY
AGAIN
;PORTB as output
iclear PORTB
icount from 0 to FFH send it to DAC
;let DAC recover
bers representing the voltage magnitude for the sine of theta. This method ensures
that only integer numbers are output to the DAC by the PIC 18 microcontroller.
Table 13-5 shows the angles, the sine values, the voltage magnitudes, and the integer values representing the voltage magnitude for each angle (with 30-degree
increments). To generate Table 13-5, we assumed a full-scale voltage of 10 V for
DAC output (as designed in Figure 13-11). Full-scale output of the DAC is
achieved when all the data inputs of the DAC are HIGH. Therefore, to achieve the
full-scale 10 V output, we use the following equation.
Vout =5V+ (5xsin9)
Vout ofDAC for various angles is calculated and shown in Table 13-5. See
Example 13-9 for verification of the calculations.
Table 13-5: Angle versus Voltage Magnitude for Sine Wave
Angle 9
(degrees)
0
30
60
90
120
150
180
210
240
270
300
330
360
518
Vout (Voltage Magnitude)
Sin 9
0
0.5
0.866
1.0
0.866
0.5
0
-0.5
-0.866
-1.0
-0.866
-0.5
0
5 V + (5 V x sin 9)
5
7.5
9.33
10
9.33
7.5
5
2.5
0.669
0
0.669
2.5
5
Values Sent to DAC (decimal)
(Voltage Mag. x 25.6)
128
192
238
255
238
192
128
64
17
0
17
64
128
Example 13-9
Verify the values given for the following angles: (a) 30° (b) 60°.
Solution:
(a) Vout = 5 V + (5 V x sin 9) = 5 V + 5 x sin 30° = 5 V + 5 x 0.5 = 7.5 V
DAC input value = 7.5 V x 25.6 = 192 (decimal)
(b) Vout = 5 V+(5 Vx sin 9) = 5 V+ 5 x sin 60° = 5 V+ 5 x 0.866= 9.33 V
DAC input value = 9.33 V x 25.6 = 238 (decimal)
To find the value sent to the DAC for various angles, we simply multiply
the Vout voltage by 25.60 because there are 256 steps and full-scale Vout is 10
volts. Therefore, 256 steps /10 V = 25.6 steps per volt. To further clarify this, look
at the following code. This program sends the values to the DAC continuously (in
an infinite loop) to produce a crude sine wave. See Figure 13-12.
;Program 13-3
OVER MOVLW upper (TABLE)
MOVWF TBLPTRU
MOVLW high (TABLE)
MOVWF TBLPTRH
MOVLW low (TABLE)
MOVWF TBLPTRL
CLRF TRISB
AGAIN TBLRD*
MOVF TABLAT, W
XORLW OxO
BZ
OVER
MOVWF PORTB
INCF TBLPTRL, F
BRA AGAIN
ORG Ox250
DB D t 128 1 D ' 192 ' D 1 238
TABLE:
I
I
1 I D I 255 1 , D I 238 ' I D 1 192
DB D'12S1 ,D 1 64' ,D'17I,D'1' ,D'17',D I 64' ,DID'
1
END
ito get a better looking sine wave,
;Table 13-5 for 2-degree angles
CHAPTER 13: ADC, DAC, AND SENSOR INTERFACING
regenerate
519
Volts
10
9
8
7
6
5
+-----'
4
3
2
o
1---1----+---1---I---I--+--+--I===!---+===+---+-- Degrees
30
60
90
120 150
180 210 240
270
300
330
360
Figure 13-12. Angle vs. Voltage Magnitude for Sine Wave
Programming DAC in C
//Program 13-3C. This is the C version of Program 13-3.
#include <pI8F458.h>
rom const unsigned char WAVEVALUE[12] ={128,192,238,255,
238,192,128,64,
17/ O,17,64}
i
void main ()
{
unsigned char Xi
TRISB=O;
while (1)
(
for(x=O;x<12;x++)
PORTB = WAVEVALUE(x];
}
}
Review Questions
I. In a DAC, input is ___ (digital, analog) and output is _ _ (digital, analog).
2. In an ADC, input is
(digital, analog) and output is _ _ (digital, analog).
3. DAC0808 is a(n)
-bit D-to-A converter.
4. (a) The output ofDAC0808 is in
(current, voltage).
(b) True or false. The output of DAC0808 is ideal to drive a motor.
520
SECTION 13.4: SENSOR INTERFACING AND SIGNAL CONDITIONING
This section will show how to interface sensors to the microcontroller. We
examine some popular temperature sensors and then discuss the issue of signal
conditioning. Although we concentrate on temperature sensors, the principles discussed in this section are the same for other types of sensors such as light and pressure sensors.
Temperature sensors
Transducers convert physical data
such as temperature, light intensity, flow,
and speed to electrical signals. Depending
on the transducer, the output produced is
in the form of voltage, current, resistance,
or capacitance. For example, temperature
is converted to electrical signals using a
transducer called a thermistor. A thermistor responds to temperature change by
changing resistance, but its response IS
not linear, as seen in Table 13-6.
Table 13-6: Thermistor Resistance
vs. Temperature
Temperature (C)
o
25
50
75
100
Tf(K ohms)
29.490
10.000
3.893
1.700
0.817
From William Kleitz, Digital Electronics
The complexity associated with writing software for such nonlinear
devices has led many manufacturers to market a linear temperature sensor. Simple
and widely used linear temperature sensors include the LM34 and LM35 series
from National Semiconductor Corp. They are discussed next.
LM34 and LM35 temperature sensors
The sensors of the LM34 series are precision integrated-circuit temperature
sensors whose output voltage is linearly proportional to the Fahrenheit temperature. See Table 13-7. The LM34 requires no external calibration because it is internally calibrated. It outputs 10mV for each degree of Fahrenheit temperature. Table
13-7 is a selection guide for the LM34.
The LM35 series sensors are precision integrated-circuit temperature sensors whose output voltage is linearly proportional to the Celsius (centigrade) temTable 13-7: LM34 Temperature Sensor Series Selection Guide
Part
Scale
LM34A
LM34
LM34CA
LM34C
LM34D
Temperature Range
Accuracy
Output
-50 F to
-50 F to
-40 F to
-40 F to
-32 F to
+2.0F
+3.0F
+2.0F
+3.0 F
+4.0F
10
10
10
10
10
+300
+300
+230
+230
+212
F
F
F
F
F
mV/F
mV/F
mV/F
mVIF
mVIF
Note: Temperature range is in degrees Fahrenheit.
CHAPTER 13: ADC, DAC, AND SENSOR INTERFACING
521
Table 13-8: LM35 Temperature Sensor Series Selection Guide
Part
LM35A
LM35
LM35CA
LM35C
LM35D
Temperature Range
-55 C to +150 C
-55 C to +150 C
-40 C to +110 C
-40 C to +110 C
OCto +100 C
Accuracy
+1.0 C
+1.5 C
+1.0 C
+1.5 C
+2.0 C
Output Scale
10 mV/C
IOmV/C
10 mV/C
10 mV/C
10 mV/C
Note: Temperature range is in degrees Celsius.
perature. The LM35 requires no external calibration because it is internally calibrated. It outputs 10mV for each degree of centigrade temperature. Table 13-8 is
the selection guide for the LM35. (For further information see http://www.national.com.)
Signal conditioning and interfacing the LM35 to the PIC18
Signal conditioning is widely used in the world
of data acquisition. The most common transducers
Analog world
(temperature,
produce an output in the form of voltage, current,
pressure,
etc.)
charge, capacitance, and resistance. We need to convert these signals to voltage, however, in order to send
input to anA-to-D converter. This conversion (modifiTransducer
cation) is commonly called signal conditioning. See
Figure 13-13. Signal conditioning can be a current-tovoltage conversion or a signal amplification. For
Signal
example, the thermistor changes resistance witb temconditioning
perature. The change of resistance must be translated
into voltages in order to be of any use to an ADC.
ADC
Look at the case of connecting an LM34 to an ADC of
the PIC18F458. The AID has 10-bit resolution with a
maximum of 1,024 steps and the LM34 (or LM35)
Microcontroller
produces 10mV for every degree of temperature
change. Now, if we use the step size of 10 mY, the V out Figure 13-13. Getting
will be 10,240 mV (10.24 V) for full-scale output. This Data From the Analog
is not acceptable even though the maximum tempera- World
ture sensed by the LM34 is 300 degrees F, and the
highest output for the AID we will get is 3,000 mV
(3.00 V). Now, if we use the step size of2.5 mY, the Vout will be 1,024 x 2.5 mV
= 2,560 mV (2.56 V) for full-scale output. That means we must set V ref = 2.56 V.
This makes the binary output number for the AID 4 times the real temperature (10
mV/2.5 m V = 4). We can scale it by dividing it by 4 to get the real number for temperature. See Table 13-9.
Figure 13-14 shows the connection of a temperature sensor to the
PIC18F458. Notice that we use the LM336-2.5 zener diode to fix the voltage
across the 10K pot at 2.5 volts. The use of the LM336-2.5 should overcome any
fluctuations in the power supply.
,
1
I
I
522
t
t
I
I
5V
PIC18F458
Vee
I
LM35 or
LM34
PORTD
-
r
RAO
2.5k
)
"... GND
RA3(Vref+)
n
-
r
L s: s:
10k
Set to
2.56 V
-.L
.
'"'"cr>
-
~
Figure 13-14. PIC18F458 Connection to Temperatnre Sensor
Table 13-9: Temperature vs. Vout for PIC18 with Vref = 2.56 V
~SS = 2.5 m~
Temp. (F) Yin (mV)
0
0
1
10
2
20
3
30
10
100
20
200
300
30
40
400
50
500
60
600
70
700
80
800
90
900
100
1000
#of steps Binary Vout (b9-bO)
0
0000000000
4
0000000100
8
0000001000
0000001100
12
0000101000
20
80
0001010000
120
0001111000
00 10100000
160
200
00 11001000
00 11110000
240
0100101100
300
01 01000000
320
0101101000
360
01 10010000
400
Temp. in Binary
00000000
00000100
00000010
00000011
00001010
00010100
00011110
00101000
00110010
00111100
01001011
01010000
01011010
01100100
Example 13-10
In Table 13-9, verify the PIC output for a temperature of 70 degrees. Find values in the
PICI8 AID registers of ADRESL andADRESH.
Solution:
The step size is 2.56/1,024 = 2.5 mV because Vref= 2.56 V.
For the 70 degrees temperature we have 700 mV output because the LM34 provides 10
mV output for every degree. Now, the number of steps are 700 mV/2.5 mV = 300 in
decimaL Now 300 = 0101000000 in binary and the PICI8 AID output registers have
ADRESL = 0 I 00000 and ADRESH = 0000000 I.
CHAPTER 13: ADC, DAC, AND SENSOR INTERFACING
523
Reading and displaying temperature
Programs 13-4 and 13-4C show code for reading and displaying temperature in both Assembly and C respectively.
The programs correspond to Figure 13-14. Regarding these two programs,
the following points must be noted:
(I) The
(2) The
makes PCFG =
(3) The
LM34 (or LM35) is connected to channel 0 (RAO pin).
channel AN3 (RA3 pin) is connected to the Vref of 2.56 V. That
0010 for the ADCONI register.
I O-bit output of the AID is divided by 4 to get the real temperature.
The algorithm is as follows: (a) Shift right the ADRESL 2 bits, (b) rotate
the ADRESH 2 bits, and (c) OR the ADRESH with ADRESL together to get the
8-bit output for temperature.
;Program 13-4
;this program reads the sensor and displays it on PORTD
L_Byte
SET Ox20
;set a location Ox20 for L Byte
;set a location Ox21 for H-Byte
H_Byte
SET Ox21
BIN TEMP
SET Ox22
;set a location Ox22 for BIN_TEMP
CLRF TRISD
;make PORTD an output
BSF TRISA,O ;make RAO an input pin for analog volt
BSF TRISA,3 ;make RA3 an input pin for Vref volt
MOVLW Ox81
;Fosc/64, channel 0, AID is on
MOVWF ADCONO
MOVLW OxCS
;right justified, Fosc/64,
MOVWFADCON1
;ANO = analog, AN3 = Vref+
OVER CALL DELAY
;wait for Tacq (sample and hold time)
BSF
ADCONO, GO
; start conversion
BACK BTFSC ADCONO, DONE; keep polling end-of-conversion (EOC)
BRA
BACK
;wait for end-of-conversion
MOVFFADRESL,L_Byte
;save the low byte
MOVFFADRESH,H_Byte
;save the high byte
CALL ALGO_10_to_8
;make it an 8-bit value
MOVFFBIN_TEMP,PORTD
;display the temp on PORTD
BRA
OVER
;keep repeating it
i----------------
ALGO- 10 - to- 8
RRNCF L_Byte, F
RRNCF L_Byte, W
ANDLW Ox3F
MOVWF L_Byte
RRNCF H_Byte, F
RRNCF H_Byte, W
ANDLW OxCO
IORWF L_Byte, W
MOVWF BIN TEMP
RETURN
,
0
______
;rotate right twice
;mask the upper 2 bits
;rotate right through carry twice
;mask the lower 6 bits
;combine low and high
-----
IIProgram 13-4C
void main(void)
{
unsigned char L_Byte , H_Byte , Bin_Temp;
TRISD=O;
Ilmake PORTD output port
TRISAbits.TRISAO=l; llRAO = INPUT for analog input
524
TRISAbits.TRISA2~1;
ADCONO
ADCON1
~
Ox81;
OxCS;
lIRA2 ~ INPUT for vref input
IIFosc/64, channel 0, AID is on
Ilright justified, Fosc/64,
llANO ~ analog, AN3 ~ Vref+
while (1)
(
MSDelay(l);
Ilgive AID channel time to sample
ADCONObits.GO
1;
Iistart converting
while(ADCONObits.DONE ~~ 1);
Ilwait for EOC
L_Byte~ADRESL;
Iisave the low byte
H_Byte~ADRESH;
Iisave the high byte
L_Byte»~2;
I Ishift right
L_Byte&~Ox3F;
Ilmask the upper 2 bits
H_Byte«~6;
Iishift left 6 times
H_Byte&~OxCO;
Ilmask the lower 6 bits
Bin_Temp~ L_ByteIH_Byte;
PORTD~Bin_Temp;
}
Review Questions
I. True or false. The transducer must be connected to signal conditioning circuitry before it is sent to the ADC.
2. The LM35 provides
mV for each degree of
(Fahrenheit,
Celsius) temperature.
3. The LM34 provides __ mV for each degree of _ _ (Fahrenheit, Celsius)
temperature.
4. Why do we set the Vref of the PIC to 2.56 V if the analog input is connected
to the LM35?
5. In Question 4, what is the temperature if the ADC output is 0011 100l?
SUMMARY
This chapter showed how to interface real-world devices such as DAC
chips, ADC chips, and sensors to the PIC. First, we discussed both parallel and
serial ADC chips, then described how the ADC module inside the PICI8 works
and explained how to program it in both Assembly and C. Next we explored the
DAC chip, and showed how to interface it to the PIC. In the last section we studied sensors. We also discussed the relation between the analog world and a digital
device, and described signal conditioning, an essential feature of data acquisition
systems.
PROBLEMS
SECTION 13.1: ADC CHARACTERISTICS
I. True or false. Sensor output is in analog.
2. True or false. A lO-bit ADC has lO-bit digital output.
3. True or false. ADC0848 is an 8-bit ADC.
CHAPTER 13: ADC, DAC, AND SENSOR INTERFACING
525
4. True or false. MAX II 12 is a 10-bitADC.
5. True or false. An ADC with 8 channels of analog input must have 8 pins, one
for each analog input.
6. True or false. For a serial ADC, it takes a longer time to get the converted digital data out of the chip.
7. True or false. ADC0848 has 4 channels of analog input.
8. True or false. MAX II 12 has 8 channels of analog input.
9. True or false. ADC0848 is a serial ADC.
10. True or false. MAXII12 is a parallel ADC.
II. Which of the following ADC sizes provides the best resolution?
(a) 8-bit (b) 10-bit (c) 12-bit (d) 16-bit (e) They are all the same.
12. In Question II, which provides the smallest step size?
13. Calculate the step size for the following ADCs, if V ref is 5 V:
(a) 8-bit (b) 10-bit (c) 12-bit (d) 16-bit
14. With Vref= 1.28 V, find the Yin for the following outputs:
(b) D7-DO = 10011001
(c) D7-DO = 1101100
(a) D7-DO = 1IIIIlll
15. In the ADC0848, what should be the Vref value if we want a step size of 5 mV?
16. With Vref+ = 2.56 V and Vref- = Gnd, find the Yin for the following outputs:
(a) D7-DO = Illlllll
(b) D7-DO = 10011001
(c) D7-DO = 01101100
SECTION 13.2: ADC PROGRAMMING IN THE PICI8
17. True or false. The PIC 18F452/458 has an on-chip AID converter.
18. True or false. AID of the PICI8 is an 8-bitADC.
19. True or false. PICI8F452/458 has 8 channels of analog input.
20. True or false. The unused analog pins of the PIC18F452/458 can be used for
1/0 pins.
21. True or false. The AID conversion speed in the PIC 18F452/458 depends on the
crystal frequency.
22. True or false. Upon power-on reset, the AID module of the PIC 18F452/458 is
turned on and ready to go.
23. True or false. The AID module of the PICI8F452/458 has an external pin for
the start-conversion signal.
24. True or false. The AID module of the PICI8F452/458 can convert only one
channel at a time.
25. True or false. The AID module ofthe PICI8F452/458 can have multiple external Vref+ at any given time.
26. True or false. The AID module of the PICI8F452/458 can use the Vdd for
Vref+.
27. In the AID of PIC 18 what happens to the converted analog data? How do we
know that the ADC is ready to provide us the data?
28. In the AID ofPICI8 what happens to the old data if we start conversion again
before we pick up the last data?
29. Assume Vref- = Gnd. For the AID ofPICI8, find the step size for each of the
following Vref+:
(a) Vref = 1.024 V
526
(b) Vref = 2.048 V
(c) Vref = 2.56 V
30. In the PICI8, what should be the Vrefvalue if we want a step size of2 mV?
31. In the PICI8, what should be the Vrefvalue if we want a step size of 3 mV?
32. With a step size of I mV, what is the analog input voltage if all outputs are I?
33. With Vref= 1.024 V, find the Yin for the following outputs:
(a) 09-00 = 0011111111 (b) 09-00 = 0010011000 (c) 09-00 = 0011010000
34. In the AID ofPICI8, what should be the Vrefvalue if we want a step size of 4
mV?
35. With Vref+ = 2.56 V and Vref- = Gnd, find the Yin for the following outputs:.
(a) 09-00 = 1111111111 (b) 09-00 = 1000000001 (c) 09-00 = 1100110000
36. Find the conversion time for the following cases if XTAL = 8 MHz:
(a) Foscl2
(b) Fosc/4 (c) Fosc/8
(d) Fosc/16
(e) Fosc/32
37. Find the conversion time for the following cases ifXTAL = 12 MHz:
(a) Fosc/8
(b) Fosc/16
(c) Fosc/32
(d) Fosc/64
38. How do we start conversion in the PICI8?
39. How do we recognize the end of conversion in the PICI8?
40. The PIC18F452/458 can have a minimum of
channels of analog input.
41. In the PICI8F452/458, what ports are used for the analog channels?
42. Which register of the PICI8 is used to designate the number of AID channels?
43. Which register ofthe PICI8 is used to select the AID's conversion speed?
44. Which register of the PICI8 is used to select the analog channel to be converted?
45. Find the value for the AOCONO register if we want Fosc/8, channel 0, and
AOONon.
46. Find the value for the AOCONI register if we want Fosc/64, 3 channels of analog input, and right-justified output.
47. Find the value for the AOCONO register if we want Foscl2, channel 2, and
AOON off.
48. Find the value for the AOCONI register if we want Fosc/32, 2 channels of analog input with external source for Vref+, and left-justified output.
49. Give the name of the interrupt flags for the AID of the PICI8F452/458. State
to which register they belong.
50. Upon power-on reset, the AID of the PIC I 8F452/458 is given (low, high) priority.
SECTION 13.3: DAC INTERFACING
51. True or false. OAC0808 is the same as OAC1408.
52. Find the number of discrete voltages provided by the n-bit OAC for the following:
(a) n = 8 (b) n = 10 (c) n = 12
53. For DAC1408, ifIref= 2 rnA, show how to get the lout of 1.99 when all inputs
are HIGH.
54. Find the lout for the following inputs. Assume Iref = 2 rnA for OAC0808.
(a) 10011001
(d) 00100010
(b) 11001100
(e) 00001001
(c) 11101110
(t) 10001000
CHAPTER 13: ADC, DAC, AND SENSOR INTERFACING
527
55. To get a smaller step, we need a DAC with ___ (more, fewer) digital
inputs.
56. To get full-scale output, what should be the inputs for DAC?
SECTION 13.4: SENSOR INTERFACING AND SIGNAL CONDITIONING
What does it mean when a given sensor is said to have a linear output?
The LM34 sensor produces
mV for each degree of temperature.
What is signal conditioning?
What is the purpose of the LM336 Zener diode around the pot setting the Vref
57.
58.
59.
60.
in Figure 13-14?
ANSWERS TO REVIEW QUESTIONS
SECTION 13.1: ADC CHARACTERISTICS
1.
Number of steps and Vrefvoltage
2.
8
3.
4.
5.
6.
True
(a)8 (b)8
1.28 V/256 ~ 5 mV
(a) 0.7 VI 5 mV~ 140 in decimal and D7-DO ~ 10001100 in binary.
(a) I VI 5 mV~ 200 in decimal and D7-DO ~ 11001000 in binary.
SECTION 13.2: ADC PROGRAMMING IN THE PICI8
1.
2.
3.
4.
5.
6.
7
8.
9.
10.
Vref
10
False
False
I mV
(a) 700 mV (1010111100), (b) 1000 mV (1111101000)
(a) 2 channels (b) 6 channels
True
1.6
DONE bit of the ADCONO register
SECTION 13.3: DAC INTERFACING
1.
2.
3.
4.
Digital, analog
Analog, digital
8
(a) current (b) true
SECTION 13.3: SENSOR INTERFACING AND SIGNAL CONDITIONING
1.
2.
3.
4.
5.
528
True
10, Celsius
10, Fahrenheit
Using the 8-bit part of the 10-bit ADC, it gives us 256 steps, and 2.56 V/256 ~ 10 mY. The
LM35 produces 10 mV for each degree of temperature, which matches the ADC's step size.
00111001 ~ 57, which indicates it is 57 degrees.
CHAPTER 14
USING FLASH AND
EEPROM MEMORIES
FOR DATA STORAGE
OBJECTIVES
Upon completion ofthis chapter, you will be able to:
»
»
»
»
»
»
»
»
Contrast and compare various types of semiconductor memories
in terms of their capacity, organization, and access time
Describe the relationship between the number of memory locations
on a chip, the number of data pins, and the chip capacity
Define Flash ROM memory and describe its use in PIC18-based systems
Contrast and compare PROM, EPROM, UV-EPROM, EEPROM,
Flash memory EPROM, and mask ROM memories
Code PIC18 Assembly and C programs for writing data into PIC18
Flash memory space
Code PIC18 Assembly and C programs for erasing the Flash memory
in PIC18
Explain how to write data to EEPROM memory of the PIC18
Explain how to read data from EEPROM memory of the PIC18
529
In this chapter we discuss how to access data stored in both Flash and EEPROM memories of the PICI8F. In Section 14.1 we study semiconductor memory
concepts with emphasis on different types of ROM. In Section 14.2, the writing of
data into PIC 18F Flash memory is discussed. The accessing of EEPROM in the
PIC18 is explored in Section 14.3.
SECTION 14.1: SEMICONDUCTOR MEMORY
In this section we discuss various types of semiconductor memories and
their characteristics such as capacity, organization, and access time. In the design
of all microprocessor-based systems, semiconductor memories are used as primary
storage for code and data. Semiconductor memories are connected directly to the
CPU and are the memory that the CPU first asks for information (code and data).
For this reason, semiconductor memories are sometimes referred to as primary
memory. The most widely used semiconductor memories are ROM and RAM.
Before we discuss different types of RAM and ROM, we discuss some important
terminology common to all semiconductor memories, such as capacity, organization, and speed.
Memory capacity
The number of bits that a semiconductor memory chip can store is called
chip capacity. It can be in units of Kbits (kilobits), Mbits (megabits), and so on.
This must be distinguished from the storage capacity of computer systems. While
the memory capacity of a memory IC chip is always given in bits, the storage
capacity of a computer system is given in bytes. For example, an article in a technical journal may state that the 128M chip has become popular. In that case, it is
understood, although it is not mentioned, that 128M means 128 megabits because
the article is referring to an IC memory chip. However, if an advertisement states
that a computer comes with 128M memory, it is understood that 128M means 128
megabytes because it is referring to a computer system.
Memory organization
Memory chips are organized into a number oflocations within the Ie. Each
location can hold 1 bit, 4 bits, 8 bits, or even 16 bits, depending on how it is
designed internally. The number of bits that each location within the memory chip
can hold is always equal to the number of data pins on the chip. How many locations exist inside a memory chip? That depends on the number of address pins. The
number oflocations within a memory IC always equals 2 to the power ofthe number of address pins. Therefore, the total number of bits that a memory chip can
store is equal to the number oflocations times the number of data bits per location.
To summarize:
1. A memory chip contains 2x locations, where x is the number of address pins.
2. Each location contains y bits, where y is the number of data pins on the chip.
3. The entire chip will contain 2x x y bits, where x is the number of address pins
and y is the number of data pins on the chip.
530
Speed
Table 14-1: Powers of2
One of the most important characteristics of a
memory chip is the speed at which its data can be
accessed. To access the data, the address is presented to
the address pins, the READ pin is activated, and, after a
certain amount of time has elapsed, the data shows up at
the data pins. The shorter this elapsed time, the better,
and consequently, the more expensive the memory chip .
The speed of the memory chip is commonly referred to
as its access time. The access time of memory chips
varies from a few nanoseconds to hundreds of nanoseconds, depending on the Ie technology used in the
design and fabrication process.
The three important memory characteristics of
capacity, organization, and access time will be explored
extensively in this chapter. Table 14-1 serves as a reference for the calculation of memory characteristics.
Examples 14-1 and 14-2 demonstrate these concepts.
;,;x=_ _ _ _ _~2;"x_
-;-I".O_ _ _ _ _ _='IK':'-_
-;-1.".1_ _ _ _ _ _2"'K':'-_
12
4K
-::--::------~~.:.1"'3_ _ _ _ _ _S.:"K':'-_
.:.1. ,.4_ _ _ _ _--"-16='K':'-_
.:.1"'S_ _ _ _ _--"::32"'K':'-_
.:.1",6_ _ _ _ _-,-:.64"'K':'-_
17
12SK
-::--::-----~~~IS
2S6K
~----~~~-=1.;,.9_ _ _ _ _"'S.:,,12"'K=-_
-=2.;. 0_ _ _ _ _---'I-=M=-_
7271_ _ _ _ _~2"'M=-_
7272_ _ _ _ _ _4-=M...:...._
72"'3_ _ _ _ _---'S:,oM...:...._
72..,.4_ _ _ _ _--,1:.c6"'M...:...._
72"'S_ _ _ _ _....:3:,-:2"'M=-_
26
64M
27
12SM
Example 14-1
A given memory chip has 12 address pins and 4 data pins. Find:
(a) the organization, and (b) the capacity.
Solution:
(a) This memory chip has 4,096 locations (2 12 = 4,096), and each location can hold 4
bits of data. This gives an organization of 4,096 x 4, often represented as 4Kx4.
(b) The capacity is equal to 16K bits because there is a total of 4K locations and each
location can hold 4 bits of data.
Example 14-2
A Sl2K memory chip has S pins for data. Find:
(a) the organization, and (b) the number of address pins for this memory chip.
Solution:
(a) A memory chip with S data pins means that each location within the chip can hold
8 bits of data. To find the number of locations within this memory chip, divide the
capacity by the number of data pins. SI2K1S = 64K; therefore, the organization for
this memory chip is 64KxS.
(b) The chip has 16 address lines because 2 16 = 64K.
CHAPTER 14: USING FLASH AND EEPROM MEMORIES
531
ROM (read-only memory)
ROM is a type of memory that does not lose its contents when the power
is turned off. For this reason, ROM is also called nonvolatile memory. There are
different types of read-only memory, such as PROM, EPROM, EEPROM, flash
EPROM, and mask ROM. Each is explained below.
PROM (programmable ROM) and OlP
PROM refers to the kind of ROM that the user can bum information into.
In other words, PROM is a user-programmable memory. For every bit of the
PROM, there exists a fuse. PROM is programmed by blowing the fuses. If the
information burned into PROM is wrong, that PROM must be discarded because
its internal fuses are permanently blown. For this reason, PROM is also referred to
as OTP (one-time programmable). Programming ROM, also called burning ROM,
requires special equipment called a ROM burner or ROM programmer.
EPROM (erasable programmable ROM) and UV-EPROM
EPROM was invented to allow changes in the contents of PROM after it is
burned. In EPROM, one can program the memory chip and erase it thousands of
times. This is especially necessary during development of the prototype of a
microprocessor-based project. A widely used EPROM is called UV-EPROM,
where UV stands for ultraviolet. The only problem with UV-EPROM is that erasing its contents can take up to 20 minutes. All UV-EPROM chips have a window
through which the programmer can shine ultraviolet (UV) radiation to erase its
contents. For this reason, EPROM is also referred to as UV-erasable EPROM or
simply UV-EPROM. Figure 14-1 shows the pins for a UV-EPROM chip.
To program a UV-EPROM chip, the following steps must be taken:
I. Its contents must be erased. To erase a chip, remove it from its socket on the
system board and place it in EPROM erasure equipment to expose it to UV
radiation for 15-20 minutes.
2. Program the chip. To program a UV-EPROM chip, place it in the ROM burner (programmer). To bum code or data into EPROM, the ROM burner uses
12.5 volts or higher, depending on the EPROM type. This voltage is referred
to as Vpp in the UV-EPROM data sheet.
3. Place the chip back into its socket on the system board.
As can be seen from the above steps, not only is there an EPROM programmer (burner), but there is also separate EPROM erasure equipment. The main
problem, and indeed the major disadvantage, of UV-EPROM is that it cannot be
erased and programmed while it is in the system board. To find a solution to this
problem, EEPROM was invented.
Notice the patterns of the IC numbers in Table 14-2. For example, part
number 27128-25 refers to UV-EPROM that has a capacity of 128K bits and an
access time of 250 nanoseconds. The capacity of the memory chip is indicated in
the part number and the access time is given with a zero dropped. In part numbers,
C refers to CMOS technology. Notice that 27XX refers to UV-EPROM chips.
532
Table 14-2: Some UV-EPROM Chips
Part #
Capacity
Org.
16K
2Kx8
2716
32K
4KX8
2732
2732A-20
32K
4Kx8
27C32-1
32K
4Kx8
64K
2764-20
8Kx8
64K
2764A-20
8Kx8
64K
27C64-12
8Kx8
128K
27128-25
16Kx8
27CI28-12
128K
16Kx8
27256-25
256K
32Kx8
27C256-15
256K
32Kx8
27512-25
512K
64Kx8
27C512-15
512K
64Kx8
27COIO-15
1,024K
I 28Kx8
27C020-15
2,048K
256Kx8
27C040-15
4,096K
512Kx8
Access
450 ns
450 ns
200 ns
450 ns
200 ns
200 ns
120 ns
250 ns
120 ns
250 ns
ISO ns
250 ns
ISO ns
ISO ns
ISO ns
150 ns
Pins
24
24
24
24
28
28
28
28
28
28
28
28
28
32
32
32
Vpp
25 V
25 V
21 V
12.5 V CMOS
21 V
12.5 V
12.5 V CMOS
21 V
12.5 V CMOS
12.5 V
12.5 V CMOS
12.5 V
12.5 V CMOS
12.5 V CMOS
12.5 V CMOS
12.5 V CMOS
Example 14-3
For ROM chip 27128, find the number of data and address pins.
Solution:
The 27128 has a capacity of 128K bits. It has 16Kx8 organization (all ROMs have 8
data pins), which indicates that there are 8 pins for data and 14 pins for address
(2 14 = 16K).
2764
[[]W[][[]
Vpp
A12
A7
A6
A5
Vpp
A12
A7
A6
A5
A7
A6
A5
A7
A6
A5
A4
A4
A4
A4
A3
A2
A1
AD
00
01
02
GND
A3
A2
A1
AD
00
01
02
GND
A3
A3
A2
A2
A1
A1
AD
AD
00 00
01
01
02 02
GND GND
Vpp
A12
A7
A6
A5
C
C
C
C
e
A4e
A3 e
A2 e
A1 e
AD e
00 e
01 e
02 D
GND C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P Vee
P PGM
P A8
p A9
P A11
pOE
P A10
P CE
P N.C.
pOl
P 06
P 05
P 04
P 03
~rn[]lliJ
i===
Vee
PGM
Vee Vee
A13
A8
A8
A8
A9
A9
A9
A11
~
~
OE OENpp OE
A10 A10
A10
CE
CE
CE
07
07
07
06
06
06
05
05
05
04
04
04
03
03
03
Vee
A14
A13
A8
A9
'1P
OE
A10
CE
07
06
05
04
03
FIgure 14-1. Pm ConfiguratIOns for 27xx ROM FamIly
CHAPTER 14: USING FLASH AND EEPROM MEMORIES
533
EEPROM (electrically erasable programmable ROM)
EEPROM has several advantages over EPROM, such as the fact that its
method of erasure is electrical and therefore instant, as opposed to the 20-minute
erasure time required for UV-EPROM. In addition, in EEPROM one can select the
byte to be erased, in contrast to UV-EPROM, in which the entire contents of ROM
are erased. The main advantage of EEPROM is that one can program and erase its
contents while it is still in the system board. It does not require physical removal
of the memory chip from its socket. In other words, unlike UV-EPROM, EEPROM does not require an external erasure and programming device. To utilize
EEPROM fully, the designer must incorporate the circuitry to program the EEPROM into the system board. In general, the cost per bit for EEPROM is much
higher than for UV-EPROM. In Section 14.3 we show how to access the prcIs
on-chip EEPROM.
Table 14-3: Some EEPROM and Flash Chips
EEPROMs
Org.
2KxS
SKxS
SKxS
32KxS
32KxS
Speed
250 ns
250 ns
250 ns
150 ns
250 ns
Pins
24
2S
2S
2S
2S
5V
5V
5 V CMOS
5V
5 V CMOS
Capacity
Org.
Speed
Pins
Vpp
256K
1,024K
2,04SK
32KxS
12SKxS
256KxS
200 ns
150 ns
150 ns
32
32
32
12 V CMOS
12 V CMOS
12 V CMOS
Part No.
Capacity
2S16A-25
16K
2S64A
64K
2SC64A-25
64K
2SC256-l5
256K
256K
2SC256-25
Vpp
Flash
Part No.
2SF256-20
2SFOIO-15
2SF020-15
Flash memory EPROM
Since the early 1990s, flash EPROM has become a popular user-programmable memory chip, and for good reasons. First, the erasure of the entire contents
takes less than a second, or one might say in a flash, hence its name, flash memory. In addition, the erasure method is electrical, and for this reason it is sometimes
referred to as flash EEPROM. To avoid confusion, it is commonly called flash
memory. The major difference between EEPROM and flash memory is that when
flash memory's contents are erased (or written to), the entire device is erased, in
contrast to EEPROM, where one can erase a desired section or byte. In recent
decades, Flash memory contents are divided into blocks and the erasure (or write)
is done block by block. Unlike EEPROM, Flash memory has no byte erasure (or
write) option. Because Flash memory can be programmed while it is in its socket
on the system board, it has replaced the UV-EPROM for the storage of810S ROM
of the PC. Nowadays, Flash memory is widely used for mass storage devices such
as PDAs, cell phones, USB memory sticks, and MP3 players. Some computer sci534
entists believe that Flash memory will replace the hard disk as a mass storage
medium. This would increase the performance of the computer tremendously,
because Flash memory is semiconductor memory with access time in the range of
100 ns compared with disk access time in the range of tens of milliseconds. For
this to happen, flash memory's program/erase cycles must become infinite, just
like hard disks. Program/erase cycle refers to the number of times that a chip can
be erased and programmed (written to) before it becomes unreliable. At this time,
the program/erase cycle is in the 100,000s for Flash and EEPROM, in the 1,000s
for UV-EPROM, and infinite for RAM and hard disks.
Mask ROM
Mask ROM refers to a kind of ROM in which the contents are programmed
by the IC manufacturer. In other words, it is not a user-programmable ROM. The
term mask is used in IC fabrication. Because the burning process is costly, mask
ROM is used when the needed volume is high (hundreds of thousands) and it is
absolutely certain that the contents will not change. It is common practice to use
UV-EPROM or flash for the development phase of a project; and only after the
code/data have been finalized is the mask version of the product ordered. The main
advantage of mask ROM is its cost, because it is significantly cheaper than other
kinds of ROM; but if an error is found in the data/code, the entire batch must be
thrown away. Many manufacturers of 8051 microcontrollers support the mask
ROM version of the 8051. Note that all ROM memories have 8 bits for data pins;
therefore, the organization is x8.
RAM (random access memory)
RAM memory is called volatile memory because cutting off the power to
the IC results in the loss of data. Sometimes RAM is also referred to as RAWM
(read and write memory), in contrast to ROM, which cannot be written to. There
are three types of RAM: static RAM (SRAM), NY-RAM (nonvolatile RAM), and
dynamic RAM (DRAM). Each is explained separately.
SRAM (static RAM)
Storage cells in static RAM memo- I--r==\,==,---'
ry are made of flip-flops and therefore do
24
Vee
A7D 1
not require refreshing in order to keep their
23
A8
A6D 2
data. This is in contrast to DRAM, dis3
22
A9
A5D
cussed below. The problem with the use of
21
WE
A4D 4
flip-flops for storage cells is that each cell
20
OE
A3D 5
requires at least 6 transistors to build, and
6
19
A10
A2D
the cell holds only 1 bit of data. In recent
7
18
CS
A1
years, the cells have been made of 4 tran8
17
1/08
AO
9
16
sistors, which still is too many. The use of 1/01
1/07
15
1/06
4-transistor cells plus the use of CMOS 11020 10
14
1/05
technology has given birth to a high-capac- 1/030 11
12
13
1/04
GND
0
ity SRAM, but its capacity is far below that
of DRAM. Table 14-4 shows some exam- Figure 14-2. 2Kx8 SRAM Pius
ples of SRAM. Figure 14-2 shows the pin
CHAPTER 14: USING FLASH AND EEPROM MEMORIES
535
diagram for an SRAM chip. In Figure 14-2, notice that WE is write enable, and
OE is output enable, for read and write signals, respectively.
Table 14-4: Some SRAM and NV-RAM Chips
SRAM
Part No.
Capacity
6116P-1
16K
16K
6116P-2
6116P-3
16K
6116LP-l
16K
6116LP-2
16K
16K
6116LP-3
64K
6264P-10
6264LP-70
64K
64K
6264LP-12
256K
62256LP-10
62256LP-12
256K
Org.
2Kx8
2Kx8
2Kx8
2Kx8
2Kx8
2Kx8
8Kx8
8Kx8
8Kx8
32Kx8
32Kx8
Speed
100 ns
120 ns
150 ns
100 ns
120 ns
150 ns
100 ns
70 n~
120 ns
100 ns
120 ns
Pins
24
24
24
24
24
24
28
28
28
28
28
Vpp
CMOS
CMOS
CMOS
Low-power CMOS
Low-power CMOS
Low-power CMOS
CMOS
Low-power CMOS
Low-power CMOS
Low-power CMOS
Low-power CMOS
Vpp
NV-RAM from Dallas Semiconductor
Capacity
Org.
Speed
Pins
OS 1220Y-150
16K
OS 1225AB-150 64K
OS1230Y-85
256K
2Kx8
8Kx8
32Kx8
150 ns
150 ns
85 ns
24
28
28
Part No.
NV-RAM (nonvolatile RAM)
Whereas SRAM is volatile, there is a new type of nonvolatile RAM called
NV-RAM. Like other RAMs, it allows the CPU to read and write to it, but when
the power is turned off the contents are not lost. NV-RAM combines the best of
RAM and ROM: the read and write ability of RAM, plus the nonvolatility of
ROM. To retain its contents, every NV-RAM chip internally is made of the following components:
1. It uses extremely power-efficient (very low power consumption) SRAM cells
built out of CMOS.
2. It uses an internal lithium battery as a backup energy source.
3. It uses an intelligent control circuitry. The main job of this control circuitry is
to monitor the V cc pin constantly to detect loss of the external power supply.
If the power to the Vee pin falls below out-of-tolerance conditions, the control
circuitry switches automatically to its internal power source, the lithium battery. The internal lithium power source is used to retain the NY-RAM contents
only when the external power source is off.
It must be emphasized that all three of the components above are incorporated into a single IC chip, and for this reason nonvolatile RAM is a very expen-
536
sive type of RAM as far as cost per bit is concerned. Offsetting the cost, however,
is the fact that it can retain its contents up to ten years after the power has been
turned off and allows one to read and write in exactly the same way as SRAM. See
Table 14-4 for NV-RAM parts made by Dallas Semiconductor.
DRAM (dynamic RAM)
Since the early days of the computer, the need for huge, inexpensive
read/write memory has been a major preoccupation of computer designers. In
1970, Intel Corporation introduced the first dynamic RAM (random access memory). Its density (capacity) was 1,024 bits and it used a capacitor to store each bit.
Using a capacitor to store data cuts down the number of transistors needed to build
the cell; however, the capacitor requires constant refreshing due to leakage. This
is in contrast to SRAM (static RAM), whose individual cells are made of flipflops. Because each bit in SRAM uses a single flip-flop, and each flip-flop requires
6 transistors, SRAM has much larger memory cells and consequently lower density. The use of capacitors as storage cells in DRAM results in much smaller net
memory cell size.
The advantages and disadvantages of DRAM memory can be summarized
as follows. The major advantages are high density (capacity), cheaper cost per bit,
and lower power consumption per bit. The disadvantage is that it must be refreshed
periodically because the capacitor cell loses its charge; furthermore, while DRAM
is being refreshed, the data cannot be accessed. This is in contrast to SRAM's flipflops, which retain data as long as the power is on, do not need to be refreshed, and
whose contents can be accessed at any time. Since 1970, the capacity of DRAM
has exploded. After the lK-bit (1,024-bit) chip came the 4K-bit in 1973, and then
the 16K chip in 1976. The 1980s saw the introduction of 64K, 256K, and finally
1M and 4M memory chips. The 1990s saw 16M, 64M, 256M, and the beginning
of IG-bit DRAM chips. In the 2000s, 2G-bit chips are standard, and as the fabrication process gets smaller, larger memory chips will be rolling off the manufacturing line. Keep in mind that when talking about IC memory chips, the capacity
is always assumed to be in bits. Therefore, a I M chip means a I-megabit chip and
a 256K chip means a 256-kilobit memory chip. When talking about the memory
of a computer system, however, it is always assumed to be in bytes.
Packaging issue in DRAM
In DRAM there is a problem in packing a large number of cells into a single chip with the normal number of pins assigned to addresses. For example, a 64K
chip (64Kxl) must have 16 address lines and 1 data line, requiring 16 pins to send
in the address if the conventional method is used. This is in addition to Vee power,
ground, and read/write control pins. Using the conventional method of data access,
the large number of pins defeats the purpose of high density and small packaging,
so dearly cherished by IC designers. Therefore, to reduce the number of pins needed for addresses, multiplexing/demultiplexing is used. The method used is to split
the address in half and send in each half of the address through the same pins,
thereby requiring fewer address pins. See Table 14-5. Internally, the DRAM structure is divided into a square of rows and columns. The first half of the address is
called the row and the second half is called the column. For example, in the case
CHAPTER 14: USING FLASH AND EEPROM MEMORIES
537
of DRAM of 64Kxl organization, the first
half of the address is sent in through the 8
DIN 0 2
15 o CAS
pins AO-A7, and by activating RAS (row
3
WE 0
14 o DOUT
address strobe), the internal latches inside
4
RAS
0
13
o A6
DRAM grab the first half of the address.
5
AO 0
12 o A3
Afier that, the second half of the address is
6
A20
11 OA4
sent in through the same pins, and by activat7
A10
10 o A5
ing CAS (column address strobe), the internal
Vee 0 8
90 A7
latches inside DRAM latch the second half of
the address. This results in using 8 pins for Figure 14-3. 256Kxl DRAM
addresses plus RAS and CAS, for a total of
10 pins, instead of the 16 pins that would be
required without multiplexing. To access a bit of data from DRAM, both row and
column addresses must be provided. For this concept to work, there must be a 2by-I multiplexer outside the DRAM circuitry and a demultiplexer inside every
DRAM chip. Due to the complexities associated with DRAM interfacing (RAS,
CAS, the need for multiplexer and refreshing circuitry), there are DRAM controllers designed to make DRAM interfacing much easier. However, many small
microcontroller-based projects that do not require much RAM (usually less than
64K bytes) use SRAM of types EEPROM and NV-RAM, instead of DRAM.
Table 14-5: Some Widely Used DRAMs
A80~OGND
Part No.
4164-15
41464-8
41256-15
41256-6
414256-10
511000P-8
514100-7
Speed
150 ns
80 ns
150 ns
60 ns
100 ns
80 ns
70 ns
Capacity
64K
256K
256K
256K
1M
1M
4M
Org.
64Kxl
64Kx4
256Kxl
256Kxl
256Kxl
IMxl
4Mxl
Pins
16
18
16
16
20
18
20
DRAM organization
In the discussion of ROM, we noted that all of them have 8 pins for data.
This is not the case for DRAM memory chips, which can have xl, x4, x8, or xl6
organizations. See Example 14-4.
Example 14-4
Discuss the number of pins set aside for addresses in each of the following memory
(b) 16Kx4 SRAM
chips:
(a) 16Kx4 DRAM
Solution:
Because 214 = 16K:
(a) For DRAM we have 7 pins (AO-A6) for the address pins and 2 pins for RAS and
CAS.
(b) For SRAM we have 14 pins for address and no pins for RAS and CAS because they
are associated only with DRAM. In both cases we have 4 pins for the data bus.
538
In memory chips, the data pins are also called 1/0. In some DRAMs there
are separate Din and Dou! pins. Figure 14-3 shows a 256Kxl DRAM chip with pins
AO-AS for address, RAS and CAS, WE (write enable), and data in and data out,
as well as power and ground.
Review Questions
I. The speed of semiconductor memory is in the range of
(a) microseconds (b) milliseconds
(c) nanoseconds (d) picoseconds
2. Find the organization and chip capacity for each ROM with the indicated number of address and data pins:
(a) 14 address, S data (b) 16 address, S data (c) 12 address, S data
3. Find the organization and chip capacity for each RAM with the indicated number of address and data pins:
(b) 13 address, 4 data SRAM
(a) 11 address, 1 data SRAM
(c) 17 address, S data SRAM
(d) S address, 4 data DRAM
(e) 9 address, I data DRAM
(f) 9 address, 4 data DRAM
4. Find the capacity and number of pins set aside for address and data for memory chips with the following organizations:
(a) 16Kx4 SRAM
(b) 32KxS EPROM
(c) IMxl DRAM
(d) 256Kx4 SRAM
(e) 64KxS EEPROM
(f) IMx4 DRAM
5. Which of the following is (are) volatile memory?
(a) EEPROM
(b) SRAM
(c) DRAM
(d) NY-RAM
SECTION 14.2: ERASING AND WRITING TO FLASH IN THE
PIC18F
The PICISF comes with three types of memory (a) SRAM, (b) Flash, and
(c) EEPROM. The SRAM is for general purpose usage including function registers, as we have seen throughout the book. The EEPROM is used for storing data
only. While the Flash memory is used primarily to store program (code), we can
also use it for storing fixed data such as look-up tables as we have seen throughout the book. In Chapter 6 we discussed how to use the TBLRD instruction to read
the fixed data stored in program Flash. In this section, we discuss how to write to
Flash memory. In the next section, we discuss how to access the EEPROM memory in the PICIS.
There are two ways to store (write) information (code or data) to the Flash
memory or erase its content: (a) using an external Flash programmer (burner) such
as PIC START, and (b) using instructions such as TBLWR. In this section, we show
how to use the TBLWR (table write) instruction to write to Flash memory. We will
also show how to erase the contents of Flash memory. Due to similarities between
the TBLRD and TBLWR instructions, it is very helpful to understand the material in Section 6.3 of Chapter 6, where we showed how to use the TBLRD instruction to read data stored in the Flash ROM.
CHAPTER 14: USING FLASH AND EEPROM MEMORIES
539
Using TBLWR to write data to Flash
There are some major similarities between the TBLRD and TBLWR
instructions. From Chapter 6, recall that in using the TBLRD instruction, we use
the TBLPTR register as pointer to the data in Flash and the TABLAT register as a
temporary place to store the data fetched from Flash. In the same way, the TBLWR
instruction writes data held in the TABLAT register to the Flash ROM location
whose address is pointed to by the TBLPTR register. In terms of autoincrement
/autodecrement, the TBLRD and TBLWR instructions are exactly the same. See
Table 14-6.
Table 14-6: PIC18 Table Write Instructions
Instruction
TBLWT*
TBLWT*+
TBLWT*TBLWT+*
Function
Table Write
Table Write with post-inc
Table Write with post-dec
Table Write with pre-inc
Description
After write, TBLPTR stays the same
Write and increment TBLPTR
Write and decrement TBLPTR
Increment TBLPTR and then write
There is a major difference between the TBLRD and TBLWR instructions.
While the TBLRD reads individual bytes from Flash, the TBLWR writes a block
of 8 bytes to Flash. The TBLRD instruction reads one byte at a time from the Flash
into the TABLAT registers, which means we must save the contents of the TABLAT before the next read wipes it out. The TBLWR instruction uses what is called
short write and long write to write to Flash. In the short write, we use the TBLWR
instruction to write a block of 8 bytes of data into 8 TABLAT registers one byte at
a time. After the short write is done, we use the long write to actually store (write,
or one might say bum) the entire block of 8 bytes into the Flash. The long write is
done with the help of a register called EECONl, shown in Figure 14-4. Notice that
the EECON I register is used for both Flash and EEPROM memory, as we will see
in the next section. Also contrast the difference between the Flash and EEPTROM
memory. In Flash memory, the write or erase process is done on a block of data,
while in EEPROM we can write or erase one byte at a time, which means it is byteaccessible memory. Readings for both Flash and EEPROM memories are in byte
sizes. The block size for Flash memory varies among the Flash memories depending on their size and intended application. The block size for write/erase in the
PICI84580 is 8 bytes, while in other Flash memories it is 64 or 256 bytes. The
breaking of the PIC 18F Flash into blocks of 8 bytes means the memory addresses
must be on the 8-byte boundaries. This means that the lower three bits of the
address A21-AO of the Flash ROM location must be all zeros. See Figure 14-5.
540
IEEPGD I CFGS
FREE
I WRERR I WERN I WR# I
RD#
EEPGD Flash Program or Data EEPROM Memory select bit
I = Access Program Flash memory
o= Access Data EEPROM memory
CFGS Flash Program/Data EE or Configuration Select bit
I = Access Configuration Registers
o = Access Program Flash or Data EEPROM memory
FREE Flash Row Erase Enable bit
1 = Erase the Program Flash memory row addresses by TBLPTR on the next
WR command (this bit is cleared when the Erase operation is completed)
o = Perform write only
WERR Write Error Flag bit
1 = A write operation is prematurely terminated
o= The write operation is completed
WREN Write Enable bit
I = Allows write cycle
0= Inhibits write to the EEPROM or Flash memory
WR# Write Control bit. This is an an active-LOW signal used for both Flash and
EEPROM. We can only make it HIGH by software and the PIC will make it
LOW automatically when the write cycle is completed
I = initiates the write cycle to Flash or EEPROM (also used for initiating
Erase / write cycle).
o = Write cycle is completed
RD#
Read Control bit. This is an an active-LOW signal used by EEPROM only. We
can only make it HIGH by software and the PIC will make it LOW
automatically when the read cycle is completed.
1 = Initiates the read cycle to EEPROM
0= Does not initiate an EEPROM read
Figure 14-4. EECONI (EEPROM Control Register, also used for Flash)
CHAPTER 14: USING FLASH AND EEPROM MEMORIES
541
HEX
ADDRESSES
0000
0008
0010
0018
0020
Byte
o
Byte
1
2
3
4
5
6
7
DDDDDDDD
DDDDDDDD
DDDDDDDD
DDDDDDDD
0028
FFF8
DDDDDDDD
Figure 14-5. Flash Memory 8-Byte Boundaries
Although there are 8 TABLAT registers for the short write, they are not
accessible individually. These 8 TABLAT registers are internal and are used solely for the purpose of the short write using the TBLWRT instruction. Compare
Figures 14-6 and 14-7 to contrast reading and writing to the Flash memory.
Steps in writing to Flash memory
Assuming that an area of Flash memory is erased, we can use the following steps to write a block of 8 bytes of data to the Flash memory:
(I) Load the TBLPTR registers with the address of the first byte being
written.
(2) Using the TBLWR instruction, write 8 bytes of data to the TABLAT
registers one after another. This is the end of the short write.
(3) Set the EECONI register for the write operation by setting (a) EEPGD
= 1, (b) CFGS = 0, and (c) WREN = 1.
(4) Disable all interrupts globally with "BCF INTCON, GIE".
(5) Write 55H to the EECON2 dummy register. This is the start of a long
write.
(6) Write AAH to the EECON2 dummy register.
(7) Set WR# to 1 with the instruction "BSF EECON1, WE". With WE = 1,
the write cycle begins.
(8) It will take about 2 ms to finish writing the 8 bytes to Flash. During this
write cycle, the CPU is stalled and will not allow fetching any opcode. Upon completion of the write cycle, the WE# bit will go back low automatically to indicate
that the write cycle is finished. This step concludes the end of long-write cycle.
(9) Reenable the interrupts globally with "BSF INTCON, GIE".
Notice from step 4 that we must disable the interrupts to prevent any interruption of the write cycle (long write). If writing to Flash is interrupted by the reset
pin (MCLR) or the WDT (watch dog timer), the WERR (write error) bit of the
542
EECON I will go HIGH to indicate that. The good thing is the EEPGD bit of the
EECONI remains HIGH, allowing us to fix the error by rewriting the data to
Flash. The EECON2 register does not exist physically and cannot be accessed. It
is used exclusively for the purpose of writing/erasing the Flash/EEPROM memory. Program 14-1 shows how to write 8 bytes of data to Flash locations starting at
address 400H. After writing the bytes, we read and display them on PORTS one
byte at a time to verify the write operation.
The C language version of Program 14-1 is given at the end of this section.
Program
Memory
00000
00001
------------_ .... _-
._.---------_._._--
00002
00003
/""
----------------_./""
~
------------_._._--
TBLPTR
------------_._._--
FFFFF
I
/"
.. -----------------
TABLAT
I
v
-
-------------------
Figure 14-6. Reading from Flash
Program
Memory
TABLAT
.~
Byte
7
Short write
I
II
II
I
!I--;'"~
"'°1 _ )"
-_ xxxxo,r - - - - - - -
I n the process of long
write the data is written
from TABLAT to the Flash
memory.
XXXX1,
,------XXXX2,
,------XXXX3,
r-------
XXXX4
XXXX5 f--------f---------
------
XXXX6 f--------------------- XXXX7 I- _____ -_
FFFFF : - - - - - - - -
Figure 14-7. Writing to Flash
CHAPTER 14: USING FLASH AND EEPROM MEMORIES
543
Program 14-1 (a) writes the message "GOOD BYE" to Flash memory
starting at location 400H, and (b) reads the data from Flash and places it in
PORTB one byte at a time.
;Program 14-1
COUNT
EQU Ox20
MOVLW
OxOO
MOVWF
TBLPTRL
;load the low byte of address
Ox04
MOVLW
MOVWF
TBLPTRH;load the high byte of address
;start a short write
MOVLW
A'G'
;load the 'G' byte into WREG
MOVWF
TABLAT
;move it to TABLATch reg
TBLWT*+
;perform short write increment address
MOVLW
A'O'
;load the '0' byte into WREG
MOVWF
TABLAT
;move it to TAB LATch reg
TBLWT*+
;perform short write increment address
MOVLW
A'O'
;load the '0' byte into WREG
MOVWF
TABLAT
;move it to TABLATch reg
TBLWT*+
;perform short write
MOVLW
A'D'
;load the 'D' byte into WREG
MOVWF
TABLAT
;move it to TABLATch reg
TBLWT*+
;perform short write
MOVLW
A'
;load the space into WREG
TABLAT
;move it to TABLATch reg
MOVWF
TBLWT*+
;perform short write
MOVLW
A'B'
;load the 'B' byte into WREG
MOVWF
TABLAT
;move it to TABLATch reg
TBLWT*+
;perform short write
MOVLW
A'Y'
;load the 'Y' byte into WREG
MOVWF
TABLAT
;move it to TABLATch reg
TBLWT*+
;perform short write
MOVLW
A'E'
;load the 'E' byte into WREG
MOVWF
TABLAT
;move it to TABLATch reg
TBLWT*+
;perform short write
;start the long write cycle (write to Flash itself)
OxOO
MOVLW
TBLPTRL
MOVWF
;load the low byte of address
Ox04
MOVLW
MOVWF
TBLPTRH;load the high byte of address
BSF
EECON1,EEPGD
;point to Flash memory
BCF
EECON1,CFGS
;access Flash program
BSF
EECON1,WREN
;enable write
INTCON,GIE
;disable all interrupts
BCF
55H
MOVLW
;wreg = 55h
EECON2
;write to dummy reg
MOVWF
OAAH
MOVLW
;wreg = aah
EECON2
;write to dummy reg
MOVWF
544
BSF
EECON1,WR
;now write it to Flash
NOP
;wait
BSF
INTCON,GIE
;enable all interrupts
BCF
EECON1,WREN
;disable write to memory
;read them back one byte at a time and examine the
;bytes on PORTB
MOVLW
OxOO
MOVWF
TBLPTRL;reload the low byte of address
MOVLW
Ox04
MOVWF
TBLPTRH;reload the high byte of address
CLRF
TRISB
;PORTB an output port
MOVLW
Ox8
;counter = 8
MOVWF
COUNT
OVER TBLRD*+
;read the byte to TABLAT and increment
MOVFF
TABLAT,PORTB
;send it to PORTB
CALL
DELAY
;wait enough to see the byte
DECF COUNT,F
;decrement counter
DECFSZ
COUNT,F
BRA
OVER
;continue for all the bytes
If the size of the block is not 8 bytes, then the rest of the unused block will
be untouched. See Program 14-2.
Program 14-2 (a) writes the message "HELLO" to Flash memory starting
at location 450H, and (b) reads the data from Flash and places it in PORTB one
byte at a time.
;Program 14-2
COUNT
EQU Ox20
MOVLW
Ox50
MOVWF
;load the low byte of address
TBLPTRL
MOVLW
Ox04
MOVWF
TBLPTRH;load the high byte of address
;start a short write
MOVLW
A'H'
;load the 'H' byte into WREG
MOVWF
TABLAT
;move it to TABLATch reg
TBLWT*+
;perform short write and increment
MOVLW
A'E'
;load the 'E' byte into WREG
MOVWF
TABLAT
;move it to TABLATch reg
TBLWT*+
;perform short write and increment
MOVLW
A'L'
;load the 'L' byte into WREG
MOVWF
TABLAT
;move it to TABLATch reg
TBLWT*+
;perform short write
MOVLW
A'L'
;load the 'L' byte into WREG
MOVWF
TABLAT
;move it to TABLATch reg
TBLWT*+
;perform short write
MOVLW
A'O'
;load the '0' byte into WREG
MOVWF
TABLAT
;move it to TABLATch reg
CHAPTER 14: USING FLASH AND EEPROM MEMORIES
545
TBLWT*+
;perform short write
;start the long write cycle (write to Flash itself)
MOVLW
Ox50
MOVWF
TBLPTRL
;load the low byte of address
MOVLW
Ox04
MOVWF
TBLPTRH
; load the high byte of address
BSF
EECON1,EEPGD
;point to Flash memory
EECON1,CFGS
BCF
;access Flash program
BSF
EECON1,WREN
;enable write
BCF
INTCON,GIE
;disable all interrupts
;wreg = 55h
55H
MOVLW
;write to dummy reg
MOVWF
EECON2
MOVLW
OAAH
;wreg = aah
;write to dummy reg
MOVWF
EECON2
BSF
EECON1,WR
;now write it to Flash
NOP
iwait
BSF
INTCON,GIE
;enable all interrupts
BCF
EECON1,WREN
;disable write to memory
;read them back one byte at a time and examine the
;bytes on PORTB
MOVLW
Ox50
MOVWF
TBLPTRL ;reload the low byte of address
MOVLW
Ox04
TBLPTRH;reload the high byte of address
MOVWF
CLRF
TRISB
;PORTB an output port
MOVLW
Ox05
;counter = 5
MOVWF
COUNT
OVER TBLRD*+
;read the byte and increment
MOVFF
TABLAT,PORTB
;send it to PORTB
CALL
DELAY
;wait enough to see the byte
DECF COUNT,F
;dec counter
DECFSZ
COUNT,F
BRA
OVER
;continue for all the bytes
Program 14-3 (a) transfers a block of data from the code space of the PICI8 chip
into RAM, (b) then writes the same data from RAM to Flash, and (c) reads the
data from new Flash locations and sends it to the serial port of the PICI8 one byte
at a time.
; Program 14-3
COUNT
EQU OxOB
BUFRAM
EQU Ox20
MOVLW D'S'
;number of bytes to retrieve
MOVWF COUNT
MOVLW high (BUFRAM) ;point to buffer
MOVWF FSROH
546
MOVLW low (BUFRAM)
MOVWF FSROL
MOVLW upper (CODE_DATA)
;load TBLPTR
MOVWF TBLPTRU
MOVLW high (CODE_DATA)
MOVWF TBLPTRH
MOVLW low (CODE_DATA)
MOVWF TBLPTRL
;retrieve the data from program memory
READ BLOCK
TBLRD*+
;read into TABLAT, and increment
MOVF TABLAT, W
;get data
MOVWF POSTINCO
;store data
DECFSZ COUNT
; done?
BRA READ BLOCK
; repeat
MOVLW upper (NEW_DATA)
;load TBLPTR
MOVWF TBLPTRU
MOVLW high (NEW_DATA)
MOVWF TBLPTRH
MOVLW low (NEW_DATA)
MOVWF TBLPTRL
MOVLW high (BUFRAM)
;point to buffer
MOVWF FSROH
MOVLW low (BUFRAM)
MOVWF FSROL
MOVLW 8
;number of bytes in RAM
MOVWF COUNT
;move the data back to program memory
WRITE BACK
MOVF POSTINCO, W
;get a byte from RAM
MOVWF TABLAT
;store the byte in table latch
TBLWT*+
;perform a short write
DECFSZ COUNT
;loop until buffers are full
BRA WRITE BACK
MOVLW upper (NEW_DATA) ;load TBLPTR
MOVWF TBLPTRU
MOVLW high (NEW_DATA)
MOVWF TBLPTRH
MOVLW low (NEW_DATA)
MOVWF TBLPTRL
BSF EECON1, EEPGD ;point to Flash program memory
BCF EECON1, CFGS
;access Flash program memory
BSF EECON1, WREN
;enable write to memory
BCF INTCON, GIE
;disable interrupts
MOVLW 55h
;write 55h
MOVWF EECON2
MOVLW OAAh
;write OAAh
CHAPTER 14: USING FLASH AND EEPROM MEMORIES
547
MOVWF EECON2
;start program (CPU stall)
BSF EECONl, WR
NOP
BSF INTCON, GIE
ire-enable interrupts
BCF EECONl, WREN
;disable write to memory
;read them back one byte at a time and send serially
BSF TRISD,7
;PORTD.7 as in input
MOVLW Ox20
; enable transmit and low baud rate
MOVWF
TXSTA
;write to reg
BCF
PIRl,TXIF
MOVLW
D' 15'
;9600 bps (Fosc/(64*Speed)-I)
MOVWF
SPBRG
;write to reg
BCF TRISC, TX ;make TX pin of PORTC an output
BSF RCSTA, SPEN ;enable the entire serial port
MOVLW B
;number of bytes in RAM
MOVWF COUNT
MOVLW upper (NEW_DATA) ; load TBLPTR
MOVWF TBLPTRU
MOVLW high (NEW_DATA)
MOVWF TBLPTRH
MOVLW low (NEW_DATA)
MOVWF TBLPTRL
CLRF TRISB
;PORTB an output port
MOVLW
OxB
icounter
B
MOVWF
COUNT
LN
TBLRD*+
;read the character
TABLAT,W
MOVF
Rl
BTFSS PIRl, TXIF ;wait until the last bit is gone
BRA Rl
;stay in loop
MOVWF
TXREG ;load the value to be transmitted
DECFSZ COUNT
;loop until buffers are full
BRA LN
; repeat
;
Steps in erasing Flash memory
Although we can use external Flash programmers to erase the Flash memory contents, the prCI8 allows us to write a program to erase the Flash memory.
The erasure process works on block-size, not byte-size data. The minimum block
size for the erasure is 64 bytes. That means the lowest 6 bits of addresses are all
zeros, making them 64-byte block boundaries. We can use the following steps to
erase a single 64-byte block of Flash memory:
I. Load the TBLPTR registers with the address of the block being erased.
2. Set the EECON 1 register for the erase operation by setting
(a) EEPGD = 1, (b) CFGS = 0, (c) WREBN = I, and (d) FREE = 1.
3. Disable all interrupts globally using "BCF INTCON, GIE".
4. Write 55H to the EECON2 dummy register.
548
5. Write AAH to the EECON2 dummy register.
6. Set WR# to I with the instruction "BSF EECON1, WE". With WE = I,
the erase cycle begins.
7. It will take about 2 ms to finish erasing the block of 64 bytes. During
this erase cycle, the CPU is installed and will not allow fetching of any
opcode. Upon completion of the erase cycle, the WE# bit will go back
HIGH automatically to indicate the erase cycle is finished.
8. Reenable the interrupts globally using "BCF INTCON, GIE".
Program 14-4 shows how to erase the 64-byte block.
;Program 14-4: This program erases the Flash
;memory starting at location Ox500.
ORG 0
MOVLW
upper (MYDATA)
MOVWF
TBLPTRH
;load the upper address
high (MYDATA)
MOVLW
MOVWF
TBLPTRH ;load the high byte of address
low (MYDATA)
MOVLW
MOVWF
TBLPTRL
;load the low byte of address
BSF
EECON1,EEPGD
;point to Flash memory
BCF
EECON1,CFGS
;access Flash program
BSF
EECON1,WREN
;enable write
;enable row erase operation
BSF EECON1, FREE
INTCON,GIE
BCF
;disable all interrupts
MOVLW
55H
;wreg = 55h
MOVWF
EECON2
;write to dummy reg
MOVLW
;wreg = aah
OAAH
MOVWF
EECON2
;write to dummy reg
BSF
EECON1,WR
;now write it to Flash
NOP
;wait
INTCON,GIE
;enable all interrupts
BSF
EECON1,WREN
;disable write to memory
BCF
HERE BRA
HERE
ORG 500H
MYDATA data "ABCDEFGH"
END
Examine Program 14-5. It combines erasing, writing, and reading of the
Flash memory.
;Program 14-5: This program erases the message of
;"GOOD BYE" from Flash addresses Ox1200 and replaces
;it with "HELLO".
upper (MYDATA)
MOVLW
MOVWF
TBLPTRU
;load the upper address
high
(MYDATA)
MOVLW
CHAPTER 14: USING FLASH AND EEPROM MEMORIES
549
MOVWF
TBLPTRH ;load the high byte of address
MOVLW
low (MYDATA)
MOVWF
TBLPTRL
;load the low byte of address
BSF
EECONl,EEPGD
;point to Flash memory
BCF
EECONl,CFGS
;access Flash program
BSF
EECONl,WREN
;enable write
;enable row erase operation
BSF EECONl, FREE
BCF
INTCON,GIE
;disable all interrupts
MOVLW
55H
;wreg = 55h
MOVWF
EECON2
;write to dummy reg
MOVLW
OAAH
;wreg = aah
MOVWF
EECON2
;write to dummy reg
BSF
EECONl,WR
;now write it to Flash
NOP
;wait
BSF
INTCON,GIE
;enable all interrupts
BCF
EECONl,WREN
;disable write to memory
MOVLW
upper (MYDATA)
MOVWF
TBLPTRU
;load the upper address
MOVLW
high (MYDATA)
MOVWF
TBLPTRH ;load the high byte of address
MOVLW
low (MYDATA)
MOVWF
TBLPTRL
;load the low byte of address
;start a short write
MOVLW
A'H'
;load the byte into WREG
MOVWF
TABLAT
;move it to TABLATch reg
TBLWT*+
;perform short write and increment
MOVLW
A'E'
;load the byte into WREG
MOVWF
TABLAT
;move it to TABLATch reg
TBLWT*+
;perform short write and increment
MOVLW
A'L'
;load the byte into WREG
MOVWF
TABLAT
;move it to TABLATch reg
TBLWT*+
;perform short write
MOVLW
A'L'
;load the byte into WREG
MOVWF
TABLAT
;move it to TABLATch reg
TBLWT*+
;perform short write
MOVLW
;load the byte into WREG
A'O'
MOVWF
;move it to TAB LATch reg
TABLAT
TBLWT*+
;perform short write
;start the long write cycle (write to Flash itself)
BSF
EECONl,EEPGD
;point to Flash memory
BCF
EECONl,CFGS
BSF
EECONl,WREN
;enable write
BCF
;disable all interrupts
INTCON,GIE
MOVLW
55H
;wreg = 55h
MOVWF
EECON2
;write to dummy reg
MOVLW
OAAH
;wreg = aah
MOVWF
EECON2
;write to dummy reg
550
EECONl,WR
;now write it to Flash
BSF
NOP
;wait
INTCON,GIE
BSF
;enable all interrupts
EECONl,WREN
BCF
;disable write to memory
;read them back one byte at a time and examine the
;bytes on PORTB
MOVLW
upper (MYDATA)
MOVWF
TBLPTRU
;load the upper address
MOVLW
high (MYDATA)
TBLPTRH ;load the high byte of address
MOVWF
MOVLW
low (MYDATA)
;load the low byte of address
MOVWF
TBLPTRL
CLRF TRISB
;PORTB an output port
;counter = 5
Ox05
MOVLW
MOVWF
COUNT
OVER TBLRD*+
;read byte to TABLAT and point to next
MOVFF
TABLAT,PORTB
;send it to PORTB
CALL
DELAY ;wait enough to see byte on PORTB
COUNT,F
;decrement counter
DECF
OVER
;continue for all the bytes
BNZ
ORG 1200H
MYDATA data "GOOD BYE"
END
Erasing and writing to Flash memory in C
Programs 14-6C through 14-8C are the C versions of earlier programs.
/*Program 14-6C: This C program (a) writes the message "GOOD BYE" to Flash memory starting at location
400H, (b) reads the data from Flash and places it in
PORTB one byte at a time. */
#include <p18Cxxx.h>
void Delay(unsigned int itime);
void main ()
{
unsigned char x;
//write to program memory
TBLPTR = (short long)Ox0400;
TABLAT= 'G' ;
asm TBLWTPOSTINC endasm
TABLAT= ' 0' ;
asm TBLWTPOSTINC endasm
TABLAT= '0' ;
asm TBLWTPOSTINC endasm
//load TBLPTR
//load in TABLAT
//short write
//load in TABLAT
//short write
//load in TABLAT
//short write
CHAPTER 14: USING FLASH AND EEPROM MEMORIES
551
TABLAT= ' D' ;
asm TBLWTPOSTINC
TABLAT=' , ,.
asm TBLWTPOSTINC
TABLAT= ' B' ;
asm TBLWTPOSTINC
TABLAT= ' Y' ;
asm TBLWTPOSTINC
TABLAT= ' E' ;
asm TBLWTPOSTINC
endasm
endasm
endasm
endasm
endasm
//long write
TBLPTR = (short long)Ox0400;
EECONlbits.EEPGD=l;
EECONlbits.CFGS=O;
EECONlbits.WREN=l;
INTCONbits.GIE=O;
EECON2=Ox55;
EECON2=OxAA;
EECONlbits.WR=l;
asm NOP endasm
INTCONbits.GIE=l;
EECONlbits.WREN=O;
//load in TABLAT
//short write
//load in TABLAT
//short write
/ /load in TABLAT
//short write
//load in TABLAT
//short write
//load in TABLAT
//short write
//reload TBLPTR
//read from program memory send to PORTB
TBLPTR = (short long)Ox0400; //reload TBLPTR
for(x=O;x<8;x++) {
asm TBLRDPOSTINC endasm
PORTB=TABLAT;
Delay(250);
}
}
//Program 14-7C: This C program erases the Flash
//memory starting at location Ox500.
#include <p18Cxxx.h>
#pragma romdata const_table = Ox500
const rom char my_const_array[lO] = "GOOD BYE";
#pragma romdata
void main ()
{
//erase program memory
TBLPTR = (short long)Ox0500;
EECONlbits.EEPGD=l;
552
//load TBLPTR
EECONlbits.CFGS=O;
EECONlbits.WREN=l;
EECONlbits.FREE=l;
INTCONbits.GIE=O;
EECON2=Ox55;
EECON2=OxAA;
EECONlbits.WR=l;
asm NOP endasm
INTCONbits.GIE=l;
EECONlbits.WREN=O;
}
//Program 14-8C: This C program erases the message of
//"GOOD BYE" from Flash addresses Ox1200 and replaces
flit with "HELLO".
#include <p18Cxxx.h>
void Delay(unsigned int itime);
#pragma romdata const_table = Ox1200
const rom char my_const_array[lO] = "GOOD BYE";
#pragma romdata
void main ()
{
unsigned char X;
//erase program memory
TBLPTR = (short long)Ox1200;
EECONlbits.EEPGD=l;
EECONlbits.CFGS=O;
EECONlbits.WREN=l;
EECONlbits.FREE=l;
INTCONbits.GIE=O;
EECON2=Ox55;
EECON2=OxAA;
EECONlbits.WR=l;
asm NOP endasm
INTCONbits.GIE=l;
EECONlbits.WREN=O;
TBLPTR = (short long)Ox1200;
TABLAT=' H' ;
asm TBLWTPOSTINC endasm
TABLAT= ' E' ;
asm TBLWTPOSTINC endasm
TABLAT= ' L' ;
//load TBLPTR
//load TBLPTR
//load in TABLAT
//short write
//load in TABLAT
//short write
//load in TABLAT
CHAPTER 14: USING FLASH AND EEPROM MEMORIES
553
asm TBLWTPOSTINC
TABLAT= • L' ;
asm TBLWTPOSTINC
TABLAT= • O' ;
asm TBLWTPOSTINC
endasm
endasm
endasm
//long write
TBLPTR = (short long)Ox1200;
EECONlbits.EEPGD=l;
EECONlbits.CFGS=O;
EECONlbits.WREN=l;
INTCONbits.GIE=O;
EECON2=Ox55;
EECON2=OxAA;
EECONlbits.WR=l;
asm NOP endasm
INTCONbits.GIE=l;
EECONlbits.WREN=O;
//short write
//load in TABLAT
//short write
//load in TABLAT
//short write
//reload TBLPTR
//read from program memory send to PORTB
TBLPTR = (short long)Ox1200;
//reload TBLPTR
for(x=O;x<8;x++) {
asm TBLRDPOSTINC endasm
PORTB=TABLAT;
Delay(250) ;
}
}
Review Questions
I. True or false. The PIC l8F Flash memory can be used for both program code
2.
3.
4.
5.
6.
7.
554
and data.
True or false. The PIC l8F SRAM memory can be used for both program code
and data.
True or false. In the PICI8F, writing to Flash is not allowed.
True or false. Reading from Flash memory is in byte size, while writing to it is
in block size.
True or false. During the long write, the CPU keeps fetching and executing the
instructions.
What is the size of the block for writing to Flash memory in the PIC18F458?
What is the size of the block for erasing the Flash memory in the PIC18F458?
SECTION 14.3: READING AND WRITING TO DATA EEPROM IN THE PIC18
The vast majority of the members of the PICI8 family come with some
EEPROM memory. The amount varies from 256 bytes to a few K depending on
the family member. For example, the PICI8F4520 has 256 bytes of EEPROM
while PIC 184585 has only 1,024 bytes. Table 14-7 shows some of the family
members and their EEPOM space. While the Flash memory in PIC 18F can be used
for storing both code and data, the EEPROM space is used exclusively for storing
data. Of the three memory spaces that PICI8 has, the SRAM and EEPROM are
used for data only while the Flash is used mainly for program and sometimes for
fixed data storage. See Figure 14-8.
Table 14-7: EEPROM Size for Some PIC18 Chips
Part No. On-Chip Flash On-chip RAM On-chip EEPROM
PICI8FI220
4KB
256 B
256 B
PIC18FI230
4KB
256 B
128 B
PICI8F2410 16 KB
768 B
OB
PIC18F4520 32 KB
1,536 B
256 B
PIC18F4580 32 KB
1,536 B
256 B
PICI8F4585 48KB
3,328 B
1,024 B
Note: On-chip RAM does not include the SFR space.
FLASH
PC
000000
RAM
EEPROM
FSR
EEADD
000
000
XFF
FFF
1FFFFF
Figure 14-8. Contrasting PIC18F Memories
CHAPTER 14: USING FLASH AND EEPROM MEMORIES
555
Writing data to EEPROM
There are four registers associated with the EEPROM. They are as follows:
(a) EEADR: An 8-bit register, used as pointer to EEPROM location.
(b) EEDATA: An 8-bit register, holds data to be written to EEPROM.
(c) EECONI: See Figure 14-4. Used by both EEPROM and Flash.
(d) EECON2: The dummy register. Used by both EEPROM and Flash.
Notice that the EEADR (EE address) register is only 8 bits wide in the
PIC 18F452/458. The 8-bit address gives us a total space of 256 bytes, which
should cover the size of the EEPROM in these chips. In microcontroller chips such
as PIC18F4585, which have 1,024 bytes of EEPROM, we have the low-byte and
high-byte addresses for the EEADR and they are called EEADRL and EEADRH.
Steps in writing to EEPROM
To write a byte of data to a location in the EEPROM memory, we go
through the following steps:
1. Load the EEADR registers with the address of the EEPROM location we
want to write the data byte to.
2. Load the EEDATA registers with the data byte we want to write to EEP
ROM.
3. Set the EECONI register for the EEPROM write by making
(a) EEPOD = 0, (b) CFOS = 0, and (c) WREN = 1.
4. Disable all interrupts globally using "BCF lNTCON, GlE".
5. Write 55H to the EECON2 dummy register.
6. Write AAH to the EECON2 dummy register.
7. Set WR# to I with the instruction "BSF EECON1, WE".
With WE = 1, the write cycle begins.
8. Upon completion of the write cycle, the WE# bit will be cleared
automatically to indicate that the write cycle is finished.
9. Re-enable the interrupts globally using "BCF lNTCON, GlE".
I 0. The WREN bit should be cleared to prevent an accidental write to the
EEPROM by some runaway program.
In the above steps notice the last one. It is important to make WREN = 0,
because the PIC 18 will not do that automatically. The following program writes
a single ASCII letter of 'H' to EEPROM address 10H.
MOVLW
OxlO ;starts at location lOH of EEPROM
MOVWF
EEADRD
;load the EEPROM address
AIHI
MOVLW
;load the byte into WREG
MOVWF
EEDATA
;move it to EEDATA reg
;point to EEPROM memory
BCF
EECON1,EEPGD
EECON1,CFGS
BCF
BSF
EECON1,WREN
;enable write
lNTCON,GlE
;disable all interrupts
BCF
MOVLW
Ox55
;wreg = 55h
556
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
EECON2
OxAA
EECON2
EECONl,WR
INTCON,GIE
EECONl,WREN
;write to dummy reg
;wreg = aah
;write to dummy reg
;now write it to Flash
;enable all interrupts
;disable write to memory
Steps in reading from EEPROM
Reading a byte from the EEPROM memory is simple and straightforward
as shown in the following steps:
I. Load the EEARD register with the address of the EEPROM location we
want to read from.
2. Set the EECONI register for the EEPROM read by making
(a) EEPGD = 0, (b) CFGS = 0, and (c) RD = I.
3. Within the next instruction cycle, the PICI8 will automatically fetch the
data from the EEPROM location and place it in the EEDATA register.
The only thing we have to do is to move data from the EEDTAT
register to a safe place before we do another read. The following shows
how to read a byte from EEPROM and place it in PORTB:
MOVLW
OxlO
;read location lOR of EEPROM
MOVWF
EEADR
;load the EEPROM address
BCF
EECONl,EEPGD
;point to EEPROM memory
EECONl,CFGS
BCF
BSF
EECONl,RD
;enable read
NOP ;data is fetched from EEPROM to EEDATA reg
MOVFF
EEDATA,PORTB
;place the data in PORTB
Program 14-9 (a) writes the message "HELLO" to EEPROM memory
starting at location 0, and (b) reads the data back from EEPROM and places it in
PORTB one byte at a time.
;Program 14-9: Writing to EEPROM
MOVLW OxO
;starts at location OR of EEPROM
MOVWF EEADR
;load the EEPROM address
MOVLW A'R'
;load the byte into WREG
MOVWF EEDATA
;move it to EEDATA reg
CALL EE WRT
INCF EEADR,F
;point to next location
MOVLW A'E'
;load the byte into WREG
MOVWF EEDATA
;move it to EEDATA reg
CALL EE WRT
INCF EEADR,F
;point to next location
MOVLW A'L'
;load the byte into WREG
MOVWF EEDATA
;move it to EEDATA reg
CALL EE WRT
CHAPTER 14: USING FLASH AND EEPROM MEMORIES
557
INCF EEADR,F
;point to next location
MOVLW A'L'
;load the byte into WREG
MOVWF EEDATA
;move it to EEDATA reg
CALL EE WRT
INCF EEADR,F
;point to next location
MOVLW A'O'
;load the byte into WREG
MOVWF EEDATA
;move it to EEDATA reg
CALL EE WRT
INCF EEADR,F
;point to next location
;read EEPROM one byte at a time and send it to
;PORTB
MOVLW OxO ;starts at location OH of EEPROM
MOVWF EEADR
;load the EEPROM address
BCF EECON1,EEPGD
;point to EEPROM memory
BCF EECON1,CFGS
MOVLW Ox05
;count ; 5
MOVWF COUNT
CLRF TRISB
;make PORTB output port
OVER BSF EECON1,RD
;enable read
NOP
MOVFF EEDATA,PORTB ;read the data to PORTB
CALL DELAY
;wait
INCF EEADR,F
;point to next location
DECF COUNT,F
;decrement counter
;keep repeating
BNZ OVER
HERE BRA HERE
EE WRT
BCF EECON1,EEPGD
;point to EEPROM memory
BCF EECON1,CFGS
BSF EECON1,WREN
;enable write
BCF INTCON,GIE
;disable all interrupts
MOVLW Ox55
;wreg ; 55h
;write to dummy reg
MOVWF EECON2
MOVLW OxAA
;wreg ; aah
MOVWF EECON2
;write to dummy reg
BSF EECON1,WR
;now write it to Flash
BSF INTCON,GIE
;enable all interrupts
EE WAIT
BTFSS PIR2,EEIF
BRA EE WAIT
BCF PIR2,EEIF
RETURN
558
Program 14-10 (a) moves a block of data from the code space of the PICI8 chip
into EEPROM, and (b) then reads the same data from EEPROM and sends it to
the serial port of the PIC 18, one byte at a time.
#include p18f458.inc
COUNT
BUFRAM
EQU
EQU
OxOB
Ox20
MOVLW D'8'
;number of bytes to retrieve
MOVWF COUNT
MOVLW OH
;starts at location OH of EEPROM
MOVWF EEADR
;load the EEPROM address
MOVLW upper (CODE_DATA)
;load TBLPTR
MOVWF TBLPTRU
MOVLW high (CODE_DATA)
MOVWF TBLPTRH
MOVLW low (CODE_DATA)
MOVWF TBLPTRL
;retrieve the data from program memory
READ BLOCK
TBLRD*+
;read into TABLAT, and increment
MOVF TABLAT, W
;get data
MOVWF EEDATA
;load data
CALL EE WRT
;save data
INCF EEADR,F
;point to next location
DECFSZ COUNT
; done?
BRA READ BLOCK
; repeat
;read them back one byte at a time and send to serial
;port
BSF TRISD,7
;PORTD.7 as in input
MOVLW Ox20 ;enable transmit and low baud rate
MOVWF TXSTA
;write to reg
BCF
PIRl,TXIF
MOVLW D'15'
;9600 bps (Fosc / (64 * Speed) - 1)
MOVWF SPBRG
;write to reg
BCF TRISC, TX ;make TX pin of PORTC an output
BSF RCSTA, SPEN ;enable the entire serial port
MOVLW 8
;number of bytes in RAM
MOVWF COUNT
MOVLW
OxO ;start at location OH of EEPROM
MOVWF
EEADR
;load the EEPROM address
CLRF TRISB
;make PORTB an output port
MOVLW
Ox8
;counter = 8
MOVWF
COUNT
CHAPTER 14: USING FLASH AND EEPROM MEMORIES
559
CALL EE RD
CALL SEND COM
INCF EEADR,F
DECFSZ COUNT
BRA LN
HERE BRA HERE
;read the character
;send character to serial port
LN
;loop until buffers are full
; repeat
i-------------
SENDCOM
Sl
BTFSS PIR1, TXIF ;wait unil the last bit is gone
BRA Sl
;stay in loop
MOVWF TXREG
;load the value to be transferred
RETURN
;return to caller
i-------------
EE WRT
BCF EECON1,EEPGD
BCF EECON1,CFGS
BSF EECON1,WREN
BCF INTCON,GIE
MOVLW Ox55
MOVWF EECON2
MOVLW OxAA
MOVWF EECON2
BSF
EECON1,WR
BSF INTCON,GIE
EE_WAIT BTFSS PIR2,EEIF
BRA EE WAIT
BCF PIR2,EEIF
RETURN
;point to EEPROM memory
;enable write
;disable all interrupts
;wreg = 55h
;write to dummy reg
;wreg = aah
;write to dummy reg
;now write it to Flash
;enable all interrupts
;--------------
EE RD
BCF EECON1,
BCF EECON1,
BSF EECON1,
MOVF EEDATA,
RETURN
EEPGD
CFGS
RD
W
i--------------
ORG Ox0300
CODE DATA
DATA "MOVE ME"
END
560
;point to DATA memory
;EEPROM read
;W = EEDATA
Accessing the EEPROM in C
Program 14-11 C shows how to write and read the EEPROM memory in C
language. This is the C version of an earlier program.
Program 14-11C (a) writes the message "YES" to EEPROM memory, and (b) then
reads the same data from EEPROM and sends it to PORTB one byte at a time.
j jProgram 14-11C
#include <p18F458.h>
void EE_WRT(void);
unsigned char EE_READ(void);
void Delay(unsigned int itime);
void main ()
(
unsigned char X;
TRISB=O;
//make PORTB output
//write to EEPROM
EEADR=OxO;
//EEPROM location
EEDATA='Y';
//write this char to it
EE_WRT() ;
EEADR=Oxl;
EEDATA= ' E ' ;
EE_WRT() ;
EEADR=Ox2;
EEDATA= ' S ' ;
EE_WRT() ;
EECONlbits.WREN=O; //disable write
//read from EEPROM and place it on PORTB
EECONlbits.RD=l;
lienable read
EEADR =OxO;
//EEPROM location
x=EE_READ();
//read data from EEPROM
PORTB=x;
//place it on PORTB
Delay(250) ;
//EEPROM location
EEADR =Oxl;
x=EE_READ() ;
//place it on PORTB
PORTB=x;
Delay(250) ;
EEADR =Ox2;
//EEPROM location
x=EE_READ () ;
PORTB=x;
//place it on PORTB
while (1) ;
EECONlbits.EEPGD=O;//point to EEPROM
EECONlbits.CFGS=O;
EECONlbits.WREN=l; lienable write
INTCONbits.GIE=O; //disable interrupts
EECON2=Ox55;
EECON2=OxAA;
CHAPTER 14: USING FLASH AND EEPROM MEMORIES
561
EECONlbits.WR=li
INTCONbits.GIE=li
while(!PIR2bits.EEIF)
PIR2bits.EEIF=Oi
i
}
unsigned char EE_READ()
{
EECONlbits.EEPGD=Oi
EECONlbits.CFGS=Oi
EECONlbits.RD=li
return (EEDATA) i
}
Program 14-12C (a) transfers a block of data from Flash to RAM, (b) writes the
block to EEPROM memory, and (b) then reads the same data from EEPROM and
sends it to the serial port one byte at a time.
//Program 14-12C
#include <pI8f458.h>
void EE_WRT(void) i
unsigned char EE_READ(void);
void SerTx(unsigned char) i
void main(){
rom far char* RomPointer="MOVE ME";
char RamString[7] i
unsigned char x,ch,k=sizeof(RomPointer) i
TXSTA=Ox20;
//choose low baud rate,8-bit
SPBRG=15i
//9600 baud rate, XTAL = 10 MHz
TXSTAbits.TXEN=li
RCSTAbits.SPEN=li
//move the string to RAM
for(x=Oi x <7iX++){
RamString[x]=RomPointer[x]
i
}
//move the string to EEPROM
for(x=Oi x <7iX++){
EEADR=Xi
EEDATA=RamString[x] i
EE_WRT () i
}
EECONlbits.WREN=Oi//disable write
//read from EEPROM and send serially
for(x=Oix<7i X++){
562
EEADR=x;
ch=EE_READ () ;
SerTx (ch) ;
}
while(l) ;//infinite loop
}
EECONlbits.EEPGD=O; //point to EEPROM
EECONlbits.CFGS=O;
EECONlbits.WREN=l;
lienable write
//disable interrupts
INTCONbits.GIE=O;
EECON2=Ox55;
EECON2=OxAA;
EECONlbits.WR=l;
INTCONbits.GIE=l;
while(!PIR2bits.EEIF) ;
PIR2bits.EEIF=O;
}
unsigned char EE_READ()
{
EECONlbits.EEPGD=O;
EECONlbits.CFGS=O;
EECONlbits.RD=l;
return (EEDATA) ;
//point to EEPROM
}
void SerTx(unsigned char c)
(
while (PIRlbits.TXIF==O) ; //wait until transmitted
TXREG=c;
//place character in buffer
}
Review Questions
1. True or false. The PIC 18 EEPROM memory is used for both program code and
data.
2. True or false. The PICI8F4580 has 1,024 bytes of EEPROM memory.
3. True or false. In the PICI8, EEPROM contents are lost when power is cut off
to the chip.
4. True or false. In the PICI8, EEPROM memory is read and write memory.
5. True or false. Every PICI8F chip comes with I KB of EEPROM.
6. What is the advantage of the EEPROM over Flash?
CHAPTER 14: USING FLASH AND EEPROM MEMORIES
563
SUMMARY
This chapter described memory interfacing with S03115 I-based systems.
We began with an overview of semiconductor memories. Types of memories were
compared in terms of their capacity, organization, and access time.
ROM (read-only memory) is nonvolatile memory typically used to store
programs. The relative advantages of various types of ROM were described in this
chapter, including PROM, EPROM, UV-EPROM, EEPROM, flash memory
EPROM, and mask ROM.
RAM (random-access memory) is typically used to store data or programs.
The relative advantages of its various types, including SRAM, NY-RAM, checksum byte RAM, and DRAM, were discussed.
The Flash memory space of the PICIS was discussed, and programs were
written in both Assembly and C to access it. Finally, the EEPROM memory of the
PIC IS chip was explored and we showed how to access it in both Assembly and
C.
PROBLEMS
SECTION 14.1: SEMICONDUCTOR MEMORY
I. What is the difference in capacity between a 4M memory chip and 4M of computer memory?
2. True or false. The more address pins, the more memory locations are inside the
chip. (Assume that the number of data pins is fixed.)
3. True or false. The more data pins, the more each location inside the chip will
hold.
4. True or false. The more data pins, the higher the capacity of the memory chip.
5. True or false. The more data pins and address pins, the greater the capacity of
the memory chip.
6. The speed of a memory chip is referred to as its ~_ _ _ _ __
7. True or false. The price of memory chips varies according to capacity and
speed.
S. The main advantage of EEPROM over UV-EPROM is _ _ _ _ _ __
9. True or false. SRAM has a larger cell size than DRAM.
10. Which of the following, EPROM, DRAM, or SRAM, must be refreshed periodically?
II. Which memory is used for PC cache?
12. Which of the following, SRAM, UV-EPROM, NV-RAM, or DRAM, IS
volatile memory?
13. RAS and CAS are associated with which memory?
(a) EPROM (b) SRAM (c) DRAM (d) all of the above
14. Which memory needs an external multiplexer?
(a) EPROM (b) SRAM (c) DRAM (d) all of the above
15. Find the organization and capacity of memory chips with the following pins:
(a) EEPROM AO-AI4, DO-07 (b) UV-EPROM AO-A12, DO-07
564
(c) SRAM AO-AII, DO-D7
(d) SRAM AO-AI2, DO-D7
(e) DRAM AO-AIO, DO
(f) SRAM AO-AI2, DO
(g) EEPROM AO-AII, DO-D7 (h) UV-EPROM AO-AIO, DO-D7
(i) DRAM AO-A8, DO-D3
(j) DRAM AO- A 7, DO-D7
16. Find the capacity, address, and data pins for the following memory organizations:
(b) 32Kx8 ROM
(a) 16Kx8 ROM
(d) 256Kx8 EEPROM
(c) 64Kx8 SRAM
(e) 64Kx8 ROM
(f) 64Kx4 DRAM
(h) 4Mx4 DRAM
(g) IMx8 SRAM
(i) 64Kx8 NV-RAM
SECTION 14.2: ERASING AND WRITING TO FLASH IN THE PICI8F
17. True or false. The Flash memory in PIC 18F is used primarily for the program
code.
18. True or false. The Flash memory in PIC 18F can be also used for storing fixed
data.
19. True or false. The maximum memory space for program memory in PICI8F is
2M bytes.
20. True or false. Reading data from Flash memory can be done one byte at a time.
21. True or false. Writing data to Flash memory can be done one byte at a time.
22. True or false. Writing data to Flash memory must be done in blocks of 64
bytes.
23. True or false. Erasing of Flash memory can be done one byte at a time.
24. True or false. The use of the EECON2 register in writing/erasing of Flash
memory must is optional.
25. What registers are used in reading the fixed data stored in Flash memory?
26. What registers are used in writing fixed data to Flash memory?
27. What registers are used in erasing the Flash memory?
28. What is the difference between the WREN and WR bits in the EECONI register?
29. What registers are used by the TBLRD instruction?
30. What registers are used by the TBLWRT instruction?
31. Explain the difference between the short write and the long write in the PIC 18.
32. During which write is the fetching of the opcode suspended by the CPU?
33. What is the size of the block of data for writing to Flash memory III
PIC184580?
34. What is the size of the block of data for erasing the Flash memory III
PIC184580?
35. Indicate all the addresses that have an 8-byte boundary:
(a) 5lOH
(b) 512H
(c) 514H
(d) 516H
(e) 518H
(f) 51AH
(g) 51 CH
(h) 51EH
36. Indicate all the addresses that have a 64-byte boundary:
(a) 500H
(b) 520H
(c) 540H
(d) 560H
(e) 580H
(f) 5AOH
(g) 5COH
37. Give the boundary addresses for the address range of2000-2020H that can be
CHAPTER 14: USING FLASH AND EEPROM MEMORIES
565
used in writing to Flash.
3S. Give the boundary addresses for the address range of 2000--2 100H that can be
used in erasing of Flash memory.
39. Write a program to erase a section of Flash and then write the message "Hello
World" to it.
40. For Problem 39, write a program to verify the write operation by reading it and
sending it to the serial port one byte at a time
SECTION 14.3: READING AND WRITING TO DATA EEPROM IN THE
PICISF
41. True or false. The EEPROM memory in the PICISF is used primarily for the
program code.
42. True or false. The EEPROM memory in the PIC1SF is used for data only.
43. True or false. Every PIC1SF member has at least 256 bytes of EEPROM
memory.
44. True or false. Reading data from EEPROM memory can be done one byte at a
time.
45. True or false. Writing data to EEPROM memory can be done one byte at a
time.
46. True or false. Writing data to EEPROM memory must be done in blocks of 64
bytes.
47. True or false. Erasing of data in EEPROM memory can be done one byte at a
time.
4S. True or false. The use of the EECON2 register in reading and writing of EEPROM memory is optional.
49. True or false. The EECON2 register is used by both the Flash and EEPROM
memory write operation.
50. What registers are used in reading data from EEPROM memory?
51. What registers are used in writing data to EEPROM memory?
52. Give the major differences between Flash and EEPROM in the PICIS.
53. What is the size of the block of data for writing to EEPROM memory in the
PIClS?
54. Which bits of the EECONI are used by the read operation of the EEPROM?
55. Why do we disable the interrupts during the write cycle of Flash/EEPROM
memory?
56. Why don't we disable the interrupts during the read cycle of Flash/EEPROM
memory?
57. Write a program to write the message "Hello World" to EEPROM.
5S. For Problem 57, write a program to verify the write operation by reading it and
sending it to the serial port one byte at a time.
ANSWERS TO REVIEW QUESTIONS
SECTION 14.1: SEMICONDUCTOR MEMORY
I.
c
2.
(a) 16Kx8, 128K bits
566
(b) 64Kx8, 512K
(c) 4Kx8, 32K
3.
4.
5.
(a) 2KxI, 2K bits
(b) 8Kx4, 32K
(e) l28Kx8, 1M
(d) 64Kx4, 256K
(e) 256Kxl, 256K
(I) 256Kx4, 1M
(a) 64K bits, 14 address, and 4 data
(b) 256K, 15 address, and 8 data
(d) 1M, 18 address, and 4 data
(c) I M, 10 address, and I data
(I) 4M, 10 address, and 4 data
(e) 512K, 16 address, and 8 data
b, c
SECTION 14.2: ERASING AND WRITING TO FLASH IN THE PICI8F
1.
2.
3.
4.
5.
6.
7.
True
False
False
True
False
8 bytes
64 bytes
SECTION 14.3: READING AND WRITING TO DATA EEPROM IN THE PICI8
1.
2.
3.
4.
5.
6.
False
False
False
True
False
In EEPROM we can write a single byte of data, while in Flash, we must write a block of data.
CHAPTER 14: USING FLASH AND EEPROM MEMORIES
567
CHAPTER 15
CCPANDECCP
PROGRAMMING
OBJECTIVES
Upon completion of this chapter, you will be able to:
»
»
»
»
»
»
»
Understand the compare and capture features of the PIC18
Examine the use of timers in CCP and ECCP modules
Explain how the compare feature of CCP and ECCP modules works
Explain how the capture feature of CCP and ECCP modules works
Code programs for compare and capture features in Assembly and C
Explain how the PWM (pulse width modulation) works in both CCP
and ECCP
Code programs to create PWM in Assembly and C
569
This chapter discusses the capture/compare/pulse width modulation (CCP)
features of the PICI8. In Section IS.I. we show the difference between standard
and enhanced CCP modules. In Section IS.2, we describe the compare feature
while Section IS.3 deals with the capture feature of the PICI8. The pulse width
modulation (PWM) of the PICI8 is shown in Section IS.4. An overview of ECCP
is given in Section IS.S. In all these sections we use both Assembly and C language programs to show these important features of the PIC 18.
SECTION 15.1: STANDARD AND ENHANCED CCP
MODULES
Depending on the family member, the PICI8 has anywhere between 0 and
S CCP modules inside it. The multiple CCP modules are designated as CCP I,
CCP2, CCP3, and so on (CCPx). In recent years, the PWM feature of the CCP has
been enhanced greatly for better DC motor control, producng what is called
enhanced CCP (ECCP). Therefore, a given family member can have two standard
CCP modules and one or more ECCP modules, all on a single chip. See
Table IS-I. The ECCP modules are discussed in Chapter 17.
CCP and timers
Table 15-1: PIC18 CCP and ECCP Modules
To program these Ch'
#ofCCP
# of ECCP
~~IP~~~------~~~~--~~~~~~~
CCP modules, we must PICI8F2220
2
0
understand PICI8 timers. =-P':;':IC="I~8=F:=4722:;':Oo-----=-----~----
I
I
Review timers in Chapter 9 =-P-::IC:::'I~8;::F"'4:'::S~27/4:-:S:-::2-::-0-----''-------:'-----
I
I
before you embark on this PIC 18F4S8/4S80
I
I
chapter. Depending on the !..P':;':IC:::';I~8:':'F':::6':::SJ:::'I':::O=~-~------''-------
2
3
CCP feature used, the
timer usage is different. The allocation of the timers among the CCP features is
shown in Table IS-2.
Table 15-2: PIC18 Usage of Timers
CCPmode
Timer
Capture
Timerl or Timer3
Compare
Timerl or Timer3
PWM
Timer2
Note: The T3CON register is used to choose the timer for the compare and capture modes.
The CCP registers
Each CCP module has three registers associated with it. They are as follows:
(a) CCPxCON is an 8-bit control register. We select one of the compare,
capture, and PWM modes using this register. See Figure IS-I.
570
(b) and (c) CCPRxL and CCPxH form the low byte and the high byte of
the 16-bit register. This 16-bit register can be used either as a 16-bit compare register, or a 16-bit capture register, or an 8-bit duty cycle register by the PWM, but
not all at the same time. See Figures 15-1 and 5-2. The CCPICON register selects
the mode of operation.
I OCIBI I OCIB21 CCPIM3 ICCPIM21 CCPIMq CCPIMO I
DCIBI Duty Cycle Bit 1. Used only in PWM mode.
Bit I of the lO-bit duty cycle register used in PWM
DCIBO Duty Cycle Bit O. Used only in PWM mode.
The least-significant bit (bit 0) of the lO-bit duty cycle register. Used in PWM.
The CCPxL register is used as bit 2 to bit 9 of the lO-bit duty cycle register.
CCPIM3-CCIMO CCPI Mode Select
0000
CCPI~off
Reserved
000 I
00 I 0
Compare mode. Toggle CCPI output pin on match.
(CCPlIF bit is set.)
00 I I
Reserved
0100
oI 0 I
oI
oI
I0
I I
1000
I 00 I
I0I0
101 I
I Ixx
Capture mode,
Capture mode,
Capture mode,
Capture mode,
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
Compare mode. Initialize CCP I pin LOW, on compare match
force CCPI pin HIGH. (CCPlIF is set.)
Compare mode. Initialize CCPI pin HIGH, on compare match
force CCPI pin LOW. (CCPIIF is set.)
Compare mode. Generate software interrupt on compare
match. (CCPIIF bit is set, CCPI pin is unaffected.)
Compare mode. Trigger special event. (CCPlIF bit is set, and
Timerl or Timer3 is reset to zero.)
PWM mode
Figure 15-1. CCPl Control Register. (This register selects one ofthe operation modes of Capture, Compare, or PWM.)
I
CCPRlH
II
CCPRIL
I
10151014101310121011 1010 I 09 108 11 07 106 105 104 1D3 I 02 1D1 I DO 1
Figure 15-2. CCP High and Low Registers
CHAPTER 15: CCP AND ECCP PROGRAMMING
571
CCP pins
Each CCP module has a single pin assigned to it. That means that a PIC 18
family member with two standard CCP modules (e.g., PICl8F65Jl 0) has two pins,
one assigned to each of the CCPs. See Figure 15-3. In the case of the enhanced
CCP (ECCP), although it has a single pin, we can program up to four pins to be
used by the PWM feature of the ECCP, as we will see at the end of this chapter
and in Chapter 17.
MCLRNPP
40
RB7/PGD
RAO/ANO/CVREF
2
39
RB6/PGC
RA1/AN1
3
38
RB5/PGM
RA2/AN2NREF- -
4
37
RB4
RA3/AN3NREF+
5
36
RB3/CANRX
RA4fTOCKI
6
35
RB2/CANTXIINT2
RA5/AN4/SS/LVDIN
7
34
RB111NT1
REO/AN5/RD
8
33
RBOJ/NTO
RE1/AN6IWRlClOUT
9
32
VDD
RE2/AN7/CS/C20UT
10
31
VSS
VDD
11
30
RD7/PSP7/P1 D
VSS
12
29
13
28
14
27
RCOm osom CKI
15
26
RC7/RX/DT
RC1fT10SI
16
25
RC6fTX/CK
RC2/CCP1
17
24
RC5/SDO
RC3/SCK/SCL -
18
23
RC4/SDIISDA
RDO/PSPO/C 11N+ -
19
22
RD3/PSP3/C2IN-
OSC1/CLKI
OSC2/CLKO/RA6 _
RD1/PSP1/C1IN-
-----j 20
PIC18F458
-
RD6/PSP6/P1C
RD5/PSP5/P1 B
RD4/PSP4/ECCP1/P1A
21 ~ RD2/PSP2/C2IN+
Figure 15-3. Standard CCP Pins in PIC18F458/4580 (452/4520)
Review Questions
1. True or false. The PIC 18 chip can have multiple CCP modules inside a single
chip.
2. True or false. The CCPl register is a 16-bit register.
3. True or false. A single pin is associated with each of the standard CCP modules.
4. Give the pin number used for the standard CCPI in the PICI8F452/458 (or
PIC 18F4520/4580) chip.
572
SECTION 15.2: COMPARE MODE PROGRAMMING
The Compare mode of the CCP module is selected using the select bits in
the CCPxCON register. The Compare mode can cause an event outside the microcontroller. This event can be simply turning on a device connected to the CCP pin.
or the start of an ADC conversion. This event is caused when the content of the
Timer! (or Timer3) register is equal to the 16-bit CCPRIH:CCPRIL register. To
use the compare mode ofthe CCP, we must load both the 16-bit (CCPIH:CCPIL)
and the Timer! (or Timer3) register with some initial values. As Timer! (or
Timer3) counts up, its value is constantly compared with the CCPRIH:CCPRIL
register and when a match occurs, the CCPI pin can perform one of the following
actions:
(a) Drive high the CCPI pin
(b) Drive low the CCP I pin
(c) Toggle the CCPI pin
(d) Remain unaffected
(e) Trigger a special event with a hardware interrupt and clear the timer
We use the CCPICON register to select one of the above actions. See
Example 15-1. Note that upon match, the CCPIIF will also go HIGH. See Figure
15-5. Notice that for the above options of (a), (b), and (c) to work, the CCP pin
must be configured as an output pin. From Figure 15-4 we use the T3CON register to select Timer! or Timer3 for the Compare mode. In PIC18F452/458 (or their
newer version, PIC 18F4520/4580) chips with both CCP1 and ECCPI modules on
the chip, we can assign Timer1 to CCP1 and Timer3 to ECCP1, therefore making
them work independently of each other. Also note that only option (e), the special
event trigger, will cause Timer! (or Timer3) to clear, while in other cases we must
clear the timer.
Example 15-1
Using Figures 15-1 and 15-4, find the following:
(a) The CCPICON register value for Compare mode if we want to toggle the CCP1 pin
upon match
(b) The T3CON register value if we want to to use Timer3 for the Compare mode of
CCP1 with no prescaler
Solution:
(a) From Figure 15-1 we have 00000010 (binary) or Ox20 for the CCPICON register.
(b) From Figure 15-4 we have 01000010 (binary) or Ox42 for the nCON register.
There are many applications for the compare feature. One application can
be to count the number of people going through a door and closing the door when
it reaches a certain number.
CHAPTER 15: CCP AND ECCP PROGRAMMING
573
I RDI61 T3CCP21 T3CKPSI IT3CKPSOI T3CCPII T3SYNC ITMR3CSI TMR30N
RDI6
D7
16-bit read/write enable bit
1 = Timer3 16-bit is accessible in one 16-bit operation.
o = Timer3 16-bit is accessible in two 8-bit operations.
06D3 assigns Timer3 or Timer! to CPP 1 and CCP2 modules
T3CCP2:T3CCPI
ECCP 1 (or CCP2)
CCPI
Timer 1
Timer!
(clock source for compare/capture)
00=
Timerl
Timer3
(clock source for compare/capture)
o1
Timer3
(clock source for compare/capture)
1 x =
Timer3
T3CKPSI :T3CKPSO 05 04
00=1:1
o 1 = 1:2
1 0 = 1:4
1 1 = 1:8
TISYNC
D2
TMR3CS
01
TMR30N
00
Timer3 Input Clock Prescaler Selector
Prescale value
Prescale value
Prescale value
PrescaI e value
Timer3 External Clock Input Synchronization Control bit
U sed only when TMR3CS = 1 and clock comes from an
external source. IfTMR3CS = 0, this bit is not used.
1 = 00 not synchronize external clock input.
0= Synchronize external clock input.
Timer 3 Clock Source Select bit
1 = External clock from pin RCO (T 1OSI or T 1CKI)
0= Internal clock (Fosc/4)
Timed ON and OFF Control bit
I = Enable (start) Timer3
o = Stop Timer3
Figure 15-4. T3CON (Timer 3 Control) Register
I CCPIIFI
I
"
CCPlIF CCPlIF Interrupt Flag bit
Compare Mode
0= Timer! (or Timer3) match did not occur.
1 = Timer! (or TimerJ) match occurred (must be cleared by software).
Capture Mode
o = Timer I (or Timer3) register capture did not occur.
1 = Timer 1 (or Timer3) register capture occurred (must be cleared by software).
Figure 15-5. PIRI (Peripheral Interrupt flag register 1) Contains the
CCPlIFFlag
574
TMR1H
TMR3H
TMR1L
TMR3L
Register Select
(T3ECCP1 :T3CCP1
CCP1
(RC2)
CCPR1H
CCPR1L
Figure 15-6. Compare Mode Operation
Steps for programming the Compare mode
The following steps are taken in programming the Compare mode:
1.
2.
3.
4.
5.
6.
7.
Initialize the CCPl CON register for the compare option.
Initialize the T3CON register for Timer! (or Timer3).
Initialize the CCPRIH:CCPRIL registers.
Make the CCPI pin an output pin.
Initialize Timer! (or Timer3) register values.
Start Timerl (or Timer3).
Monitor the CCPIIF flag (or use an interrupt).
Program 15-1 shows an example of the Compare mode. It uses Timer3 as
a counter and counts the number of pulses fed to Timer3. The pulses could be the
number of people going into an elevator. When the count reaches 10, it toggles the
LED connected to the CCPI pin.
For Program 15-1 assume that a I-Hz pulse is connected to the Timer3 pin
and an LED is connected to the CCP I pin. Timer3 is being used as a counter.
Using the Compare mode, this Assembly language program will toggle the LED
every 10 pulses.
J1..fL
PIC18F
452/458
T1CKI (RCO)
LED
CCP1 (RC2)
Figure 15-7. Drawing for Programs 15-1 and 15-1C
CHAPTER 15: CCP AND ECCP PROGRAMMING
575
;Program 15-1
MOVLW Ox02
MOVWF CCPICON
;Compare mode, toggle upon match
MOVLW Ox42
jTimer3 for Compare, 1:1 prescaler
MOVWF T3CON
BCF
TRISC,CCPl
;CCPl pin as output
BSF
TRISC,TICKI
;T3CLK pin as input pin
MOVLW Dr 10 r
MOVWF CCPRlL
;CCPRIL
10
MOVLW OxO
;CCPRIH
0
MOVWF CCPRIH
OVERCLRF
TMR3H
;clear TMR3H
CLRF
TMR3L
;clear TMR3L
BCF
PIRl,CCPlIF
;clear CCPlIF
BSF
T3CON,TMR30N
jstart Timer3
Bl
BTFSS PIRl, CCPlIF
BRA
Bl
;---------CCP toggle CCP pin upon match
B2
BCF
T3CON, TMR30N
; stop Timer3
GOTO
OVER
; keep doing it
//Program 15-1C is a C version of Program 15-1
CCPICON=Ox02;
//Compare mode, toggle upon match
T3CON=Ox42;
//Timer3 for Compare, 1:1 prescaler
TRISCbits.TRISC2=O; //CCPl pin an output
TRISCbits.TRISCO=l;
//T3CLK pin an input
CCPRIL=10;
//load CCPRIL
CCPRIH=O;
//load CCPRIH
while{l)
(
TMR3H=0;
TMR3L=0;
PIRlbits.CCPlIF=O;
//clear CCPIIF flag
T3CONbits.TMR30N=1; //turn on Timer3
while{PIRlbits.CCPlIF==O) ii/wait for CCPIIF
//CCP toggles CCP pin upon match
T3CONbits.TMR30N=0; //stop Timer3
Examine Program 15-2: For this program we assume that the
= 10 MHz. It programs the CCPl module in Compare
mode to create a square wave with a period of 40 ms on the CCPl pin continuously. The square wave has a 50% duty cycle, which means it is high 50% of each
period. This is an example of how Timerl is used in compare mode. See Figure
15-8. Because the timer uses the Fosc/4, we have 112.5 MHz = 0.4 ~s for the clock.
A 40 ms period gives us 20 ms for high and low portions ofthe square wave. Now
20 ms I 0.4 ~s = 50,000 or C350 in hex. This is the value we load into
CCPRIH:CCPRIL for the Compare mode.
PIC18452/458 has Fosc
576
I
RD16
RD16
I
I
T1CKPS1
I
I
T1CKPSO TlOSCEN
I
T1SYNC
I TMR1CS ITMRlON I
D7
16-bit read/write enable bit
I ~ Timer! 16-bit is accessible in one 16-bit operation.
o ~ Timer I 16-bit is accessible in two 8-bit operations.
06
Not used
TlCKPS2:TlCKPSO 0504 Timer! prescaler selector
o 0 ~ I: I
Prescale value
o I ~ 1:2 Prescale value
I 0 ~ 1:4
Prescale value
I I ~ 1:8
Prescale value
TlOSCEN
03
Timer! oscillator enable bit
I ~ Timer! oscillator is enabled
o ~ Timer! oscillator is shut off
TlSYNC
02
Timer! synchronization (used only when TMRI CS
counter mode to synchronize external clock input)
If TMRI CS ~ 0, this bit is not used.
TMRICS
01
Timer! clock source select bit
I ~ External clock from pin Rcorr 1CKI
o ~ Internal clock (Fosc/4 from XTAL)
TMRION
DO
Timer! ON and OFF control bit
I ~ Enable (start) Timer I
o ~ Stop Timer I
~
1 for
Figure 15-8. nCON (Timer 1 Control) Register
Program 15-2 creates a square wave with a 40 ms period and 50% duty
cycle on CCPI pin using the Compare mode.
;Program 15-2
MOVLW Ox02
MOVWF CCPICON ;Compare mode, toggle upon match
MOVLW OxO
MOVWF T3CON
;use Timerl for Compare mode
MOVLW OxO
MOVWF TICON
;Timerl, internal CLK, 1:1 prescale
BCF
TRISC,CCPl
;CCPl pin as output
MOVLW OxC3
MOVWF CCPRIH
;CCPRIH = OxC3
MOVLW Ox50
CHAPTER 15: CCP AND ECCP PROGRAMMING
577
MOVWF CCPR1L
;CCPR1L = Ox50
OVER CLRF TMR1H
;clear TMR1H
;clear TMR1L
CLRF TMR1L
PIR1, CCPlIF
;clear CCPlIF
BCF
BSF
T1CON,TMR1ON ;start Timerl
Bl
BTFSS PIR1, CCPlIF
BRA
Bl
;CCP toggles CCPl pin upon match
T1CON,TMR1ON ;stop Timerl
BCF
GOTO OVER
;keep doing it
//Program 15-2C is the C version of Program 15-2.
CCP1CON=Ox02;
//compare mode, toggle upon match
T3CON=OxO;
//Timer1 for Compare, 1:1 prescaler
T1CON=OxO;
//Timer1 internal clk, 1:1 prescaler
TRISCbits.TRISC2=O; //make CCP1 pin an output
TRISCbits.TRISCO=l; //make T1CLK pin an input
CCPR1H=OxC3;
//load CCPR1H
CCPR1L=Ox50;
//load CCPR1L
while (1)
{
TMR1H=O;
//clear Timer1
TMRIL=O;
PIRlbits.CCP1IF=O;
//clear CCP1IF flag
T1CONbits.TMR10N=1;
//turn on Timer1
while (PIR1bits.CCP1IF==O) ;
//wait for CCP1IF
//CCP toggles CCP1 pin upon match
T1CONbits.TMR10N=O;
//stop Timer1
Review Questions
1. True or false. We can use any timers we want for the Compare mode.
2. True or false. There is a single pin associated with the Compare mode.
3. True or false. In Compare mode, the CCP pin must be configured as an input
pm.
4. Which register is used to choose the timer for the Compare mode?
578
SECTION 15.3: CAPTURE MODE PROGRAMMING
We select Capture mode with the bit selection in the CCP I CON register. In
Capture mode, an event at the CCP pin will cause the contents of the Timer I (or
Timer3) register to be loaded into the 16-bit CCPRIH:CCPRIL register. That
means, for the Capture mode to work, the CCP pin must be configured as an input
pin. The event that causes the contents of Timer! (or Timer 3) to be captured into
the CCPRIH:CCPRIL register can be a High-to-Low (falling-edge) pulse or Lowto-High (rising-edge) pulse. As far as the edge-triggering pulse is concerned, we
have the following four options to choose from:
(a) every falling-edge pulse
(b) every rising-edge pulse
(c) every fourth rising-edge pulse
(d every 16th rising-edge pulse
One of the above options can be chosen by selection bits in the CCPICON
register. See Example 15-2. Notice that for any of the above options to work, the
CCP pin must be configured as an input pin.
Example 15-2
Using Figures 15-1 and 15-4, fmd the following:
(a) The CCPICON register value for Capture mode if we want to capture on the rising
edge of every pulse
(b) The T3CON register value if we want to to use Timer3 for Capture mode of the
CCP I with no prescaler
Solution:
(a) From Figure 15-1, we have 00000101 (binary) or Ox05 for the CCPICON register.
(b) From Figure 15-4, we have 01000010 (binary) or Ox42 for the T3CON register.
One application of Capture mode is measuring the frequency of an incoming pulse. See Program 15-3.
Steps for programming Capture mode
The following steps are used in programming Capture mode for measuring
the period of a pulse:
I. Initialize the CCPICON register for capture.
2. Make the CCPl pin an input pin.
3. Initialize the T3CON register to select Timer! or Timer3.
4. Read the Timerl (or Timer3) register value on the first rising edge and
save it.
5. Read the Timer! (or Timer3) register value on the second rising edge
and save it.
6. Subtract the value in step 4 from the value in step 5.
CHAPTER 15: CCP AND ECCP PROGRAMMING
579
TMR1H
TMR1L
TMR3H
TMR3L
Register Select
(T3ECCP1 :T3CCP1
CCP1
(RC2)
Prescaler
lXI--+!
divide by
1 4 16
CCPR1H
CCPR1L
Figure 15-9. Capture Mode Operation
Measuring the period of a pulse
Program 15-3 shows an example of capture mode. See Figure 15-9. It
measures the period of the pulse fed to the CCP pin. The measurement is in terms
of the number of clock cycles, Tsclk (l/(Fosc/4)). See Figure 15-10.
Fosc 14
Single
Pulse
t
j
Figure 15-10. Measuring Pulse Period in Terms of Fosc/4 Clock Period
For Program 15-3 assume a pulse is being fed to the CCPI pin. Using
Capture mode, this Assembly language program measures the period of the pulse
and puts the results on PORTS and PORTD. The measurement is in terms of the
Fosc/4 clock period. See Figure 15-11.
Jl.fL
PIC18F
452/458
-
PORTS.
CCP1 (RC2)
PORTD ..
~
.
FIgure 15-11. Drawmg for Examples 15-3 and 15-3C.
580
;Program 15-3
MOVLW Ox05
MOVWF CCP1CON
;Capture mode rising edge
MOVLW OxO
MOVWF T3CON
;Timer1 for Capture
MOVLW OxO
MOVWF T1CON
; Timer1 , internal CLK, 1:1 prescale
CLRF
TRISB
;make PORTB output port
CLRF
TRISD
;make PORTD output port
BSF
TRISC,CCP1
;make CCP1 pin an input
MOVLW OxO
MOVWF CCPR1H
; CCPR1H = 0
; CCPR1L = 0
MOVWF CCPR1L
OVER CLRF
TMR1H
;clear TMR1H
CLRF
TMRlL
;clear TMR1L
BCF
PIR1,CCP1IF
;clear CCP1IF
RE 1 BTFSS PIR1, CCPlIF
BRA
RE 1
;stay here for 1st rising edge
BSF
T1CON, TMR10N
istart Timerl
BCF
PIR1,CCP1IF
;clear CCP1IF for next
RE 2 BTFSS PIR1, CCPlIF
BRA
RE 2
;stay here for 2nd rising edge
BCF
T1CON,TMR10N
;stop Timer1
MOVFF TMR1L, PORTB
;put low byte on PORTB
MOVFF TMR1H, PORTD
;put high byte on PORTD
GOTO
OVER
;keep doing it
//program 15-3C is the C version of Program 15-3.
CCP1CON=Ox05;
/ /Capture mode on every rising edge
T3CON=OxO;
//Timer1 for capture
T1CON=OxO;
//Timer1 internal clk, 1:1 prescaler
TRISB=O;
//make PORTB output port
TRISD=O;
//make PORTD output port
TRISCbits.TRISC2=1;
//make CCP1 pin an input
CCPR1L=O;
//CCPR1L
0
CCPR1H=O;
//CCPR1H = 0
while (1)
{
TMR1H=O;
//clear Timer1
TMR1L=O;
PIR1bits.CCP1IF=O;
//clear CCP1IF flag
while (PIR1bits. CCPlIF==O) ;
/ /wait for 1st rising edge
T1CONbits.TMR10N=1;
//start Timer1
PIR1bits.CCP1IF=O;
//clear CCPIF for next edge
while (PIR1bits. CCPlIF==O) ;
/ /wait for 2nd rising edge
T1CONbits.TMR10N=O;
//stop Timer1
PORTB=CCPR1L;
PORTD=CCPR1H;
//display the clock count
}
CHAPTER 15: CCP AND ECCP PROGRAMMING
581
One problem in measuring the period in the above program is the rate of
error due to overhead associated with the program. One way to reduce the effect
of the overhead is to use every fourth or every sixteenth rising edge.
Measuring pulse width
One of the most widely used applications of Capture mode is measuring
the pulse width. A large number of devices measure things such as distance, temperature, and so on, in which the quantity is provided in terms of the pulse width
instead of traditional voltage or current. In these devices, the output is provided in
pulse-width-modulated (PWM) form. In a device with PWM output, the output has
a fixed frequency and the variable duty cycle provides the quantity we are measuring. For example, the MAX6666/6667 temperature sensors from Maxim Corp.
"convert the ambient temperature into a ratiometric PWM output with temperature
information contained in the duty cycle of the output square wave." According to
their data sheets the output is a square wave with a nominal frequency of 35 Hz at
+25°C. The output format is decoded as follows:
Temperature (0C)
= 235 - (400 x tl) 1 t2
(Equation 15-1)
where tl is fixed with a typical value of 10 ms and t2 is modulated by the temperature. In the above formula, T = tl + t2 where T is the period of the pulse, tl is
the high portion ofthe pulse, and t2 is the low portion, as shown in Figure 15-12.
With tl = 10 and t2 = 20 ms, we get temperature = 235 - (400 x 10 ms) 120 ms =
235 - 200 = 35°C. Program 15-4 shows how to measure the duty cycle using
Capture mode.
...-t1 .....
---,II
'----,-----I
..-... t2
--..
Figure 15-12. Duty Cycle for MAX6666176 Temperature Sensor (Maxim
Corp.)
582
;Program 15-4
FLAG EQU Ox10
;f1ag register for steps in detection
DISP EQU OxO
;f1ag for capture complete
RF
EQU Ox1
;f1ag for rising or falling edge
ORG OxOOOO
GOTO MAIN
ORG Ox0008
BTFSC PIR1,CCP1IF
;Is it CCP1?
GOTO CCP ISR
iservice CCPl
RETFIE
;else return
MAIN MOVLW Ox05
MOVWF CCP1CON
;Capture mode rising edge
MOVLW OxO
MOVWF T3CON
;Timer1 for Capture
MOVLW OxO
MOVWF T1CON ;Timerl, internal CLK, 1:1 prescale
CLRF TRISB
;make PORTB output port
CLRF TRISD
;make PORTD output port
BSF
TRISC,CCP1
;make CCP1 pin an input
CLRF CCPR1H
; CCPR1H = 0
CLRF CCPR1L
;CCPR1L = 0
BSF
PIE1,CCPlIE
;enable CCP1 interrupt
BSF INTCON,PEIE
;enable peripheral interrupt
BSF
;enable all interrupts
INTCON,GIE
OVER CLRF TMR1H
;clear TMR1H
CLRF TMR1L
;clear TMR1L
WAIT BTFSS FLAG, DISP
;Is capture complete?
BRA WAIT
;else wait
BCF FLAG,DISP
;clear flag for next capture
MOVLW Ox03
SUBWF TMR1L,F
;subtract the overhead
MOVFF TMR1L,PORTB
;put low byte on PORTB
MOVFF TMR1H,PORTD
;put high byte on PORTD
GO TO OVER
; keep doing it
CCP ISR
BTFSS FLAG,RF
;Is it rising edge?
GOTO RISE ISR
;service rising edge
GOTO FALL ISR
;else service falling edge
RISE ISR
BSF
T1CON, TMR10N
; start Timer1
BSF FLAG,RF
;ready for falling edge
BCF CCP1CON,O
;detect falling edge
BCF PIR1,CCP1IF ;clear interrupt
RETFIE
;return and wait for falling edge
FALL ISR
BCF
T1CON, TMR10N
; stop Timer1
BSF FLAG,DISP
;capture complete
BCF FLAG,RF
;ready for rising edge
BSF CCP1CON,O
;detect rising edge
BCF PIR1, CCPlIF ;clear interrupt
RETFIE
ireturn capture complete
END
CHAPTER IS: CCP AND ECCP PROGRAMMING
583
II Program 15-4C
#include "pI8f458.h"
void CCPl ISR(void);
void rising (void) ;
void falling(void);
unsigned char disp
0;
unsigned char rf ~ 0;
#pragma interrupt chk_isr
void chk_isr (void)
if
(PIRlbits.CCPIIF~~I)
CCPl ISR();
#pragma code My_HiPrio_Int~Ox0008
void My_HiPrio_Int (void)
{
asm
GOTO chk isr
endasm
}
#pragma code
void main()
(
IICapture mode rising edge
IITimerl for Capture
TICON~OxO;
IITimerl, internal CLK, 1:1 pre scale
TR1SB~OxO;
Ilmake PORTB output port
TR1SD~OxO;
Ilmake PORTD output port
TRISCbits.TRISC2~1;
Ilmake CCPl pin an input
CCPRIH~OxO;
I ICCPRIH ~ 0
CCPRIL~OxO;
IICCPRIL ~ 0
PIElbits.CCPIIE~I;
lienable CCPl interrupt
INTCONbits.PEIE~I;
lienable peripheral interrupt
INTCONbits.GIE~I;
lienable all interrupts
CCPICON~Ox05;
T3CON~OxO;
while (1)
{
TMRIH~OxO;
TMRIL~OxO;
while
(disp~~o)
;
disp~O;
TMRIL-~15;
Iisubtract the overhead
PORTB~TMRIL;
Ilput low byte on PORTB
Ilput high byte on PORTD
PORTD~TMRIH;
}
584
Ilclear TMRIH
Ilclear TMRIL
Ills data ready to display?
Ilclear the flag
void CCPl ISR ()
{
if
rising () ;
else falling();
(rf~~O)
void rising ()
{
TICONbits.TMRION~l;
rf~l;
CCPICONbits.CCPIMO~O;
PIRlbits.CCPlIF~O;
//start Timerl
//ready for falling edge
//detect falling edge
//clear interrupt
void falling ()
TICONbits.TMRION~O;
disp~l;
rf~O;
CCPICONbits.CCPIMO~l;
PIRlbits.CCPlIF~O;
//stop Timerl
//capture complete
//ready for rising edge
//detect rising edge
//clear interrupt
}
Notice that in the company's web site for data sheets the output for a given
device is identified as analog (voltage or current) or PWM.
Review Questions
I. True or false. In Capture mode, the CCP pin must be configured as an input
pm.
2. True or false. We can use only Timers 1 and 3 for Capture mode.
3. True or false. The timer's register values are transferred to CCPRIH:CCPRI L
every time the CPU is reset.
4. True or false. After the timer's register values are transferred to
CCPRIH:CCPRIL, the timer's registers are cleared.
5. Which register is used to choose the timer for Capture mode?
CHAPTER 15: CCP AND ECCP PROGRAMMING
585
SECTION 15.4: PWM PROGRAMMING
Another feature ofCCP is pulse width modulation (PWM). The PWM feature allows us to create pulses with variable widths. Although we can program
timers to create PWM, the CCP module makes the programming of PWM much
easier and less tedious. PWM is widely used in industrial controls such as DC
motor controls, as we will see in Chapter 17. Indeed the PWM is so widely used
that Microchip has enhanced the PWM capabilities of the newer generation of the
PIC18 family members and has designated them as ECCP (enhanced CCP). We
will study ECCP in the next section. The main di fference between ECCP and standard CCP is the PWM capability. In creating pulses with variable widths for the
PWM, two factors are important: The period of the pulse and its duty cycle. The
duty cycle (DC) is the portion of the pulse that stays HIGH relative to the entire
period. Very often the DC is stated in the form of percentages. For example, a
pulse with a 4 ms period that stays HIGH for 1 ms has DC of25% (1 ms 14 ms =
25%), as shown in Figure 15-13.
25% DC
50% DC
75% DC
100% DC
J
Figure 15-13. Period and Duty Cycle
The period of PWM
The CCP module uses Timer2 and its associated register, PR2, for the
PWM time-base, which means that the frequency of the PWM is a fraction of the
Fosc, the crystal frequency. It uses the PR2 register to set the PWM period as follows:
Tpwm = [(PR2) + 1 ] 4 x N x Tosc
(Equ. 15-2)
where Tosc is the inverse of lIFosc, the crystal frequency, Tpwm is the
desired PWM period, and N is the prescaler of 1, 4, or 16 set by the Timer2 control register (T2CON). Therefore, we can get the value for the PR2 register as follows:
(Equ. 15-3)
PR2 = [Fosc 1 (Fpwm x 4 x N)]- 1
From Equation 15-2, we can conclude that the maximum value for Tpwm
can be achieved when N = 16 and PR2 = 255. Therefore, we have:
Tpwm = [(255) + 1 ] x 4 x 16 x Tosc = 16,382 Tosc
which means that the minimum allowed Fpwm = Fosc/16,382.
586
Examine Examples 15-3 to 15-5 to see the calculation of the PWM period.
Example 15-3
Find the PR2 value and the prescaler needed to get the following PWM frequencies.
Assume XTAL = 20 MHz.
(a) 1.22 kHz, (b) 4.88 kHz, (c) 78.125 kHz
Solution:
(a) PR2 value = [(20 MHz / (4 x 1.22 kHz)]- 1 = 4,097, which is larger than 255, the
maximum value allowed for the PR2. Now choosing the prescaler of 16 we get
PR2 value = [(20 MHz / (4 x 1.22 kHz x 16)]- 1 = 255
(b) PR2 value = [(20 MHz / (4 x 4.88 kHz)] - 1 = 1,023, which is larger than 255, the
maximum value allowed for the PR2. Now choosing the prescaler of 4 we get
PR2 value = [(20 MHz / (4 x 4.88 kHz x 4)]- I = 255
(c) PR2 value
= [(20 MHz / (4 x 78.125 kHz)]- I = 63
Example 15-4
Find the PR2 value for the following PWM frequencies. Assume XTAL = 10 MHz and
prescaler = 1.
(a) 10kHz, (b) 25 kHz
Solution:
(b) PR2 value = [(10 MHz / (4 x 10 kHz x 1)]- I = 250 - I = 249
(c) PR2 value = [(10 MHz / 4 x 25 kHz xl) - I = 100 - 1 = 99
Example 15-5
Find the minimum and maximum Fpwm frequency allowed for XTAL = 10 MHz. State
the PR2 and prescaler values for the minimum and maximum Fpwm.
Solution:
We get the minimum Fpwm by making PR2
10 MHz / (4 x 16 x 256) = 610 Hz.
=
255 and prescaler = 16, which gives us
We get the maximum Fpwm by making PR2 = 1 and prescaler = I, which gives us 10
MHz / (4 x I x I) = 2.5 MHz.
CHAPTER 15: CCP AND ECCP PROGRAMMING
587
The duty cycle of PWM
As stated earlier, the duty cycle of PWM is the portion of the pulse that
stays HIGH relative to the entire period. To set the duty cycle, the CCP module
uses the 10-bit register of DCIB9:DCIBO. The IO-bit register ofDCIB9:DCIB0
is formed from 8 bits ofCCPRIL and 2 bits from the CCPICON register, where
CCPRIL is the upper 8 bits and DCIB2:DCIBI of the CCPICON are the lower 2
bits of the IO-bit register. In reality, CCPRLl is the main register for the duty cycle
and the lower 2 bits of DCIB2:DCIBI are for the decimal point portion of the
duty cycle and are set as follows:
DCIB2
0
0
I
1
DCIBI
0
1
0
1
Decimal points
0
0.25
0.5
075
It must be noted that the value for the duty cycle register of the CCPRIL
is always some percentage of the PR2 register. For example, if PR2 = 50, and we
need a 20% duty cycle, then CCPRLI = 10 because 20% x 50 = 10. In this case,
DCIDB2:DCIB1 = 00. Now assume that we want a 25% duty cycle for the same
PR2. Because 50 x 25% = 12.5, we make CCPRLl = 12 and DCIB2:DCIBI = 10
to take care of the 0.5 part. See Example 15-6 for further clarification.
Example 15-6
Find the values of registers PR2, CCP I RL, and DC IB2:DC IB 1 for the following PWM
frequencies if we want a 75% duty cycle. Assume XTAL = 10 MHz.
(a) 1 kHz b) 2.5 kHz
Solution:
(a)
Using the PR2 = Fosc / (4 x Fpwm x N) equation, we must set N = 16 for prescale.
Therefore, we have
PR2 = [(10 MHz / (4 x 1 kHz x 16)]- 1 = 156 - 1 = 155 and because 155 x 75% =
116.25 we have CCPRIL = 116 and DCIB2:DCIBI = 01 for the 0.25 portion.
(b)
Using the PR2 = Fosc / (4 x Fpwm x N) equation, we can set N = 4 for prescale.
Therefore, we have
PR2 = [(10 MHz / (4 x 2.5 kHz x 4)]- 1 = 250 - 1 = 249 and because 249 x 75% =
186.75 we have CCPRIL = 186 and DCIB2:DCIBI = 11 for the 0.75 portion.
588
ITOUTPs311 TOUTPs211 TOUTPS 111 TOUTPSO I TMR20N IT2CKPS 1 IT2CKPSO I
DO
06
Not used
D7
TOUTPS3:TOUTPSO 06-03
00 0 0 ~ 1: I
00 0 I ~ 1:2
00 I 0 ~ 1:3
00 1 1 ~ 1:4
II I 0
II I I
TMR20N
~
~
I: 15
I: 16
Timer 2 Output Postscale Select bits
Postscale value
Postscale value
Postscale value
Postscale value
Postscale value
Postscale value
02
Timer 2 ON and OFF Control bit
I ~ Enable (start) Timer2
o ~ Stop Timer2
T2CKPSl:T2CKPSO 01-00 Timer2 Clock Prescale Select bits
o 0 ~ Pre scale is 1.
o I ~ Pre scale is 4.
I x ~ Prescale is 16.
Figure 15-14. nCON (Timer2 Control) Register
I
TMR2IF
ITMR2IF I TMRIIF I
Timer 2 Interrupt overflow Flag bit
o ~ TMR2 value is not equal to PR2 register.
I
~
TMR2 value is equal to PR2 register.
The location of the TMRxIF in the PIR register can vary in future products.
Figure 15-15. PIRI (Peripheral Interrupt Flag Register 1) Has the TMR2IF Flag
Steps in programming PWM
The following steps are taken to program the PWM feature of the CCP
module:
I.
2.
3.
4.
5.
6.
Set the PWM period by writing to the PR2 register.
Set the PWM duty cycle by writing to CCPRI L for the higher 8 bits.
Set the CCP pin as an output.
Using the T2CON register. set the pre scale value. See Figure 15-14.
Clear the TMR2 register.
Configure the CCPICON register for PWM and set DCIB2:DCIBI
bits for the decimal portion of the duty cycle.
7. Start Timer2.
Examine Programs 15-5 and 15-5C to see how the PWM feature is programmed. These programs use the TMR2IF flag. See Figure 15-15.
CHAPTER 15: CCP AND ECCP PROGRAMMING
589
Using data from Example 15-6, Program 15-5 will create a 2.5 kHz PWM
frequency with a 75% duty cycle on the CCPI pin.
;Program lS-S
;clear CCPICON reg
CLRF
CCPICON
MOVLW D'249'
MOVWF PR2
;7S% duty cycle
MOVLW D' 186'
MOVWF CCPRlL
;make PWM pin an output
BCF
TRISC,CCPl
jTimer2, 4 prescale, no postscaler
MOVLW OxOl
MOVWF T2CON
;PWM mode, 11 for DCIBl:BO
MOVLW Ox3C
MOVWF CCPICON
;clear Timer2
TMR2
CLRF
BSF
T2CON,TMR20N
;turn on Timer2
AGAIN BCF PIRl,TMR2IF
;clear Timer2 flag
OVER BTFSS PIRl, TMR2 IF
;wait for end of period
BRA
OVER
; continue
GOTO
AGAIN
//program IS-SC is the C version of Program IS-S.
CCPICON=O;
//clear CCPICON reg
PR2=249;
//7S% duty cycle
CCPRIL=186;
TRISCbits.TRISC2=O;
//make PWM pin an output
//Timer2, 4 prescale, no postscaler
T2CON=OxOl;
//PWM mode, 11 for DCIBl:BO
CCPICON=Ox3C;
//clear Timer2
TMR2=O;
//turn on Timer2
T2CONbits.TMR20N=1;
while (1)
{
PIRlbits.TMR2IF=O;
//clear Timer2 flag
while (PIRlbits.TMR2IF==O) ; //wait for end of period
The role of CCPR I H in the process of creating the duty cycle must be
noted. A copy of the duty cycle value in register CCPRIL is given to CCPRIH as
soon as we start Timer2. Timer2 goes through the following stages in creating the
PWM:
(a) The CCPRIL is loaded into CCPRIH and the CCPI pin goes HIGH to
start the beginning of the period.
(b) As TMR2 counts up, the TMR2 value is compared with both the
CCPRIH and PR2 registers.
(c) When the TMR2 and CCPRIH (which is the same as CCPRIL) values
are equal, the CCP pin is forced low. That ends the duty cycle portion of the
period.
(d) The TMR2 keeps counting up until its value matches the PR2. At that
point, the CCP pin goes high, indicating the end of one period and the beginning
590
First CCPR 1L, then PR2
CCP1
'--_ _ _..J-~)(I (RC2)
Figure 15-16. TMR2 and PR2 Role in Creating the Duty Cycle
Period
(PR2)
I
I
I
~~:-----1.~L-_;',
Duty Cycle
,ITMR2; PR2
CCPR1L
Figure 15-17. TMR2 Relation to CCPRIL and PR2 in PWM
of the next one. It also clears Timer2 for the next round. The CCPRIL is loaded
into CCPRIH, and the process continues. See Figures 15-16 and 15-17.
Notice that because the CCPRIL is a fraction of PR2, Timer2 matches
CCPRIL first before it matches PR2, unless we have a 100% duty cycle. In that
case, Timer2 matches both CCPRIL and PR2 at same time because they have
equal values for the 100% duty cycle.
Duty cycle and Fosc
The PIC 18 datasheet gives the relation between the Fosc and duty cycle
period as follows:
Tdutycycle = (DCIB9:DCIBO value) x Tosc x N
(Equ. 15-4)
where Tosc = I / F osc and N is the prescaler of I, 4, or 16 set by the Timer2
control register. To get the value for the DCIB9:DCIBO register, we can rearrange
the above equation as follows:
DCIB9:DCIBO
=
[(Fosc / ( Fdutycycle x N) 1
(Equ. 15-5)
To calculate the the maximum resolution (number of bits) that can be used
for the PWM, the PIC manual gives the following equation:
Maximum PWM Resolution (bits) = log(Fosc / Fpwm) / log(2) bits.
Notice that the maximum resolution is 10 bits.
CHAPTER 15: CCP AND ECCP PROGRAMMING
591
Review Questions
I.
2.
3.
4.
5.
6.
True or false. Every standard CCP module has only one PWM pin.
How many standard CCP modules do we have in the PIC18F458/4580?
True or false. For CCP I, we must use PR2 to set the PWM period.
True or false. For CCPI, we must use CCPRIL to set the PWM duty cycle.
Which pin of the PIC I 8F458/4580 is used for PWM?
True or false. The duty cycle is always a fraction of the period, unless we want
a 100% duty cycle.
SECTION 15.5: ECCP PROGRAMMING
A large number of the PICI8F family members come with ECCP
(enhanced CCP) in addition to the standard CCP. While the standard CCP modules
are called CCP I, CCP2, and so on, the ECCP modules are designated as ECCP I,
ECCP2, and so on. Just like standard CCP, the ECCP has its own pins and registers. The PIC I 8F452/458 chip uses pin RD4 (PORTD.4) for the ECCPI pin, while
pin RC2 (PORTC.2) is used by the standard CCP I. See Figure 15-18. Figure 1519 shows the ECCP! control register.
:t==
MCLRNPP _.
RAO/ANO/CVREF
2
RA1/AN1
RB7/PGD
39
RB6/PGC
3
38'
RB5/PGM
RA2/AN2NREF-
4
37
RB4
RA3/AN3NREF+
5
36
RB3/CANRX
RA4fTOCKI - - , 6
35
RB2/CANTX/INT2
7
34
RB111NT1
33
RBO/INTO
RA5/AN4/SS/LVDIN
REO/AN5/RD
8
RE1/AN6IWR/C10UT
9
32
VDD
RE2/AN7/CS/C20UT
10
31
VSS
11
30
RD7/PSP7/P1D
12
29
RD6/PSP6/P1 C
13
28
RD5/PSP5/P1 B
14
27
RD4/PSP4/ECCP/P1A
15
26
RC7/RX/DT
RC11T1OS1 - - ' 16
25
RC6ITX/CK
RC2/CCP1 _ _ 17
24 ! - - RC5/SDO
VDD
~-~
VSS
OSC1/CLKI
OSC2/CLKO/RA6 _.
RCOIT1 OSO/T1 CKI
PIC18F458
RC3/SCK/SCL
18
RDO/PSPO/C 11N+
19
" ~ ''''''''''''
22
RD3/PSP3/C2IN-
20
21
RD2/PSP2/C2IN+
RDlIPSP1/C1IN-
Figure 15-18. ECCP Pins for PWM in PIC18F458/4580 (452/4520)
592
jEPWMIMljj EPWMIMO jEOClBljjEOCIBOj
j
D7
j
jECCPIM3jj ECCPIM21 ECCPIMlj ECCPIMO
I
DO
EPWMIMl:EPWMlMO PWM output pin configuration. It allows the use of a single
pin for the capture/compare mode, or four pins for the PWM.
In compare/capture mode, only pin PIA (R04) is used. In that case, there is no selection for these two bits.
In PWM mode, the options for these two bits are as follows:
00
oI
10
01
P I A is used for a modulated output. PI B, PIC, and PI 0 are used as 110.
Full-Bridge output forward. PI D modulated. PI A active. PIB and PI C inactive.
Halt~Bridge output. PIA and PI 0 modulated with deadband control, PIC and
PID used as 110.
Full-Bridge output reverse. PIB modulated, PIC active. PIA and PIO inactive.
EDCIBIO:EDCIBI PWM Duty Cycle least-significant bits. Used in PWM only.
The least-significant bits (Bit I and Bit 0) of the 10-bit duty cycle register are
used in PWM. The ECCPR I L register is used as Bit 2 to Bit 9 of the 10-bit
duty cycle register.
ECCPIM3-ECCIMO ECCPI Mode Select
o 0 0 0 ECCP I is off
0001
Reserved
Compare Mode. Toggle ECCP I output pin on match.
0010
(ECCPlIF bit is set.)
001 I
Reserved
01 00
oI 0 I
oI I 0
oI I I
I 000
100 I
101 0
101 I
1 I 00
I I 0 I
I I 10
I I I I
Capture
Capture
Capture
Capture
Mode,
Mode,
Mode,
Mode,
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
Compare Mode. Initialize ECCPI pin LOW, on compare
match, force CCP1 pin HIGH. (ECCPIIF is set.)
Compare Mode. Initialize CCPI pin HIGH, on compare match,
force CCPI pin LOW. (ECCPlIF is set.)
Compare Mode. Generate software interrupt on compare match.
(ECCPIIF bit is set, ECCPI pin is unaffected.)
Compare Mode. Trigger special event (ECCPIIF bit is set, and
Timer! or Timer3 is reset to zero.)
PWM
PWM
PWM
PWM
Mode;
Mode;
Mode;
Mode;
PIA,
PIA,
PIA,
PIA,
PIC
PIC
PIC
PIC
active-HIGH; PI B and PI D active-HIGH
active-HIGH; PIB and PID active-LOW
active-LOW; PIB and PID active-HIGH
active-LOW; PIB and PID active-LOW
Figure 15-19. ECCPl Control Register. (This register selects one ofthe operation modes of Capture, Compare, or PWM of EECPt.)
CHAPTER 15: CCP AND ECCP PROGRAMMING
593
The ECCPl also has the registers of ECCPRIL, ECCPRIH, and ECCPCONI. Register PIR2 has the ECCPlIF flag. See Figures 15-20 and 15-21. Just
like the standard CCP, it uses Timer 1, Timer2, and Timer3 to program the features
of compare-capture and PWM. See Table 15-3.
I
II
ECCPRlH
ECCPRIL
I
lOIS 10141013 1012 lOll IDIO I 09 108 11 07 106 1 D5 104 1 03 102 1 01 1DO I
Figure 15-20. ECCP High and Low Registers
D
I ECCPlIFJ
ECCPlIF ECCPlIF Interrupt Flag bit.
Compare Mode
o ~ Timer! (or Timer3) match did not occur
I ~ Timer! (or Timer3) match occurred (must be cleared by software)
Capture Mode
o~ Timer! ( or Timer3) register capture did not occur
I ~ Timer! (or Timer3) register capture occurred (must be cleared by software)
Figure 15-21. PIR2 (Peripheral Interrupt Flag Register 2) Contains the
ECCPlIF Flag
Table 15-3: PIC1S Use of Timers for ECCP1
ECCPmode
Capture
Compare
PWM
Timer
Timer! or Timer3
Timer! or Timer3
Timer2
Steps for programming the Compare mode in ECCP
Programming the ECCP 1 in compare mode is identical to the standard
CCP, except we use the ECCP registers. The following steps are taken in programming the Compare mode for ECCP1:
1.
2.
3.
4.
5.
6.
7.
594
Initialize the ECCP 1CON register for the compare option.
Initialize the T3CON register for Timer! (or Timer3).
Initialize the ECCPRIH:ECCPRIL registers.
Make the ECCPl pin an output pin.
Initialize the Timer! (or Timer3) register values.
Start Timerl (or Timer3).
Monitor the ECCPlIF flag (or use an interrupt).
Program 15-6 shows an example of the Compare mode. It uses Timer3 as
a counter and counts the number of pulses fed to Timer3. When the count reaches
20, it toggles the LED connected to the ECCPI pin.
For Program 15-6 assume that a I-Hz pulse is connected to the Timer3 pin
and an LED is connected to the CCPI pin. Timer3 is being used as a counter.
Using the Compare mode, this Assembly language program will toggle the LED
every 20 pulses.
;Program 15-6
MOVLW Ox02
MOVWF ECCPICON ; Compare mode, toggle upon match
MOVLW Ox42
MOVWF T3CON
i Timer3 for Compare, 1:1 prescaler
BCF
TRISD,ECCPl
;ECCP pin as output
BSF
TRISC,TICKI
;T3CLK pin as input pin
MOVLW D'20'
MOVWF ECCPRIL
;ECCPRIL
20
MOVLW OxO
;ECCPRIH
0
MOVWF ECCPRIH
OVERCLRF
TMR3H
iclear TMR3H
CLRF
TMR3L
;clear TMR3L
BCF
PIR2,ECCPlIF
;clear ECCPlIF
jstart Timer3
BSF
T3CON,TMR30N
Bl
BTFSS PIR2, ECCPlIF
BRA
Bl
;---------CCP toggle CCP pin upon match
B2
BCF
T3CON, TMR30N
; stop Timer3
GOTO
OVER
; keep doing it
//Program 15-6C is the C version of Program 15-6.
ECCPICON=Ox02;
//Compare mode, toggle upon match
T3CON=Ox42;
//Timer3 for Compare, 1:1 prescaler
TRISDbits.TRISD4=0;
//make ECCPl pin an output
TRISCbits.TRISCO=l;
//make T3CLK pin an input
ECCPRIL=20;
//load ECCPRIL
//load ECCPRIH
ECCPR1H=0;
while (1)
{
TMR3H=0;
TMR3L=0;
PIR2bits.ECCPIIF=0;
//clear ECCPIIF flag
T3CONbits.TMR30N=1;
//turn on Timer3
while (PIR2bits.ECCPIIF==0) ;
//wait for CECPIIF
//ECCP toggles ECCP pin upon match
T3CONbits.TMR30N=0;
//stop Timer3
}
CHAPTER 15: CCP AND ECCP PROGRAMMING
595
Steps for programming the Capture mode in ECCP
Programming the ECCP I in capture mode is identical to the standard CCP,
except that we use the ECCP registers. The following steps are taken in programming the Capture mode of ECCP I for measuring the period of a pulse:
I.
2.
3.
4.
Initialize the ECCPICON register for the Capture option.
Make the ECCPI pin an input pin.
Initialize the T3CON register to select Timer! or Timer3.
Read the Timer! (or Timer3) register value on the first rising edge and
save it.
5. Read the Timerl (or Timer3) register value on the second rising edge
and save it.
6. Subtract the value in step 4 from the value in step 3.
For Program 15-7 assume that a pulse is being fed to the ECCPI pin. Using
the Capture mode, this Assembly language program measures the period of the
pulse and puts it on PORTB and PORTC. The measure is in terms of the Fosc/4
clock period.
;Program 15-7
MOVLW Ox05
MOVWF ECCP1CON
;Capture mode on rising edge
MOVLW OxO
MOVWF T3CON
;Timer1 for capture
MOVLW OxO
;Timer1, internal clk, 1:1 prescale
MOVWF T1CON
CLRF
TRISB
;make PORTB output port
;make PORTC output port
CLRF
TRISC
;make ECCP1 pin an input
TRISD,ECCP1
BSF
MOVLW OxO
MOVWF CCPR1H
;ECCPR1H = 0
MOVWF CCPR1L
;ECCPR1L = 0
;clear TMR1H
OVER CLRF
TMR1H
;clear TMR1L
CLRF
TMR1L
BCF
PIR2,ECCP1IF
;clear ECCP1IF
RE 1 BTFSS PIR2, ECCPlIF
;stay here for 1st rising edge
BRA
RE 1
BSF
T1CON,TMR10N
istart Timerl
;clear ECCP1IF for next
BCF
PIR2,ECCP1IF
RE 2 BTFSS PIR2, ECCPlIF
;stay here for 2nd rising edge
BRA
RE 2
BCF
T1CON,TMR10N
; stop Timer1
MOVFF TMR1L,PORTC
;put low byte on PORTC
;put high byte on PORTD
MOVFF TMR1H, PORTD
; keep doing it
GOTO
OVER
((Program 15-7C is the C version of Program 15-7.
ECCP1CON=Ox05;
((Capture mode on every rising edge
596
T3CON=OxO;
//Timer1 for capture
//Timer1, internal clk, 1:1 prescaler
T1CON=OxO;
//make PORTB output port
TRISC=O;
//make PORTD output port
TRISD=O;
//make ECCP1 pin an input
TRISDbits.TRISD4=1;
ECCPR1L=O;
/ /ECCPR1L
0
//ECCPR1H = 0
ECCPR1H=O;
while (1)
(
//clear Timer1
TMR1H=O;
TMR1L=O;
PIR2bits.ECCP1IF=O;
//clear ECCP1IF flag
while (PIR2bits.ECCP1IF==O) ; //wait for 1st rising edge
T1CONbits.TMR10N=1;
//start Timer1
PIR2bits.ECCP1IF=O;
//clear ECCPIF for next edge
while (PIR2bits.ECCP1IF==O) ; //wait for 2nd rising edge
T1CONbits.TMR10N=O;
//stop Timer1
PORTC=CCPR1L;
//display the clock count
PORTD=CCPR1H;
}
PWM features of ECCP
The main difference between the ECCP and standard CCP module is the
PWM capability. The standard CCP allows only a single pin for PWM output. This
is not enough for implementation of the H-Bridge used widely in DC motor control. As we will see in Chapter 17, we need four pins to drive the H-Bridge for DC
motor control. The ECCP allows the use of four pins for the implementation of
Full-Bridge or two pins for the Half-Bridge. The four pins used by the ECCP are
shown in Table 15-4. In terms ofthe duty cycle calculation, ECCPI is the same as
CCP I. It uses the PR2 for the duty cycle.
Table 15-4: PIC18 UsaGe of Pins for ECCPl
ECCPmode
RD4
RD5
RD6
1/0
1/0
ECCPI
ComQare/CaQture
Dual OutQut PWM
PIA
PIB
I/O
PIB
PIC
PIA
Quad OutQut PWM
Note: 1/0 means they are used for input/output purpose or other functions
ated with the pins.
RD7
1/0
I/O
PID
associ-
Steps in programming PWM of ECCP
The following steps are taken to program the PWM feature of the ECCP
module:
I. Set the PWM period by writing to the PR2 register.
2. Set the PWM duty cycle by writing to ECCPRI L for the higher 8 bits.
CHAPTER 15: CCP AND ECCP PROGRAMMING
597
3.
4.
5.
6.
Set the ECCP pins as output.
Using the T2CON register, set the prescale value.
Clear the TMR2 register.
Configure the ECCPICON register for PWM and set the
EDCIB2:EDCIBI bits for the decimal portion of the duty cycle.
7. Start Timer2.
Notice that in programming the compare/capture features, we can assign
Timerl to standard CCPI and Timer3 to ECCPI (or vice versa). For the PWM,
however, there is only one register for setting the duty cycle. As a result, if we program the PWM feature for both CCPI and ECCPI, then they will have the same
period because there is only one PR2 to set the period. In Chapter 17 we will show
how to use ECCP for DC motor control using all four pins in H-Bridge implementations.
Review Questions
I.
2.
3.
4.
5.
True or false. Every ECCP module can use only one pin for PWM.
How many ECCP modules does the PICI8F458/4580 have?
True or false. For ECCPI, we must use PR2 to set the PWM period.
True or false. For ECCPI, we must use CCPRIL to set the PWM duty cycle.
Which pins of the PIC I 8F458/4580 are used for PWM?
SUMMARY
This chapter began by describing the CCP features of the PICI8 family. We
discussed both the standard CCP and enhanced CCP (ECCP) modules and
described each of the compare, capture, and PWM features. We showed how to use
Timer! or Timer3 as the time basis for the compare and capture modes. We also
showed how PWM uses Timer2 to create the pulse width modulation.
PROBLEMS
SECTION 15.1: STANDARD AND ENHANCED CCP MODULES
True or false. Every member of the PIC 18 family has an on-chip CCP module.
True or false. The PIC 18F452/458 has only one standard CCP.
True or false. The PICI8F452/458 has only one ECCP module.
True or false. Each CCP module has a 16-bit register accessible as CCPRL and
CCPRH.
5. True or false. Each CCP module has a single pin.
6. Give the number of standard and enhanced CCP (ECCP) modules in the
I.
2.
3.
4.
PIC18F4520/4580.
7. Give the pin used for standard CCP in the 40-pin DIP package of the
PIC 18F458/4580.
598
SECTION IS.2: COMPARE MODE PROGRAMMING
8. True or false. We use register CCPICON to choose the Compare mode.
9. True or false. We can use TimerO and Timer2 for Compare mode.
10. True or false. To use Compare mode, we must make the CCP pin an output pin.
II. Which timers can be used for the Compare mode?
12. Assuming that we are using Timer! for the Compare mode, indicate when the
CCP pin is driven HIGH.
13. Which register holds the CCP flag bit?
14. Find the value for the CCPICON register in compare mode if we want to drive
HIGH the CCP pin upon match.
IS. Find the value for the CCP I CON register in compare mode if we want to drive
LOW the CCP pin upon match.
16. Find the value for the CCPICON register in compare mode if we want to toggle the CCP pin upon match.
17. Rewrite Program IS-I (or IS-IC) for Timerl.
18. Rewrite Program IS-I (or IS-IC) for the count of 1000.
19. Rewrite Program IS-2 (or IS-2C) for Timer3.
20. Rewrite Program IS-2 (or IS-2C) to create a square wave with a frequency of
100 Hz.
SECTION IS.3: CAPTURE MODE PROGRAMMING
True or false. We use the CCPI CON register to choose the Capture mode.
True or false. We can use TimerO and Timer2 for Capture mode.
True or false. To use Capture mode, we must make the CCP pin an output pin.
Which timers can be used for the capture mode?
Find the value for the CCPICON register in capture mode if we want to capture on the falling edge.
26. Find the value for the CCPICON register in capture mode if we want to capture every fourth rising edge.
27. Find the value for the T3CON register if we want to use Timer! for capture
mode.
28. Rewrite Program IS-3 (or IS-3C) for Timer3.
21.
22.
23.
24.
2S.
SECTION IS.4: PWM PROGRAMMING
29. True or false. We use the CCPICON register to choose the PWM mode.
30. True or false. We can use TimerO and Timer! for the PWM mode.
31. True or false. To use PWM mode, we must make the CCP pin an output pin.
32. Which timer can be used for PWM mode for the standard CCPI?
33. Find the value for the CCPICON register for PWM mode.
34. Of the CCPRIL and CCPRIH registers, which one is used to set the duty
cycle?
3S. Which register holds the DCIB2:DCIBI bits?
36. What is the role of the DCIB2:DCIBI bits in creating the duty cycle?
37. What is the value for the DCIB2:DCIBI bits if we want 0.7S for the decimal
CHAPTER 15: CCP AND ECCP PROGRAMMING
599
points part of the duty cycle?
38. In programming the PWM, the value loaded into the CCPRLl is always a
_ _ _ _ _ _ _ (fraction, multiple) of the PR2 value.
39. Find the values of registers PR2, CCPIRL, and DCBIB2:DClBI bits for the
PWM frequency of2 kHz with 25% duty cycle. Assume XTAL = 10 MHz.
40. Find the values of registers PR2, CCPlRL, and DCBlB2:DClBl bits for the
PWM frequency of 1.8 kHz with duty cycle of25%. Assume XTAL = 10 MHz.
41. Find the values of registers PR2, CCPIRL, and DCBIB2:DClBl bits or the
PWM frequency of 1.5 kHz with duty cycle of25%. Assume XTAL = 10 MHz.
42. Find the values of registers PR2, CCPlRL, and DCBlB2:DCIBI bits for the
PWM frequency of 1.2 kHz with duty cycle of25%. Assume XTAL = 10 MHz.
SECTION 15.5: ECCP PROGRAMMING
True or false. We use ECCPICON to choose the PWM mode.
True or false. We can use Timer! or Timer3 for the PWM mode in ECCP.
True or false. To use capture mode, we must make the ECCP pin an output pin.
Which timer can be used for the PWM mode for ECCPl?
Which register holds the ECCPlIF flag bit?
Find the value for the ECCPI CON register in compare mode if we want to
drive HIGH the ECCP pin upon match.
49. In the PIC 18F452/458, give the pin used for ECCP for compare/capture mode.
50. Which timers can be used for the compare mode in ECCP?
51. Which pins are used for PWM in ECCPI?
52. Find the value for the ECCPlCON register in compare mode if we want to
drive HIGH the ECCP pin upon match.
53. Find the value for the ECCPlCON register in PWM mode if we want to have
H-Bridge where PIA and PIC are active high and the rest are active low.
54. Of the ECCPRlL and ECCPRIH registers, which one is used to set the duty
cycle?
55. Which register holds the EDCIB2:EDCIBI bits?
56. What is role of the EDClB2:EDCIBl bits in creating duty cycle?
57. What is value for the EDClB2:EDClBI bits if we want 0.5 for the decimal
points part of the duty cycle?
58. In programming the PWM, the value loaded into ECCPRLl is always a
_ _,--_ _ _ _ (fraction, multiple) of the PR2 value.
59. Find the values of registers PR2, ECCPlRL, and EDCBlB2:EDCIBl bits for
the PWM frequency of2 kHz with 25% duty cycle. Assume XTAL = 10 MHz.
60. Find the values of registers PR2, ECCPlRL, and EDCBIB2:DClBl bits for
the PWM frequency of 1.8 kHz with duty cycle of 25%. Assume XTAL =
10 MHz.
61. Find the values of registers PR2, ECCPlRL, and EDCBlB2:DCIBI bits for
the PWM frequency of 1.5 kHz with duty cycle of 25%. Assume XTAL =
10 MHz.
62. Find the values of registers PR2, ECCPlRL, and EDCBIB2:DCI BI bits for
the PWM frequency of 1.2 kHz with duty cycle of 25%. Assume XTAL =
10 MHz.
43.
44.
45.
46.
47.
48.
600
ANSWERS TO REVIEW QUESTIONS
SECTION 15.1: STANDARD AND ENHANCED CCP MODULES
1.
2.
3.
4.
True
True
True
RC2 (PORTC.2)
SECTION 15.2: COMPARE MODE PROGRAMMING
1.
2.
3.
4.
False
True
True
T3CON
SECTION 15.3: CAPTURE MODE PROGRAMMING
1.
2.
3.
4.
5.
True
True
False
False
T3CON
SECTION 15.4: PWM PROGRAMMING
1.
2.
3.
4.
5.
6.
True
One
True
True
RC2
True
SECTION 15.5: ECCP PROGRAMMING
I.
2.
3.
4.
5.
False. Up to four pins.
One
True
False
RD4-RD7
CHAPTER 15: CCP AND ECCP PROGRAMMING
601
CHAPTER 16
SPI PROTOCOL AND
DS1306 RTC
INTERFACING
OBJECTIVES
Upon completion of this chapter, you will be able to:
»
»
»
»
»
»
»
»
»
»
Understand the Serial Peripheral Interfacing (SPI) protocol
Explain how the SPI read and write operations work
Examine the SPI pins SDO, SDI, CE, and SCLK
Code programs in Assembly and C for SPI
Explain how the real-time clock (RTC) chip works
Explain the function of the DS1306 RTC pins
Explain the function of the DS1306 RTC registers
Understand the interfacing ofthe DS1306 RTC to the PIC18
Code programs to display time and date in Assembly and C
Explore and program the alarm and interrupt features of the RTC
603
This chapter discusses the SPI bus and shows the interfacing and programming of the DS1306 real-time clock (RTC), an SPI chip. In Section 16.1, we
describe SPI bus connection and protocol. In Section 16.2, we describe the
DS 1306 RTC's pin functions and show its interfacing and programming with the
PICI8. The C programming ofDS1306 is shown in Section 16.3. The alarm feature of the DS1306 is discussed in Section 16.4.
SECTION 16.1: SPI BUS PROTOCOL
The SPI (serial peripheral interface) is a bus interface connection incorporated into many devices such as ADC, DAC, and EEPROM. In this section we
examine the pins of the SPI bus and show how the read and write operations in the
SPI work.
SPI bus
The SPI bus was originally started by Motorola Corp. (now Freesca1e), but
in recent years has become a widely used standard adapted by many semiconductor chip companies. SPI devices use only 2 pins for data transfer, called sm (Din)
and SDO (Dout), instead of the 8 or more pins used in traditional buses. This
reduction of data pins reduces the package size and power consumption drastically, making them ideal for many applications in which space is a major concern.
The SPI bus has the SCLK (shift clock) pin to synchronize the data transfer
between two chips. The last pin of the SPI bus is CE (chip enable), which is used
to initiate and terminate the data transfer. These four pins, SDI, SDO, SCLK, and
CE, make the SPI a 4-wire interface. See Figure 16-1. There is also a widely used
standard called a 3-wire interface bus. In a 3-wire interface bus, we have SCLK
and CE, and only a single pin for data transfer. The SPI 4-wire bus can become a
3-wire interface when the SDI and SDO data pins are tied together. However, there
are some major differences between the SPI and 3-wire devices in the data transfer protocol. For that reason, a device must support the 3-wire protocol internally
in order to be used as a 3-wire device. Many devices such as the DS 1306 RTC
(real-time clock) support both SPI and 3-wire protocols.
I
SOO X'SOO
SOl
SOl
SCLK
SCLK
CE
CE
DO
...
_.'
_.-
07 - - - - 07
,
~C
DO
~C
!
I
ST~L:U
Figure 16-1. SPI Bus vs. Traditional Parallel Bus Connection to
Microcontroller
604
I
SPI read and write protocol
In connecting a device with an SPI bus to a microcontroller, we use the
microcontroller as the master while the SPI device acts as a slave. This means that
the microcontroller generates the SCLK, which is fed to the SCLK pin of the SPI
device. The SPI protocol uses SCLK to synchronize the transfer of information
one bit at a time, where the most-significant bit (MSB) goes in first. During the
transfer, the CE must stay HIGH. The information (address and data) is transferred
between the microcontroller and the SPI device in groups of 8 bits, where the
address byte is followed immediately by tbe data byte. To distinguish between the
read and write, the D7 bit of the address byte is always I for write, while for the
read, the D7 bit is LOW, as we will see next.
Steps for writing data to an SPI device
In accessing SPI devices, we have two modes of operation: single-byte and
multi byte. We will explain each one separately.
Single-byte write
The following steps are used to send (write) data in single-byte mode for
SPI devices, as shown in Figure 16-2:
I. Make CE = I to begin writing.
2. The 8-bit address is shifted in one bit at a time, with each edge of
SCLK. Notice that A 7 = I for the write operation, and the A 7 bit goes
in first.
3. After all 8 bits of the address are sent in, the SPI device expects to
receive the data belonging to that address location immediately.
4. The 8-bit data is shifted in one bit at a time, with each edge of the
SCLK.
5. Make CE = 0 to indicate the end of the write cycle.
CE /
SCLK
SOl
--1-'7=11 A6 1A5 1A4 1A3 1A2 1A1 1AD 107 106 105 104 103 102 101 1DO I--
SOO
Figure 16-2. SPI Single-Byte Write Timing (Notice A7 = 1)
Multibyte burst write
Burst mode writing is an effective means ofloading consecutive locations.
In burst mode, we provide the address of the first location, followed by the data
for that location. From then on, while CE = I, consecutive bytes are written to consecutive memory locations. In this mode, the SPI device internally increments the
CHAPTER 16: SPI PROTOCOL AND DS1306 RTC INTERFACING
605
address location as long as CE is HIGH. The following steps are used to send
(write) multiple bytes of data in burst mode for SPI devices as shown in
Figure 16-3:
I. Make CE = I to begin writing.
2. The 8-bit address of the first location is provided and shifted in one bit
at a time, with each edge of SCLK. Notice that A 7 = I for the write
operation and the A 7 bit goes in first.
3. The 8-bit data for the first location is provided and shifted in one bit at
a time, with each edge of the SCLK. From then on, we simply provide
consecutive bytes of data to be placed in consecutive memory locations.
In the process, CE must stay high to indicate that this is a burst mode
multibyte write operation.
4. Make CE = 0 to end writing.
eE /
11111111 11111111 11111111 11111111 11111111 11111111
seLK
SOl
"-
---1 AOORO
1 OATAO 1 OATA1 1 OATA2 1 OATA3 IOATAN.11t----
Figure 16-3. SPI Burst (MultiByte) Mode Writing
Steps for reading data from an SPI device
In reading SP! devices, we also have two modes of operation: single-byte
and multibyte. We will explain each one separately.
Single-byte read
The following steps are used to get (read) data in single-byte mode from
SP! devices as shown in Figure 16-4:
I. Make CE = 1 to begin writing.
2. The 8-bit address is shifted in one bit at a time, with each edge of
SCLK. Notice that A 7 = 0 for the read operation, and the A 7 bit goes in
first.
3. After all 8 bits of the address are sent in, the SPI device sends out data
belonging to that location.
4. The 8-bit data is shifted out one bit at a time, with each edge of the
SCLK.
5. Make CE = 0 to indicate the end of the read cycle.
eE /
SCLK
SOl ----jA7=01 A6 1 A5 1 A4 1 A3 1 A2 1 A1 1 AO 1 - 1 - - - - - - - - - - - - SOO - - - - - - - - - - - - - - 1 1 07 1 06 1 05 1 04 1 03 1 02 1 01 1 DO
Figure 16-4. SPI Single-Byte Read Timing (Notice A7 = 0)
606
I--
Multibyte burst read
Burst mode reading is an effective means of bringing out the contents of
consecutive locations. In burst mode, we provide the address of the first location
only. From then on, while CE = I, consecutive bytes are brought out from consecutive memory locations. In this mode, the SPI device internally increments the
address location as long as CE is HIGH. The following steps are used to get (read)
multiple bytes of data in burst mode for SPI devices, as shown in Figure 16-5:
1. Make CE = I to begin reading.
2. The 8-bit address of the first location is provided and shifted in one bit
at a time, with each edge ofSCLK. Notice that A 7 = 0 for the read operation, and the A 7 bit goes in first.
3. The 8-bit data for the first location is shifted out one bit at a time, with
each edge of the SCLK. From then on, we simply keep getting consecutive bytes of data belonging to consecutive memory locations. In the
process, CE must stay HIGH to indicate that this is a burst mode
multibyte read operation.
4. Make CE = 0 to end reading.
cr/
seLK
~
11111111 11111111 11111111 11111111 11111111 11111111
-----l ADDRO
SDO ------ll DATAO 1DATA1 1DATA2 1DATA3
SDI
1 - 1-
-
-
-
-
-
-
-
-
-
-
-
-
IDATAN- 1
-
-
-
11----
Figure 16-5. SPI Burst (MultiByte) Mode Reading
Review Questions
I.
2.
3.
4.
5.
True or false. The SPI protocol writes and reads information in 8-bit chunks.
True or false. In SPI, the address is immediately followed by the data.
True or false. In an SPI write cycle, bit A7 of the address is LOW.
True or false. In an SPI write, the LSB goes in first.
State the difference between the single-byte and burst modes in terms of the
CE signal.
CHAPTER 16: SPI PROTOCOL AND DS1306 RTC INTERFACING
607
SECTION 16.2: DS1306 RTC INTERFACING AND
PROGRAMMING
The real-time clock (RTC) is a widely used device that provides accurate
time and date information for many applications. Many systems such as the x86
IBM PC come with such a chip on the motherboard. The RTC chip in the IBM PC
provides the time components of hour, minute, and second, in addition to the
date/calendar components of year, month, and day. Many RTC chips use an internal battery, which keeps the time and date even when the power is off. Although
some microcontrollers, such as the DS5000T, come with the RTC already embedded into the chip, we have to interface the vast majority of them to an external RTC
chip. One of the most widely used RTC chips is the DS 12887 from Dallas
Semiconductor/Maxim Corp. This chip is found in the vast majority of x86 PCs.
The original IBM PC/AT used the MC14618B RTC from Motorola. The DSI2887
is the replacement for that chip. It uses an internal lithium battery to keep operating for over 10 years in the absence of external power. The DS 12887 is a parallel
RTC with 8 pins for the data bus. In this chapter, we interface and program the
DS 1306 RTC, which has an SPI bus. According to the DS 1306 data sheet from
Maxim, it keeps track of "seconds, minutes, hours, day of week, date, month, and
year with leap-year compensation valid up to year 2099." The DS 1306 RTC provides the above information in BCD format only. It supports both 12-hour and 24hour clock modes, with AM and PM in the 12-hour mode. It does not support the
Daylight Savings Time option. The DS 1306 has a total of 128 bytes of nonvolatile
RAM. It uses 28 bytes of RAM for clock/calendar and control registers, and the
other 96 bytes of RAM are for general-purpose data storage. Next, we describe the
pins of the DS 1306. See Figure 16-6.
V CC2
Pin I provides an external back-up
supply voltage to the chip. This pin is connected to an external rechargeable power
source. This option is called trickle charge.
If this pin is not used, it must be grounded.
0
1 Vcc2
VCC1 16 0
0
2 Vbat
32kHz 15 0
0
3 X1
VCCIF14 0
Vbat
0
4 X2
SDO 13 0
Pin 2 can be connected to an external
+3 V lithium battery, thereby providing the
power source to the chip externally as backup supply voltage. We must connect this pin
to ground if it is not used.
0
5 INTO
SDI12 0
0
6 INT1
SCLK 11 0
0
7 1-Hz
CE10 0
0
8 GND
SERMODE 9 0
V CC1
Pin 16 is used as the primary external Figure 16-6. DS1306 RTC Chip
voltage supply to the chip. This primary (from MaximlDallas Semiconductor)
external voltage source is generally set to +5 V. When Vcc I falls below the Vbat
voltage level, the DS1306 switches to Vbat and the external lithium battery provides power to the RTC. According to the DS 1306 data sheet "upon power-up, the
device switches from Vbat to Vcc I when Vcc I is greater than Vbat+0.2 Volts."
Because we can connect the standard 3 V lithium battery to the Vbat pin, the Vcc I
voltage level must remain above 3.2 V in order for the Vccl to remain as the primary voltage source to the chip. This nonvolatile capability of the RTC prevents
608
Veo1
Vcc2
rl
Vbat
-
~I
-
V",~p'ima'Y
rl
Vbat
veo1h
- r-
VOC2~Se'O"da'Y ~ I
VC'2~ ~
-
-
Figure 16-7. DS1306 Power Connection Options (Maxim/Dallas Semiconductor)
any loss of data. See Figure 16-7.
GND
Pin 8 is the ground.
SDI (Serial Din)
The
pin provides the path to bring data into the chip, one bit at a time.
SDO (Serial Dout)
The SDO pin provides the path to bring data out of the chip, one bit at a
time.
32KHz
This is an output pin providing a 32.768 kHz frequency. This frequency is
always present at the pin.
X1-X2
These are input pins that allow the DS 1306 connection to an external crystal oscillator to provide the clock source to the chip. We must use the standard
32.768 kHz quartz crystal. The accuracy of the clock depends on the quality of this
crystal oscillator. See Figure 16-8. Heat can cause a drift on the oscillator. To avoid
this, we use the DS32KHZ chip, which automatically adjusts for temperature variations. Note that when using the DS32KHZ or similar clock generators, we only
need to connect X 1 because the X2 loopback is not required.
SCLK (serial clock)
An input pin is used for the serial clock to synchronize the data transfer
between the DS 1306 and the microcontroller.
1-Hz
An output pin provides a I-Hz square wave frequency. The DS 1306 creates the I-Hz square wave automatically. To get this I-Hz frequency to show up
on the pin, however, we must enable the associated bit in the DS 1306 control register.
sm
CE
Chip enable is an input pin and an active-HIGH signal. During the read and
write cycle time, CE must be high.
INTO#
Interrupt request is an output pin and an active-LOW signal. To use INTO,
the interrupt-enable bit in the RTC control register must be set HIGH. The interrupt feature of the DS 1306 is discussed in Section 16.4.
INT1
Interrupt request is an output pin and an active-HIGH signal. To use INTI,
the interrupt-enable bit in the RTC control register must be set HIGH. The inter-
CHAPTER 16: SPI PROTOCOL AND DS1306 RTC INTERFACING
609
rupt feature of the DS 1306 is discussed in Section 16.4.
SERMODE (serial mode selection)
Pin 9 is an input pin. If it is HIGH, then the SPI mode is selected. If it is
connected to ground, the 3-wire mode is used. In our application, the SERMODE
pin is connected to the Vee pin because we program the 1306 chip using the SPI
protocol.
V CCif
Pin 14 is the interface logic power-supply input. This pin allows interfacing of the DS 1306 with systems with 3 V logic in mixed supply systems. See the
DS 1306 data sheet if you are using a power source other than 5 V in your system.
I
D __
~' -,-.~
Exlemal _
s~~ ~
SC~~
SERIAL
INTERFACE
r
INPUT
SHIFT
REGISTER
I..
~
1
I: 32,768 Hz
r+
CLOCK, CALENDAR,
AND ALARM
REGISTERS
r+
CONTROL
REGISTERS
•
. . . . . .~
~
INTO
INT1
1 Hz
USER
RAM
SERMODE
Figure 16-8. Simplified Block Diagram of DS1306 (MaximlDallas Semiconductor)
Importance of the WP bit in the Control register
As shown in Table 16-1, the Control register has an address of 8FH for
write and OFH for read. The most important bit in the Control register is the WP
bit. The WP bit is undefined upon reset. In order to write to any of the registers of
the DS1306, we must clear the WP bit first. See Figure 16-9. Upon powering up
the DS 1306, we have to clear the WP bit at least once. This means that after initializing the DS 1306 we can write protect all the registers by making WP = 1.
WP
WP (Write Protect) If the WP bit is set high, the DS 1306 prevents any write operation
to its registers. Upon power-up, the WP bit is undefined. Therefore, we must
make WP = 0 before we can write to any of the registers. This must be done
once upon power-up of the DS1306.
The other bits of the Control register are explained in the next section.
Figure 16-9. WP Bit of DS1306 Control Register (write location address is 8FH)
610
Address map of the 051306
The DS 1306 has a total of 128 bytes of RAM space with addresses
00-7FH. The first fifteen locations, OO-OE, are set aside for RTC values of time,
date, and alarm data. The next three bytes are used for the control and status registers. They are located at addresses OF-II in hex. The next 14 bytes from addresses 12H to I FH are reserved and cannot be used. That leaves 96 bytes, from
addresses 20H to 7FH, available for general purpose data storage. That means the
entire 128 bytes of RAM are accessible directly for read or write except the
addresses 12-IFH. Table 16-1 shows the address map of the DS1306. In this section we study the time and date. The alarm is examined in Section 16.4.
Table 16-1: Registers of the DS1306 (modified from datasheet)
HEX ADDRESS
D7
D6
D5
D4
D3
D2
READ
WRITE
0
°OXX 001
°OxXS01'-l-- 0 ,. i
1100SMEINC
___SEC
0
S 1
1 MIN
Ox02- -O~S2 I ·-0-24 I 20HRl10HR I
HOURS
D1
i"·
Ox03
~~~:
~-0~83
-'I
O~P~A
~~~---j-~
Ox06
OxS6
ox07L oxS7!
Oxos
Oxss
Ox09
OxS9
f
OxOA I OxOSA,
1
1-0-+
I -~-'~[)t~
0
-OxOE
OxSD
10 YEAR
120
~~~_ -+ri:~~ .-~---
.
'1;
. --_.
i
Pt
.
00-59
I
00-23
;_Q.0::§.9
DAY----i
01~~~~1h~
-1
YEAR
00-99
.. _S_E_C "LARMO______
Oo.-_59_~
MIN ALARM0c:--_ .. _ I' ..00-59_
HOUR ALARMO
~ 00-23
~~_
01,12 PIA
DAY ALARMO
I
01-07 ,
~~~:c::~11-+ ~~~~
HOUR ALARM 1
I 0
0
CS~~~~LR~~~~~R
TRICi<LE
RANGE
in HEX
~t~---~·· ~~:~~I
... _ - -
M , 24 I 20-H.R.. 110 HRI-
OxSE - - M
·_O;'_10_;~_:1f'Ox~;~:)
~---.
M __;_10_SEC ALi\RMQ.;.__
~.
10 MIN ALARMO i
-M.
24 I
HR[.10 HRI.
.
12' PIA
I
M
!
0
0' 0
0
~~~-{ ~~:~ +~~-~ ~ri~:C::~11
OxOD
0---·-
DO
DAY
00-23
1
I
ALARM101~~~;/A,
-1-
~~~~~~;EG_IS_TE_R ..--==r_---~~
_ _-
Time and date address locations and modes
The byte addresses 0-6 are set aside for the time and date, as shown in
Table 16-2. Table 16-2 is extracted from Table 16- L It shows a summary of the
address locations in read/write modes with data ranges for each location. The
DS 1306 provides data in BCD format only. Notice the data range for the hour
mode. We can select 12-hour or 24-hour mode with bit 6 of hour location 02.
When D6 = I, the 12-hour mode is selected, and D6 = 0 provides us the 24-hour
mode. In the 12-hour mode, we decide the AM and PM with the bit 5. If D5 = 0,
the AM is selected and D5 = I is for the PM. Example 16-1 shows how to get the
range of the data acceptable for the hour location.
CHAPTER 16: SPI PROTOCOL AND DS1306 RTC INTERFACING
611
Table 16-2: DS1306 Address Locations for Time and Date (extracted from Table 16-1)
Hex Address
Read
00
01
02
Location
Write
80
81
82
03
04
05
06
83
84
85
86
Function
Seconds
Minutes
Hours, 12-Hour Mode
Hours, 12-Hour Mode
Hours, 24-Hour Mode
Day of the Week, Sun = 1
Day of the Month
Month
Year
Data Range
BCD
00-59
00-59
01-12
01-12
00-23
01-07
01-31
01-12
00-99
Range in hex
00-59
00-59
41-52 AM
61-72 PM
00-23
01-07
01-31
01-12
00-99
Example 16-1
Using Table 16-1, verify the hour location values in Table 16-2.
Solution:
(a) For 24-hour mode, we have D6 = O. Therefore, the range goes from 0000 0000 to
00100011, which is 00-23 in BCD.
(b) For 12-hour mode, we have D6 = 1 and D5 = 0 for AM. Therefore, the range goes
from 0100 0001 to 01010010, which is 41-52 in BCD.
(c) For 12-hour mode, we have D6 = 1 and D5 = 1 for PMn. Therefore, the range goes
from 0110 0001 to 0111 0010, which is 61-72 in BCD.
PIC18 interfacing to 051306 using M55P module
The DS 1306 supports both SPI and 3-wire modes. In DS 1306, we select
the SPI mode by connecting the SERMODE pin to Vcc. If SERMODE = Gnd,
then the 3-wire protocol is used. In this section, we use SPI mode only. The MSSP
(Master Synchronous Serial Port) module inside the PIC 18 supports SPI bus protocol. Three registers are associated with SPI of the MSSP module. They are SSPBUF, SSPCONI, and SSPSTAT. To transfer a byte of data, we place it in SSPBUF.
The SSPBUF register also holds the byte received via the SPI bus. Figures 16-10
and 16-11 show the other two major registers of the PIC18 for SPI interfacing. We
use SSPCON I to select the SPI mode operation of the PICI8. Notice that the
SSPEN bit in the SSPCON I register must be set to HIGH to allow the use of the
PIC 18 pins for SPI data bus protocol. We must also choose the SPI Master mode
using the SSPM3:SSPMO bits of SSPCONI. In our application, we will use
Fosc/64 speed for best performance in data transfer between the PIC 18 and the
DS1306 RTC.
After the selection of SSPCON I, we must also select the proper bits for
timing in the SSP STAT register, as shown in Figure 16-11. In our application, we
send data to an SPI device on the rising edge, and receive data from the SPI device
in the middle of the SCLK clock pulse.
Because we are using the SPI feature of the PIC 18 to communicate with
612
our SPI device, we must use the designated pins for the SPI signals. They are RC2
(CE), RC3 (SCLK), RC4 (SDI), and RC5 (SDO), as shown in Figure 16-12.
SSPEN
SSPEN
05
I
I
SSPM3
I
SSPM2
SSPMI
I
SSPMO
I
Synchronous Serial Port Enable bit
I = Enables serial port and configures SCK, SDO, and sm
as serial port pins
o = Disables serial port and configures these pins as 110 ports
SPI Mode Selection bits
SSPM3:SSPMO 03-00
0010 = SPI Master, clock = Fosc/64
0001 = SPI Master, clock = Fosc/16
0000 = SPI Master, clock = Fosc/4
The rest of the bits are unused in our implementation of SPI.
We use SPI in master mode.
Figure 16-10. SSPCONI - SSP Control Register 1
Note: Portion shown is used for SPI.
SMP
BF
CKE
SMP
D7
Sample bit
I = Input data sampled at end of data output time
o= Input data sampled at middle of data output time
CKE
06
SPI Clock Edge Select bit
I = Transmit occurs on transition from active to idle clock
state.
o = Transmit occurs on transition from idle to active clock
state.
BF
DO
Buffer Full Status bit. Used for receive only.
I = Receive complete, SSPBUF is full.
o = Receive not complete, SSPBUF is empty.
The rest of the bits are used for ]2C module.
Figure 16-11. SSPSTAT - SSP Status Register
Note: Portion shown is used for SPI.
CHAPTER 16: SPI PROTOCOL AND DS1306 RTC INTERFACING
613
PIC 18F452/458
SOI(RC4)
SOO(RC5)
SCLK(RC3)
CE(RC2)
OS1306
T
SOl
~ SOO
X1
I I
! DS32KHZ
X2 -NC
SCLK
CE
SERMOOE
GNO
I
vee
-==-
Figure 16-12. DS1306 Connection to PIC18
Note: For more accuracy, we use the OS32KHZ chip in place of a crystal.
Setting the time in Assembly
Program 16-1 initializes the clock at 16:58:55 using the 24-hour clock
mode. It uses the single-byte operation for writing into the control register of the
OS 1306 and multibyte burst mode for writing seconds, minutes, and hours.
Regarding the SPI subroutine in Program 16-1, we must note the following points:
I. In order for the PIC 18 to transfer a byte of data using SPI protocol, it
must be placed in SSPBUF.
2. After writing to SSPBUF, we must monitor the BF flag bit of the
SSPSTAT register to ensure the entire byte has been transferred.
3. SSPBUF is also used as the destination for incoming data from an SPI
device. This happens as data is being sent. The BF flag indicates that
the entire byte has been received.
;Program 16-1: Setting the Time
MOVLW OxOO
MOVWF SSPSTAT ;read at middle, send on active edge
MOVLW Ox22
MOVWF SSPCONI ;enable master SPI, Fosc / 64
;make PORTC output
CLRF TRISC
BSF TRISC,SDI
;except SDI
send control byte to DS1306 in single-byte mode
BSF
PORTC, RC2
;make CE = 1 for single-byte
CALL SDELAY
MOVLW Ox8F
;DS1306 control register address
CALL SPI
MOVLW OxOO
;clear WP bit for write
614
CALL SPI
BCF PORTC,RC2
;make CE = 0 to end write (single-byte)
CALL SDELAY
;-- send the data to DS1306 in burst mode
BSF
PORTC,RC2 ;make CE = 1 (start multibyte write)
MOVLW Ox80
;seconds register address
CALL SPI
;send address
MOVLW Ox55
;55 seconds
CALL SPI
;send seconds
MOVLW Ox58
;58 minutes
jsend minutes
CALL SPI
;24-hour clock at 16 hours
MOVLW Ox16
CALL SPI
isend hour
;make CE = 0 (end multibyte write)
BCF PORTe, RC2
;-- SPI write/read subroutine
SPI MOVWF SSPBUF
;load SSPBUF for transfer
WAIT BTFSS SSPSTAT, BF
; wai t for all bits
BRA WAIT
;get the received byte
MOVF SSPBUF,W
;return with byte in WREG
RETURN
END
Setting the date in Assembly
Program 16-2 shows how to set the date to October 19th, 2004.
;Program 16-2: Setting the Date
MOVLW OxOO
MOVWF SSPSTAT ;read at middle, send on active edge
MOVLW Ox22
MOVWF SSPCON1
;master SPI enable, Fosc / 64
CLRF TRISC
;make PORTC output
BSF TRISC,SDI
;except SDI
BSF
PORTC, RC2
;enable the RTC
MOVLW Ox8F
;DS1306 control register address
CALL SPI
;clear WP bit for write
MOVLW OxOO
CALL SPI
BCF PORTC,RC2
;turn off RTC
send the date to DS1306
; enable the RTC
BSF
PORTC, RC2
MOVLW Ox84
;date register address
CALL SPI
;send address
MOVLW Ox19
;19th of the month
jsend date
CALL SPI
MOVLW Ox10
;October
;send month
CALL SPI
MOVLW Ox04
;2004
CALL SPI
isend year
BCF PORTC,RC2
;disable RTC
;-- SPI write/read subroutine
CHAPTER 16: SPI PROTOCOL AND DS1306 RTC INTERFACING
615
SPI MOVWF SSPBUF
WAITBTFSS SSPSTAT,BF
BRA WAIT
MOVF SSPBUF,W
RETURN
END
;load SSPBUF for transfer
;wait for all bits
;get the received byte
;return with byte in WREG
RTCs setting, reading, and displaying time and date
Program 16-3 is the complete Assembly code for setting, reading, and displaying the time and date. The times and dates are sent to the IBM PC screen via
the serial port after they are converted from packed BCD to ASCII.
iProgram 16-3
#include p18f458.inc
D1uL EQU D'2'
; 1 microsecond delay byte
DR1uL EQU OxOD
;register for 1 microsecond delay
DAY
EQU 10H
ifor day of the week
MON
EQU llH
; fileReg starting with month
DAT
EQU 12H
ifor day of the month
YR
EQU 13H
ifor year
HR
EQU 14H
ifor hour
MIN
EQU 15H
ifor minutes
SEC
EQU 16H
ifO r seconds
CNT
EQU 20H
ifor counter
TMP
EQU 21H
ifor conversions
MOVLW OxOO
MOVWF SSPSTAT ;read at middle, send on active edge
MOVLW Ox22
MOVWF SSPCON1
;master SPI enable, Fosc / 64
CLRF TRISC
;make PORTC output
BSF TRISC,SDI
;except SDI
BSF TRISC,RX
;and RX
enable USART communication
MOVLW B'00100000'
;enable transmit and low baud
MOVWF TXSTA
;write to reg
MOVLW D'15'
;9600 bps (Fosc / (64 * Speed) - 1)
MOVWF SPBRG
;write to reg
BCF TRISC, TX
;make TX pin of PORTC an output pin
BSF RCSTA, SPEN
;enable the serial port
j--
start a new line for USART communications
MOVLW OxOA
;form feed
CALL TRANS
MOVLW OxOD
jnew line
CALL TRANS
;-- send control byte to DS1306
BSF
PORTC, RC2
; enable the RTC
CALL SDELAY
MOVLW Ox8F
;control register address
CALL SPI
MOVLW OxOO
;clear WP bit for write
616
,
;-RDA
;--
SND
CALL SPI
BCF PORTC,RC2
;disable RTC
CALL SDELAY
send the time followed by date
PORTC,RC2
BSF
; enable the RTC
MOVLW Ox80
iseconds register address for write
CALL SPI
;send address
MOVLW Ox55
;55 seconds
CALL SPI
isend seconds
MOVLW Ox58
;58 minutes
jsend minutes
CALL SPI
MOVLW Ox16
;24-hour clock at 16 hours
CALL SPI
;send hour
MOVLW Ox3
; Tuesday
CALL SPI
;send day of the week
MOVLW Ox19
;19th of the month
CALL SPI
;send day of the month
jOctober
MOVLW Ox10
jsend month
CALL SPI
MOVLW Ox04
;2004
CALL SPI
;send year
BCF PORTC,RC2
;disable RTC
CALL SDELAY
get the time and date from DS1306
BSF
PORTe, RC2
; enable the RTC
CALL SDELAY
MOVLW OxOO
iseconds register address for read
CALL SPI
;send address to DS1306
CALL SPI
;start getting time/date
MOVWF SEC
isave the seconds
CALL SPI
;get the minutes
MOVWF MIN
jsave the minutes
CALL SPI
;get the hour
MOVWF HR
;save the hour
CALL SPI
;get the day
MOVWF DAY
;save the day
CALL SPI
;get the date
jsave the date
MOVWF DAT
CALL SPI
;get the month
MOVWF MON
jsave the month
CALL SPI
;get the year
MOVWF YR
isave the year
BCF PORTC,RC2
;disable RTC
convert packed BCD to ASCII and display
LFSR FSRO,Ox11
;address of fileReg for time/date
MOVLW D'6'
;6 bytes of data to display
jset up the counter
MOVWF CNT
MOVFF INDFO,TMP
;get the data for high nibble
MOVLW OxFO
iclear low nibble
ANDWF TMP,F
;keep in TMP register
SWAPF TMP,F
;switch high and low nibbles
CHAPTER 16: SPI PROTOCOL AND DS1306 RTC INTERFACING
617
;convert to ASCII
MOVLW Ox30
IORWF TMP,W
;put in WREG
;display the data
CALL TRANS
;get the data and point to next
MOVFF POSTINCO,TMP
;clear high nibble
MOVLW OxOF
;keep in TMP register
ANDWF TMP,F
;convert to ASCII
MOVLW Ox30
;put in WREG
IORWF TMP,W
CALL TRANS
;display the data
MOVLW ':'
CALL TRANS
iIS it the last one?
DECFSZ CNT
BRA SND
ino
i1ine feed
MOVLW OxOD
CALL TRANS
BRA RDA
;keep reading time/date and display them
,
SPI write/read subroutine
SPI MOVWF SSPBUF
;load SSPBUF for transfer
WAITBTFSS SSPSTAT,BF
;wait for all bits
BRA WAIT
MOVF SSPBUF,W
;get the received byte
;return with byte in WREG
RETURN
i----serial data transfer subroutine
TRANS BTFSS PIRl, TXIF
;wait until the last bit is gone
BRA TRANS
;stay in loop
;load the value to be transmitted
MOVWF TXREG
;return to caller
RETURN
;----short delay
;low byte of delay
SDELAY: MOVLW
DluL
jstore in register
MOVWF DRluL
DSI
DECF DRluL, F
;stay until DRluL becomes 0
BNZ
DSI
RETURN
END
Review Questions
1. True or false. All of the RAM contents of the DS 1306 are nonvolatile.
2. How many bytes of RAM in the DS 1306 are set aside for the clock and date?
3. How many bytes of RAM in the DSI306 are set aside for general-purpose
applications?
4. True or false. The DS 1306 has a single pin for Din.
5. Which pin of the DS1306 is used for Clock in SPI connection?
6. True or false. To use the DSI306 in SPI mode, we make SERMODE = GND.
618
SECTION 16.3: 051306 RTC PROGRAMMING IN C
In this section, we program the OS1306 in PICIS C language. Before you
embark on this section, make sure you understand the basic concepts of the
OS1306 chip covered in the first section.
Setting the time and date in C
Program 16-4C shows how to set the time and date for the OS 1306 configuration in Figure 16-12.
//Program 16-4C : Setting time and date
#include <p18f458.h>
unsigned char SPI(unsigned char);
void SDELAY(int ms);
void main ()
SSPSTAT
0; //read at middle, send on active edge
Ox22;
SSPCON1
//master SPI enable, Fosc / 64
TRISC = 0;
//make PORTC output
TRISCbits.TRISC4
1; / / except SDI
TRISCbits.TRISC7
1; / land RX
PORTCbits.RC2 = 1;
lienable the RTC
SDELAY(l);
SPI (Ox8F) ;
//control register address
SPI (OxOO) ;
//clear WP bit for write
PORTCbits.RC2
0;
fiend of single-byte write
SDELAY(l) ;
1·,
PORTCbits.RC2
//begin multibyte write
SPI (Ox80) ;
//seconds register address
SPI(Ox55) ;
//55 seconds
SPI (Ox58) ;
//58 minutes
SPI (Ox16);
//24-hour clock at 16 hours
SPI(Ox3) ;
//Tuesday
SPI(Ox19) ;
//19th of the month
SPI(Ox10) ;
//October
SPI(Ox04) ;
//2004
PORTCbits.RC2
0;
fiend multibyte write
SDELAY(l) ;
}
//-- SPI Write/Read subroutine
unsigned char SPI(unsigned char myByte)
{
SSPBUF = myByte;
//load SSPBUF for transfer
while(!SSPSTATbits.BF);
//wait for all bits
return SSPBUF;
//return with received byte
CHAPTER 16: SPI PROTOCOL AND DS1306 RTC INTERFACING
619
Reading and displaying the time and date in C
Program 16-5C shows how to read the time, convert it to ASCII, and send
it to the PC screen via the serial port.
IIProgram 16-5C : Reading and Displaying Time
#include <pI8f458.h>
unsigned char SPI(unsigned char);
void TRANS (unsigned char);
void BCDtoASCllandSEND(unsigned char);
void SDELAY(int ms);
void main ()
unsigned char data[7];
Ilholds date and time
unsigned char tmp;
Ilfor BCD to ASCII conversion
int i;
SSPSTAT = 0;
Ilread at middle, send on active edge
SSPCON1 = Ox22;
Ilmaster SPI enable, Fosc I 64
TRISC
= 0;
Ilmake PORTC output
TRISCbits.TRISC4
1;
Ilexcept SDI
TRISCbits.TRISC7
1;
Iland RX
TXSTA = Ox20;
lienable transmit and low baud
SPBRG = 15;
119600 bps (Fosc I (64 * Speed) - 1)
RCSTAbits.SPEN
1;
lienable the serial port
TRANS (OxOA) ;
Ilform feed
TRANS (OxOD) ;
Iinew line
11-- get the time and date from RTC and save them
while (1)
(
PORTCbits.RC2
1·,
SDELAY(l) ;
SPI(OxOO) ;
for(i=0;i<7;i++)
Ilbegin multibyte read
Iiseconds register address
{
data [i]
= SPI (OxOO); Ilget time/date and save
}
PORTCbits.RC2 = 0;
Ilend of multibyte read
11-- convert time/date and display MM:DD:YY:HH:MM:SS
BCDtoASCllandSEND(data[5]); lithe month
BCDtoASCIlandSEND(data[4]); lithe date
BCDtoASCllandSEND(data[6]); lithe year
BCDtoASCIIandSEND(data[2]); lithe hour
BCDtoASCIIandSEND(data[l]); lithe minute
BCDtoASClIandSEND(data[O]); lithe second
TRANS (OxOD) ;
Iinew line
}
620
//-- SPI Write/Read
unsigned char SPI(unsigned char myByte)
(
SSPBUF = myByte;
while(lSSPSTATbits.BF) ;
return SSPBUF;
}
void TRANS (unsigned char myChar) //serial data transfer
(
while(lPIRlbits.TXIF) ;
TXREG = myChar;
/ /load the value to be transmitted
}
void BCDtoASCIlandSEND(unsigned char myValue)
{
unsigned char tmp
tmp
tmp & OxFO;
tmp = tmp > > 4;
tmp = tmp I Ox30;
TRANS (tmp) ;
tmp
myValue;
tmp = tmp & OxOF;
tmp = tmp I Ox30;
TRANS (tmp) ;
TRANS ( , : ' ) ;
myValue;
//mask lower nibble
//swap it
//make it ASCII
//display
//for other digit
//mask upper nibble
/ /make it ASCII
//display
//display separator
}
void SDELAY(int ms)
unsigned int if j;
for{i=Oii<msii++)
for(j=O;j<135;j++) ;
Review Questions
I. True or false. All of the RAM contents of the DS 1306 are volatile.
2. What locations of RAM in the DS 1306 are set aside for the clock and date?
3. What locations of RAM in the DS1306 are set aside for general-purpose applications?
4. True or false. The DS 1306 has a single pin for Dout.
5. True or false. CE is an output pin.
6. True or false. To use the DS1306 in SPI mode, we make SERMODE = VCC.
CHAPTER 16: SPI PROTOCOL AND DS1306 RTC INTERFACING
621
SECTION 16.4: ALARM AND INTERRUPT FEATURES OF
THE 051306
In this section, we program the alann and interrupt features of the DS 1306
chip using Assembly and C languages. These powerful features of the DSI306 can
be very useful in many real-world applications. In the DS 1306 there are two
alanns, calledAlarmO andAlarml, each with their own hardware interrupts. There
is also a I -Hz square wave output pin, which we discuss next. These features are
accessed with the Control register shown in Figure 16-13.
o
WP
o
o
I
0
I
I-Hz
I AIEl
AIEO
WP (Write Protect) If the WP bit is set high, the DS 1306 prevents any write operation
to its registers. We must make WP = 0 before we can write to any of the
registers. Upon power-up, the WP bit is undefined. Therefore, we must make
WP = 0 before we can write to any of the registers.
I-Hz (I-Hz outpnt enable) If this bit is set HIGH, it allows the I-Hz frequency to
come out of the I-Hz pin of the DS1306. By making it LOW, we get High-Z on
the I -Hz pin. Notice that the I -Hz frequency is automatically generated by the
DS1306, but it will not show up at the I-Hz pin unless we set this bit to HIGH.
AIEO
Alarm interruptO enable. If AIE 0= 1, the INTO pin will be asserted LOW when
all three bytes of the real time (hh:mm:ss) are the same as the alarm bytes
of hh:mm:ss. Also, if AlE = I, the cases of once-per-second, once-per-minute,
and once-per-hour will assert LOW the INTO pin.
AIEl
Alarm interrupti enable. If AIEl = I, the INTI pin will be asserted HIGH when
all three bytes of the real time (hh:mm:ss) are the same as the alarm bytes
of hh:mm:ss. Also, if AlE = 1, the cases of once-per-second, once-per-minute,
and once-per-hour will assert HIGH the INTI pin.
Figure 16-13. DS1306 Control Register (Write location address is 8FH)
Programming the 1-Hz feature
The I -Hz pin of the DS 1306 provides us a square wave output of I -Hz frequency. Internally, the DS 1306 generates the I -Hz square wave automatically but
it is blocked. We must enable the I-Hz bit in the Control register to let it show up
on the I-Hz pin. This is shown below. Because we are writing to a single location,
burst mode is not used.
MOVLW OxOO
MOVWF SSPSTAT
;middle read, active edge send
MOVLW Ox22
MOVWF SSPCON1
;master SPI enable, Fosc / 64
CLRF TRISC
;make PORTC output
BSF
TRISC,SDI ;except SDI
send control byte to enable write first (Figure 16-13)
BSF
PORTC, RC2 ;enable the RTC
622
,
CALL SDELAY
MOVLW Ox8F
; Control register address
CALL SPI
MOVLW OxO
;clear WP bit for write
CALL SPI
BCF
PORTC,RC2
;disable RTC
CALL SDELAY
send control byte to enable 1 Hz signal after WP
0
BSF
PORTC,RC2
ienable the RTC
CALL SDELAY
MOVLW Ox8F
; Control register address
CALL SPI
MOVLW Ox04 ;enable 1 Hz signal in Control register
CALL SPI
BCF
PORTC, RC2
;disable RTC
CALL SDELAY
AlarmO, Alarm1, and interrupt
There are two time-of-day alarms in the DS 1306 chip. They are referred to
as AlarmO and Alarml. We can access AlarmO by writing to its registers located at
addresses 87H through 8AH, as shown in Table 16-3. Alarm 1 is accessed by writing to its registers located at addresses 8BH through 8EH, as shown in Table
16-3. During each clock update, the RTC compares the clock registers and alarm
registers. When the values stored in the timekeeping registers of 0, 1, and 2 match
the values stored in the alarm registers, the corresponding alarm flag bit (IRQFO
or IRQF1) in the status register will go HIGH. See Figure 16-14. Because polling
the IRQxF is too time-consuming, we can enable the AlEx bit in the Control register, and make it a hardware interrupt coming out of the INTO and INTI pins.
o
o
o
o
o
o
I IRQFl I IRQFO I
IRQFO (Interrupt 0 Request Flag) The IRQFO bit will go HIGH when all three bytes
of the current real time (hh:mm:ss) are the same as the AlarmO bytes ofhh:mm:ss. Also,
the cases of once-per-second, once-per-minute, and once-per-hour will assert HIGH the
IRQO bit. We can use polling to see the status ofIRQFO. However, in the Control register, if we makeAIEO ~ I, IRQFO will assert LOW the INTO pin, making it a hardware
interrupt. Any read or write of the AlarmO registers will clear IRQFO.
IRQFl (Interrupt 0 Request Flag) The IRQFI bit will go HIGH when all three bytes
of the current real time (hh:mm:ss) are the same as the Alarm I bytes ofhh:mm:ss. Also,
the cases of once-per-second, once-per-minute, and once-per-hour will assert HIGH the
IRQI bit. We can use polling to see the status ofIRQFI. However, in the Control register, if we make AIEl ~ I, IRQFI will assert HIGH the INTI pin, making it a hardware
interrupt. Any read or write of the Alarml registers will clear IRQFI.
Figure 16-14. Status Register (Read location address is IOU)
CHAPTER 16: SPI PROTOCOL AND DS1306 RTC INTERFACING
623
Table 16-3: DS1306 Address Locations for Time, Calendar, and Alarm
Hex Address
Function
Read Write
D7
OOH 80H
Seconds
0
OIH 81H
Minute
0
02H 82H Hours, 12-Hour Mode
0
Hours, 12-Hour Mode
0
Hours, 24-Hour Mode
0
03H 83H Da;i of the Week, Sun = 1 0
0
04H 84H Oa;i of the Month
05H 85H Month
0
06H 86H Year
0
o or 1
07H 87H SECAlarmO
o or I
08H 88H MIN AlarmO
o or I
09H 89H Hour AlarmO, 12-Hour
o or I
Hour AlarmO, 12-Hour
oor I
Hour AlarmO, 24-Hour
OA
8A
oor I
Da;i AlarmO
OBH 8BH SECAlarml
o or I
OCH 8CH MIN Alarml
oor I
DOH 80H Hour Alarml, 12-Hour
o or 1
oor 1
Hour Alarml, 12-Hour
Hour Alarml, 24-Hour
oor I
OEH 8EH Oa;i Alannl
o or I
CONTROL REGISTER
OFH 8FH
10H 90H
STATUS REGISTER
IIH 91H
TRICKLE REGISTER
12-IFH 82-9FH
RESERVED
20-7FH AO-FFH 96-BYTE USER RAM
Data Range
BCD
Possible Hex Range
00-59
00-59
00-59
00-59
01-12
41-52 AM
01-12
61-72 PM
00-23
00-23
01-07
01-07
01-31
01-31
01-12
01-12
00-99
00-99
00-59
00-59 or 89-A9
00-59 or 89-A9
00-59
01-12
41-52 or CI-A2 AM
01-12
61-72 or DI-F2 PM
00-23
00-23 or 80-A3
1-7
01-07
00-59
00-59 or 89-A9
00-59
00-59 or 89-A9
01-12
41-52 or CI-A2 AM
01-12
61-72 or DI-F2 PM
00-23
00-23 or 80-A3
1-7
01-07
Alarm and IRQ output pins
The alarm interrupts of INTO and [NT I can be programmed to occur at
rates of (a) once per week (b) once per day, (c) once per hour, (d) once per minute,
and (f) once per second. Next, we look at each of these.
Once-per-day alarm
Table 16-3 shows the address locations belonging to the alarm seconds,
alarm minutes, alarm hours, and alalID days. Notice the 07 bits of these locations.
An alarm is generated every day when 07 of the day alarm location is set to HIGH.
Therefore, to program the alarm for once-per-day, we must (a) write the desired
time for the alarm into the hour, minute, and second of Alarm locations, and (b) set
HIGH 07 of the alarm day. See Table 16-4. As the clock keeps the time, when all
three bytes of hour, minute, and second for the real-time clock match the values in
the alarm hour, minute, and second, the IRQxF flag bit in the Status register of the
DS1306 will go high. We can poll the IRQxF bit in the Status register, which is a
waste of microcontroller resources, or allow the hardware INTx pin to be activated upon matching the alarm time with the real time. It must be noted that in order
624
to use the hardware INTx pin of the OSl306 for an alarm, the interrupt-enable bit
for alarm in control register (AlEx) must be set HIGH. We will examine the
process shortly.
Once-per-hour alarm
To program the alarm for once per hour, we must set HIGH 07 of both the
day alarm and hour alarm registers. See Table 16-4.
Once-per-minute alarm
To program the alarm for once per minute, we must set HIGH 07 of all
three, day alarm, hour alarm, and minute alarm locations. See Table 16-4.
Once-per-second alarm
To program the alarm for once per second, we must set HIGH 07 of all
four locations of alarm day, alarm hour, alarm minute, and alarm second. See
Table 16-4.
Once-per-week alarm
To program the alarm for once per week, we must clear 07 of all four locations of alarm day, alarm hour, alarm minute, and alarm second. See
Table 16-4.
Table 16-4: OS1306 Time-of-day Alarm Mask Bits
Alarm Register Mask Bits (07)
Seconds
I
0
0
0
Minutes Hours Oays
0
0
0
0
0
0
I
I
I
I
I
Function
Alarm once per second
Alarm when seconds match (once-per-minute)
I
Alarm when minutes and seconds match (once-per-hour)
I
I Alarm when hours, minutes, and seconds match
(once-per-day)
o Alarm when day, hours, minutes, and seconds match
(once-per-week)
Example 16-2
Using Table 16-4, find the values we must place in the Alarml register if we want to
have an alarm activated at 16:05:07, and from then on once-per-minute at 7 seconds past
the minute.
Solution:
Because we use 24-hour clock, we have D6 = 0 for the HR register. Therefore, we have
1001 0110 for 16 in BCD. This means that we must put value 96H into register location
8D of the DS1306. Notice that D7 is I, according to Table 16-4.
For the MIN register, we have 10000101 for 05 in BCD. This means that we must put
value 85H into register location 8C of the DS1306. Notice that D7 is I, according to
Table 16-4.
For the SEC register we have 0000 0111 for 07 in BCD. This means that we must put
value 07H into register location 8B of the DS 1306. Notice that D7 is 0 according to
Table 16-4.
For once-per-minute to work, we must make sure that D7 of Alarm I day is also set to
I. See Table 16-4.
CHAPTER 16: SPI PROTOCOLANO OS1306 RTC INTERFACING
625
Using INTO of 081306 to activate the PIC18 interrupt
We can connect the INTO bit of the DS 1306 to the external interrupt pin of
the PIC 18 (INTO). See Figure 16-15. This allows us to perform a task once per day,
once per minute, and so on. Example 16-2 shows the values needed for the AlarmO
registers. Program 16-6 uses the AlarmO interrupt (INTO) to send the message
"YES" to the serial port once per minute, at exactly 8 seconds past the minute.
PIC 18F452/458
SOI(RC4)
SOO(RC5)
SCLK(RC3)
CE(RC2)
INTO(RBO)
OS1306
><
SOl
r
Vee
SOO
SCLK
CE
INTO
SERMOOE
I
X1
X2 I-NC
I
I DS32KHZ I
I
I
I
GNO
I
vee
----
Figure 16-15. DS1306 Connection to PIC18 with Hardware INTO
;Program 16-6
D1uL EQU
D' 2'
;1 microsecond delay byte
DR1uL EQU
OxOD
;register for 1 microsecond delay
ORG
OxOO
BRA MAIN
;bypass INT vector table
ORG
Ox08
BTFSC INTCON,INTOIF
;Was it INTO?
BRA
INTO ISR
;yes, go to INTO ISR
RETFIE
ORG
Ox28
;-- initialize SPI, INTO, and USART
MAIN CLRF TRISC
;make PORTC output
BSF
TRISC, SDI
;except SDI
BSF
TRISC, RX
;and RX
BSF
TRISB, INTO
;make RBO input for interrupt
MOVLW OxOO
MOVWF SSPSTAT
;middle read, active edge send
MOVLW Ox22
MOVWF SSPCON1
;master SPI enable, Fosc / 64
BCF
INTCON2,INTEDGO ;make INTO negative-edge
;triggered
BSF
INTCON,INTOIE
;enable INTO
MOVLW B'00100000' ;enable transmit and choose low baud
MOVWF TXSTA
;write to reg
MOVLW D'15'
;9600 bps (Fosc / (64 * Speed) - I}
MOVWF SPBRG
;write to reg
626
BCF
TRISC, TX ;make TX pin of PORTC an output pin
BSF
RCSTA, SPEN
;enable the serial port
BSF
INTCON,GIE
;enable interrupts globally
;-- send control byte to enable write
BSF
PORTC,RC2
;enable the RTC
CALL SDELAY
MOVLW Ox8F
;control register
CALL SPI
MOVLW OxO
;clear WP bit for write
CALL SPI
BCF
PORTC, RC2
;disable RTC
CALL SDELAY
send the data
BSF
PORTC, RC2 ;enable for multibyte write
MOVLW Ox87
;AlarmO address
CALL SPI
i8end address
jalarm at 8 seconds
MOVLW Ox08
jsend second
CALL SPI
MOVLW Ox80
;once-per-minute
CALL SPI
;send minute
MOVLW Ox80
;once-per-minute
CALL SPI
i8end hour
MOVLW Ox80
ionce-per-minute
CALL SPI
;send day
BCF PORTC,RC2
;end of multibyte write
CALL SDELAY
;-- send control byte to enable INTO
BSF
PORTC, RC2
; enable the RTC
CALL SDELAY
MOVLW Ox8F
;control register of DS1306
CALL SPI
MOVLW Ox01
;enable INTO pin of DS1306
CALL SPI
BCF PORTC,RC2
;disable RTC
CALL SDELAY
LOOP BRA LOOP
;wait for interrupt
;-- service AlarmO
INTO ISR
BS F
PORTC, RC2
;enable the RTC
CALL SDELAY
MOVLW Ox8F
;control register
CALL SPI
MOVLW Ox04
;1 Hz on, AlarmO off
CALL SPI
BCF PORTC,RC2
;disable RTC
CALL SDELAY
;-- send AlarmO seconds to reset alarm
BSF
PORTC, RC2
; enable the RTC
CALL SDELAY
MOVLW Ox87
;AlarmO seconds register
CALL SPI
CHAPTER 16: SPI PROTOCOL AND DS1306 RTC INTERFACING
627
MOVLW Ox08
jat 8 seconds
CALL SPI
BCF PORTC,RC2
;disable RTC
CALL SDELAY
;-- begin displaying
MOVLW upper (MESSAGE)
MOVWF TBLPTRU
MOVLW high (MESSAGE)
MOVWF TBLPTRH
MOVLW low (MESSAGE)
MOVWF TBLPTRL
NEXT TBLRD*+
;read the characters
MOVF TABLAT, W
;place it in WREG
IORLW OxO
BZ
OVER
; if end of line, start over
CALL TRANS
; send char to serial port
BRA NEXT
; repeat for the next character
;-- send control byte to enable INTO
OVER BSF
PORTC, RC2
; enable the RTC
CALL SDELAY
MOVLW Ox8F
icontrol register
CALL SPI
MOVLW Ox01
;1 Hz off, AlarmO on
CALL SPI
BCF PORTC,RC2
;disable RTC
CALL SDELAY
BCF
INTCON,INTOIF
RETFIE
;-- SPI subroutine
;-- serial data transfer subroutine
;-- delay for SPI communications
RETURN;SEE PREVIOUS PROGRAMS FOR ABOVE SUBROUTINES
;--message to be displayed upon interrupt
MESSAGE:
DB
OxOA, OxOD, "Yes" , 0
END
The following is the C version of the above program.
//Program 16-6C
#include <p18f458.h>
//INSERT FUNCTION PROTOTYPES
#pragma interrupt chk_isr //used for high priority interrupt only
void chk_isr (void)
if (INTCONbits.INTOIF==l)//INTO caused interrupt?
INTO ISR( );
//Yes. Execute INTO program
}
#pragma code My_HiPrio_Int=Ox0008 //high-priority interrupt
void My_HiPrio_Int (void)
{
628
asm
GOTO chk isr
endasm
}
#pragma code
void main (void)
(
11--
initialize SPI, INTO, and USART
TRISC=Ox90;
Ilmake PORTC output, except SDI and RX
TRISBbits.TRISBO=l;
Ilmake RBO input for interrupt
SSPSTAT=OxO;
Ilmiddle read, active edge send
SSPCON1=Ox22;
Ilmaster SPI enable, Fosc I 64
INTCON2bits.INTEDGO=0;
Ilmake INTO negative edge
Iitriggered
INTCONbits.INTOIE=l;
lienable INTO
TXSTA=Ox20;
lienable transmit and choose low baud
SPBRG=15;
119600 bps (Fosc I (64 * Speed) - 1)
RCSTAbits.SPEN=l;
lienable the serial port
lienable interrupts globally
INTCONbits.GIE=l;
to
enable
write
11-- send control byte
PORTCbits.RC2=1;
lienable the RTC
MSDelay (1) ;
SPI(Ox8F) ;
Ilcontrol register address
SPI(OxO) ;
lienable write
PORTCbits.RC2=0;
Iidisable RTC
MSDelay (1) ;
11-- send the data
PORTCbits.RC2=1;
lienable the RTC
MSDelay (1) ;
SPI(Ox87);
IIAlarmO address
SPI(Ox08);
Iialarm at 8 seconds
SPI(Ox80);
Iionce-per-minute
Iionce-per-minute
SPI (Ox80);
Iionce-per-minute
SPI (Ox80);
PORTCbits.RC2=0;
Iidisable RTC
MSDelay(l) ;
11-- send control byte to enable INTO
PORTCbits.RC2=1;
lienable the RTC
MSDelay(l) ;
SPI (Ox8F) ;
Ilcontrol register
SPI (Ox01) ;
lienable INTO
PORTCbits.RC2=0;
Iidisable RTC
MSDelay(l) ;
while(l);
Ilwait for interrupt
}
11-- service AlarmO
void INTO ISR ()
unsigned char mess []
unsigned char i;
PORTCbits.RC2=1;
= {OxOD OxOA, 1 Y 1 ,rE r , r S I ,O} ;
I
lienable the RTC
CHAPTER 16: SPI PROTOCOL AND DS1306 RTC INTERFACING
629
MSDelay(l) ;
SPI(Ox8F) ;
Ilcontrol register
SPI(Ox04);
III Hz on, AlarmO off
PORTCbits.RC2=O;
Iidisable RTC
MSDelay(l) ;
11-- send AlarmO seconds to reset alarm
PORTCbits.RC2=1;
lienable the RTC
MSDelay(l) ;
SPI(Ox87) ;
IIAlarmO seconds register
SPI(Ox08) ;
Ilat 8 seconds
PORTCbits.RC2=O;
Iidisable RTC
MSDelay(l) ;
11-- begin sending the data
for(i=O;mess [i] !=O;i++)
TRANS(mess[i]) ;
11-- send control byte to enable INTO
PORTCbits.RC2=1;
lienable the RTC
MSDelay (1) ;
SPI (Ox8F) ;
Ilcontrol register
SPI(Ox01);
III Hz offbits. AlarmO on
PORTCbits.RC2=O;
Iiturn off RTC
INTCONbits.INTOIF=O;
}
II--SEE PREVIOUS EXAMPLES FOR SUBROUTINES
In the last program, we send a message to the serial port to indicate that the
alarm has occurred. We can use the 32 kHz output to sound an actual alarm.
Because 32 kHz is too high a frequency for human ears, however, we can use multiple D flip flops to bring down the frequency. See Figure 16-16. The modification
of Program 16-6 for Figure 16-16 is left to the reader.
A
PIC 18F452/458
DS1306
SDI
SDO
SCLK
CE
I
I
I
~·:'I~ffJll r-'I. ~~r-"I
1-==_
-, - -, _.
Figure 16-16. DS1306 Connection to PIC1S with Buzzer Control
Review Questions
I.
2.
3.
4.
5.
Which bit of the Control register belongs to the I-Hz pin?
True or false. The INTO pin is an input for the DS 1306.
True or false. The INTO pin is active-LOW.
Which bit of the Control register belongs to the Alarml interrupt?
Give the address locations for Alarm!.
630
SUMMARY
This chapter began by describing the SPI bus connection and protocol. We
also discussed the function of each pin of the DS 1306 RTC chip. The DS 1306 can
be used to provide a real-time clock and dates for many applications. Various features of the RTC were explained, and numerous programming examples were
given.
PROBLEMS
SECTION 16.1: SPI BUS PROTOCOL
1.
2.
3.
4.
5.
6.
7.
True or false. The SPI bus needs an external clock.
True or false. The SPI CE is active-LOW.
True or false. The SPI bus has a single Din pin.
True or false. The SPI bus has multiple Dout pins.
True or false. When the SPI device is used as a slave, the SCLK is an input pin.
True or false. In SPI devices, data is transferred in 8-bit chunks.
True or false. In SPI devices, each bit of information (data, address) is transferred with a single clock pulse.
8. True or false. In SPI devices, the 8-bit data is followed by an 8-bit address.
9. In term of data pins, what is the difference between the SPI and 3-wire connections?
10. How does the SPI protocol distinguish between the read and write cycles?
SECTION 16.2: DS1306 RTC INTERFACING AND PROGRAMMING
11. The DS 1306 DIP package is a(n) ~_-pin package.
12. Which pin is assigned as primary Vee?
13. In the DS 1306, how many pins are designated as address/data pins?
14. True or false. The DS 1306 needs an external crystal oscillator.
15. True or false. The DS1306's crystal oscillator and heat affect the time-keeping
accuracy.
16. In DS 1306, what is the maximum year that it can provide?
17. Describe the functions of pins SDI, SDO, and SCLK.
18 CE is an
(input, output) pin.
19. The CE pin is normally
(LOW, HIGH) and needs a
(LOW,
HIGH) signal to be activated.
20. Who keeps the contents of the DS 1306 time and date registers if power to the
primary Vee pin is cut off?
21. Vbat pin stands for
and is an
(input, output) pin.
22. For the DS1306 chip, pin Vcc2 is connected to _~ (Vee> GND).
23. SERMODE is an
(input, output) pin and it is connected to _ _ for
SPI mode.
24. Vcel is an ____ (input, output) pin and is connected to _ _ voltage.
25. I-Hz is an
(input, output).
CHAPTER 16: SPI PROTOCOL AND DS1306 RTC INTERFACING
631
26.
27.
28.
29.
INTO is an
(input, output) pin.
32KHz is an
(input, output) pin.
INTI is an
(input, output) pin.
OS 1306 has a total of _ _bytes oflocations. Give the addresses for read and
write operations.
30. What are the contents of the OS 1306 time and date registers if power to the
Vee pin is lost?
31. What are the contents of the general-purpose RAM locations if power to the
Veel is lost?
32. When does the OS1306 switch to a battery energy source?
33. What are the addresses assigned to the real-time clock (time) registers?
34. What are the addresses assigned to the calendar?
35. Which register is used to set the AM/PM mode? Give the bit location of that
register.
36. Which register is used to set the 24-hour mode? Give the bit location of that
register.
37. At what memory location does the DS1306 store the year 2007?
38. What is the address of the last location of RAM for the DS \306?
39. True or false. The DS\306 provides data in BCD format only.
40. Write a program to get the year data in BCD and send it to ports PORTB and
PORTD.
41. Write a program to get the hour and minute data in BCD and send it to ports
PORTB and PORTD.
42. Write a program to set the time to 9:15:05 PM.
43. Write a program to set the time to 22:47:19.
44. Write a program to set the date to May 14,2009.
45. What are the roles of Vb at and Vcc2?
SECTION 16.3: DS\306 RTC PROGRAMMING IN C
46. Write a C program to display the time in AM/PM mode.
47. Write a C program to get the year data in BCD and send it to ports PORTB and
PORTD.
48. Write a C program to get the hour and minute data and send it to ports PORTB
and PORTD.
49. Write a C program to set the time to 9: 15:05 PM.
50. Write a C program to set the time to 22:47: 19.
51. Write a C program to set the date to May 14,2009.
52. In Question 51, how does the RTC keep track of the century?
SECTION 16.4: ALARM AND INTERRUPT FEATURES OF THE DS\306
(input, output) pin and active(LOW, HIGH).
53. INTO is an
54. I-Hz is an
(input, output) pin.
55. Give the bit location of the Control register belonging to the alarm interrupt.
Show how to enable it.
632
56. Give the bit location of the Control register belonging to the I-Hz pin. Show
how to enable it.
57. Give the bit location of the Status register belonging to the AlannO interrupt.
58. Give the bit location of the Status register belonging to the Alannl interrupt.
59. True or False. For the 32KHz output pin, the frequency is set and cannot be
changed.
60. Give sources of interrupts that can activate the INTI pin.
61. Why do we want to direct the AIEO (AlannO flag) to an IRQ pin?
62. What is the difference between the IRQFO and AIEO bits?
63. What is the difference between the IRQFI and AIEl bits?
64. How do we allow the square wave to come out of the I-Hz pin?
65. Which register is used to set the once-per-second Alannl?
66. Explain how the IRQIF pin is activated due to the once-per-minute alann
option.
ANSWERS TO REVIEW QUESTIONS
SECTION 16.1: SPI BUS PROTOCOL
1.
2.
3.
4.
S.
True
True
False
False
In single-byte mode, after each byte, the CE pin must go LOW before the next cycle. In burst
mode, the CE pin stays HIGH for the duration of the burst (multibyte) transfer.
SECTION 16.2: DS1306 RTC INTERFACING AND PROGRAMMING
1.
2.
3.
4.
S.
6.
True. Only ifVbat is connected to an external battery.
7
96
True
Pin II is SCLK.
False. SERMODE ~ Vcc
SECTION 16.3: DS1306 RTC PROGRAMMING IN C
1.
2.
3.
4.
S.
6.
True
0-6
20-7FH
True
False
False
SECTION 16.4: ALARM AND INTERRUPT FEATURES OF THE DS1306
1.
2.
3.
4.
S.
Bit 2
False
True
Bit 1
Byte addresses of OB-OE (in hex) for read and 8B-8E (in hex) for write
CHAPTER 16: SPI PROTOCOLANO OS1306 RTC INTERFACING
633
CHAPTER 17
MOTOR CONTROL:
RELAY, PWM, DC, AND
STEPPER MOTORS
635
This chapter discusses motor control and shows PIC 18 interfacing with
relays, optoisolators, stepper motors, and DC motors. In Section 17.1, the basics
of relays and optoisolators are described. Then we show their interfacing with the
PICI8. In Section 17.2, stepper motor interfacing with the PICl8 is shown. The
characteristics of DC motors are discussed in Section 17.3, along with their interfacing to the PIC 18. We will also discuss the topic of PWM (pulse width modulation). In Section 17.4, the CCP feature of PICI8 is used to control DC motors,
while the ECCP usage in motor control is shown in Section 17.5. We use both
Assembly and C in our programming examples.
SECTION 17.1: RELAYS AND OPTOISOLATORS
This section begins with an overview of the basic operations of electromechanical relays, solid-state relays, reed switches, and optoisolators. Then we
describe how to interface them to the PICI8. We use both Assembly and C language programs to demonstrate their control.
Electromechanical relays
A relay is an electrically controllable switch widely used in industrial controls, automobiles, and appliances. It allows the isolation of two separate sections
of a system with two different voltage sources. For example, a +5 V system can be
isolated from a 120 V system by placing a relay between them. One such relay is
called an electromechanical (or electromagnetic) relay (EMR) as shown in Figure
17-1. The EMRs have three components: the coil, spring, and contacts. In Figure
17-1, a digital +5 V on the left side can control a 12 V motor on the right side without any physical contact between them. When current flows through the coil, a
magnetic field is created around the coil (the coil is energized), which causes the
armature to be attracted to the coil. The armature's contact acts like a switch and
closes or opens the circuit. When the coil is not energized, a spring pulls the armature to its normal state of open or closed. In the block diagram for electomechanical relays (EMR) we do not show the spring, but it does exist internally. There are
all types of relays for all kinds of applications. In choosing a relay the following
characteristics need to be considered:
I. The contacts can be normally open (NO) or normally closed (NC). In the NC
type, the contacts are closed when the coil is not energized. In the NO, the contacts are open when the coil is unenergized.
2. There can one or more contacts. For example, we can have SPST (single pole,
single throw), SPDT (single pole, double throw), and DPDT (double pole, double throw) relays.
3. The voltage and current needed to energize the coil. The voltage can vary from
a few volts to 50 volts, while the current can be from a few rnA to 20 rnA. The
relay has a minimum voltage, below which the coil will not be energized. This
minimum voltage is called the "pull-in" voltage. In the datasheet for relays we
might not see current, but rather coil resistance. The VIR will give you the pullin current. For example, ifthe coil voltage is 5 V, and the coil resistance is 500
ohms, we need a minimum of 10 rnA (5 V/500 ohms = \0 rnA) pull-in current.
636
4. The maximum DCi AC voltage and current that can be handled by the contacts.
This is in the range of a few volts to hundreds of volts, while the current can
be from a few amps to 40 A or more, depending on the relay. Notice the difference between this voltage/current specification and the voltage/current
needed for energizing the coil. The fact that one can use such a small amount
of voltage/current on one side to handle a large amount of voltage/current on
the other side is what makes relays so widely used in industrial controls.
Examine Table 17-1 for some relay characteristics.
Table 17-1: Selected DIP Relay Characteristics (www.Jameco.com)
Part No.
106462CP
138430CP
106471CP
138448CP
129875CP
Contact Form
SPST-NO
SPST-NO
SPST-NO
SPST-NO
DPDT
Coil Volts
5VDC
5VDC
12VDC
12 VDC
5VDC
---t
Coil Ohms
500
500
1000
1000
62.5
Contact Volts-Current
100 VDC-0.5 A
100 VDC-0.5 A
100 VDC-0.5 A
100 VDC-0.5 A
30VDC-I A
___
Common
Normally
Closed
I
~---
t
Normally
Open
Common
Normally
Open
(b) SPDT
(a) SPST
---l
---l
t
t
Normally
Closed
Common
Normally
Open
(c) DPDT
Figure 17-1. Relay Diagrams
CHAPTER 17: MOTOR CONTROL: RELAY, PWM, DC, AND STEPPER MOTORS
637
Driving a relay
Digital systems and microcontroller pins lack sufficient current to drive the
relay. While the relay's coil needs around 10 rnA to be energized, the microcontroller's pin can provide a maximum of 1-2 rnA current. For this reason, we place
a driver, such as the ULN2803, or a power transistor between the microcontroller
and the relay as shown in Figure 17-2.
+5V
+5V
+5V
PIC18F
ULN2803
10
2
+12V
106462
4.7k
18
RBO
6
8
9
-
-
Figure 17-2. PIC18 Connection to Relay
Program 17-1 turns the lamp on and off shown in Figure 17-2 by energizing and de-energizing the relay every few ms.
; Program 17-1
R3
SET
Ox20
R4
SET
Ox21
ORG OH
BCF TRISB,O
OVER BSF PORTB,O
CALL DELAY
BCF
PORTB,O
CALL DELAY
BRA OVER
DELAY MOVLW OxFF
MOVWF R4
MOVLW OxFF
D1
MOVWF R3
D2
NOP
NOP
DECF R3,F
BNZ D2
DECF R4,F
BNZ
D1
RETURN
638
;set aside location Ox20 for R3
;loc. Ox21 for R4
;PORTB.O as output
;turn on the lamp
;turn off the lamp
Solid-state relay
Another widely used relay is the solid-state relay. See Table 17-2. In this
relay, there is no coil, spring, or mechanical contact switch. The entire relay is
made out of semiconductor materials. Because no mechanical parts are involved
in solid-state relays, their switching response time is much faster than that of
electromechanical relays. Another advantage of the solid-state relay is its greater
life expectancy. The life cycle for the electromechanical relay can vary from a few
hundred thousand to a few million operations. Wear and tear on the contact points
can cause the relay to malfunction after a while. Solid-state relays, however, have
no such limitations. Extremely low input current and small packaging make solidstate relays ideal for microprocessor and logic control switching. They are widely
used in controlling pumps, solenoids, alarms, and other power applications. Some
solid-state relays have a phase control option, which is ideal for motor-speed control and light-dimming applications. Figure 17-3 shows control of a fan using a
solid-state relay (SSR).
Table 17-2: Selected Solid-State Rela.l: Characteristics
Part No.
l43058CP
139053CP
l62341CP
l72591CP
175222CP
176647CP
PIC18F
RBO
Contact S~le
SPST
SPST
SPST
SPST
SPST
SPST
t
~www.Jameco.com2
Contact Volts
240VAC
240VAC
240VAC
60VDC
60VDC
120 VDC
Control Volts
4-32VDC
3-32VDC
3-32 VDC
3-32 VDC
3-32 VDC
3-32 VDC
Contact Current
3A
25A
lOA
2A
4A
5A
re
162341
c
1
4
~~
I
ZERO
VOLTAGE
CIRCUIT
r
FAN
2
..1
~J
T
FIgure 17-3. PIC18 Connection to a SolId-State Relay
CHAPTER 17: MOTOR CONTROL: RELAY, PWM, DC, AND STEPPER MOTORS
639
Reed switch
Another popular switch is the reed switch. When the reed switch is placed
in a magnetic field, the contact is closed. When the magnetic field is removed, the
contact is forced open by its spring. See Figure 17-4. The reed switch is ideal for
moist and marine environments where it can be submerged in fuel or water. Reed
switches are also widely used in dirty and dusty atmospheres because they are
tightly sealed.
M
A
G
N
E
T
REED SWITCH
(Closed)
LAMP
(ON)
REED SWITCH
(Open)
LAMP
(OFF)
Figure 17-4. Reed Switch and Magnet Combination
Optoisolator
In some applications we use an optoisolator (also called optocoupler) to
isolate two parts of a system. An example is driving a motor. Motors can produce
what is called back EMF, a high-voltage spike produced by a sudden change of
current as indicated in the V = Ldi/dt formula. In situations such as printed circuit
board design, we can reduce the effect of this unwanted voltage spike (called
ground bounce) by using decoupling capacitors (see Appendix C). In systems that
have inductors (coil winding), such as motors, a decoupling capacitor or a diode
will not do the job. In such cases we use optoisolators. An optoisolator has an LED
(light-emitting diode) transmitter and a photosensor receiver, separated from each
other by a gap. When current flows through the diode, it transmits a signal light
across the gap and the receiver produces the same signal with the same phase but
a different current and amplitude. See Figure 17-5. Optoisolators are also widely
used in communication equipment such as modems. This device allows a computer to be connected to a telephone line without risk of damage from power surges.
The gap between the transmitter and receiver of optoisolators prevents the electrical current surge from reaching the system.
640
IL74
OPTOISOLATOR
ILQ74
OPTOISOLATOR
ILD74
OPTOISOLATOR
6
16
8
2
5
2
7
3
4
3
6
4
5
2
15
3
14
4
13
5
12
6
11
7
10
8
9
Figure 17-5. Optoisolator Package Examples
Interfacing an optoisolator
The optoisolator comes in a small Ie package with four or more pins.
There are also packages that contain more than one optoisolator. When placing an
optoisolator between two circuits, we must use two separate voltage sources, one
for each side, as shown in Figure 17-6. Unlike relays, no drivers need to be placed
between the microcontroller/digital output and the optoisolators.
ILD74
OPTOISOLATOR
PIC18F
8
2
3
RBO~--------i-,
4
7
6
+12V
LAMP
5
330
+5V
Figure 17-6. Controlling a Lamp via an Optoisolator
CHAPTER 17: MOTOR CONTROL: RELAY, PWM, DC,AND STEPPER MOTORS
641
Review Questions
I. Give one application where would you use a relay.
2. Why do we place a driver between the microcontroller and the relay?
3. What is an NC relay?
4. Why are relays that use coils called electromechanical relays?
5. What is the advantage of a solid-state relay over EMR?
6. What is the advantage of an optoisolator over an EM relay?
SECTION 17.2: STEPPER MOTOR INTERFACING
This section begins with an overview of the basic operation of stepper
motors. Then we describe r - - - - - - - - - - - - - - - - - - - ,
how to interface a stepper
A
motor to the PIC 18. Finally,
we use Assembly language
programs to demonstrate control of the angle and direction
of stepper motor rotation.
Stepper motors
A stepper motor is a
widely used device that translates electrical pulses into
mechanical movement. In
applications such as disk
drives, dot matrix printers,
B
and robotics, the stepper
motor is used for position
control. Stepper motors commonly have a permanent magA
net rotor (also called the
shaft) surrounded by a stator
(see Figure 17-7). There are
Average
also steppers called variable
North
reluctance stepper motors that
S
do not have a permanent magnet rotor. The most common
stepper motors have four stator windings that are paired
N
Average
with a center-tapped common
South
as shown in Figure 17-8. This
type of stepper motor is commonly referred to as a fourphase or unipolar stepper
B
motor. The center tap allows a
change of current direction in LF"'ig-u-r-e-l=-=7:--7=-.-:R=-o-t-o-r-:-A""Jj-g-nm-e-nt--------..l
§
8
642
each of two coils when a winding is
grounded, thereby resulting in a polari-
-=-::t=~:::;:::;:::::~
ty change of the stator. Notice that while
a conventional motor shaft runs freely, ~ _
1--\---the stepper motor shaft moves in a fixed C
COM
repeatable increment, which allows one D =~=~~~::::~I-~-C-O-M
to move it to a precise position. This
repeatable fixed movement is possible
as a result of basic magnetic theory !.:::-_----::=-:"...-,,,....,,.--=:--:::-_ _ _ _--'
where poles of the same polarity repel Figure 17-8. Stator Winding
and opposite poles attract. The direction Configuration
of the rotation is dictated by the stator
poles. The stator poles are determined by the current sent through the wire coils.
As the direction of the current is changed, the polarity is also changed causing the
reverse motion of the rotor. The stepper motor discussed here has a total of six
leads: four leads representing the four stator windings and two commons for the
center-tapped leads. As the sequence of power is applied to each stator winding,
the rotor will rotate. There are several widely used sequences, each of which has
a different degree of precision. Table 17-3 shows a two-phase, four-step stepping
sequence.
Note that although we can start with any of the sequences in Table 17-3,
once we start we must continue in the proper order. For example, if we start with
step 3 (0110), we must continue in the sequence of steps 4, 1, 2, etc.
Table 17-3: Normal Four-Step Sequence
Clockwise Ste!! #
1
2
3
4
~
Winding A
I
1
0
0
Winding B
0
1
1
0
Winding C
0
0
1
I
Windinll D Counter1
0
0
I
dOT
Step angle
How much movement is associated with a single step? This depends on
the internal construction of the motor, in particular the number of teeth on the stator and the rotor. The step angle is the minimum degree of rotation associated with
a single step. Various motors have different step angles. Table 17-4 shows some
step angles for various motors. In
Table 17-4, notice the term steps per Table 17-4: Stepper Motor Step Angles
revolution. This is the total number of
steps needed to rotate one complete
rotation or 360 degrees (e.g., 180
steps x 2 degrees = 360).
It must be noted that perhaps
contrary to one's initial impression, a
stepper motor does not need more terminalleads for the stator to achieve
smaller steps. All the stepper motors
Step Angle
Steps per Revolution
0.72
500
1.8
200
2.0
180
2.5
144
5.0
72
7.5
48
.:;.15::....-_ _ _ _ _ _--=2~4_ _ _ _ __
CHAPTER 17: MOTOR CONTROL: RELAY, PWM, DC, AND STEPPER MOTORS
643
discussed in this section have four leads for the stator winding and two COM wires
for the center tap. Although some manufacturers set aside only one lead for the
common signal instead of two, they always have four leads for the stators. See
Example 17-1. Next we discuss some associated terminology in order to understand the stepper motor further.
Example 17-1
Describe the PICI8 connection to the stepper motor of Figure 17-9 and code a program
to rotate it continuously.
Solution:
The following steps show the PICI8 connection to the stepper motor and its programming:
1. Use an ohmmeter to measure the resistance of the leads. This should identifY which
COM leads are connected to which winding leads.
2. The common wire( s) are connected to the positive side of the motor's power supply.
In many motors, +5 V is sufficient.
3. The four leads of the stator winding are controlled by four bits of the PICI8 port
(RBO--RB3). Because the PIC 18 lacks sufficient current to drive the stepper motor
windings, we must use a driver such as the ULN2003 to energize the stator. Instead
of the ULN2003, we could have used transistors as drivers, as shown in Figure
17-11. However, notice that if transistors are used as drivers, we must also use
diodes to take care of inductive current generated when the coil is tnrned off. One
reason that using the ULN2003 is preferable to the use of transistors as drivers is
that the ULN2003 has an internal diode to take care of back EMF.
MyReg
R2
BACK
SET
Ox30
SET
Ox20
CLRF TRISB
MOVLW Ox66
MOVWF MyReg
MOVFF MyReg,PORTB
RRNCF MyReg,F
CALL DELAY
BRA
BACK
;loc 30H for MyReg
;loc 20H for R2 Reg
;Port B as output
;load step sequence
;issue sequence to motor
;rotate right clockwise
;wait
;keep going
DELAY
Dl
MOVLW OxFF
MOVWF R2
NOP
DECF R2,F
BNZ Dl
RETURN
END
Change the value of DELAY to set the speed of rotation.
We can use the single-bit instructions BSF and BCF instead of RRNCF to create the
sequences.
644
___To stepperI motor
+5
4.7k
PICI8F
suppy
!5
.~
4.7k
4.7k
4.7k
RBO
"
RBI
"
RB2
RB3
"
:
:
..
:::v
Use one power supply for
Unipolar
Stepper Motor
ULN2003
9
;
:
1
0
'1111'
I""
the motor and ULN 2003
and another for the 8051
-+5.
Figure 17-9. PIC1S Connection to Stepper Motor
Steps per second and rpm relation
The relation between rpm (revolutions per minute), steps per revolution,
and steps per second is as follows.
Steps per second =
rpm x Steps per revolution
60
The 4-step sequence and number of teeth on rotor
The switching sequence shown earlier in Table 17-3 is called the 4-step
switching sequence because after four steps the same two windings will be "ON".
How much movement is associated with these four steps? After completing every
four steps, the rotor moves only one tooth pitch. Therefore, in a stepper motor with
200 steps per revolution, the rotor has 50 teeth because 4 x 50 = 200 steps are needed to complete one revolution. This leads to the conclusion that the minimum step
angle is always a function of the number of teeth on the rotor. In other words, the
smaller the step angle, the more teeth the rotor passes. See Example 17-2.
Example 17-2
Give the number of times the four-step sequence in Table 17-3 must be applied to a
stepper motor to make an 80-degree move if the motor has a 2-degree step angle.
Solution:
A motor with a 2-degree step angle has the following characteristics:
Step angle:
2 degrees
Steps per revolution:
180
45
Movement per 4-step sequence: 8 degrees
Number of rotor teeth:
To move the rotor 80 degrees, we need to send 10 consecutive 4-step sequences,
because lOx 4 steps x 2 degrees = 80 degrees.
CHAPTER 17: MOTOR CONTROL: RELAY, PWM, DC, AND STEPPER MOTORS
645
Looking at Example 17-2, one might wonder what happens if we want to
move 45 degrees, because the steps are 2 degrees each. To allow for finer resolutions, all stepper motors allow what is called an 8-step switching sequence. The 8step sequence is also called ha/.fstepping, because in the 8-step sequence each step
is half of the normal step angle. For example, a motor with a 2-degree step angle
can be used as a I-degree step angle ifthe sequence of Table 17-5 is applied.
Table 17-5: Half-Step 8-Step Sequence
Clockwise Stel! # Winding A
I
I
2
I
I
3
4
0
5
0
6
0
7
0
8
0
Winding B
0
0
I
I
I
0
0
0
Winding C
0
0
0
0
I
1
1
0
WindingD CounterI
clockwise
0
0
0
0
0
1
1
t
Motor speed
The motor speed, measured in steps per second (steps/s), is a function of
the switching rate. Notice in Example 17-1 that by changing the length of the time
delay loop, we can achieve various rotation speeds.
Holding torque
The following is a definition of holding torque: "With the motor shaft at
standstill or zero rpm condition, the amount of torque, from an external source,
required to break away the shaft from its holding position. This is measured with
rated voltage and current applied to the motor." The unit of torque is ounce-inch
(or kg-em).
Wave drive 4-step sequence
In addition to the 8-step and the 4-step sequences discussed earlier, there is
another sequence called the wave drive 4-step sequence. It is shown in Table 17-6.
Notice that the 8-step sequence of Table 17-5 is simply the combination of the
wave drive 4-step and normal 4-step normal sequences shown in Tables 17-6 and
17 -3, respectively. Experimenting with the wave drive 4-step sequence is left to
the reader.
Table 17-6: Wave Drive 4-Step Sequence
Clockwise Stel! # Winding A Winding B Winding C Winding D Counterclockwise
1
1
0
0
0
2
0
1
0
0
3
0
0
1
0
4
0
0
0
1
l
646
t
Table 17-7: Selected Stel!l!er Motor Characteristics
Part No.
l5l86lCP
l71601CP
164056CP
Ste~
Anllie
7.5
3.6
7.5
Drive Sl'stem
uniEolar
uniEolar
biEolar
~www.Jameco.com~
Volts Phase Resistance
5V
9 ohms
7V
20 ohms
6 ohms
5V
Current
550 rnA
350 rnA
800 rnA
Unipolar versus bipolar stepper motor interface
There are three common types of stepper motor interfacing: universal,
unipolar, and bipolar. They can be identified by the number of connections to the
motor. A universal stepper motor has eight, while the unipolar has six and the bipolar has four. The universal stepper motor can be configured for all three modes,
while the unipolar can be either unipolar or bipolar. Obviously the bipolar cannot
be configured for universal nor unipolar mode. Table 17-7 shows selected stepper
motor characteristics. Figure 17-10 shows the basic internal connections of all
three type of configurations.
Unipolar stepper motors can be controlled using the basic interfacing
shown in Figure 17-11, whereas the bipolar stepper requires H-Bridge circuitry.
Bipolar stepper motors require a higher operational current than the unipolar; the
advantage of this is a higher holding torque.
(a) Universal
(b) Unipolar
(c) Bipolar
Figure 17-10. Common Stepper Motor Types
Using transistors as drivers
Figure 17-11 shows an interface to a unipolar stepper motor using transistors. Diodes are used to reduce the back EMF spike created when the coils are
energized and de-energized, similar to the electromechanical relays discussed earlier. TIP transistors can be used to supply higher current to the motor. Table 17-8
lists the common industrial Darlington transistors. These transistors can accommodate higher voltages and currents.
CHAPTER 17: MOTOR CONTROL: RELAY, PWM, DC,AND STEPPER MOTORS
647
+V Motor
4.7k
A
B
To Stepper
Motor
C
~4--C:>D
Use TIP120
Darlington transistor if
the motor needs
several amps.
L.-..../
COM
L.-""/
COM
Figure 17-11. Using Transistors for Stepper Motor Driver
Table 17-8: Darlington Transistor Listing
NPN
PNP
TIP II 0
TIPIII
TIP 11 2
TIP120
TIPI21
TIPI22
TIPI40
TIPI41
TIPI42
TIPI15
TIPl16
TIP II 7
TIPI25
TIPI26
TIPI27
TIPI45
TIPI46
TIPI47
648
V ceo {volts}
60
80
100
60
80
100
60
80
100
Ic
{am~s}
2
2
2
5
5
5
10
10
10
hfe {common}
1000
1000
1000
1000
1000
1000
1000
1000
1000
Controlling stepper motor via optoisolator
In the first section of this chapter we examined the optoisolator and its use.
Optoisolators are widely used to isolate the stepper motor's EMF voltage and keep
it from damaging the digital/microcontroller system. This is shown in Figure
17-12. See Examples 17-3 and 17-4.
·5
J
·12
470
470
470
PIC18F
<70
,
,
RBO
RBI
RB2
RB3
3
4
6
5
8
7
The optoisolator provides
additional protection of the
8051.
ILQ74
Opta
"
1k
"
"
~
1k
"v
~
10
1k
fL
1k
~
"
Unipolar
Stepper Motor
ULN2803
10
~
v
l
;
~
:::
0
"'" I" "
Use one power supply for
the molorand ULN2003
and another for the 8051.
.12
Figure 17-12. Controlling Stepper Motor via Optoisolator
Example 17-3
A switch is connected to pin RD7 (PORTD.7). Write a program to monitor the status of
SW and perform the following:
(a) If SW = 0, the stepper motor moves clockwise.
(b) If SW = 1, the stepper motor moves counterclockwise.
Solution:
MyReg
BACK
OVER
;loc 30H for MyReg
SET Ox30
;RD7 as input pin
BSF TRISD,RD7
CLRF TRISB
;Port B as output
;load step sequence
MOVLW Ox66
MOVWF MyReg
;check the SW
BTFSS PORTD,RD7
BRA OVER
;It is high. Make it clockwise
MOVFF MyReg,PORTB
;issue sequence to motor
RRNCF MyReg,F
;rotate right clockwise
CALL DELAY
;wait
BRA BACK
;keep going
MOVFF MyReg,PORTB
;issue sequence to motor
RLNCF MyReg,F
;rotate left clockwise
;wait
CALL DELAY
BRA BACK
;keep going
CHAPTER 17: MOTOR CONTROL: RELAY, PWM, DC, AND STEPPER MOTORS
649
Stepper motor control with PIC18 C
The PICl8 C version of the stepper motor control is given below. In this
program we could have used « (shift left) and »(shift right) as was shown in
Chapter 7.
#include <p18f458.h>
void main ()
(
//PORTB as output
TRISB~OxO;
while(l)
(
PORTB ~ Ox66;
MSDelay(lOO) ;
PORTB ~ OxCC;
MSDelay(lOO) ;
PORTB ~ Ox99;
MSDelay(lOO) ;
PORTB ~ Ox33;
MSDelay(lOO) ;
}
Example 17-4
A switch is connected to pin RD7. Write a C program to monitor the status of SW and
perform the following:
(a) If SW = 0, the stepper motor moves clockwise.
(b) If SW = I, the stepper motor moves counterclockwise.
Solution:
#include <p18f458.h>
#define SW PORTDbits.RD7
void MSDelay(int ms);
void main ()
(
//RD7 as input pin
//PORTB as output
TRISD~Ox80;
TRISB~OxO;
while (1)
{
i f (SW
~~
0)
(
PORTB ~ Ox66;
MSDelay(lOO) ;
PORTB ~ OxCC;
MSDelay(lOO) ;
PORTB ~ Ox99;
MSDelay(lOO) ;
PORTB ~ Ox33;
MSDelay(lOO) ;
}
else
(
PORTB ~ Ox66;
MSDelay(lOO) ;
PORTB ~ Ox33;
650
Example 17-4 Cont.
MSDelay(lOO) ;
PORTB = Ox99;
MSDelay(lOO) ;
PORTB = OxCC;
MSDelay(lOO) ;
}
}
void MSDelay(unsigned int value)
{
unsigned int X, Yi
for(x=O;x<1275;x++)
for(y=O;y<value;y++) ;
}
Review Questions
1. Give the 4-step sequence ofa stepper motor if we start with OlIO.
2. A stepper motor with a step angle of 5 degrees has __ steps per revolution.
3. Why do we put a driver between the microcontroller and the stepper motor?
SECTION 17.3: DC MOTOR INTERFACING AND PWM
This section begins with an overview of the basic operation of DC motors.
Then we describe how to interface a DC motor to the PICI8. Finally, we use
Assembly and C language programs to demonstrate the concept of pulse width
modulation (PWM) and show how to control the speed and direction of a DC
motor.
DC motors
A direct current (DC) motor is another widely used device that translates
electrical pulses into mechanical movement. In the DC motor we have only + and
- leads. Connecting them to a DC voltage source moves the motor in one direction. By reversing the polarity, the DC motor will move in the opposite direction.
One can easily experiment with the DC motor. For example, small fans used in
many motherboards to cool the CPU are run by DC motors. By connecting their
leads to the + and - voltage source, the DC motor moves. While a stepper motor
moves in steps of I to IS degrees, the DC motor moves continuously. In a stepper
motor, if we know the starting position we can easily count the number of steps the
motor has moved and calculate the final position of the motor. This is not possible
in a DC motor. The maximum speed of a DC motor is indicated in rpm and is given
in the data sheet. The DC motor has two rpms: no-load and loaded. The manufacturer's data sheet gives the no-load rpm. The no-load rpm can be from a few thousand to tens ofthousands. The rpm is reduced when moving a load and it decreases as the load is increased. For example, a drill turning a screw has a much lower
rpm speed than when it is in the no-load situation. DC motors also have voltage
and current ratings. The nominal voltage is the voltage for that motor under normal conditions, and can be from I to 150 V, depending on the motor. As we
increase the voltage, the rpm goes up. The current rating is the current consumpCHAPTER 17: MOTOR CONTROL: RELAY, PWM, DC,AND STEPPER MOTORS
651
tion when the nominal voltage is applied with no load, and can be from 25 rnA to
a few amps. As the load increases, the rpm is decreased, unless the current or voltage provided to the motor is increased, which in turn increases the torque. With a
fixed voltage, as the load increases, the current (power) consumption of a DC
motor is increased. If we overload the motor it will stall, and that can damage the
motor due to the heat generated by high current consumption.
Unidirectional control
Figure 17-13 shows the DC motor rotation for clockwise (CW) and counterclockwise (CCW) rotations. See Table 17-9 for selected DC motors.
Table 17-9: Selected DC Motor Characteristics
Part No.
154915CP
154923CP
I 77498CP
181411CP
Nominal Volts
3V
3V
4.5 V
5V
Volt RanGe
1.5-3 V
1.5-3 V
3-14 V
3-14 V
1www.Jameco.com~
Current
0.070 A
0.240 A
0.150 A
0.470 A
RPM
5,200
16,000
10,300
10,000
-- +
Clockwise
Rotation
Torgue
4.0 g-cm
8.3 g-cm
33.3 g-cm
18.8 g-cm
+
CounterClockwise
Rotation
Figure 17-13. DC Motor Rotation (Permanent Magnet Field)
Bidirectional control
With the help of relays or some specially designed chips we can change the
direction of the DC motor rotation. Figures 17-14 through 17-17 show the basic
concepts ofR-Bridge control of DC motors.
Figure 17-14 shows the connection of an R-Bridge using simple switches.
All the switches are open, which does not allow the motor to tum.
652
+V
SWITCH
SWITCH
1
2
SWITCH
3
SWITCH
4
MOTOR NOT
RUNNING
Figure 17-14. "-Bridge Motor Configuration
Figure 17-15 shows the switch configuration for turning the motor in one
direction. When switches 1 and 4 are closed, current is allowed to pass through the
motor.
+V
SWITCH
Current
Flow
SWITCH
1
2
SWITCH
3
SWITCH
4
CLOCKWISE
DIRECTION
Figure 17-15. H-Bridge Motor Clockwise Configuration
Figure 17-16 shows the switch configuration for turning the motor in the
opposite direction from the configuration of Figure 17-15. When switches 2 and 3
are closed, current is allowed to pass through the motor.
CHAPTER 17: MOTOR CONTROL: RELAY, PWM, DC, AND STEPPER MOTORS
653
+V
Current
Flow
SWITCH
SWITCH
1
2
SWITCH
SWITCH
4
3
COUNTER
CLOCKWISE
DIRECTION
Figure 17-16. H-Bridge Motor Counterclockwise Configuration
Figure 17·17 shows an invalid configuration. Current flows directly to
ground, creating a short circuit. The same effect occurs when switches I and 3 are
closed or switches 2 and 4 are closed.
-+V
;
!
Jl
-
SWITCH
1
j
'-I
SWITCH
3
SWITCH
2
M
-
h
,....
SWITCH
.,
--
+
4
INVALID STAT E
(SHORT CIRCUIl)
Figure 17-17. H-Bridge in an Invalid Configuration
Table 17·\0 shows some of the logic configurations for the H·Bridge
design.
H-Bridge control can be created using relays, transistors, or a single IC
solution such as the L293. When using relays and transistors, you must ensure that
invalid configurations do not occur.
654
Table 17-10: Some H-Bridge Logic Configurations for Figure 17-14
Motor Operation
Off
Clockwise
Counterclockwise
Invalid
SW1
Open
Closed
Open
Closed
SW2
Open
Open
Closed
Closed
SW3
Open
Open
Closed
Closed
SW4
Open
Closed
Open
Closed
Although we do not show the relay control of an H-Bridge, Example 17-5
shows a simple program to operate a basic H-Bridge.
Example 17-5
A switch is connected to pin RD7 (PORTD.7). Using a simulator, write a program to
simulate the H-Bridge in Table 17-10. We must perform the following:
(a) IfDIR = 0, the DC motor moves clockwise.
(b) If DIR = 1, the DC motor moves counterclockwise.
Solution:
BCF TRISB,O
BCF TRISB,l
BCF TRISB,2
BCF TRISB,3
BSF TRISD,7
MONITOR:
BTFSS PORTD,7
BRA CLOCKWISE
BSF PORTB,O
BCF PORTB,l
BCF PORTB,2
BSF PORTB,3
BRA MONITOR
CLOCKWISE:
BCF PORTB,O
BSF PORTB,l
BSF PORTB,2
BCF PORTB,3
BRA MONITOR
;PORTB.O as output for switch 1
switch 2
.1
"
.2
switch 3
;
.3"
switch 4
; make PORTD. 7 an input DIR
1/
; switch
;switch
; switch
;switch
1
2
3
4
;switch 1
;switch 2
;switch 3
;switch 4
View the results on your simulator. This example is for simulation only
and should not be used on a connected system.
See http://www.MicroDigitalEd.com for additional information on using
H-Bridges.
Figure 17-18 shows the connection of the L293 to an PICI8. Be aware that
the L293 will generate heat during operation. For sustained operation of the motor,
use a heat sink. Example 17-6 shows control of the L293.
CHAPTER 17: MOTOR CONTROL: RELAY, PWM, DC, AND STEPPER MOTORS
655
:12V
·5
"" ''" ""
,
,
PICI8F
RBO
RBI
ILQ74
Oplo
·12
8
vee1
VCC2
L293
1
"
L.........2.,
~
1k
,•
I:!"
ill-
1k
RB2
+1~V
J16
01
ENA6LE
2
INPUT 1
?
INPUT 2
OUTPUT 1 3
OUTPUT 2
6
03
0'
1k
GNO
Use a separate power
supply for the motor and
L293 than for the PIC18F
PIC18F
02
M
4,5,12, 13
The optoisolator provides
additional protection of the
~
-!-
~
01,02.03, D4
are lN4004
.
FIgure 17-18. BIdIrectIonal Motor Control Usmg an L293 ChIp
Example 17-6
Figure 17-18 shows the connection of an L293. Add a switch to pin RD7 (PORTD.7).
Write a program to monitor the status of SW and perform the following:
(a) IfSW = 0, the DC motor moves clockwise.
(b) IfSW = 1, the DC motor moves counterclockwise.
Solution:
°
BCF
TRISB,
BCF
TRISB,l
BCF
TRISB,2
BSF
TRISD,7
BSF
PORTB,O
CHK
BTFSS PORTD, 7
CWISE
BRA
BCF
PORTB,l
BSF
PORTB,2
BRA
CHK
CWISE BSF
PORTB, 1
BCF
PORTB, 2
BRA
CHK
656
;enable the chip
;turn the motor counterclockwise
;turn motor clockwise
Pulse width modulation (PWM)
The speed of the motor depends on three factors: (a) load, (b) voltage, and
(c) current. For a given fixed load we can maintain a steady speed by using a
method called pulse width modulation (PWM). By changing (modulating) the
width of the pulse applied to the DC motor we can increase or decrease the amount
of power provided to the motor, thereby increasing or decreasing the motor speed.
Notice that, although the voltage has a fixed amplitude, it has a variable duty cycle.
That means the wider the pulse, the higher the speed. PWM is so widely used in
DC motor control that some microcontrollers come with the PWM circuitry
embedded in the chip. In such microcontrollers all we have to do is load the proper registers with the values of the high and low portions of the desired pulse, and
the rest is taken care of by the microcontroller. This allows the microcontroller to
do other things. For microcontrollers without PWM circuitry, we must create the
various duty cycle pulses using software, which prevents the microcontroller from
doing other things. The ability to control the speed of the DC motor using PWM
is one reason that DC motors are preferable over AC motors. AC motor speed is
dictated by the AC frequency of the voltage applied to the motor and the frequency is generally fixed. As a result, we cannot control the speed of the AC motor
when the load is increased. As was shown earlier, we can also change the DC
motor's direction and torque. See Figure 17-19 for PWM comparisons.
Jl
Y.POWER
25% DC
y, POWER
50% DC
o/.aPOWER
75% DC
~
FULL POWER
100% DC
~
n
U
n
U
n
U
L
Figure 17-19. Pulse Width Modulation Comparison
DC motor control with optoisolator
As we discussed in the first section of this chapter, the optoisolator is indispensable in many motor control applications. Figures 17-20 and 17-21 show the
connections to a simple DC motor using a bipolar and a MOSFET transistor.
Notice that the PIC 18 is protected from EMI created by motor brushes by using an
optoisolator and a separate power supply.
Figures 17-20 and 17-21 show optoisolators for control of single directional motor control, and the same principle should be used for most motor applications. Separating the power supplies of the motor and logic will reduce the possibility of damage to the control circuity.
CHAPTER 17: MOTOR CONTROL: RELAY, PWM, DC, AND STEPPER MOTORS
657
Figure 17-20 shows the connection of a bipolar transistor to a motor.
Protection of the control circuit is provided by the optoisolator. The motor and
PIC 18 use separate power supplies. The separation of power supplies also allows
the use of high-voltage motors. Notice that we use a decoupling capacitor across
the motor; this helps reduce the EMI created by the motor. The motor is switched
on by clearing bit Pl.O.
+12V
lN4004
i ..r-
00",=
+5V
PICI8F
330
ILD74
OPTOISOLATOR
1
RBO
2
8
¥~
U"
10k
g
'v
TIP120
',",
7
+12V
100k
..l
..!.
.!..
G~( .!..
.
.
.",
.
FIgure 17-20. DC Motor Connection usmg a Darlmgton TransIstor
Figure 17-21 shows the connection of a MOSFET transistor. The optoisolator protects the PICI8 from EMI. The zener diode is required for the transistor
to reduce gate voltage below the rated maximum value. See Example 17-7.
+12V
Figure 17-21. DC Motor Connection using a MOSFET Transistor
658
Example 17-7
Refer to the figure in this example. Write a program to monitor the status of the switch
and perform the following:
(a) IfPORTD.7 = I, the DC motor moves with 25% duty cycle pulse.
(b) IfPORTO.7 = 0, the DC motor moves with 50% duty cycle pulse.
Solution:
BCF TRISB,RBO
BSF TRISD,RD7
BCF PORTB,RBO
;PORTB.O as output
;PORTD.7 as input
;turn off motor
BTFSS PORTD,RD7
BRA
PWM 50
BSF PORTB,RBO
;high portion of pulse
CHK
CALL DELAY
BCF PORTB,RBO
;low portion of pulse
CALL DELAY
CALL DELAY
CALL DELAY
BRA
CHK
PWM 50
BSF PORTB,RBO
;high portion of pulse
CALL DELAY
CALL DELAY
BCF PORTB,RBO
;low portion of pulse
CALL DELAY
CALL DELAY
BRA CHK
+12V
'5V
4.7k
r'1
RD7
1N4004 -
O.M : ;;;
MOTOR
'5V
ILD74
330
OPTOISOLATOR
1
,
*~
7
]~(
.!
f2f2-
PIC18F
RBO
~
2
.2.
10k
V
TJP120
',"
+12V
100k
~
,.,.
CHAPTER 17: MOTOR CONTROL: RELAY, PWM, DC, AND STEPPER MOTORS
659
DC motor control and PWM using C
Examples 17-8 through 17-10 show the PIC18 C version of the earlier programs controlling the DC motor.
Example 17-8
Refer to Figure 17-18 for connection of the motor. A switch is connected to pin RD7.
Write a C program to monitor the status of SW and perform the following:
(a) If SW = 0, the DC motor moves clockwise.
(b) If SW = 1, the DC motor moves counterclockwise.
Solution:
#include <p18f458.h>
#define
#define
#define
#define
SW PORTDbits.RD7
ENABLE PORTBbits.RBO
MTR 1 PORTBbits.RB1
MTR-2 PORTBbits.RB2
void main ()
{
TRISD=Ox80;
TRISB=OxO;
SW = 1;
ENABLE = 0;
MTR_1 = 0;
MTR_2 = 0;
//make RD7 input pin
//make PORTB output
while (1)
{
ENABLE = 1;
if(SW == 1)
{
MTR 1
MTR 2
1·,
0;
MTR 1
MTR 2
1·,
}
else
{
}
} }
660
0;
Example 17-9
Refer to the figure in this example. Write a C program to monitor the status of SW and
perform the following:
(a) If SW = 0, the DC motor moves with 50% duty cycle pulse.
(b) If SW = 1, the DC motor moves with 25% duty cycle pulse.
Solution:
#include <p18f458.h>
#define SW PORTDbits.RD7
#define MTR PORTBbits.RBI
void MSDelay(unsigned int value);
void main()
{
//make RD7 input pin
//make RBI output pin
TRISD=Ox80;
TRISB=OxFD;
while (1)
{
if(SW == 1)
{
MTR = 1;
MSDelay(25) ;
MTR = 0;
MSDelay(75) ;
}
else
{
MTR = 1;
MSDelay(50) ;
MTR = 0;
MSDelay(50) ;
} }
void MSDelay(unsigned int value)
{
unsigned char x, y;
for(x=O; x<1275; x++)
for(y=O; y<value; y++);
}
+12V
.5V
1N4004
4.7k
.5V
~~
.~
A
0.1"
=~ ~OTO~
Y
ILD74
330
OPTOISOLATOR
RD7
10k
PIC18F
R80
."
TIP120
7
'+--t+12V
100k
CHAPTER 17: MOTOR CONTROL: RELAY, PWM, DC, AND STEPPER MOTORS
661
Example 17-10
Refer to Figure 17-20 for connection to the motor. Two switches are connected to pins
RDO and RDI. Write a C program to monitor the status of both switches and perform
the following:
SW2 (RDl) SWI (RDO)
DC motor moves slowly (25% duty cycle).
o
0
DC motor moves moderately (50% duty cycle).
o
I
DC motor moves fast (75% duty cycle).
I
0
DC motor moves very fast (100% duty cycle).
I
I
Solution:
#include <p18f458.h>
#define MTR PORTBbits.RB1
void MSDelay(unsigned int value);
void main ()
{
unsigned int duty;
TRISB = OxFD;
TRISD = OxFF;
while (1)
{
duty = PORTD&Ox03;
duty++;
duty *= 25;
MTR = 1;
MSDelay(duty) ;
MTR = 0;
MSDelay(lOO-duty) ;
} }
Review Questions
I. True or false. The permanent magnet field DC motor has only two leads for +
and - voltages.
2. True or false. Just like a stepper motor, one can control the exact angle of a DC
motor's move.
3. Why do we put a driver between the microcontroller and the DC motor?
4. How do we change a DC motor's rotation direction?
5. What is stall in a DC motor?
6. True or false. PWM allows the control of a DC motor with the same phase, but
different amplitude pulses.
7. The RPM rating given for the DC motor is for
(no-load, loaded).
662
SECTION 17.4: PWM MOTOR CONTROL WITH CCP
We examined the CCP (Compare Capture Pulse-Width-Modulation) part of
the PIC452!458 in Chapter 15. One of the features of the CCP is the pulse width
modulation (PWM) as we saw in Section 15.4 of Chapter 15. In this section we
use the PWM feature of the CCP to control DC motors. Review the programming
of the PWM in Section 15.4 before embarking on this section.
DC motor control with CCP
Recall from Section 15.4 that the PWM part of the CCP is programmed by
using the PR2 and Timer2 registers. Program 17-2 is the rewrite of Example 17-7
using the PWM feature of the CCPI. Notice that Program 17-2 is the modified version of Program 15-5 in Chapter 15. Program 17-2C is the C version of Program
17-2. In Program 17-2 (and 17-2C), an input switch is being monitored. If the
switch is low, the PICI8 creates a 50% duty cycle PWM using the CCPI module.
If the switch is high, a 25% duty cycle PWM is created. Recall from Chapter 15
that we must use PR2 and Timer2 registers for creating PWM pulses.
+12V
'5V
4.7k
1N4004 ~
-1=
RD7
RC2
O.l,F : :
MOTOR
'5V
330
ILD74
OPTOISOLATOR
1
PIC18F
~
,
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10k
,
t/
."
TIP120
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100k
2.!
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,:...
'----
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FIgure 17-22: DC Motor Control Usmg CCPl Pm
;Program 17-2
BCF
TRISC, CCPl
;make PWM output pin
BSF
TRISD,RD7
;make RD7 input pin
;PWM MODE, 11 for DC1Bl:BO
MOVLW Ox3C
MOVWF CCP1CON
MOVLW D' 100'
;set period to 100 * Fosc/4
MOVWF PR2
;Timer2, 4 prescale, no postscaler
MOVLW OxOl
MOVWF T2CON
AGAIN BTFSS PORTD,RD7
;Is the switch high?
BRA T2DUTY
ina, then 50%
;25% duty cycle
MOVLW D' 25'
BRA LOAD
;50% duty cycle
T2DUTY MOVLW D'50'
CHAPTER 17: MOTOR CONTROL: RELAY, PWM, DC, AND STEPPER MOTORS
663
BRA LOAD
LOAD MOVWF CCPRlL
CLRF
TMR2
T2CON,TMR20N
BSF
BCF
PIR1,TMR2IF
OVER BTFSS PIR1,TMR2IF
BRA
OVER
GOTO
AGAIN
;load duty cycle
;clear Timer2
i turn on Timer2
;clear Timer2 flag
;wait for end of period
; continue
The following is the C version of the above program.
//Program 17-2C
#include <p18f458.h>
void main()
{
TRISC ~ OxFB;
TRISD ~ Ox80;
CCP1CON ~ Ox3C;
PR2~100;
T2CON~Ox01;
//make CCP1 output pin
//make RD7 input pin
//PWM MODE, 11 for DC1B1:BO
//set period to 100 * 16/Fosc
//4 prescaler, no postscaler
while (1)
{
if(PORTDbits.RD7~~1)
CCPR1L
else
CCPR1L
25;
//25% duty cycle
50;
//50% duty cycle
//clear Timer2
PIR1bits.TMR2IF~0;
//clear Timer2 flag
T2CONbits.TMR20N~1;
//start Timer2
while(PIR1bits.TMR2IF~~0) ii/wait for end of period
TMR2~OxO;
}
}
Review Questions
I.
2.
3.
4.
5.
664
True or false. For standard CCPI, we use the RC2 pin for PWM.
True or false. For standard CCPI, the CCPl pin must be configured as output.
In standard CCP I, we use
to set the period for PWM.
In standard CCPI, we use
to set the duty cycle for PWM.
True or false. In standard CCPI, we must use Timer! for PWM.
SECTION 17.5: DC MOTOR CONTROL WITH ECCP
The PIC18F452/458 (or 4520/4580) comes with one standard CCP and one
enhanced CCP (ECCP). Indeed, in recent years the CCP module has been deemphasized while the ECCP is becoming more prominent in the PIC 18 family.
The reason is that ECCP allows the implementation of the H-Bridge for bidirectional control of the DC motor in addition to the capture/compare mode present in
the standard CCP. In this section, we use the ECCP feature of the PIC 18 to control
the DC motor. Before embarking on this section, the basic concept of ECCP programming in Chapter 15 needs to be reviewed.
Bidirectional DC motor control with ECCP
ECCP allows the implementation of the H-Bridge for bidirectional movement of the DC motor because it uses 4 pins instead of a single pin as is used in
standard CCP. As we saw in Section 17.3 of this chapter, the bidirectional DC
movement needs some kind ofH-Bridge circuitry. The ECCP module of the PICl8
implements the entire H-Bridge circuitry internally. It uses RD7-RD4
(PORTD.7-PORTDA) for this purpose as shown in Figures 17-23 through 17-26.
MCLRNPP
40
RB7/PGD
RAO/ANO/CVREF
2
39
RB6/PGC
RAlIAN1
3
38
RB5/PGM
RA2/AN2NREF-
4
37
RB4
RA3/AN3NREF+
5
36
RB3/CANRX
RA4fTOCKI
6
35
RB2/CANTX/INT2
RA5/AN4/SS/LVDIN
7
34
RB111NT1
REO/AN5/RD
8
33
RBO/INTO
RE 1/AN6/wR/C 1OUT
9
32
VDD
RE2/AN7/CS/C20UT
10
31
VSS
VDD
11
30
RD7/PSP7/P1D
VSS
12
29
RD6/PSP6/P1 C
OSC1/CLKI
OSC2/CLKO/RA6
13
28
RD5/PSP5/P1 B
14
27
RD4/PSP4/ECCP/P1 A
RCOfT1 OSOfT1 CKI
15
26
RC7/RX/DT
RC1fT10SI
16
25
RC6fTX/CK
RC2/CCP1
17
24
RC5/SDO
RC3/SCK/SCL
18
23
RC4/SDI/SDA
RDO/PSPO/C1IN+
19
22
RD3/PSP3/C2IN-
20
21
RD2/PSP2/C2IN+
RD1/PSP1/C1IN-
PIC18F458
Figure 17-23. ECCP Pins for PWM in PIC18F458/4580 (452/4520)
CHAPTER 17: MOTOR CONTROL: RELAY, PWM, DC, AND STEPPER MOTORS
665
-veePIC18F
r-
I~
OUTPUT '1'
PlA(RD4)
r-
OUTPUT '0'
PLB(RD5)
I--
/l
~I
OC
MOTOR
I~
OUTPUT '0'
PLC(RD6)
~
,....
.nnnn
I-
PLD(RD7)
'-
\1
<}-
-:::-
Figure 17-24. Forward Current Flow Using ECCP (from Microchip)
-veer
PIC18F
lOUTPUT '0'
PlA(RD4)
PLB(RD5)
PLC(RD6)
.nnnn
OUTPUT '1'
OUTPUT '0'
v
~
DC
I-
I~
I-
(
)
MOTOR
-
PLD(RD7)
o::=-
Figure 17-25. Reverse Current Flow Using ECCP (from Microchip)
666
~I
-
11
(]-
IEPWMIMIII EPWMIMO I EDCIBIIIEDCIBOI
I
D7
I
IECCPIM311 ECCPIM21 ECCPIMI I ECCPIMO
I
DO
EPWMIM1:EPWMIMO PWM output pin configuration. It allows the use of a single
pin for the capture/compare mode, or four pins for the PWM.
In compare/capture mode, only pin PIA (RD4) is used. In that case, there is no selection for these two bits.
In the PWM mode the options for these two bits are as follows:
00
01
PIA is used as a modulated output. PIB, PIC, and PID are used as I/O.
Full-Bridge output forward. PID modulated, PIA active. PIB and PIC inactive.
10
Half-Bridge output. PIA and PID modulated with deadband control, PIC and
PID used as I/O.
Full-Bridge output reverse. PIB modulated, PIC active. PIA and PID inactive.
II
EDCIBlO:EDCIBI PWM Duty Cycle least-significant bits. Used in PWM only.
The least-significant bits (Bit I and Bit 0) of the lO-bit duty cycle register are
used in PWM. The ECCPRIL register is used as Bit 2 to Bit 9 of the lO-bit
duty cycle register.
ECCPIM3-ECCIMO ECCPI Mode Select
o 0 0 0 ECCPI is off
Reserved
000 I
Compare Mode. Toggle ECCPI output pin on match.
00 I 0
(ECCP lIF bit is set.)
Reserved
00 I I
0100
oI 0 I
oI I 0
oI I I
Capture mode,
Capture mode,
Capture mode,
Capture mode,
1000
Compare mode. Initialize ECCPI pin low; on compare match,
force CCPI pin HIGH. (ECCPlIF is set.)
Compare mode. Initialize CCPI pin HIGH; on compare match,
force CCPI pin LOW. (ECCPlIF is set.)
Compare mode. Generate software interrupt on compare
match. (ECCP IIF bit is set, ECCP I pin is unaffected.)
Compare mode. Trigger special event. (ECCPliF bit is set, and
Timer! or Timer3 is reset to zero.)
100 I
I0 I0
I0I I
I
I
I
I
I 00
101
I I0
I I I
PWM Mode;
PWM Mode;
PWM Mode;
PWM Mode;
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
PIA,
PIA,
PIA,
PIA,
PIC
PIC
PIC
PIC
active-HIGH; PIB and PID active-HIGH
active-HIGH; PIB and PID active-LOW
active-LOW; PIB and PID active-HIGH
active-LOW; PIB and PID active-LOW
Figure 17-26. ECCPl Control Register. (This register selects one of the operation
modes of Capture, Compare, or PWM of EECP1)
CHAPTER 17: MOTOR CONTROL: RELAY, PWM, DC, AND STEPPER MOTORS
667
Program 17-3 shows Full-Bridge implementation of the PWM for ECCP
module. For the implementation of Half-Bridge and other applications of PWM
using the ECCP module, see the PIC 18 manual.
;Program 17-3
CLRF TRISD
MOVLW D' 100'
MOVWF PR2
MOVLW D' 50 I
MOVWF ECCPR1L
MOVLW OxCF
MOVWF ECCP1CON
MOVLW Ox24
MOVWF T2CON
AGAIN CLRF TMR2
BCF
PIR1,TMR2IF
WAIT BTFSS PIR1,TMR2IF
BRA WAIT
BRA AGAIN
;make PORTD output
;period = 100 * 16/Fosc
;duty = 50%
;reverse full-bridge PWM
i4 postscaler,
turn on Timer2
;start pulse
;clear flag
;wait for period
;da it again
The following is the C version of the above program.
//Program 17-3C
#include <p18f458.h>
void main()
{
TRISD=O;
PR2=100;
ECCPR1L=50;
ECCP1CON=OxCF;
T2CON=Ox24;
while
//make PORTD output
//period = 100 * 16/Fosc
//duty = 50%
//reverse full-bridge PWM
//4 postscaler,turn on Timer2
(1)
{
TMR2=0;
//start pulse
PIR1bits.TMR2IF=O;
//clear flag
while (PIR1bits.TMR2IF==0) ; //wait for period
}
}
Review Questions
I. True or false. For ECCPl, we use the R03-RDO pins for Full-Bridge.
2.
3.
4.
5.
668
True or false. For ECCPI, the PIA to PIO pins must be configured as output.
In ECCPI, we use
to set the period for PWM.
In ECCPI, we use
to set the duty cycle for PWM.
True or false. In ECCPI, we must use Timer2 for PWM.
SUMMARY
This chapter continued showing how to interface the PIC 18 with realworld devices. Devices covered in this chapter were the relay, optoisolator, stepper motor, and DC motor.
First, the basic operation of relays and optoisolators was defined, along
with key terms used in describing and controlling their operations. Then the PICI8
was interfaced with a stepper motor. The stepper motor was then controlled via an
optoisolator using PICI8 Assembly and C programming languages.
The PIC 18 was interfaced with DC motors. A typical DC motor will take
electronic pulses and convert them to mechanical motion. This chapter showed
how to interface the PICI8 with a DC motor. Then, simple Assembly and C programs were written to show the concept ofPWM.
Control systems that require motors must be evaluated for the type of
motor needed. For example, you would not want to use a stepper in a high-velocity application or a DC motor for a low-speed, high-torque situation. The stepper
motor is ideal in an open-loop positional system and a DC motor is better for a
high-speed conveyer belt application. DC motors can be modified to operate in a
closed-loop system by adding a shaft encoder, then using a microcontroller to
monitor the exact position and velocity of the motor. In the last two sections, we
showed how to use CCP and ECCP features ofPICI8 to control DC motors.
PROBLEMS
SECTION 17.1: RELAYS AND OPTOISOLATORS
I. True or false. The minimum voltage needed to energize a relay is the same for
all relays.
2. True or false. The minimum current needed to energize a relay depends on the
coil resistance.
3 Give the advantages of a solid-state relay over an EM relay.
4. True or false. In relays, the energizing voltage is the same as the contact
voltage.
5. Find the current needed to energize a relay if the coil resistance is 1,200 ohms
and the coil voltage is 5 V.
6. Give two applications for an optoisolator.
7 Give the advantages of an optoisolator over an EM relay.
8. Of the EM relay and solid-state relay, which has the problem of back EMF?
9. True or false. The greater the coil resistance, the worse the back EMF voltage.
10. True or false. We should use the same voltage sources for both the coil voltage
and contact voltage.
SECTION 17.2: STEPPER MOTOR INTERFACING
II. If a motor takes 90 steps to make one complete revolution, what is the step
angle for this motor?
12. Calculate the number of steps per revolution for a step angle of 7.5 degrees.
CHAPTER 17: MOTOR CONTROL: RELAY, PWM, DC, AND STEPPER MOTORS
669
13. Finish the nonnal four-step sequence clockwise if the first step IS 0011
(binary).
14. Finish the nonnal four-step sequence clockwise if the first step IS 11 00
(binary).
IS. Finish the nonnal four-step sequence counterclockwise ifthe first step is 1001
(binary).
16. Finish the nonnal four-step sequence counterclockwise if the first step is OlIO
(binary).
17. What is the purpose of the ULN2003 placed between the PICI8 and the stepper motor? Can we use that for 3A motors?
18. Which of the following cannot be a sequence in the nonnal four-step sequence
for a stepper motor?
(a) CCH (b) DDH
(c) 99H
(d) 33H
19. What is the effect of a time delay between issuing each step?
20. In Question 19, how can we make a stepper motor go faster?
SECTION 17.3: DC MOTOR INTERFACING AND PWM
21. Which motor is best for moving a wheel exactly 90 degrees?
22. True or false. Current dissipation of a DC motor is proportional to the load.
23. True or false. The rpm of a DC motor is the same for no-load and loaded.
24. The rpm given in data sheets is for
(no-load, loaded).
25. What is the advantage of DC motors over AC motors?
26. What is the advantage of stepper motors over DC motors?
27. True or false. Higher load on a DC motor slows it down if the current and voltage supplied to the motor are fixed.
28. What is PWM, and how is it used in DC motor control?
29. A DC motor is moving a load. How do we keep the rpm constant?
30. What is the advantage of placing an optoisolator between the motor and the
microcontroller?
ANSWERS TO REVIEW QUESTIONS
SECTION 17.1: RELAYS AND OPTOISOLATORS
I.
2.
3.
4.
5.
6.
With a relay we can use a 5 V digital system to control 12 V-120 V devices such as horns and
appliances.
Because microcontroller/digital outputs lack sufficient current to energize the relay, we need a
driver.
When the coil is not energized, the contact is closed.
When current flows through the coil, a magnetic field is created around the coil, which causes the annature to be attracted to the coil.
It is faster and needs less current to get energized.
It is smaller and can be connected to the microcontroller directly without a driver.
SECTION 17.2: STEPPER MOTOR INTERFACING
I.
0110,0011,1001,1100 for clockwise; and 0110,1100,1001,0011 for counterclockwise
2.
72
3.
Because the microcontroller pins do not provide sufficient current to drive the stepper motor
670
SECTION 17.3: DC MOTOR INTERFACING AND PWM
1.
2.
True
False
3.
Because microcontroller/digitai outputs lack sufficient current to drive the DC motor, we need
4.
5.
6.
7.
a driver.
By reversing the polarity of voltages connected to the leads
The DC motor is stalled if the load is beyond what it can handle.
False
No-load
SECTION 17.4: PWM MOTOR CONTROL WITH CCP
1.
2.
3.
4.
5.
True
True
PR2
CCPRIL
False
SECTION 17.5: DC MOTOR CONTROL WITH ECCP
1.
2.
3.
4.
5.
False
True
PR2
CCPRIL
True
CHAPTER 17: MOTOR CONTROL: RELAY, PWM, DC, AND STEPPER MOTORS
671
APPENDIX A
PIC18 INSTRUCTIONS:
FORMAT AND
DESCRIPTION
OVERVIEW
In the' first section of this appendix, we describe the
instruction format lIf tbeMC18. Special emphasis is placed lin the
instructions using buthWREG and file registers. This section
includes a list
machine cycles (clock counts) for each of the
Plel8 instructionS.
of
In the second section of this appendix, we describe each
instruction of. tile PIeI8. In many cases, a simple programming.
example is given to clarify tlle.instruction.
673
This Appendix deals mainly with PICI8 instructions. In Section A.I, we
describe the instruction formats and categories. In Section A.2, we describe each
instruction of PIC 18 with some examples.
SECTION A.1: PIC18 INSTRUCTION FORMATS AND CATEGORIES
As shown in Figure A-I, the PIC 18 instructions fall into five categories:
I.
2.
3.
4.
5.
Bit-oriented instructions
Intructions using a literal value
Byte-oriented instructions
Table read and write instructions
Control instructions using branch and call
In this section, we describe the format and syntax with special emphasis
placed on byte-oriented instructions. For some of the instructions, the reader
needs to review the concepts of access bank and bank registers in Chapter 6
(Section 6.3).
Bit-oriented instructions
The bit-oriented instructions perform operations on a specific bit of a file
register. After the operation, the result is placed back in the same file register. For
example, the "BCF f,b,a" instruction clears a specific bit of fileReg. See
Table A-I. In these types of instructions, the b is the specific bit of the fileReg,
which can be 0 to 7, representing the DO to D7 bits of the register. The fileReg
location can be in the bank register called access bank (if a = 0) or a location within other bank registers (if a = I). Notice that if a = 0, the assembler assumes the
access bank automatically.
Table A-I: Bit-Oriented Instructions (from Microchip datasheet)
Mnemonic,
Operands
Description
Cycles
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f,
f,
f,
f,
f,
b,
b,
b,
b,
d,
a
a
a
a
a
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
1
1
1 (2 or 3)
1 (2 or 3)
1
Look at the examples that follow for clarification of bit-oriented instructions:
674
Example Instructions
Byte-oriented File Register operations
15
1
10
9
1
OPCODE
d
8
1
o
7
1
a
f (FILE
#)
1
ADDWF MYREG, W, B
=
d 0 for result destination to be WREG Register
d = 1 for result destination to be File Register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit File Register address
Byte to Byte move operations (2-word)
15
1211
1OPCODE 1
f (Source FILE
#)
1111
1MOVFF
MYREG 1, MYREG2
o
12 11
15
1
0
f (Destination FILE #)
1
f = 12-bit File Register address
Bit-oriented File Register operations
15
1
12 11
9
o
8 7
OPCODE 1 b (BIT #)1 a
1
f (FILE #)
1
BSF MYREG, bit, B
1
MOVLW Ox7F
1
GOTO label
b = 3-bit position of bit in File Register (f)
a = 0 to force Access Bank
a 1 for BSR to select bank
=
f =8-bit File Register address
Literal operations
1
o
8 7
15
OPCODE
k (literal)
1
k = 8-bit immediate value
Control operations
CALL, GOTO, and Branch operations
15
1
OPCODE
15
1
o
87
1
n<7:0> (literal)
o
12 11
1111
1
n<19:8> (literal)
1
n = 20-bit immediate value
Figure A-I. General Formatting of PIC18 Instrnctions (From MicroChip)
APPENDIX A: PIC18 INSTRUCTIONS: FORMAT AND DESCRIPTION
675
BCF
BCF
BTG
BTG
BSF
;clear bit D5 of PORTB
;clear bit D4 of TRISC reg
; toggle bit D7 of PORTC
; toggle bit DO of PORTD
;set carry flag to one
PORTB,5
TRISB,4
PORTC, 7
PORTD, 0
STATUS,C
The following example uses the fileReg in the access bank:
MyReg
SET
MOVLW OxO
MOVWF MyReg
BTG MYReg, 7
BTG MYReg,5
Ox30
;set aside lac 30H for MyReg
;WREG = 0
; MyReg = 0
; toggle bit D7 of MyReg
; toggle bit D5 of MyReg
The following example uses the fileReg in the access bank:
SET
MyReg
MOVLW
OxO
MOVWF MyReg
BTG
MYReg, 2
BTG
MYReg, 4
Ox50 ;set aside loco 50H for MyReg
:WREG = 0
; MyReg = 0
; toggle bit D2 of MyReg
; toggle bit D4 of MyReg
As we discuss in Chapter 6, when using a bank other than the access bank,
we must load the BSR (bank select register) with the desired bank number, which
can go from I to F (in hex), depending on the family member. We do that by using
the MOVLB instruction. Look at the following examples.
The example below uses a location in Bank 2 (RAM locations 200-2FFH).
YReg SET Ox30
;set aside lac 30H for YReg
MOVLB Ox2
iuse Bank 2 (address loc 230H)
MOVLW OxO
:WREG = 0
MOVWF YReg
;YReg = 0
BTG YReg,7,1 ; toggle bit D7 of YReg in bank 2
BTG YReg,5,1 ;toggle bit D5 of YReg in bank 2
The example below uses a location in Bank 4 (RAM locations 400-4FFH).
ZReg SET OxlO
;set aside lac lOH for ZReg
;use Bank 4 (address lac 4l0H)
MOVLB Ox4
MOVWL OxO
;WREG = 0
MOVWF ZReg
;ZReg = 0
BSF ZReg,6,1 ;set HIGH bit D6 of ZReg in bank 4
BSF ZReg,l,l ;set HIGH bit Dl of ZReg in bank 4
Notice that all the bit-oriented instructions start with letter B (bit). The
branch instructions also start with letter B, like "BZ target" for branch if zero, but
they are not bit-oriented.
676
Table A-2: Literal Instructions (from Microchip datasheet)
Mnemonic,
Operands
Description
Cycles
LITERAL OPERATIONS
ADDLW
Add literal and WREG
k
ANDLW
AND literal with WREG
k
IORLW
LFSR
k
f, k
1
1
1
Inclusive OR literal with WREG
Move literal (12-bit) 2nd word 2
to FSRx
1st word
MOVLB
k
Move literal to BSR <3:0>
1
MOVLW
k
Move literal to WREG
1
MULLW
k
Multiply literal with WREG
1
RETLW
SUBLW
XORLW
k
k
Return with literal in WREG
Subtract WREG from literal
2
k
1
Exclusive OR literal with WREG 1
Instructions using literal values
In this type of instruction, an operation is performed on the WREG register and a fixed value called k. See Table A-2. Because WREG is only 8-bit, the k
value cannot be greater than 8-bit. Therefore, the k value is between 0-255 (OO-FF
in hex). After the operation, the result is placed back in WREG. Look at the following examples for clarification:
MOVLW
ADDLW
Ox45 ;WREG = 45H
Ox24 ;WREG = 45H + 24H
MOVLW
ANDLW
Ox35 ;WREG = 35H
35H ANDed with OFH
OxOF ;WREG
MOVLW
XORLW
Ox55 ;WREG
55H
OxAA ;WREG = 55H EX-ORed with AAH
69H
05H
FFH
Byte-oriented instructions
There are two groups of instructions in this category. In the first group, the
operation is performed on the file register and the result is placed back in the file
register. The instruction "CLRF f,a" is an example in this group. See Table A-3. In
the second group, the operation involves both fileReg and WREG. As a result, we
have the options of placing the result in fileReg or in WREG. As an example in this
group, examine the "ADDWF f,d,a" instruction. The destination for the result can
be WREG (if d = 0) or file register (if d = I). For the fileReg location, it can be
in the access bank (if a = 0) or in other bank registers (if a = 1). Also notice that
if a = 0, the assembler assumes that automatically.
APPENDIX A: PIC18 INSTRUCTIONS: FORMAT AND DESCRIPTION
677
Table A-3: Byte-Oriented Instructions (from Microchip datasheet)
Mnemonic,
Operands
Cycles
Description
BYTE-ORIENTED FILE REGISTER OPERATIONS
1
ADDWF f, d, a Add WREG and f
ADDWFCf, d, a Add WREG and Carry bit to f 1
ANDWF f, d, a Add WREG with f
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
1
1
f, a, Clearf
f, d, a
1
Complement f
f, a, Compare f with WREG, skip =
f, a, Compare f with WREG, skip>
1
f, a, Compare f with WREG, skip <
f, d, a Decrement f
1
DECF
DECFSZ f, d, a Decrement f, Skip if 0
1
1
1
1
DCFSNZ f, d, a Decrement f, Skip if Not 0
f, d, a Increment f
INCF
INCFSZ f, d, a Increment t, Skip if 0
1
1
MOVF
f, d, a Increment f, Skip if Not 0
f, d, a Inclusive OR WREG with f
f, d, a Movef
MOVFF
fs' fd Move fs(source) to 1 st word 2
INFSNZ
IORWF
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
1
1
1
fd(destination) 2nd word
f, a Move WREG to f
f, a Multiply WREG with f
f, a Negate f
1
1
1
f, d, a Rotate Left f through Carry
f, d, a Rotate Left f (No Carry)
1
f, d, a Rotate Right f through Carry
f, d, a Rotate Right f (No Carry)
f, a, Setf
1
1
1
SUBFWB f, d, a Subtract f from WREG with
1
1
borrow
f, d, a Subtract WREG from f
SUBWFB f, d, a Subtract WREG from f with
1
1
SUBWF
borrow
TSTFSZ
f, d, a Swap nibbles in
f, a Test t, Skip if 0
XORWF
t, d, a
SWAPF
678
t
Exclusive OR WREG with
1
1
t
1
Look at the following examples.
When d = 0 and a = 0:
MyReg
MOVLW
MOVWF
MOVLW
ADDWF
SET
Ox20
Ox45
MyReg
Ox23
MyReg
;loc 20H for MyReg
;WREG = 45H
; MyReg = 45H
;WREG = 23H
;WREG = 68H (45H + 23H = 68H)
In the above example, the last instruction could have been coded as
"ADDWF MyReg,O,O".
When d = 1 and a = 0:
MyReg
MOVLW
MOVWF
MOVLW
ADDWF
SET
Ox20
Ox45
MyReg
Ox23
MyReg,F
iloc 20H for MyReg
;WREG = 45H
; MyReg = 45H
;WREG = 23H
; MyReg = 68H (45H + 23H = 68H)
In the above example, the last instruction could have been coded as
"ADDWF MyReg,F,O" or "ADDWF MyReg,J,O". As far as the MPLAB is concerned, they mean the same thing. Notice that the use ofletter F in "ADDWF
MyReg,F" is being used in place of 1.
To use banks other than the access bank, we must load the BSR register
first. The following example uses a location in Bank 2 (RAM location
200-2FFH).
When d = 0 and a = 1:
MyReg SET Ox30 ;set aside location 30H for MyReg
MOVLBOx2
iuse Bank 2 (address loc 230H)
MOVLW Ox45
;WREG = 45H
MOVWF MyReg, 1
;MyReg = 45H (loc 230H)
MOVLW Ox23
;WREG = 23H
ADDWF MyReg, 1
;WREG
68H (add loc 230H to W)
When d = 1 and a = 1:
MyReg
MOVLB
MOVLW
MOVWF
MOVLW
ADDWF
SET Ox20
Ox4
Ox45
MyReg
Ox23
MyReg,F,l
;loc 20H for MyReg
iuse bank 4
;WREG = 45H
; MyReg = 45H (loc 420H)
;WREG = 23H
; MyReg = 68H (loc 420 )
APPENDIX A: PIC18 INSTRUCTIONS: FORMAT AND DESCRIPTION
679
Register-indirect addressing mode uses FSRx as a pointer to RAM location. We have three registers, FSRO, FSRI, and FSR2, that can be used for
pointers.
Examples:
ADDWF POSTINCO ;add to W data pointed to by FSRO,
;also increment FSRO
ADDWF POSTINCl ;add to W data pointed to by FSRl
;also increment FSRl
See Example 6-6 in Chapter 6.
Table processing instructions
The table processing instructions allow us to read fixed data located in
the program ROM of the PICI8. See Table A-4. They also allow us to write into
the program ROM if it is Flash memory. Chapter 14 discusses the TBLRD and
TBLWRT instructions in detail. It also shows how to use table read and write to
access the EEPROM.
Table A-4: Table Processing Instructions (from Microchip datasheet)
Mnemonic,
Operands
DATA of
Description
Cycles
• PROGRAM MEMORY OPERATIONS
TBLRO*
Table Read
TBLRO*+
Table Read with post-increment
TBLRO*-
Table Read with post-decrement 2
TBLRO+*
Table Read with pre-increment
2
TBLwr
Table Write
2
TBLWT*+
Table Write with post-increment
2
TBLWT*-
Table Write with post-decrement 2
TBLWT+*
Table Write with pre-increment
2
2
2
Control instructions
The control instructions such as branch and call deal mainly with flow
control. See Table A-5. We must pay special attention to the target address of
the control instructions. The target address for some of the branch instructions
such as BZ (branch if zero) cannot be farther than 128 bytes away from the current instruction. The CALL instruction allows us to call a subroutine located
anywhere in the 2M ROM space of the PIC 18. See the individual instructions in
the next section for further discussion on this issue.
680
Table A-5: Control Instructions (from Microchip datasheet)
Mnemonic,
Operands
Description
CONTROL OPERATIONS
n
Branch if Carry
BC
Cycles
BN
n
Branch if Negative
1
1
BNC
n
Branch if Not Carry
1
BNN
n
Branch if Not Negative
1
BNOV
n
Branch if Not Overflow
1
BNZ
n
Branch if Not Zero
1
BOV
n
Branch if Overflow
1
BRA
n
Branch Unconditionally
2
BZ
n
Branch if Zero
CALL
n,s Call subroutine
1
2
CLRWDT
DAW
n
GOTO
NOP
NOP
POP
PUSH
1st word
2nd word
Clear Watchdog Timer
1
Decimal Adjust WREG
1
Go to address
2
1st word
2nd word
-
No Operation
1
No Operation
-
Pop top of return stack (TOS)
1
1
Push top of return stack (TOS)
1
Relative Call
2
Software device RESET
1
n
RCALL
RESET
RETFIE
s
Return from interrupt enable
2
RETLW
k
Return with literal in WREG
2
RETURN
s
Retum from Subroutine
2
Go into standby mode
1
SLEEP
-
APPENDIX A: PIC18 INSTRUCTIONS: FORMAT AND DESCRIPTION
681
SECTION A.2: THE PIC18 INSTRUCTION SET
In this section we provide a brief description of each instruction with some
examples.
ADDLWK
Add Literal to WREG
Function:
Syntax:
ADD literal value ofk to WREG
AOOLW
k
This adds the literal value of k to the WREG register, and places the result
back into WREG. Because register WREG is one byte in size, the operand k must
also be one byte.
The ADD instruction is used for both signed and unsigned numbers. Each
one is discussed separately. See Chapter 5 for discussion of signed numbers.
Unsigned addition
In the addition of unsigned numbers, the status of C, ~C, Z, N, and OV
may change. The most important of these flags is C. It becomes 1 when there is a
carry from 07 out in 8-bit (00-07) operations.
Example:
MOVLW Ox45
ADDLW Ox4F
;WREG = 45H
;WREG = 94H (45H + 4FH
94H)
;C = 0
Example:
MOVLW
ADDLW
OxFE
Ox75
;WREG = FEH
;WREG = FE + 75
73H
;C = 1
Example:
MOVLW
ADDLW
;WREG = 25H
;WREG = 67H (25H + 42H = 67H)
;C = 0
Notice that in all the above examples we ignored the status of the OV flag.
Although ADD instructions do affect OV, it is in the context of signed numbers
that the OV flag has any significance. This is discussed next.
Ox25
Ox42
Signed addition and negative numbers
In the addition of signed numbers, special attention should be given to the
overflow flag (OV) because this indicates if there is an error in the result of the
addition. There are two rules for setting OV in signed number operation. The
overflow flag is set to I:
1. If there is a carry from 06 to 07 and no carry from 07 out.
2. If there is a carry from 07 out and no carry from 06 to 07.
Notice that if there is a carry both from 07 out and from 06 to 07, OV =
682
o.
Example:
MOVLW +D'B'
ADDLW +D'4'
;W = 0000 1000
;W
0000 1100 OV = 0,
;C = 0, N = a
Notice that N = D7 = 0 because the result is positive, and OV = 0 because
there is neither a carry from D6 to D7 nor any carry beyond D7. Because OV =
0, the result is correct [(+8) + (+4) = (+12)].
Example:
MOVLW +D'66'
0100 0010
;W
ADDLW +D' 69'
-121
;W = 1000 0101
ADDWF
1000 0111
-121
;W
; (INCORRECT) C = 0, N = D7 = 1, OV
= 1
In the above example, the correct result is +135 [(+66) + (+69) = (+135)],
but the result was -121. OV = I is an indication of this error. Notice that N = 1
because the result is negative; OV = I because there is a carry from D6 to D7 and
c=o.
Example:
MOVLW -D'12'
ADDLW +D'lB'
;W = 1111 0100
;W = W + (+0001 0010)
0000 0110 (+6) correct
;W
;N = 0, OV = 0, and C = 1
Notice above that the result is correct (OV = 0), because there is a carry
from D6 to D7 and a carry from D7 out.
Example:
MOVLW -D' 30'
ADDLW +D'14'
OV
=
;W
1110 0010
;W = W + 0000 1110
;W
1111 0000 (-16, CORRECT)
;N
D7 = 1, OV = 0, C = a
0 because there is no carry from D7 out nor any carry from D6 to
07.
Example:
MOVLW -D'126'
;W = 1000 0010
ADDLW -D'127'
;W = W + 1000 0001
;W = 0000 0011 (+3, INCORRECT)
;D7 = N = 0, OV = 1
C = 1 because there is a carry from D7 out but no carry from D6 to D7.
From the above discussion we conclude that while Carry is important in
any addition, OV is extremely important in signed number addition because it is
used to indicate whether or not the result is valid. As we will see in instruction
"DAW", the DC flag is used in the addition of BCD numbers.
APPENDIX A: PICl8 INSTRUCTIONS: FORMAT AND DESCRIPTION
683
ADDWF
Add WREG and f
Function:
Syntax:
ADD WREG and fileReg
ADDWF f,d,a
This adds the fileReg value to the WREG register, and places the result in
WREG (if d = 0) or fileReg (if d = I).
The ADDWF instruction is used for both signed and unsigned numbers.
(See ADDLW instruction.)
Example:
MyReg
MOVLW
MOVWF
MOVLW
ADDWF
SET Ox20
Ox45
MyReg
Ox4F
MyReg
;WREG
;loc 20H for MyReg
;WREG = 45H
;MyReg = 45H
;WREG = 4FH
= 94H (45H + 4FH = 94H)
;C = 0
We can place the result in fileReg, as shown in the following example:
MyReg
MOVLW
MOVWF
MOVLW
ADDWF
SET Ox2O
iloc 20H for MyReg
Ox45
;WREG = 45H
MyReg
; MyReg = 45H
Ox4F
;WREG = 4FH
MyReg,F
; MyReg = 94H
; (45H + 4FH = 94H) , C = 0
For cases of a = 0 and a = I, see Section A.I in this chapter.
ADDWFC
Add WREG and Carry flag to fileReg
Function:
Syntax:
ADD WREG and Carry bit to fileReg
ADDWFC f,d,a
This will add WREG and the C flag to fileReg (Destination = WREG +
fileReg + C). If C = I prior to this instruction, I is also added to destination. If C
= 0 prior to the instruction, source is added to destination plus O. This instruction
is used in multibyte additions. In the addition of 25F2H to 3189H, for example, we
use the ADDWFC instruction as shown below.
Example when d = 0:
Assume we have the following data in RAM locations Ox 10 and Ox II
OxlO = (F2)
Oxll = (25)
Reg_L
SET OxlO ;lac OxlO for
Reg_H
SET Oxll ;loc Oxll for
BCF STATUS,C
;make carry =
MOVLW 89H
;WREG = 89H
ADDWFC Reg_L,l ;Reg_L = 89H + F2H
684
Reg_L
Reg_H
0
+ 0
= 7BH
;and C = 1
MOVLW Ox31
;WREG = 31H
ADDWFC Reg_2,1 ;Reg_H = 31H + 25H + 1
57H
Therefore the result is:
25F2H
+3189H
577BH
ANDLW
AND Literal byte with WREG
Function:
Syntax:
Logical AND literal value k with WREG
ANDLW
k
This perfonns a logical AND on the WREG and A
the Literal byte operand, bit by bit, storing the result in 0
0
the WREG.
1
1
Example:
MOVLW
ANDLW
39H
09H
09H
Ox39
Ox09
;W
;W
B AANDB
0
0
1
0
0
0
1
1
39H
39H ANDed with 09
0011 1001
0000 1001
0000 1001
Example:
MOVLW 32H
ANDLW 50H
ANDWF
iW = 32H
;AND W with
; (W = 10H)
32H
50H
10H
0011 0010
0101 0000
0001 0000
AND WREG with fileReg
Function:
Syntax:
Logical AND for byte variables
ANDWF f,d,a
This perfonns a logical AND on the fileReg value and the WREG register,
bit by bit, and places the result in WREG (if d = 0) or fileReg (if d = 1).
Example:
MyReg
MOVLW
MOVWF
MOVLW
ANDWF
39H
09H
09H
SET Ox40;set MyReg lac at Ox40
Ox39
iW = 39H
MyReg
;MyReg = 39H
Ox09
MyReg
;39H ANDed with 09 (W
09)
0011 1001
0000 1001
0000 1001
APPENDIX A: PIC18 INSTRUCTIONS: FORMAT AND DESCRIPTION
685
Example:
MyReg
MOVLW
MOVWF
MOVLW
ANDLW
32H
OFH
02H
SET Ox40;set MyReg lac at Ox40
Ox32
jW == 32H
MyReg
;MyReg = 32H
OxOF
;WREG = OFH
MyReg
;32H ANDed with OFH (W
02)
0011 0010
0000 1111
0000 0010
We can place the result in fileReg as shown in the examples below:
MyReg
MOVLW
MOVWF
MOVLW
ANDLW
SET Ox40;set MyReg lac at Ox40
Ox32
;W = 32H
MyReg
;MyReg = 32H
Ox50
;WREG = 50H
MyReg,F ;MyReg = 09, WREG = 50H
The instructions below clear (mask) certain bits of the output ports, assuming the ports are configured as output ports:
MOVLW
ANDWF
MOVLW
ANDWF
MOVLW
ANDWF
OxFE
PORTB,F
Ox7F
PORTC,F
OxF7
PORTD,F
;mask PORTB.O
(DO of Port B)
imask PORTC.7
(D7 of Port C)
;mask PORTD.3
(D3 of Port D)
Branch Condition
Function:
Conditional Branch (jump)
In this type of Branch (jump), control is transferred to a target address if
certain conditions are met. The following is list of branch instructions dealing
with the flags:
BC
BNC
BZ
BNZ
BN
BNN
BOV
BNOV
Branch if carry
Branch if no carry
Branch if zero
Branch if no zero
Branch if negative
Branch if no negative
Branch if overflow
Branch if no overflow
jump ifC = I
jump ifC = 0
jump ifZ = I
jump ifZ = 0
jump ifN = 1
jump ifN = 0
jump ifOV = I
jump ifOV= 0
Notice that all "Branch condition" instructions are short jumps, meaning
that the target address cannot be more than -128 bytes backward or + 127 bytes forward of the PC of the instruction following the jump. In other words, the target
address cannot be more than -128 to +127 bytes away from the current PC. What
686
happens if a programmer needs to use a "Branch condition" to go to a target
address beyond the -128 to +127 range? The solution is to use the "Branch condition" along with the unconditional GOTO instruction, as shown below.
ORG Ox100
MOVLW Ox87
ADDLW Ox95
NEXT
BNC
GO TO OVER
;WREG = 87H
;C = 1 after addition
;branch if C = 0
;target more than 128 bytes away
NEXT:
ORG Ox5000
MOVWF PORTD
OVER:
Branch if C
BC
Function:
Syntax:
=1
Branch if Carry flag bit = 1
BC target_address
This instruction branches if C = 1.
Example:
MOLW OxO
BACK ADDLW Ox1
BC
EXIT
BRA BACK
EXIT
;WREG = 0
;add 1 to WREG
;exit if C = 1
;keep doing it
Notice that this is a 2-byte instruction; therefore, the target address cannot
be more than -128 to +127 bytes away from the program counter. See Branch
Condition for further discussion on this issue.
BCF
Bit Clear fileReg
Function:
Syntax:
Clear bit of a fileReg
BCF f,b,a
This instruction clears a single bit of a given file register. The bit can be
the directly addressable bit of a port, register, or RAM location. Here are some
examples of its format:
BCF
BCF
BCF
BCF
STATUS,C
PORTB,5
PORTC, 7
MyReg, 1
;C = 0
; CLEAR PORTB.5 (PORTB.5 = 0)
; CLEAR PORTC.7 (PORTC.7 = 0)
; CLEAR D1 OF File Register MyFile
APPENDIX A: PIC18 INSTRUCTIONS: FORMAT AND DESCRIPTION
687
Branch if N = 1
BN
Function:
Syntax:
Jump if Negative flag bit = I
BN target_address
This instruction branches if N = 1. It is used in signed number addition.
See ADDLW instruction. Notice that this is a 2-byte instruction; therefore, the target address cannot be more than -128 to + 127 bytes away from the program counter. See Branch Condition for further discussion on this issue.
BNC
Branch if no Carry
Function:
Syntax:
Branch if Carry flag is 0
BNC target_address
This instruction examines the C flag, and if it is zero it will jump (branch)
to the target address.
Example: Find the total sum of the bytes F6H, 98H, and 8AH. Save the carries in register C_Reg.
C_Reg SET Ox20 ;set aside loc Ox20 for carries
OVER1:
OVER2:
MOVLW OxO
MOVWF C_Reg
ADDLW OxF6
BNC OVERl
INCF C_Reg,F
ADDLW Ox98
BNC OVER2
INCF C_Reg, F
ADDWF Ox8A
BNC OVER3
INCF C_Reg
o
OVER3:
Notice that this is a 2-byte instruction; therefore, the target address cannot
be more than -128 to +127 bytes away from the program counter. See Branch
Condition for further discussion on this.
BNN
Branch if Not Negative
Function:
Syntax:
Branch if Negative flag bit = 0
BNN target_address
This instruction branches if N = O. It is used in signed number addition.
See ADDLW instruction. Notice that this is a 2-byte instruction; therefore, the target address cannot be more than -128 to + 127 bytes away from the program counter. See Branch Condition for further discussion on this issue.
688
BNOV
Branch if No Overflow
Function:
Syntax:
Jump if overflow flag bit = 0
BNOV target_address
This instruction branches if OV = O. It is used in signed number addition.
See ADDLW instruction. Notice that this is a 2-byte instruction; therefore, the target address cannot be more than -128 to + 127 bytes away from the program counter. See Branch Condition for further discussion on this issue.
BNZ
Branch if No Zero
Function:
Syntax:
Jump if Zero flag is 0
BNZ target_address
This instruction branches if Z = O.
Example:
CLRF
CLRF
OVER INCF
BNZ
TRISB
PORTB
PORTB,F
OVER
;PORTB as output
;clear PORTB
;INC PORTB
;do it until it becomes zero
Example: Add value 7 to WREG five times.
COUNTER
SET Ox20 ;loc 20H for COUNTER
MOVLW Ox5
;WREG = 5
MOVWF COUNTER ; COUNTER = 05
MOVLW OxO
;WREG = 0
OVER ADDLW Ox7
;add 7 to WREG
DECF COUNTER,F ; decrement counter
BNZ OVER
;do it until counter is zero
Notice that this is a 2-byte instruction; therefore, the target address cannot
be more than -128 to +127 bytes away from the program counter. See Branch
Condition for further discussion on this issue.
BOV
Branch if Overflow
Function:
Syntax:
Jump if Overflow flag
BOV target_address
=
I
This instruction jumps ifOV = I. It is used in signed number addition. See
ADDLW instruction. Notice that this is a 2-byte instruction; therefore, the target
address cannot be more than -128 to + 127 bytes away from the program counter.
See Branch Condition for further discussion on this issue.
APPENDIX A: PIC18 INSTRUCTIONS: FORMAT AND DESCRIPTION
689
BRA
Branch unconditional
Function:
Syntax:
Branch unconditionally
BRA target_address
BRA stands for "Branch." It transfers program execution to the target
address unconditionally. The target address for this instruction must be within 1K
of program memory. This is a 2-byte instruction. The first 5 bits is the opcode and
the rest is the signed number displacement, which is added to the PC (program
counter) of the instruction following the BRA to get the target address. Therefore,
in this branch, the target address must be within -1024 to + 1023 bytes of the PC
(program counter) of the instruction after the BRA because the II-bit address can
take values of +1 024 to -1023. This address is often referred to as a relative
address because the target address is -1024 to + 1023 bytes relative to the program
counter (PC).
BSF
Bit Set fileReg
Function:
Syntax:
Set bit
BSF f, b, a
This sets HIGH the indicated bit of a file register. The bit can be any directly addressable bit of a port, register, or RAM location.
Examples:
BSF
BSF
BSF
BSF
BTFSC
PORTB,3
PORTC, 6
MyReg, 2
STATUS,C
; make PORTB.3 =
;make PORTC.6 =
; make bit D2 of
;set Carry Flag
1
1
MyReg
C = 1
1
Bit Test fileReg, Skip if Clear
Function:
Syntax:
Skip the next instruction if bit is 0
BTFSC f, b,a
This instruction is used to test a given bit and skip the next instruction if
the bit is low. The given bit can be any of the bit-addressable bits of RAM, ports,
or registers of the PICI8.
Example: Monitor the PORTB.5 bit continuously and, when it becomes low, put
55H in WREG.
HERE
690
BSF TRISB, 5
BTFSC PORTB, 5
BRA
HERE
MOVLW Ox55
;make PORTB.5 an input bit
;skip i f PORTB.5 = 0
;because PORTB.5 = 0,
;put 55H in WREG
Example: See ifWREG has an even number. Ifso, make it odd.
BTFSC WREG,O
BRA NEXT
ADDLW Oxl
;skip if it is odd
;it is even, make it odd
NEXT:
BTFSS
Bit Test fileReg, Skip if Set
Function:
Syntax:
Skip the next instruction if bit is I
BTFSS f, b, a
This instruction is used to test a given bit and skip the next instruction if
the bit is HIGH. The given bit can be any of the bit-addressable bits of RAM,
ports, or registers of the PICI8.
Example: Monitor the PORTB.5 bit
HIGH, put 55H in WREG.
BSF TRISB,S
;make
HERE
BTFSS PORTB,S ;skip
BRA
HERE
MOVLW SSH
;because
continuously and when it becomes
PORTB.S an input bit
if PORTB.S = 1
PORTB.S =
° WREG
=
SSH
Example: See ifWREG has an odd number. If so, make it even.
BTFSS WREG,O
BRA NEXT
ADDLW OxOl
;skip if it is even
;it is even, make it odd
NEXT:
BTG
Bit Toggle fileReg
Function:
Syntax:
Toggle (Complement) bit
BTG f, b, a
This instruction complements a single bit. The bit can be any bit-addressable location in the PIC 18.
Example:
BCF TRISB,O
AGAIN
BTG PORTB,O
BRA AGAIN
;make PORTB.O an output
;complement PORTB.O bit
;continuously forever
Example: Toggle PORTB. 7 a total of 150 times.
COUNTER
SET Ox20
MOVLW 'D'lS0
MOVWF COUNTER
BCF
TRISB,7
;loc 20H for COUNTER
;WREG = ISO
;COUNTER = ISO
;make PORTB.7 an output
APPENDIX A: PIC18 INSTRUCTIONS: FORMAT AND DESCRIPTION
691
OVER BTG PORTB.7
; toggle PORTB.7
DECF COUNTER,F ; decrement and put it in
; COUNTER
BNZ OVER
;do it 150 times
BZ
Branch if Zero
Function:
Syntax:
Branch if Z = 1
BZ target_address
Example: Keep checking PORTB for value 99H.
SETF TRISB
;port B as input
BACK MOVFW PORTB
; get PORTB into WREG
SUBLW Ox99
;subtract 99H from it
BZ
EXIT
;if Ox99, exit
BRA BACK
;keep checking
EXIT:
Example: Toggle PORTB 150 times.
MyReg
SET Ox40 ;loc 40H for MyReg
SETF TRISB
;port B as output
MOVLW D' 150 '
; WREG = 150
MOVWF MyReg
BACK COMF PORTB
;toggle PORTB
DECF MyReg,F
;decrement MyReg
BZ
EXIT
;if MyReg = 0, exit
BRA BACK
;keep toggling
EXIT:
Notice that this is a 2-byte instruction; therefore, the target address cannot
be more than -128 to +127 bytes away from the program counter. See Branch
Condition for further discussion on this.
CALL
Function:
Syntax:
Transfers control to a subroutine
k,s;s is used for fast context switching
CALL
The Call intruction is a 4-byte instruction. The first 12 bits are used for the
opcode and the rest (20 bits) are set aside for the address. A 20-bit address allows
us to reach the target address anywhere in the 2M ROM space of the PIC 18. If
calling a subroutine, the PC register (which has the address of the instruction after
the CALL) is pushed onto the stack and the stack pointer (SP) is incremented by
1. Then the program counter is loaded with the new address and control is transferred to the subroutine. At the end of the procedure, when RETURN is executed,
PC is popped off the stack, which returns control to the instruction after the CALL.
Notice that CALL is a 4-byte instruction, in which 12 bits are the opcode,
and the other 20 bits are the 20-bit address of an even address location. Because
692
all the PIC 18 instructions are 2 bytes in size, the lowest address bit, AO, is automatically set to zero to make sure that the CALL instruction will not land at the
middle of the targeted instruction. The 20-bit address of the CALL provides the
A20-AI part of the address and with the AO = 0, we have the 21-bit address needed to go anywhere in the 2M address space of the PIC 18.
We have two options for the "CALL k,s" instruction. They are s = 0, and
s = 1. When s = 0, it is simply calling a subroutine. With s = I, we are calling a
subroutine and we are also asking the CPU to save the three major registers of
WREG, STATUS, and BSR in internal buffers (shadow registers) for the purpose
of context-switching. This fast context-switching can be used only in the main
subroutine because the depth of the shadow registers is only one. That means no
nested call with the s = I. Look at the following case:
ORG OxO
MAIN
CALL M_SUB, 1
;call and save the registers
MOVLW Ox55 ;address of this instruction is saved on stack
ORG Ox2000
M SUB
CALL Y SUB
;we cannot use CALL Y_SUB,I
MOVLW OxAA;address of this instruction is saved on stack
RETURN, 1
;return to caller and restore the registers
;notice the s = 1 for RETURN
ORG Ox3000
Y SUB
RETURN
END
As shown in RETURN instruction, we also have two options for the
RETURN: s = 0 and s = 1. If we use s = 1 for the CALL, we must also use s = 1
for the RETURN. Notice that "CALL Target" with no number after it is interpreted as s = 0 by the assembler. Likewise, the "RETURN" with no number after
it is interpreted as s = 0 by the assembler.
APPENDIX A: PIClS INSTRUCTIONS: FORMAT AND DESCRIPTION
693
CLRF
Clear fileReg
Function:
Syntax:
Clear
CLRF f, a
This instruction clears the entire byte in the fileReg. All bits of the register
are cleared to O.
Example:
MyReg
CLRF
CLRF
CLRF
CLRF
SET Ox20 ;loc 20H for MyReg
MyReg
;clear MyReg
TRISB ;clear TRIBB (make PORTB output)
PORTB
;clear PORTB
TMR01L
;TMROL = 0
Notice that in this instruction the result can be placed in fileReg only and
there is no option for the WREG to be used as the destination.
CLRWDT
Function:
Syntax:
Clear Watchdog Timer
CLRWDT
This instruction clears the Watchdog Timer.
COMF
Complement the fileReg
Function:
Syntax:
Complement a fileReg
COMF f, d, a
This complements the contents of a given fileReg. The result is the I's
complement of the register; that is, Os become I s and I s become Os. The result
can be placed in WREG (if d = 0) or fileReg (if d = I).
Example:
AGAIN
MOVLW OxO
;WREG = 0
MOVWF TRISB
;Make PORTB an output port
MOVLW Ox55
;WREG = 01010101
MOVWF PORTB
COMF PORTB,F
; complement (toggle) PORTB
CALL DELAY
BRA AGAIN ;continuously (notice WREG = 55H)
Example:
MyReg
MOVLW
MOVWF
COMPF
Where 39H (DOlI IDOl
694
SET Ox40;set MyReg loc at Ox40
Ox39
;W = 39H
MyReg
; MyReg = 39H
MyReg,F ;MyReg = C6H and WREG
bin) becomes C6H (llOO OlIO).
39H
Example:
MyReg SET Ox40;set MyReg loc at Ox40
MOVLW Ox55
;W = 55H
MOVWF MyReg
;MyReg = 55H
COMPF MyReg,F ;MyReg AAH, WREG = 55H
where 55H (01010101) becomesAAH (1010 1010).
Example: Toggle PORTS 150 times.
COUNTER
SET Ox40 ;loc 40H for COUNTER
SETF TRISB
;port B as output
MOVLW D'150'
;WREG = 150
MOVWF COUNTER ; COUNTER = 150
MOVLW Ox55
;WREG = 55H
MOVWF PORTB
BACK COMF PORTB,F
; toggle PORTB
DECF COUNTER,F ; decrement COUNTER
BNZ BACK ; toggle until counter becomes 0
We can place the result in WREG as shown in the examples below:
MyReg SET Ox40
MOVLW
Ox39
MOVWF MyReg
COMPF MyReg
;set MyReg loc at Ox40
;W = 39H
39H
; MyReg
; MyReg = 39H and WREG = C6H
Example:
MyReg SET
Ox40
MOVLW Ox55
MOVWF MyReg
COMPF MyReg
;set MyReg loc at Ox40
;W = 55H
; MyReg = 55H
;WREG = AA and MyReg 55H SETF
CPFSEQ
Compare FileReg with WREG and skip if equal (F = W)
Function:
Syntax:
Compare fileReg and WREG and skip if they are equal
CPFSEQ f, a
The magnitudes of the fileReg byte and WREG byte are compared. If they
are equal, it skips the next instruction.
Example: Keep monitoring PORTS indefinitely for the value of 99H. Get
out only when PORTS has the value 99H.
SETF TRISB
MOVLW Ox99
BACK CPFSEQ PORTB
BRA BACK
;PORTB an input port
;WREG = 99h
;skip if PORTB has Ox99
;keep monitoring
APPENDIX A: PICl8 INSTRUCTIONS: FORMAT AND DESCRIPTION
695
Notice that CPFSEQ skips only when fileReg and WREG have equal values.
CPFSGT
Compare FileReg with WREG and skip if greater (F > W)
Function:
Syntax:
Compare fileReg and WREG and skip if fileReg > WREG.
CPFSGT f, a
The magnitudes of the file Reg byte and WREG byte are compared. If
fileReg is larger than the WREG, it skips the next instruction.
Example: Keep monitoring PORTB indefinitely for the value of 99H. Get
out only when PORTB has a value greater than 99H.
SETF TRISB
MOVLW Ox99
CPFSGT PORTB
BRA BACK
BACK
;PORTB an input port
;WREG = 99H
;skip if PORTB > 99H
;keep monitoring
Notice that CPFSGT skips only if FileReg is greater than WREG.
CPFSLT
Compare FileReg with WREG and skip if less than (F < W)
Function:
Syntax:
Compare fileReg and WREG and skip if fileReg < WREG.
CPFSLT f, a
The magnitudes of the fileReg byte and WREG byte are compared. If
fileReg is less than the WREG, it skips the next instruction.
Example: Keep monitoring PORTB indefinitely for the value of 99H. Get
out only when PORTB has a value less than 99H.
BACK:
SETF TRISB
MOVLW Ox99
CPFSEQ PORTB
BRA BACK
;PORTB an input port
;WREG = 99H
;skip if PORTB < 99H
;keep monitoring
Notice that CPFSLT skips only if FileReg < WREG.
DAW
Function:
Syntax:
Decimal-adjust WREG after addition
DAW
This instruction is used after addition of BCD numbers to convert the result
back to BCD. The data is adjusted in the following two possible cases:
1. It adds 6 to the lower 4 bits of WREG if it is greater than 9 or if DC = 1.
2. It also adds 6 to the upper 4 bits of WREG if it is greater than 9 or if C = 1.
696
Example:
;WREG = 0100 0111
;WREG = 47H + 38H = 7FH,
;invalid BCD
;WREG = 1000 0101 = 85H, valid BCD
MOVLW Ox47
ADDLW Ox38
DAW
47H
+ 38H
7FH
+
6H
85H
(invalid BCD)
(after DAW)
(valid BCD)
In the above example, because the lower nibble was greater than 9, DAW
added 6 to WREG If the lower nibble is less than 9 but DC = 1, it also adds 6 to
the lower nibble. See the following example:
MOVLW Ox29
;WREG = 0010 1001
ADDLW Ox18
;WREG = 0100 0001 INCORRECT
DAW
;WREG = 0100 0111 = 47H VALID BCD
29H
+ 18H
41H
+
(incorrect result in BCD)
6H
47H
correct result in BCD
The same thing can happen for the upper nibble. See the following example:
MOVLW Ox52
ADDLW Ox91
DAW
52H
+ 91H
E3H
+L
143H
;WREG = 0101 0010
;WREG
1110 0011 INVALID BCD
;WREG = 0100 0011 AND C = 1
(invalid BCD)
(after DAW, adding to upper nibble)
valid BCD
Similarly, if the upper nibble is less than 9 and C = 1, it must be corrected.
See the following example:
MOVLW Ox94
ADDLW Ox91·
DAW
;W
=
;W =
;W =
1000
;FOR
1001 0100
0010 0101 INCORRECT
0101, VALID BCD
85, C = 1
APPENDIX A: PIC18 INSTRUCTIONS: FORMAT AND DESCRIPTION
697
94H
+ 91H
(incorrect BCD)
125H
(after DAW, adding to upper nibble)
+L
185
It is possible that 6 is added to both the high and low nibbles. See the following example:
MOVLW
ADDLW
DAW
Ox54
;WREG = 0101 0100
Ox87
;WREG = 1101 1011 INVALID BCD
;WREG = 0100 0001, C = 1 (BCD 141)
54H
+ 87H
DBH
+ 6 6H
1 4 1H
DECF
(invalid result in BCD)
valid BCD
Decrement fileReg
Function:
Syntax:
Decrement fileReg
DECF f, d, a
This instruction subtracts 1 from the byte operand in fileReg. The result
can be placed in WREG (if d = 0) or fileReg (if d = 1).
Example:
MyReg SET Ox40
MOVLW Ox99
MOVWF MyReg
DECF MyReg,F
DECF MyReg,F
DECF MyReg,F
;set aside loc 40H
;WREG = 99H
; MyReg
99H
98H, WREG
; MyReg
; MyReg = 97H, WREG
; MyReg = 96H, WREG
for MyReg
99H
99H
99H
Example: Toggle PORTB 250 times.
COUNTER
SET Ox40 ;loc 40H for COUNTER
SETF TRISB
;PORTB as output
MOVLW D'250'
;WREG = 250
MOVWF COUNTER ; COUNTER = 250
;WREG = 55H
MOVLW Ox55
MOVWF PORTB
BACK COMF PORTB,F
; toggle PORTB
DECF COUNTER,F ; decrement COUNTER
BNZ BACK ; toggle until counter becomes 0
698
We can place the result in WREG as shown in the examples below:
MyReg SET Ox40
MOVLW Ox99
MOVWF MyReg
DECF MyReg
DECF MyReg
DECF MyReg
Example:
MyReg
MOVLW
MOVWF
DECF
DECF
DECF
DECF
DECFSZ
SET
Ox39
MyReg
MyReg
MyReg
MyReg
MyReg
iset aside loc for MyReg
;WREG = 99H
; MyReg = 99H
;WREG = 98H, MyReg = 99H
;WREG
97H, MyReg
99H
;WREG = 96H, MyReg = 99H
Ox50 ;set MyReg
;W = 39H
; MyReg = 39H
;WREG = 38H and
;WREG = 37H and
;WREG = 36H and
;WREG
35H and
loc at Ox50
MyReg = 39H
MyReg = 39H
MyReg
39H
MyReg = 39H
Decrement fileReg and Skip if zero
Function:
Syntax:
Decrement fileReg and skip if fileReg has zero in it
DECFSZ f, d, a
This instruction subtracts 1 from the byte operand of fileReg. If the result
is zero, then it skips execution of the next instruction.
Example: Toggle PORTB 250 times.
SET Ox40
CLRF TRISB
MOVLW D'250'
MOVWF COUNT
MOVLW Ox55
MOVWF PORTB
BACK COMF PORTB,F
DECFSZ COUNT,F
COUNT
BRA
DECFSNZ
Function:
Syntax:
iloc 40H for COUNT
;PORTB an output
;WREG = 250
; COUNT = 250
;WREG = 55H
;toggle PORTB
;decrement COUNT and
;skip if zero
BACK ;toggle until counter becomes 0
Decrement fileReg and skip if not zero
Decrement fileReg and skip if fileReg has other than zero
DECFSNZ f, d, a
This instruction subtracts 1 from the byte operand of fileReg. If the result
is not zero, then it skips execution of the next instruction.
APPENDIX A: PIClS INSTRUCTIONS: FORMAT AND DESCRIPTION
699
Example: Toggle PORTB 250 times continuously.
COUNT
SET Ox40 ;loc 40H for COUNT
CLRF TRISB
;PORTB an output
OVER MOVLW D'250'
;WREG = 250
MOVWF COUNT
; COUNT = 250
MOVLW Ox55
;WREG = 55H
MOVWF PORTB
BACK COMF PORTB,F
;toggle PORTB
DECFSNZ COUNT,F ;decrement COUNT and
; skip i f zero
BRA OVER
;start over
BRA BACK ;toggle until counter becomes 0
GOTO
Unconditional Branch
Function:
Syntax:
Transfers control unconditionally to a new address.
GOTO
k
In the PICI8 there are two unconditional branches (jumps): GOTO (long
jump) and BRA (short jump). Each is described next.
I. GOTO (long jump): This is a 4-byte instruction. The first 12 bits are the
opcode, and the next 20 bits are an even address of the target location. Because
all the PICI8 instructions are 2 bytes in size, the lowest address bit, AO, is
automatically set to zero to make sure that the GOTO instruction will not land
at the middle of the targeted instruction. The 20-bit address of the GOTO provides the A20-AI part of the address and with AO = 0, we have the 2I-bit
address needed to go anywhere in the 2M address space of the PIC 18.
2. BRA: This is a 2-byte instruction. The first 5 bits are the opcode and the
remaining 11 bits are the signed number displacement, which is added to the
PC (program counter) of the instruction following the BRA to get the target
address. Therefore, for the BRA instruction the target address must be
within-I023 to + 1024 bytes of the PC of the instruction after the BRA because
a II-bit address can take values of + 1023 to -1024.
While GOTO is used to jump to any address location within the 2M code
space of the PICI8, BRA is used to jump to a location within the IK ROM
space. The advantage of BRA is the fact that it takes 2 bytes of program ROM,
while GOTO takes 4 bytes. BRA is widely used in chips with a small amount
of program ROM and a limited number of pins.
Notice that the difference between GOTO and CALL is that the CALL
instruction will return and continue execution with the instruction following
the CALL, whereas GOTO will not return.
700
INCF
Increment fileReg
Function:
Syntax:
Increment
INCF f, d, a
This instruction adds 1 to the byte operand in fileReg. The result can be
placed in WREG (if d = 0) or fileReg (if d = 1).
Example:
MyReg SET Ox40
MOVLW Ox99
MOVWF MyReg
INCF MyReg,F
INCF MyReg,F
DECF MyReg,F
;set aside loc 40H for MyReg
;WREG = 99H
; MyReg
; MyReg
; MyReg
=
9AH, WREG 99H
9BH, WREG 99H
9CH, WREG 99H
Example: Toggle PORTB 5 times.
COUNTER
SET Ox40 ;loc 40H for COUNTER
SETF TRISB
;PORTB as output
MOVLW D'251'
;WREG = 251
MOVWF COUNTER ; COUNTER = 251
MOVLW Ox55
;WREG = 55H
MOVWF PORTB
BACK COMF PORTB,F
; toggle PORTB
INCF COUNTER,F ; INC COUNTER
BNC BACK ; toggle until counter becomes 0
We can place the result in fileReg as shown in the examples below:
MyReg SET Ox40
MOVLW Ox99
MOVWF MyReg
INCF MyReg
INCF MyReg
Example:
MyReg
MOVLW
MOVWF
INCF
INCFSZ
Function:
Syntax:
SET
Ox5
MyReg
MyReg
iset aside loc for MyReg
;WREG = 99H
; MyReg = 99H
;WREG = 9AH, MyReg = 99H
;WREG = 9BH, MyReg = 99H
Ox40 ;set MyReg loc at Ox40
;W = 05H
;MyReg = 05H
;WREG = 06H and MyReg = 05H
Increment fileReg and skip if zero
Increment
INCFSZ f, d, a
APPENDIX A: PIC18 INSTRUCTIONS: FORMAT AND DESCRIPTION
701
This instruction adds 1 to fileReg and if the result is zero it skips the next
instruction.
Example: Toggle PORTB 156 times.
COUNTER
SET Ox40 ;loc 40H for COUNTER
SETF TRISB
;PORTB as output
MOVLW D'156'
;WREG = 156
COUNTER
MOVWF
; COUNTER = 156
MOVLW Ox55
;WREG = 55H
MOVWF PORTB
BACK COMF PORTB,F
;toggle PORTB
INCFSZ COUNTER,F ;INC COUNTER and skip if 0
BRA BACK ;toggle until counter becomes 0
INCFSNZ
Increment fileReg and skip if not zero
Function:
Syntax:
Increment
INFSNZ f, d, a
This instruction adds I to the register or memory location specified by the
operand. If the result is not zero, it skips the next instruction.
Example: Toggle PORTB 156 times continuously.
COUNTER
SET Ox40 ;loc 40H for COUNTER
SETF TRISB
;PORTB as output
OVER MOVLW D'156'
;WREG = 156
MOVWF COUNTER ; COUNTER = 156
MOVLW Ox55
;WREG = 55H
MOVWF PORTB
BACK COMF PORTB,F
;toggle PORTB
INCFSNZ COUNTER,F;INC COUNTER, skip if not 0
BRA OVER ;start over
BRA BACK ;toggle until counter becomes 0
IORLW
Function:
Syntax:
OR K value with WREG
Logical-OR WREG with value k
IORLW
k
This performs a logical OR on the WREG register and
and stores the result in WREG.
A
0
Example:
0
MOVLW Ox30
;W = 30H
1
IORLW Ox09
inow W = 39H
1
702
k value, bit by bit,
B AORB
0
0
1
1
1
0
1
1
39H
09H
39
0011 0000
0000 1001
0011 1001
Example:
MOVLW Ox32
IORLW Ox50
32H
50H
72H
IORWF
;W
; (W
=
=
32H
72H)
0011 0010
0101 0000
0111 0010
OR FileReg with WREG
Function:
Syntax:
Logical-OR fileReg and WREG
IORWF f, d, a
This performs a logical OR on the fileReg value and the WREG register,
bit by bit, and places the result in WREG (if d = 0) or fileReg (if d = I).
Example:
MyReg
MOVLW
MOVWF
MOVLW
IORWF
39
07
3F
Example:
MyReg
MOVLW
MOVWF
MOVLW
IORWF
05
30
35
SET Ox40;set MyReg loc at Ox40
Ox39
;WREG = 39H
MyReg
; MyReg = 39H
Ox07
MyReg
;39H ORed with 07 (W = 3F)
0011 1001
0000 0111
0011 1111
SET Ox40;set MyReg loc at Ox40
Ox5
;WREG = 05H
MyReg
;MyReg = 05H
Ox30
;30H ORed with 05 (W = 35H)
MyReg
0000 0101
0011 0000
0011 0101
We can place the result in fileReg as shown in the examples below:
MOVLW Ox30
IORWF PORTB,F
;W = 30H
;W and PORTB are ORed and result
;goes to PORTB
APPENDIX A: PIC1S INSTRUCTIONS: FORMAT AND DESCRIPTION
703
Example:
MyReg
SET Ox20
MOVLW Ox54
;WREG = 54H
MOVWF MyReg
MOVLW Ox67
;WREG = 67H
IORWF MyReg,F ;OR WREG and MyReg
;after the operation MyReg = 77H
44H
67H
77H
0101 0100
0110 0111
0111 0111 Therefore MyReg will have 77H, WREG
LFSR
=
54H.
Load FSR
Function:
Syntax:
Load into FSR registers a 12-bit value ofk
LFSR f,k
;k is between 000 and FFFH
This loads a l2-bit value into one of the FSR registers ofFSRO, FSRl, or
FSR2.
LFSR 0
LFSR 1
LFSR 2
Ox200 ;FSRO = 200H
Ox050 ;FSR1 = 050H
Ox160 ;FSR2 = 160H
This is widely used in register indirect addressing mode. See Chapter 6.
MOVF (or MOVFW)
Function:
Syntax
Move fileReg to WREG
Copy byte from fileReg to WREG
MOVF f, d, a:
This instruction is widely used for moving data from a fileReg to WREG. Look
at the following examples:
CLRF
SETF
MOVFW
ANDLW
MOVWF
TRISC
TRISB
PORTB
OxOF
PORTC
;PORTC output
;PORTB as input
;copy PORTB to WREG
;mask the upper 4 bits
;put it in PORTC
Example:
CLRF
SETF
MOVFW
IORW
MOVWF
TRISD
TRISB
PORTB
Ox30
PORTD
;PORTD as output
;PORTB as input
;copy PORTB to WREG
;OR it with 30H
;put it in PORTD
This instruction can be used to copy the fileReg to itself in order to get the status
of the Nand Z flags. Look at the following example.
704
Example:
MyReg SET Ox20
MOVLW Ox54
MOVWF MyReg
MOVFW MyReg,F
MOVFF
;set aside loc Ox20 to MyReg
;W = 54H
; MyReg
54H
;My Reg = 54, also N
0 and Z
0
Move FileReg to Filereg
Function:
Syntax:
Copy byte from one fileReg to another fileReg
MOVFF fs, fd
This copies a byte from the source location to the destination. The source
and destination locations can be any of the file register locations, SFRs, or ports.
MOVFF
PORTB,MyReg
MOVFF
PORTC,PORTD
MOVFF
RCREG,PORTC
Regl,REG2
MOVFF
Notice that this a 4-byte instruction because the source and destination
address each take 12 bits of the instruction. That means the 24 bits of the instruction are used for the source and destination addresses. The 12-bit address allows
data to be moved from any source location to any destination location within the
4K RAM space of the PICI8.
MOVLB
Move Literal 4-bit value to lower 4-bit of the BSR
Function:
Syntax:
Move 4-bit value k to lower 4 bits of the BSR registers
MOVLB
k
;k is between 0 and 15 (O-F in hex)
We use this instruction to select a register bank other than the access bank.
With this instruction we can load into the BSR (bank selector register) a 4-bit value
representing one of 16 banks supported by the PICI8. That means the values
between 0000 and 1111 (O-F in hex). For examples of the MOVLB instruction,
see Chapter 6 and Section A.I in this chapter.
MOVLW
K
Move Literal to WREG
Function:
Syntax:
Move 8-bit value k to WREG
MOVLW
k;k is between 0 and 255 (O-FF in hex)
Example:
MOVLW
MOVLW
MOVLW
MOVLW
Ox55
OxO
OxC2
Ox7F
;WREG = 55H
;clear WREG (WREG = 0)
;WREG = C2H
;WREG = 7FH
This instruction, along with the MOVWF, is widely used to load fixed values into any port, SFR, or fileReg location. See the next instruction to see how it
is used.
APPENDIX A: PIC18 INSTRUCTIONS: FORMAT AND DESCRIPTION
705
MOVWF
Function:
Syntax:
Move WREG to a meReg
Copy the WREG contents to a fileReg
MOVWFf,a
This copies a byte from WREG to fileReg. This instruction is widely used
along with the MOVLW instruction to load any of the fileReg locations, SFRs, or
PORTs with a fixed value. See the following examples:
Example: Toggle PORTB.
MOVLW
Ox55
PORTB
MOVWF
MOVLW
OxAA
MOVWF
PORTB
BRA
OVER
iWREG = 55H
iWREG = AAH
ikeep toggling the PORTB
Example: Load RAM location 20H with value 50H.
MyReg SET Ox20 ;set aside the loc Ox20 for MyReg
MOVLW
Ox50
MOVWF
MyReg
iMyReg = 50H (loc 20H has 50H)
Example: Initialize the TimerO low and high registers.
MOVLW
Ox05
;WREG = 05H
MOVWF
TMROH
iTMROH = Ox5
MOVLW
Ox30
;WREG = 30H
MOVWF
TMROL
;TMROL = Ox30
MULLW
Function:
Syntax:
Multiply Literal with WREG
Multiply k x WREG
MULLW
k
This multiplies an unsigned byte k by an unsigned byte in register WREG
and the 16-bit result is placed in registers PRODH and PRODL, where PRODL
has the lower byte and PRODH has the higher byte.
Example:
MOVLW Ox5
MULLW Ox07
Example:
MOVLW OxOA
MULLW OxOF
iWREG = 5H
iPRODL = 35 = 23H, PRODH = 00
;WREG = 10
;PRODL = 10 x 15
;PRODH = 00
Example:
MOVLW Ox25
MULLW Ox78
;PRODL
;because 25H x 78H
706
=
=
150
58H, PRODH = IlH
1158H
=
96H
Example:
MOVLW D' 100'
;WREG = 100
MULLW D'200'
;PRODL = 20H, PRODH = 4EH
;(100 x 200 = 20,000 = 4E20H)
MULWF
Multiply WREG with fileReg
Multiply WREG x fileReg and place the result in
PRODH:PROFDL registers
MULWF f, a
Function:
Syntax:
This multiplies an unsigned byte in WREG by an unsigned byte in the
fileReg register and the result is placed in PRODL and PRODH, where PRODL
has the lower byte and PRODH has the higher byte.
Example:
MyReg
SET Ox20 ; MyReg has location of Ox20
MOVLW Ox5
; MyReg has Ox5
MOVWF MyReg
MOVLW Ox7
;WREG = Ox7
;PRODL = 35 = 23H, PRODH
MULWF MyReg
00
Example:
MOVLW OxOA
MOVWF MyReg
; MyReg = 10
MOVLW OxOF
;WREG = 15
;PRODL = 150 = 96H, PRODH
MULFW MyReg
00
Example:
MOVLW
MOVWF
MOVLW
MULWF
Ox25
MyReg
Ox78
Myreg
MOVLW
MOVWF
MOVLW
MULWF
;WREG = 100
D'100'
; MyReg = 100
MyReg
;WREG = 200
D'200'
20H, PRODH = 4EH
MyReg
;PRODL
; (100 x 200 = 20,000 = 4E20H)
; MyReg = Ox25
;WREG 78H
;PRODL = 58H, PRODH
; (25H x 78H = 1158H)
= 11H
Example:
NEGF
Negate fileReg
Function:
Syntax:
No operation
NEGF f, a
This performs 2's complement on the value stored in fileReg and places it
back in fileReg.
APPENDIX A: PIC18 INSTRUCTIONS: FORMAT AND DESCRIPTION
707
Example:
MyReg
SET Ox30
MOVLW Ox98
;WREG = Ox98
MOVWF MyReg
; MyReg = Ox98
NEGF
i 2 's complement fileReg
98H
10011000
01100111
1
+
01101000
1'8 complement
Now FileReg = 68H
Example:
MyReg
SET Ox10
MOVLW Ox75
;WREG = Ox75
MOVWF MyReg
; MyReg = Ox75
; 2 S complement fileReg
NEGF
I
75H
01110101
10001010
+
1'8 complement
1
10001011
Now FileReg = 7AH
Notice that in this instruction we cannot place the result in the WREG
register.
NOP
No Operation
Function:
Syntax:
No operation
NOP
This performs no operation and execution continues with the next instruction. It is sometimes used for timing delays to waste clock cyles. This instruction
only updates the PC (program counter) to point to the next instruction following
NOP. In PICI8, this a 2-byte instruction.
POP
POP Top of Stack
Function:
Syntax:
Pop from the stack
POP
This takes out the top of stack (TOS) pointed to by SP (stack pointer) and
discards it. It also decrements SP by I. After the operation, the top of the stack will
be the value pushed onto the stack previously.
PUSH Top of the Stack
PUSH
Function:
Syntax:
Push the PC onto the stack
PUSH
This copies the program counter (PC) onto the stack and increments SP by
I, which means the previous top of the stack is pushed down.
708
RCALL
Function:
Syntax:
Relative Call
Transfers control to a subroutine within I K space
RCALL target_address
There are two types of CALLs: RCALL and CALL. In RCALL, the target
address is within 1K of the current PC (program counter). To reach the target
address in the 2M ROM space of the PIC18, we must use CALL. In calling a subroutine, the PC register (which has the address of the instruction after the RCALL)
is pushed onto the stack and the stack pointer (SP) is incremented by 1. Then the
program counter is loaded with the new address and control is transferred to the
subroutine. At the end of the procedure, when RETURN is executed, PC is popped
off the stack, which returns control to the instruction after the RCALL.
Notice that RCALL is a 2-byte instruction, in which 5 bits are used for the
opcode and the remaining 11 bits are used for the target subroutine address. An 11bit address limits the range to -1024 to +1023. See the CALL instruction for discussion of the target address being anywhere in the 2M ROM space of the PIC18.
Notice that RCALL is a 2-byte instruction while CALL is a 4-byte instruction.
Also notice that the RCALL does not have the option of context saving, as CALL
has.
RESET
Function:
Syntax:
Reset (by software)
Reset by software
RESET
This instruction is used to reset the PIC 18 by way of software. After
execution of this instruction, all the registers and flags are forced to their reset condition. The reset condition is created by activating the hardware pin MCLR. In
other words, the RESET instruction is the software version of the MCLR pin.
RETFIE
Function:
Syntax:
Return from Interrupt Exit
Return from interrupt
RETFIE s
This is used at the end of an interrupt service routine (interrupt handler).
The top of the stack is popped into the program counter and program execution
continues at this new address. After popping the top of the stack into the program
counter (PC), the stack pointer (SP) is decremented by 1.
Notice that while the RETURN instruction is used at the end of a subroutine associated with the CALL and RCALL instructions, RETFIE must be used for
the interrupt service routines (ISRs).
APPENDIX A: PICIS INSTRUCTIONS: FORMAT AND DESCRIPTION
709
RETLW
Return with Literal in WREG
Function:
Syntax:
The k value is placed in WREG and the top of the stack is
the placed in PC (program counter)
RETLW
k
After execution of this instruction, the k value is loaded into WREG and
the top of the stack is popped into the program counter (PC). After popping the
top of the stack into the program counter, the stack pointer (SP) is decremented by
I. This instruction is used for the implementation of a look-up table. See Section
6.3 in Chapter 6.
RETURN
Return
Function:
Syntax:
Return from subroutine
RETURN
s
;where s = 0 or s = I
This instruction is used to return from a subroutine previously entered by
instructions CALL or RCALL. The top of the stack is popped into the program
counter (PC) and program execution continues at this new address. After popping
the top of the stack into the program counter, the stack pointer (SP) is decremented by 1. For the case of "RETURN s" where s = I, the RETURN will also
restore the context registers. See the CALL instruction for the case of s = I. Notice
that "RETURN I" cannot be used for subroutines associated with RCALL.
RLCF
Rotate Left Through Carry the fileReg
Function:
Syntax:
Rotate fileReg left through carry
RLCF f, d, a
This rotates the bits of a , - - - - - - - - - - - - - - - - - ,
fileReg register left. The bits rotated
out of fileReg are rotated into C, and
Cy
the C bit is rotated into the opposite
end of the fileReg register.
[
Example:
MyReg SET Ox30
BCF STATUS,C
MOVLW Ox99
MOVWF MyReg
RLCF MyReg,F
RLCF MyReg,F
710
-lr-M-S-S~.-=-----Ls-s-'IJ
;set aside lac 30H for MyReg
;C = 0
;WREG = 99H
;MyReg = 99H = 10011001
;now MyReg = 00110010 and
;C = 1
;now MyReg
01100101 and
;C = 0
Rotate left not through Carry
RLNCF
Function:
Syntax:
Rotate left the fileReg
RLNCF f, d, a
This rotates the bits of a fileReg
register left. The bits rotated out of
fileReg are rotated back into fileReg at
the opposite end.
[I
MSB - - - - LSB
Example:
MyReg
MOVLW
MOVWF
RLNCF
RLNCF
RLNCF
RLNCF
SET Ox20 iset aside loc 20 for MyReg
;WREG = 01101001
Ox69
; MyReg = 69B = 01101001
MyReg
MyReg,F inow MyReg
11010010
MyReg,F inow MyReg = 10100101
MyReg,F inow MyReg = 01001011
MyReg,F inow MyReg = 10010110
Notice that after four rotations, the upper and lower nibbles are swapped.
Rotate Right through Carry
RRCF
Function:
Syntax:
Rotate fileReg right through carry
RRCF f, d, a
This rotates the bits of a
file Reg register right. The bits rotated
out of the register are rotated into C,
and the C bit is rotated into the
opposite end of the register.
[I
MSB - - .. LSB
1_ ]
Cy
Example:
MyReg SET Ox20 iset
BSF STATUS,C
MOVLW Ox99
MOVWF MyReg
RRCF MyReg,F
RRCF MyReg,F
RRNCF
Function:
Syntax:
aside loc 20 for MyReg
;C = 1
;WREG = 10011001
; MyReg = 99B = 10011001
1
inow MyReg = 11001100, C
;now MyReg = 11100110, C = 0
Rotate Right not through Carry
Rotate fileReg right
RRNCF f, d, a
This rotates the bits of a fileReg reg- r - - - - - - - - - - - - - - - - ,
ister right. The bits rotated out of the register
are rotated back into fileReg at the opposite
MSB - _
.. LSB
end.
[I
APPENDIX A: PIC18 INSTRUCTIONS: FORMAT AND DESCRIPTION
r-I
711
Example:
MyReg SET Ox20 iset
MOVLW Ox66
MOVWF MyReg
RRNCF MyReg,F
RRNCF MyReg,F
RRNCF MyReg,F
RRNCF MyReg,F
aside loc 20H for MyReg
;WREG = 66H = 01100110
; MyReg = 66H = 01100110
inow MyReg = 00110011
10011001
inow MyReg
inow MyReg = 11001100
inow MyReg = 01100110
Example: We can use this instruction to swap the upper and lower nibbles.
MyReg SET Ox20 ;set aside loc 20H for MyReg
MOVLW Ox36
;WREG = 36H = 00110110
MOVWF MyReg
;MyReg = 36H = 00110110
RRNCF MyReg,F ;now MyReg = 00011011
10001101
RRNCF MyReg,F ;now MyReg
RRNCF MyReg,F ;now MyReg = 11000110
RRNCF MyReg, F ;now MyReg
01100011
63H
SETF
Set fileReg
Function:
Syntax:
Set
SETF f, a
This instruction sets the entire byte in fileReg to HIGH. All bits of the register are set to 1.
Examples:
SETF MyReg
;MyReg = 11111111
SETF TRISB ;TRISB = FFH, (makes PORTB input)
SETF PORTC
;PORTC = 1111 1111
Notice that in this instruction, the result can be placed in fileReg only and
there is no option for WREG to be used as the destination for the result.
SLEEP
Function:
Syntax:
Enter Sleep mode
Put the CPU into sleep mode
SLEEP
This instruction stops the oscillator and puts the CPU into sleep mode. It
also resets the Watchdog Timer (WDT). The WDT is used mainly with the SLEEP
instruction. Upon execution of the SLEEP instruction, the entire microcontroller
goes into sleep mode by shutting down the main oscillator and by stopping the
Program Counter from fetching the next instruction after SLEEP. There are two
ways to get out of sleep mode: (a) an external event via hardware interrupt, (b) the
internal WDT interrupt. Upon wake-up from a WDT interrupt, the microcontroller
resumes operation by executing the next instruction after SLEEP.
Check the Microchip Corp. website for application notes on WDT.
712
SUBFWB
Function:
Syntax:
Subtract fileReg from WREG with borrow
WREG - fileReg - #borrow ;#borrow is inverted carry
SUBFWB f, d, a
This subtracts fileReg and the Carry (borrow) flag from WREG and puts
the result in WREG (d = 0) or fileReg (d = I). The steps for subtraction performed
by the internal hardware of the CPU are as follows:
1.
2.
3.
4.
5.
Take the 2's complement of the fileReg byte.
Add this to register WREG.
Add the inverted Carry (borrow) flag to the result.
Ignore the Carry.
Examine the N (negative) flag for positive or negative result.
Example:
MyReg SET Ox20
BSF STATUS,C
MOVLW Ox45
MOVWF MyReg
MOVLW Ox23
SUBWF MyReg
45H
-23H
;set aside loc Ox20 for MyReg
;make Carry = 1
;WREG 45H
;MYReg = 45H
=
;WREG
45H - 23H - 0
=
22H
0100 0101
0100 0101
0010 0011 2's comp + 1101 1101
Inverted carry +
o
+22H
Because D7
positive.
(the
N
flag)
is
0010 0010
0, the result
is
This instruction sets the negative flag according to the following:
N
WREG > (fileReg + #C)
WREG = (fileReg + #C)
WREG < (fileReg + #C)
SUBLW
Function:
Syntax:
o
o
I
the result is positive
the result is 0
the result is negative and in 2's comp
Subtract WREG from Literal value
Subtract WREG from literal value k (WREG = k - WREG)
SUBLW
k
This subtracts the WREG value from the literal value k and puts the result
in WREG. The steps for subtraction performed by the internal hardware of the
CPU are as follows:
1.
2.
3.
4.
Take the 2's complement of the WREG value.
Add it to literal value k.
Ignore the Carry.
Examine the N (negative) flag for positive or negative result.
APPENDIX A: PIClS INSTRUCTIONS: FORMAT AND DESCRIPTION
713
MOVLW Ox23
SUBLW Ox45
45H
-23H
;WREG 23H
;WREG ; 45H - 23H ;
0100 0101
0010 0011 2's comp
+22H
Because D7
positive.
(the
N
flag)
is
22H
0100 0101
+1101 1101
0010 0010
0, the result
is
This instruction sets the negative flag according to the following:
N
Literal value k > WREG
Literal value k = WREG
Literal value < WREG
Example:
MOVLW Ox98
SUBLW Ox66
66H
-98H
o
o
I
the result is positive
the result is 0
the result is negative and in 2's comp
;WREG 98H
;WREG = 66H - 98H ; CEH
0110 0110
1001 1000 2's comp
CEH
Because D7 (the N flag)
negative and in 2's compo
SUBWF
Function:
Syntax:
0110 0110
+0110 1000
is
1100 1110
1, the result
is
Subtract WREG from fileReg
Subtract WREG from fileReg (Dest = fileReg - WREG)
SUBWF f, d, a
This subtracts the WREG value from the fileReg value and puts the result
in either WREG (d = 0) or fileReg (d = I). The steps for subtraction perfonned by
the internal hardware of the CPU are as follows:
I.
2.
3.
4.
714
Take the 2's complement of the WREG byte.
Add this to the fileReg register.
Ignore the carry.
Examine the N (negative) flag for positive or negative result.
Example:
MyReg SET Ox20 ; set aside loc Ox20 for MyReg
MOVLW Ox45
;WREG 45H
;MYReg ; 45H
MOVWF MyReg
;WREG ; 23H
MOVLW Ox23
22H
SUBWF MyReg,F ;MyReg ; 45H - 23H
45H
-23H
0100 0101
0010 0011 2's comp
+22H
Because D7
positive.
(the
N
flag)
is
0100 0101
+1101 1101
0010 0010
0, the result
is
This instruction sets the negative flag according to the following:
N
fileReg > WREG
the result is positive
o
fileReg = WREG
the result is 0
o
fileReg < WREG
the result is negative and in 2's comp
1
SUBWFB
Subtract WREG from fileReg with borrow
Function: Dest = fileReg - WREG - #borrow ;#borrow is inverted carry
Syntax: SUBWFB f, d, a
This subtracts the WREG value and the inverted borrow (carry) flag from
the fileReg value and puts the result in WREG (if d = 0), or fileReg (if d = 1). The
steps for subtraction performed by the internal hardware of the CPU are as follows:
I. Take the 2's complement ofWREG.
2.
3.
4.
5.
Add this to fileReg.
Add the inverted Carry flag to the result.
Ignore the carry.
Examine the N (negative) flag for positive or negative result.
Example:
MyReg SET Ox20 ;set aside loc Ox20 for MyReg
BSF
STATUS,C;C = 1
MOVLW Ox45
;WREG 45H
MOVWF MyReg
;MYReg = 45H
MOVLW Ox23
;WREG = 23H
SUBWFB MyReg,F ;MyReg = 45H - 23H - 0 = 22H
45H
-23H
0100 0101
0100 0101
0010 0011 2's comp +1101 1101
Inverted carry +
0
+22H
Because D7
positive.
(the
N
flag)
is
0010 0010
0, the result
APPENDIX A: PIC1S INSTRUCTIONS: FORMAT AND DESCRIPTION
is
715
This instruction sets the negative flag according to the following:
N
o
the result is positive
fileReg > (WREG + #C)
fileReg = (WREG + #C)
the result is 0
o
the result is negative and in 2's comp
fileReg < (WREG + #C)
I
Swap Nibbles in fiIeReg
SWAPF
Function:
Syntax:
Swap nibbles within fileReg
SAWPF f, d, a
The SWAPF instruction interchanges the lower nibble (DO-D3) with the
upper nibble (D4-D7) inside fileReg. The result is placed in WREG (d = 0) or
fileReg (d = I).
Example:
MyReg
MOVLW
MOVWF
SWAPF
TBLRD
SET OX20 ;set aside loc 20H
Ox59H
;W = 59H (0101 1001
MyReg
; MyReg
59H (0101
MyReg,F ;MyReg = 95H (1001
for MyReg
in binary)
1001)
0101)
Table Read
Function:
Syntax:
Read a byte from ROM to the TABLAT register
TBLRD *
TBLRD *+
TBLRD *TBLRD+*
This instruction moves (copies) a byte of data located in program (code)
ROM into the TableLatch (TABLAT) register. This allows us to put strings of data,
such as look-up table elements, in the code space and read them into the CPU. The
address of the desired byte in the program space (on-chip ROM) is held by the
TBLPTR register. Table A-6 shows the auto-increment feature of the TBLRD
instruction.
Table A-6: PIelS Table Read Instructions
Instruction
TBLRD*
TBLRD*+
TBLRD*TBLRD+*
Note: A byte of data
TBLPTR.
Function
Table Read
After read, TBLPTR stays the same
Table Read with post-increment (Read and increment TBLPTR)
Table Read with post-decrement (Read and decrement TBLPTR)
Table Read with pre-increment (increment TBLPTR and read )
is read into the TABLAT register from code space pointed to by
Example: Assume that an ASCII character string is stored in the on-chip
ROM program memory starting at address SOOR. Write a program to bring each
character into the CPU and send it to PORTB.
ORG
716
OOOOH
;burn into ROM starting at 0
MOVLW
MOVWF
MOVLW
MOVWF
CLRF
LOW (MESSAGE)
TBLPTRL
HIGH (MESSAGE)
TBLPTRH
TBLPTRU
;WREG = 00 low-byte addr.
; look-up table low-byte addr
;WREG = 05 = high-byte addr
; look-up table high-byte addr
;clear upper 5 bits
B8
TBLRD*+
;read the table,then increment TBLPTR
MOVF TABLAT,W
;copy to WREG (Z = 1 i f null)
BZ
EXIT
;exit if end of string
MOVWF PORTB
;copy WREG to PORTB
BRA
B8
EXIT GOTO EXIT
;---------------------message
ORG Ox500
;data burned starting at Ox500
ORG Ox500
MESSAGE
DB
"The earth is but one country and "
"mankind its citizens","Baha'u'llah",O
DB
END
In the program above, the TBLPTR holds the address of the desired byte.
After the execution of the TBLRD*+ instruction, register TABLAT has the character. Notice that TBLPTR is incremented automatically to point to the next character in the MRESSAGE table.
TBLWT
Function:
Syntax:
Table Write
Write to Flash a block of data
TBLWT*
TBLWT*+
TBLWT*TBLWT+*
This instruction writes a block of data to the program (code) space assuming that the on-chip program ROM is of Flash type. The address of the desired
location in Flash ROM is held by the TBLPTR register. The process of writing to
Flash ROM using the TBLWT instruction is discussed in Section 14.3 of Chapter
14.
TSTFSZ
Function:
Syntax:
Test fileReg. Skip if Zero
Test fileReg for zero value and skip if it is zero
TSTFSZ f, a
This instruction tests the entire contents of fileReg for value zero and skips
the next instruction if fileReg has zero in it.
Example: Test PORTB for zero continuously.
SETF TRISB
;make PORTB an input
CLRF TRISD
;make PORTD an output
APPENDIX A: PIC18 INSTRUCTIONS: FORMAT AND DESCRIPTION
717
BACK TSTFSZ PORTB
BRA
BACK
MOVFF PORTB,PORTD
Example: Toggle PORTB 250 times.
COUNTER
SET Ox40
SETF TRISB
MOVLW D'250'
MOVWF COUNTER
MOVLW Ox55
MOVWF PORTB
BACK COMF PORTB,F
DECF COUNTER,F
TSTFSZ COUNTER
BRA BACK
XORLW
;loc 40H for COUNTER
;PORTB as output
;WREG = 250
; COUNTER = 250
;WREG = 55H
;toggle PORTB
; decrement COUNTER
;test counter for 0
;keep doing it
Ex-Or Literal with WREG
Function:
Syntax:
Logical exclusive-OR Literal k and WREG
XORLW
k
This performs a logical exclusive-OR on the A
B AXORB
Literal value and WREG operands, bit by bit, storing 0
0
0
the result in WREG.
0
1
1
1
1
0
Example:
1
1
0
MOVLW Ox39
;WREG = 39H
XORLW Ox09
;WREG = 39H ORed with 09
;now, WREG = 30H
0011 1001
39H
09H
0000 1001
30
0011 0000
Example:
MOVLW Ox32
XORLW Ox50
32H
50H
62H
XORWF
Function:
Syntax:
;WREG = 32H
; (now, WREG
62H)
0011 0010
0101 0000
0110 0010
Ex-Or WREG with fileReg
Logical exclusive-OR fileReg and WREG
XORWF
f,d,a
This performs a logical exclusive-OR on the operands, bit by bit, storing
718
the result in the destination. The destination can be WREG (d
(d = I).
Example:
MyReg
MOVLW
MOVWF
MOVLW
XORWF
39H
09H
30
Example:
MyReg
MOVLW
MOVWF
MOVLW
XORWF
32H
SOH
62H
SET Ox20
Ox39
MyReg
Ox09
MyReg,F
=
0), or fileReg
jset aside loc 20h for MyReg
;WREG = 39H
; MyReg = 39H
;WREG = 09H
; MyReg = 39H ORed with 09
;MyReg = 30H
0011 1001
0000 1001
0011 0000
SET OxlS
Ox32
MyReg
OxSO
MyReg,F
;set aside loc 15 for MyReg
;WREG = 32H
;MyReg = 32H
;WREG = SOH
;now W = 62H
0011 0010
0101 0000
0110 0010.
We can place the result in WREG.
Example:
MyReg
MOVLW
MOVWF
MOVLW
XORWF
44H
67H
23H
SET OxlS
Ox44
MyReg
Ox67
MyReg
;set aside loc 15 for MyReg
;WREG = 44H
; MyReg = 44H
;WREG = 67H
44H
;now W = 23H, and MyReg
0100 0100
0110 0111
0010 0011
APPENDIX A: PIC18 INSTRUCTIONS: FORMAT AND DESCRIPTION
719
APPENDIXB
BASICS OF
WIRE WRAPPING
OVERVIEW
This appendix shows the basics of wire wrapping.
.
721
BASICS OF WIRE WRAPPING
Note: For this tutorial appendix, you will need the following:
Wire-wrapping tool (Radio Shack part number 276-1570)
30-gauge (30-AWG) wire for wire wrapping
(Thanks to Shannon Looper and Greg Boyle for their assistance on this section.)
The following describes the basics of wire wrapping:
I. There are several different types of wire-wrap tools available. The best one is
2.
3.
4.
5.
6.
7.
8.
722
available from Radio Shack for less than $10. The part number for the Radio
Shack model is 276-1570. This tool combines the wrap and unwrap functions
in the same end of the tool and includes a separate stripper. We found this to
be much easier to use than the tools that combined all these features on one
two-ended shaft. There are also wire-wrap guns, which are, of course, more
expensIve.
Wire-wrapping wire is available prestripped in various lengths or in bulk on a
spool. The prestripped wire is usually more expensive and you are restricted to
the different wire lengths you can afford to buy. Bulk wire can be cut to any
length you wish, which allows each wire to be custom fit.
Serveral different types of wire-wrap boards are available. These are usually
called perfboards or wire-wrap boards. These types of boards are sold at many
electronics stores (such as Radio Shack). The best type of board has plating
around the holes on the bottom of the board. These boards are better because
the sockets and pins can be soldered to the board, which makes the circuit more
mechanically stable.
Choose a board that is large enough to accommodate all the parts in your
design with room to spare so that the wiring does not become too cluttered. If
you wish to expand your project in the future, you should be sure to include
enough room on the original board for the complete circuit. Also, if possible,
the layout of the IC on the board needs to be such that signals go from left to
right just like the schematics.
To make the wiring easier and to keep pressure off the pins, install one standoff on each comer of the board. You may also wish to put standoffs on the top
of the board to add stability when the board is on its back.
For power hook-up, use some type of standard binding post. Solder a few single wire-wrap pins to each power post to make circuit connections (to at least
one pin for each IC in the circuit).
To further reduce problems with power, each IC must have its own connection
to the main power of the board. If your perfboard does not have built-in power
buses, run a separate power and ground wire from each IC to the main power.
In other words, DO NOT daisy chain (chip-to-chip connection is called daisy
chain) power connections, as each connection down the line will have more
wire and more resistance to get power through. See Figure B-1. However,
daisy chaining is acceptable for other connections such as data, address, and
control buses.
You must use wire-wrap sockets. These sockets have long square pins whose
edges will cut into the wire as it is wrapped around the pin.
9. Wire wrapping will not work on round legs. If you need to wrap to components, such as capacitors, that have round legs, you must also solder these connections. The best way to connect single components is to install individual
wire-wrap pins into the board and then solder the components to the pins. An
alternate method is to use an empty IC socket to hold small components such
as resistors and wrap them to the socket.
10. The wire should be stripped about I inch. This will allow 7 to 10 turns for each
connection. The first turn or turn-and-a-half should be insulated. This prevents
stripped wire from coming in contact with other pins. This can be accomplished by inserting the wire as far as it will go into the tool before making the
connection.
II. Try to keep wire lengths to a minimum. This prevents the circuit from looking
like a bird nest. Be neat and use color coding as much as possible. Use only
red wires for Vee and black wires for ground connections. Also use different
colors for data, address, and control signal connections. These suggestions will
make troubleshooting much easier.
12. It is standard practice to connect all power lines first and check them for continuity. This will eliminate trouble later on.
13. It's also a good idea to mark the pin orientation on the bottom of the board.
Plastic templates are available with pin numbers preprinted on them specifically for this purpose, or you can make your own from paper. Forgetting to
reverse pin order when looking at the bottom of the board is a very common
mistake when wire wrapping circuits.
14. To prevent damage to your circuit, place a diode (such as IN5338) in reverse
bias across the power supply. If the power gets hooked up backwards, the
diode will be forward biased and will act as a short, keeping the reversed voltage from your circuit.
15. In digital circuits, there can be a problem with current demand on the power
supply. To filter the noise on the power supply, a 100 flF electrolytic capacitor
and a 0.1 flF monolithic capacitor are connected from Vee to ground, in parallel with each other, at the entry point ofthe power supply to the board. These
two together will filter both the high- and the low-frequency noises. Instead of
using two capacitors in parallel, you can use a single 20--100 flF tantalum
capacitor. Remember that the long lead is the positive one.
16. To filter the transient current, use a 0.1 flF monolithic capacitor for each Ie.
Place the 0.1 flF monolithic capacitor between Vee and ground of each IC.
Make sure the leads are as short as possible.
Ie #1
Ie #2
Ie #3
Ie #4
FIgure B-1. DaISY Cham ConnectIOn (not recommended for power hnes)
APPENDIX B: BASICS OF WIRE WRAPPING
723
APPENDIXC
IC TECHNOLOGY AND
SYSTEM DESIGN ISSUES
OVERVIEW
This appendix provides an overview of IC technology and PIC18
interfacing. In addition, we look at the microcontroiler-based system as a
whole and examine some general issues in system design.
First, in Section C.I, we provide an overview of IC technology.
Then, in Section C.2, the internal details of PICl8 1/0 ports and interfacing are discussed. Section C.3 examines system design issues.
725
C.1: OVERVIEW OF IC TECHNOLOGY
In this section we examine IC technology and discuss some major developments in advanced logic families. Because this is an overview, it is assumed that
the reader is familiar with logic families on the level presented in basic digital
electronics books.
Transistors
The transistor was invented in 1947 by three scientists at Bell Laboratory.
In the 1950s, transistors replaced vacuum tubes in many electronics systems,
including computers. It was not until 1959 that the first integrated circuit was successfully fabricated and tested by Jack Kilby of Texas Instruments. Prior to the
invention of the IC, the use of transistors, along with other discrete components
such as capacitors and resistors, was common in computer design. Early transistors were made of germanium, which was later abandoned in favor of silicon. This
was because the slightest rise in temperature resulted in massive current flows in
germanium-based transistors. In semiconductor terms, it is because the band gap
of germanium is much smaller than that of silicon, resulting in a massive flow of
electrons from the valence band to the conduction band when the temperature rises
even slightly. By the late 1960s and early 1970s, the use of the silicon-based IC
was widespread in mainframes and minicomputers. Transistors and ICs at first
were based on P-type materials. Later on, because the speed of electrons is much
higher (about two-and-a-half times) than the speed of holes, N-type devices
replaced P-type devices. By the mid-1970s, NPN and NMOS transistors had
replaced the slower PNP and PMOS transistors in every sector of the electronics
industry, including in the design of microprocessors and computers. Since the
early 1980s, CMOS (complementary MOS) has become the dominant technology
ofIC design. Next we provide an overview of differences between MOS and bipolar transistors. See Figure C-l.
Oxide
C
B P
Cffi
EN
D
B
-
hE
Bipolar NPN Transistor
Figure C-l. Bipolar vs. MOS Transistors
726
G--[
s-
~D
, [NJ
P
[NJ
G1~s
NMOS Transistor
MOS vs. bipolar transistors
There are two types of transistors: bipolar and MOS (metal-oxide semiconductor). Both have three leads. In bipolar transistors, the three leads are
referred to as the emitter, base, and collector, while in MOS transistors they are
named source, gate, and drain. In bipolar transistors, the carrier flows from the
emitter to the collector, and the base is used as a flow controller. In MOS transistors, the carrier flows from the source to the drain, and the gate is used as a flow
controller. In NPN-type bipolar transistors, the electron carrier leaving the emitter
must overcome two voltage barriers before it reaches the collector (see Figure CI). One is the N-P junction of the emitter-base and the other is the P-N junction of
the base-collector. The voltage barrier of the base-collector is the most difficult
one for the electrons to overcome (because it is reverse-biased) and it causes the
most power dissipation. This led to the design of the unipolar type transistor called
MOS. In N-channel MOS transistors, the electrons leave the source and reach the
drain without going through any voltage barrier. The absence of any voltage barrier in the path of the carrier is one reason why MOS dissipates much less power
than bipolar transistors. The low power dissipation of MOS allows millions of
transistors to fit on a single IC chip. In today's technology, putting 10 million transistors into an IC is common, and it is all because ofMOS technology. Without the
MOS transistor, the advent of desktop personal computers would not have been
possible, at least not so soon. The bipolar transistors in both the mainframes and
minicomputers of the 1960s and 1970s were bulky and required expensive cooling
systems and large rooms. MOS transistors do have one major drawback: They are
slower than bipolar transistors. This is due partly to the gate capacitance of the
MOS transistor. For a MOS to be turned on, the input capacitor of the gate takes
time to charge up to the tum-on (threshold) voltage, leading to a longer propagation delay.
Overview of logic families
Logic families are judged according to (I) speed, (2) power dissipation, (3)
noise immunity, (4) input/output interface compatibility, and (5) cost. Desirable
qualities are high speed, low power dissipation, and high noise immunity (because
it prevents the occurrence of false logic signals during switching transition). In
interfacing logic families, the more inputs that can be driven by a single output,
the better. This means that high-driving-capability outputs are desired. This, plus
the fact that the input and output voltage levels of MOS and bipolar transistors are
not compatible mean that one must be concerned with the ability of one logic family to drive the other one. In terms of the cost of a given logic family, it is high during the early years of its introduction but it declines as production and use rise.
The case of inverters
As an example of logic gates, we look at a simple inverter. In a one-transistor inverter, the transistor plays the role of a switch, and R is the pull-up resistor. See Figure C-2. For this inverter to work most effectively in digital circuits,
however, the R value must be high when the transistor is "on" to limit the current
flow from Vee to ground in order to have low power dissipation (P = VI, where V
APPENDIX C: IC TECHNOLOGY AND SYSTEM DESIGN ISSUES
727
5 V). In other words, the lower the I, the lower the power dissipation. On the
other hand, when the transistor is "off', R must be a small value to limit the voltage drop across R, thereby making sure that V OUT is close to Vcc. This is a contradictory demand on R. This is one reason that logic gate designers use active
components (transistors) instead of passive components (resistors) to implement
the pull-up resistor R.
=
Vee
Vee
Re
Vee
Re
Out
In
Re
Low
High
~
~
~
Re must be a
very high value.
~ure
High
Low
Re must be a
very low value.
C-2. One-Transistor Inverter with Pull-up Resistor
The case of a TTL inverter with totem-pole output is shown in Figure C-3.
In Figure C-3, Q3 plays the role of a pull-up resistor.
Vee
Vee
Vee
High
High
~_ _ Out
Input
Low
f - - - Out
gure C-3. TTL Inverter with Totem-Pole Output
CMOS inverter
In the case of CMOS-based logic gates, PMOS and NMOS are used to construct a CMOS (complementary MOS) inverter as shown in Figure C-4. In CMOS
inverters, when the PMOS transistor is off, it provides a very high impedance path,
making leakage current almost zero (about 10 nA); when the PMOS is on, it provides a low resistance on the path of V DD to load. Because the speed of the hole is
slower than that of the electron, the PMOS transistor is wider to compensate for
this disparity; therefore, PMOS transistors take more space than NMOS transistors
in the CMOS gates. At the end of this section we will see an open-collector gate
in which the pull-up resistor is provided externally, thereby allowing system
designers to choose the value of the pull-up resistor.
728
"off'
J
"on"
PMOS
oV
Input 5 V
Output
J
Input 0 V
PMOS
5 V Output
NMOS
NMOS
"off'
"on"
Figure C-4. CMOS Inverter
Input/output characteristics of some logic families
In 1968 the first logic family made of bipolar transistors was marketed. It
was commonly referred to as the standard TTL (transistor-transistor logic) family.
The first MOS-based logic family, the CD4000174C series, was marketed in 1970.
The addition of the Schottky diode to the base-collector of bipolar transistors in
the early 1970s gave rise to the S family. The Schottky diode shortens the propagation delay of the TTL family by preventing the collector from going into what
is called deep saturation. Table C-I lists major characteristics of some logic families. In Table C-l, note that as the CMOS circuit's operating frequency rises, the
power dissipation also increases. This is not the case for bipolar-based TTL.
Table C-l: Characteristics of Some Logic Families
Characteristic
Vee
VIH
V1L
V OH
VOL
IlL
IIH
IOL
IOH
Propagation delay
Static power dissipation (f = 0)
Dynamic power dissipation
at f= 100 kHz
STDTTL
SV
2.0V
0.8 V
2.4 V
0.4 V
-1.6 rnA
LSTTL
SV
2.0V
0.8 V
2.7 V
0.5 V
-0.36 rnA
40 IlA
16 rnA
-400 IlA
10 ns
IOmW
20 IlA
8mA
-400 IlA
9.S ns
2mW
ALSTTL
SV
2.0V
0.8 V
2.7 V
0.4 V
-0.2 rnA
20 IlA
4mA
-400 IlA
4 ns
ImW
10mW
2mW
ImW
APPENDIX C: IC TECHNOLOGY AND SYSTEM DESIGN ISSUES
HCMOS
SV
3.IS V
l.lV
3.7 V
0.4 V
-I IlA
I IlA
4mA
4 rnA
9 ns
0.002S nW
0.17 mW
729
History of logic families
Early logic families and microprocessors required both positive and negative power voltages. In the mid-1970s, 5 V Vee became standard. In the late
1970s, advances in IC technology allowed combining the speed and drive of the S
family with the lower power of LS to form a new logic family called FAST
(Fairchild Advanced Schottky TTL). In 1985, AC/ACT (Advanced CMOS
Technology), a much higher speed version ofHCMOS, was introduced. With the
introduction of FCT (Fast CMOS Technology) in 1986, the speed gap between
CMOS and TTL at last was closed. Because FCr is the CMOS version of FAST,
it has the low power consumption of CMOS but the speed is comparable with
TTL. Table C-2 provides an overview of logic families up to FCT.
Table C-2: Logic Family Overview
Year
Product
Introduced Speed (ns)
1968
40
Std TTL
CD4KJ74C
1970
70
1971
18
LSIS
25
1977
HCIHCT
FAST
1978
6.5
AS
1980
6.2
10
ALS
1980
1985
10
AC/ACT
6.5
FCT
1986
Static Supply
Current (rnA)
30
0.3
54
0.08
90
90
27
0.08
1.5
HighlLow Family
Drive (rnA)
-2/32
-0.48/6.4
-15124
-61-6
-15/64
-15/64
-15/64
-24/24
-15/64
Reprinted by pennission of Electronic Design MagaLine, c. 1991.
Recent advances in logic families
As the speed of high-performance microprocessors reached 25 MHz, it
shortened the CPU's cycle time, leaving less time for the path delay. Designers
normally allocate no more than 25% of a CPU's cycle time budget to path delay.
Following this rule means that there must be a corresponding decline in the propagation delay of logic families used in the address and data path as the system frequency is increased. In recent years, many semiconductor manufacturers have
responded to this need by providing logic families that have high speed, low noise,
and high drive 110. Table C-3 provides the characteristics of high-performance
logic families introduced in recent years. ACQIACTQ are the second-generation
advanced CMOS (ACMOS) with much lower noise. While ACQ has the CMOS
input level, ACTQ is equipped with TTL-level input. The FCTx and FCTx-Tare
second-generation FCT with much higher speed. The "x" in the FCTx and FCTxT refers to various speed grades, such as A, B, and C, where A means low speed
and C means high speed. For designers who are well versed in using the FAST
logic family, FASTr is an ideal choice because it is faster than FAST, has higher
driving capability (IOl' IOH)' and produces much lower noise than FAST. At the
time of this writing, next to ECL and gallium arsenide logic gates, FASTr is the
fastest logic family in the market (with the 5 V Vee), but the power consumption
is high relative to other logic families, as shown in Table C-3. The combining of
730
high-speed bipolar TTL and the low power consumption of CMOS has given birth
to what is called BICMOS. Although BICMOS seems to be the future trend in IC
design, at this time it is expensive due to extra steps required in BICMOS IC fabrication, but in some cases there is no other choice. (For example, Intel's Pentium
microprocessor, a BICMOS product, had to use high-speed bipolar transistors to
speed up some of the internal functions.) Table C-3 provides advanced logic characteristics. The "x" is for different speeds designated as A, B, and C. A is the slowest one while C is the fastest one. The above data is for the 74244 buffer.
Table C-3: Advanced LOGic General Characteristics
Number Tech
110 Level
Speed (ns)
Family Year Suppliers Base
CMOSICMl)S n.O
1989 '2
CMOS
ACg
1989
2
CMOS
TTL/CMOS
ACTQ
7.5
FCTx
1987
CMOS
TTL/CMOS
4.1-4.8
3
FCTxT 1990
CMOS
TTL/TTL
4.1-4.8
2
FASTr 1990
I
BiQolar
TTL/TTL
3.9
1987
BCT
2
BICMOS TTL/TTL
5.5
Static
Current
80 I;!A
80l;!A
1.5 rnA
1.5 rnA
50 rnA
lOrnA
IOHlIoL
24724 rnA
-24/24 rnA
-15/64 rnA
-15/64 rnA
-15/64 rnA
-15/64 rnA
Reprinted by permission of Electronic Design Magazine, c. 1991.
Since the late 70s, the use of a +5 V power supply has become standard in
all microprocessors and microcontrollers. To reduce power consumption, 3.3 V
Vee is being embraced by many designers. The lowering of V cc to 3.3 V has two
major advantages: (I) it lowers the
Vee
power consumption, prolonging
External
the life of the battery in systems
pull-up
using a battery, and (2) it allows a
resistor
further reduction of line size
Input
(design rule) to submicron dimenOutput
sions. This reduction results in putting more transistors in a given die
size. As fabrication processes
improve, the decline in the line size
is reaching submicron level and
transistor densities are approaching
I billion transistors.
Figure C-S. Open Collector
-r External
Open-collector and open-drain
gates
,
pull-up
resistor
To allow multiple outputs to be connected together, we use open-collector logic gates.
In such cases, an external resistor will serve as
load. This is shown in Figures C-5 and C-6.
Figure C-6. Open Drain
APPENDIX C: IC TECHNOLOGY AND SYSTEM DESIGN ISSUES
731
SECTION C.2: PIC18110 PORT STRUCTURE AND INTERFACING
In interfacing the PIC 18 microcontroller with other IC chips or devices,
fan·out is the most important issue. To understand the PIC 18 fan-out we must first
understand the port structure of the PICI8. This section provides a detailed discussion of the PICl8 port structure and its fan-out. Itis very critical that we understand the [/0 port structure of the PICl8 lest we damage it while trying to interface it with an external device.
IC fan-out
When connecting [C chips together, we need to find out how many input
pins can be driven by a single output pin. This is a very important issue and
involves the discussion of what is called IC fan-out. The IC fan-out must be
addressed for both logic "0" and logic "1" outputs. See Example C-l. Fan-out for
logic LOW and fan-out for logic HIGH are defined as follows:
fan-out (of HIGH) =
fan-out (of LOW) =
Of the above two values, the lower number is used to ensure the proper
noise margin. Figure C-7 shows the sinking and sourcing of current when ICs are
connected together.
•
"Off"
"On"
(1\ (1\ (1\
<.
= L IlL
VOL = RoN (transistor) x
"On"
"Off"
IOH
IOL
.¢r IOL
IOL
=L
IIH
.¢r
Figure C-7. Current Sinking and Sourcing in TTL
Notice that in Figure C-7, as the number of input pins connected to a single output increases, IOL rises, which causes VOL to rise. If this continues, the rise
of VOL makes the noise margin smaller, and this results in the occurrence of false
logic due to the slightest noise.
732
Example C-I
Find how many unit loads (UL) can be driven by the output of the LS logic family.
Solution:
The unit load is defined as IlL = 1.6 mA and IIH = 40 itA. Table Col shows IOH = 400
I!A and IOL = 8 mA for the LS family. Therefore, we have
fan-out (LOW)
8mA
1.6mA
lOL
=
hL
400 I!A
lOH
fan-out (HIGH) =
=5
= 10
l/H
40 itA
This means that the fan-out is 5. In other words, the LS output must not be connected
to more than 5 inputs with unit load characteristics.
74LS244 and 74LS245 buffers/drivers
In cases where the receiver current requirements exceed the driver's capability, we must use buffers/drivers such as the 74LS245 and 74LS244. Figure C-8
shows the internal gates for the 74LS244 and 74LS245. The 74LS245 is used for
bidirectional data buses, and the 74LS244 is used for unidirectional address buses.
o
I
o
-A1
1G
Vee
1A-1
-
A2
0
Vee
r
GND
IL..-+'<....11-'
B1 B2 -
~
1Y-1
-A3
1A-2
'1"'----I1Y_2
-A4
B4-
-A5
B5 -
1A-3
'1'----11 Y-3
-A6
B6 -
1-----1
~
1A-4
B3 -
1Y-4
'1.,-----,
2A-1
2Y-1
2A-2
~'----' 2Y-2
Dire~tion
I
Enable
control
2A-3
'1.
1------1
2A-4
'1"
2Y-3
1------I'1>--~--I
GND
Function Table
2Y-4
1<3
I
Figure C-S (a). 74LS244 Octal Buffer
Enable G
L
L
H
Direction control
DIR
Operation
L
B Data to A Bus
H
A Data to B Bus
Isolation
X
Figure C-8 (b). 74LS245 Bidirectional Buffer
(Reprinted by permission of Texas Instruments, Copyright (Reprinted by permission of Texas Instruments, Copyright
Texas Instruments, 1988)
Texas Instruments, 1988)
APPENDIX C: IC TECHNOLOGY AND SYSTEM DESIGN ISSUES
733
Tri-state buffer
Notice that the
74LS244 is simply 8 triL~
state buffers in a single (a) In~ut
(b)
H
Tri-state
chip. As shown in Figure
control
C-9 a tri-state buffer has a
(active high)
single input, a single output, and the enable control
input. By activating the
enable, data at the input is
(d)
H~
transferred to the output. (c)
~ H
The enable can be an
active-LOW or an activeHigh-impedence
(open-circuit)
HIGH. Notice that the
enable input for the
74LS244 is an active-LOW Figure C-9. Tri-State Buffer
whereas the enable input
pin for Figure C-9 is active-HIGH.
l
I
74LS245 and 74LS244 fan-out
It must be noted that the output ofthe 74LS245 and 74LS244 can sink and
source a much larger amount of current than that of other LS gates. See Table
C-4. That is the reason we use these buffers for driver when a signal is travelling
a long distance through a cable or it has to drive many inputs.
Table C-4: Electrical Specifications for Buffers/Drivers
74LS244
74LS245
IOH (rnA)
3
3
IOL (rnA)
12
12
After this background on the fan-out, next we discuss the structure of
PIC 18 ports.
PIC18 port structure and operation
Because all the ports of the PICI8 are bidirectional they all have the following four components in their structure:
I.
2.
3.
4.
Data latch
Output driver
Input buffer
TRIS latch
Figure C-I 0 shows the structure of a port and its four components. Notice
that in Figure C-IO, the PICI8 ports have both the latch and buffer. Now the question is, in reading the port, are we reading the status of the input pin or are we read734
.r:;-RD LAT
..
1
1 DATA BUS
D
"-
WRPORT
ClK
Q~
OX
1
I-- D
"-
WRTRIS
TRIS=1
ClK
.
1 "P OFF
1
DATA LATCH
1
I
X
1
Q.J...
X
0
j
o IrN OFF
0 0
Vss
TRIS lATCH
'\
RD TRIS
..
1
-.J..-
1
1 Q
RDPORT
D 1
ONE
~
TTL or
SCHMITT
TRIGGER
..
En.~
V
Figure C-lO. Inputting (Reading) I from a Pin in the PICIS
ing the status of the latch? That is an extremely important question and its answer
depends on which instruction we are using. Therefore, when reading the ports
there are two possibilities: (I) reading the input pin, or (2) reading the latch. The
above distinction is very important and must be understood lest you damage the
PICI8 port. Each is described next.
Reading the pin when TRIS
= 1 (Input)
As we stated in Chapter 4, to make any bits of any port of the PIC 18 an
input port, we first must write a I (logic HIGH) to the TRIS bit. Look at the following sequence of events to see why:
I. As can be seen from Figure C-IO, a I written to the TRIS latch has "HIGH"
on its Q. Therefore, Q = I and Q = O. Because Q = I, it turns off the P transistor.
2. Because Q= 0 and is connected to the gate of the N transistor, the N transistor
is off.
3. When both transistors are off, they block any path to the ground or VCC for
any signal connected to the input pin, and the input signal is directed to the
buffer.
4. When reading the input port in instructions such as "MOVFW PORTB" we are
really reading the data present at the pin. In other words, it is bringing into the
CPU the status of the external pin. This instruction activates the read pin of
buffer and lets data at the pins flow into the CPU's internal bus. Figures C- \0
and C-II show HIGH and LOW signals at the input, respectively.
APPENDIX C: IC TECHNOLOGY AND SYSTEM DESIGN ISSUES
735
~RDlAT
..
0
DATA BUS
0
D
"""'-
WRPORT
ClK
Q~
aX
1
~
,J'
OFF
0
ZERO
"
~
1
D
"""'-
WRTRIS
TRIS=1
X.
1
DATA lATCH
I
Voo
ClK
Q..1...
X
a
o:~ OFF
J
0
0
V"
TRIS LATCH
RDTRIS
..
0
~
0
0'Ci'"""D 0
-.j....-.~
....-.
En ~
RDPORT
V
Figure C-I1. Inputting (Readmg) 0 from a Pin in the PICIS
Writing to pin when TRIS
=0 (Output)
The above discussion showed why we must write a "HIGH" to a port's
TRIS bits in order to make it an input port. What happens if we write a "0" to TRIS
that was configured as an input port? From Figure C-12 we see that when
TRIS = 0, if we write a 0 to the Data latch, then Q = 0 and Q = 1. As a result ofQ
= I, the N transistor is "on" and the P transistor is "off." If N is "on," it provides
the path to ground for the input pin. Therefore, any attempt to read the input pin
will always get the "LOW" ground signal. Figure C-13 shows what happens when
we write "HIGH" to output port (Data latch) when TRIS = O. Writing I to the Data
latch makes Q = O. As a result of that, the P transistor is "on" and the N transistor
is "off," which allows a I to be provided to the output pin. Therefore, any attempt
to read the input pin will always get the "HIGH" signal.
Avoid damaging the port
The following methods can be used as precautions to prevent damage to
the PICl8 ports:
I. Have a 10k ohms resistor on the Vee path to limit current flow.
2. Connect any input switch to a 74LS244 tri-state buffer before it is fed to the
PICI8 pin.
The above points are extremely important and must be emphasized
because many people damage their ports and afterwards wonder how it happened.
We must also use the right instruction when we want to read the status of an input
pin. Table C-5 shows the list of instructions in which reading the port reads the status of the input pin.
736
~RDlAT
•
a
0 DATA BUS
Q~
D
'--
WRPORT
•
0 1
ClK
1
a
DATA LATCH
a
~
1
D
Qc-2-
1
'--
WRTRIS
V DD
•
.....-..
1
-
..p OFF
ZERO
1 ,cN
]
0 1
ClK
Vss
TRIS LATCH
TRIS=O
C
;!
RDTRIS
Q
r-J
D
En
RD PORT
TTL or
SCHMITT
TRIGGER
I
V
Figure C-12. Outputtmg (Writing) 0 to a Pin m the PIC18
£RDlAT
•
1 DATA BUS
1
D
'--
~RPORT
ClK
Q~
•
0
Q 0
-
0
DATA LATCH
•a
V DD
..?
ON
ON E
-0
-0
WRTRIS
TR IS=O
D
'-ClK
0
Q~
1
Q
J
o
1
~~
OFF
Vss
TRIS LATCH
RD TRIS
Q
-..I
RDPORT
..r--,
TTL or
SCH MITT
TRIG GER
D
En ~
V
Figure C-13. Outputting (Writing) 1 to a Pin in the PIC18
APPENDIX C: IC TECHNOLOGY AND SYSTEM DESIGN ISSUES
737
Table COS: Some of the Instructions Reading the Status of Input Port
Mnemonics
MOVFW PORTx
TSTFSZ f
BTFSS f,b
BTFSC f, b
CPFSEQ f
Examples
MOVFW PORTB
TSTFSZ PORTC
BTFSS PORTD, 0
BTFSC PORTB,7
CPFSEQ PORTB
PIC18 port fan-out
Now that we are familiar with the port structure of the PICI8, we need to
examine the fan-out for the PIC 18 microconctroller. While the early chips were
based on NMOS IC technology, today's PIC 18 microcontrollers are all based on
CMOS technology. Note, however, that while the core of the PIC 18 microcontroller is CMOS, the circuitry driv- Table C-6: PIC18 Fan-out for PORTS
ing its pins is all TTL compatible.
That is, the PICl8 is a CMOS-based ~P~in§-_ _ _~F;.;;a;;;n~-o~u;;.;t;....._ _ _ _ _=
product with TTL-compatible pins . .:,;IO::..L=--_ _ _..::8,,::.5:....mA=-=---_ _ _ _ __
All the ports of the PICI8 have the .:"IO::..H:..::...._ _ _-.,.;:3:....mA:.:;;:,,;=--_ _ _ _ __
same I/O structure, and therefore the =II:::L:--_ _ _-.:..I..t::f0=._ _ _ _ _ _ __
same fan-out. Table C-6 provides the .;.:II.:,;H:......,,-:--.--_...:I..1f0::..:.--:--::---:-_ _ _ __
I/O characteristics of PIC 18F458 Note: Negative current is defined as current
sourced by the pin.
ports.
74LS244 driving an output
pin
In some cases, when an
PICI8 port is driving multiple inputs,
or driving a single input via a long
wire or cable (e.g., printer cable), we
can use the 74 LS244 as a driver.
When driving an off-board circuit,
placing the 74LS244 buffer between
your PICI8 and the circuit is essential because the PIC 18 lacks sufficient current. See Figure C-14.
PIC18
74LS244
DO Printer
PORTB
1---+D--f-D7
data
port
RDOI------~I)_-STROBE
RD11--------<
RD21--------<
BUSY
74LS244
Figure C-14. PIC18 Connection to
Printer Signals
738
SECTION C.3: SYSTEM DESIGN ISSUES
In addition to fan-out, the other issues related to system design are power
dissipation, ground bounce, Vcc bounce, crosstalk, and transmission lines. In this
section we provide an overview of these topics.
Power dissipation considerations
Power dissipation of a system is a major concern of system designers,
especially for laptop and hand-held systems in which batteries provide the power.
Power dissipation is a function of frequency and voltage as shown below:
Q=CV
since
£
CV
T
T
F=
1
T
and 1=
il
T
I=CVF
now
P
=
VI= CraF
In the above equations, the effects offrequency and Vcc voltage should be
noted. While the power dissipation goes up linearly with frequency, the impact of
the power supply voltage is much more pronounced (squared). See Example C-2.
Example C-2
Compare the power consumption of two microcontroller-based systems. One uses 5 V
and the other uses 3 V for Vcc.
Solution:
Because P = VI, by substituting I = VIR we have P = V21R. Assuming that R = I, we
have P = 52 = 25 Wand P = 32 = 9 W. This results in using 16 W less power, which
means power saving of 64%. (16/25 x 100) for systems using 3 V for power source.
Dynamic and static currents
Two major types of currents flow through an IC: dynamic and static. A
dynamic current is I = CVF. It is a function of the frequency under which the component is working. This means that as the frequency goes up, the dynamic current
and power dissipation go up. The static current, also called DC, is the current consumption of the component when it is inactive (not selected). The dynamic current dissipation is much higher than the static current consumption. To reduce
power consumption, many microcontrollers, including the PIC18, have powersaving modes. In the PIC 18, the power saving mode is called sleep mode. We
describe the sleep mode next.
APPENDIX C: IC TECHNOLOGY AND SYSTEM DESIGN ISSUES
739
Sleep mode
In sleep mode the on-chip oscillator is frozen, which cuts off frequency to
the CPU and peripheral functions, such as serial ports, interrupts, and timers.
Notice that while this mode brings power consumption down to an absolute minimum, the contents of RAM and the SFR registers are saved and remain
unchanged.
Ground bounce
One of the major issues that designers of high-frequency systems must
grapple with is ground bounce. Before we define ground bounce, we will discuss
lead inductance of IC pins. There is a certain amount of capacitance, resistance,
and inductance associated with each pin of the Ie. The size of these elements
varies depending on many factors such as length, area, and so on.
The inductance of the pins is commonly referred to as self-inductance
because there is also what is called mutual inductance, as we will show below. Of
the three components of capacitor, resistor, and inductor, the property of selfinductance is the one that causes the most problems in high-frequency system
design because it can result in ground bounce. Ground bounce occurs when a massive amount of current flows through the ground pin caused by many outputs
changing from HIGH to LOW all at the same time. See Figure C-15(a). The voltage is related to the inductance of the ground lead as follows:
As we increase the system frequency, the rate of dynamic current, dildt, is
also increased, resulting in an increase in the inductance voltage L (di/dt) of the
ground pin. Because the LOW state (ground) has a small noise margin, any extra
voltage due to the inductance can cause a false signal. To reduce the effect of
ground bounce, the following steps must be taken where possible:
1. The V cc and ground pins of the chip must be located in the middle rather than
at opposite ends of the IC chip (the 14-pin TTL logic IC uses pins 14 and 7 for
ground and V ce). This is exactly what we see in high-performance logic gates
such as Texas Instruments' advanced logic AC 11000 and ACTlIOOO families.
For example, the ACTlIOl3 is a l4-pin DIP chip in which pin numbers 4 and
II are used for the ground and V cc, instead of 7 and 14 as in the traditional
TTL family. We can also use the SOIC packages instead of DIP.
2. Another solution is to use as many pins for ground and V cc as possible to
reduce the lead length. This is exactly why all high-performance microprocessors and logic families use many pins for V cc and ground instead of the traditional single pin for V cc and single pin for GND. For example, in the case of
Intel's Pentium processor there are over 50 pins for ground, and another 50
pins for V cc.
740
00
01
02
03
~
~
~
~
Vout
Time
ICCL
Ground
Ground bounce occurs when data
switches from all 1s to all Os
Figure C-1S. (a) Ground Bounce
Transient current going from 0 to 1
(b) Transient Current
The above discussion of ground bounce is also applicable to V cc when a
large number of outputs changes from the LOW to the HIGH state; this is referred
to as Vee bounce. However, the effect of V cc bounce is not as severe as ground
bounce because the HIGH ("I") state has a wider noise margin than the LOW
("0") state.
Filtering the transient currents using decoupling capacitors
In the TTL family, the change of the output from LOW to HIGH can cause
what is called transient current. In a totem-pole output in which the output is
LOW, Q4 is on and saturated, whereas Q3 is off. By changing the output from the
LOW to the HIGH state, Q3 turns on and Q4 turns off. This means that there is a
time when both transistors are on and drawing current from V cc. The amount of
current depends on the RoN values ofthe two transistors, which in tum depend on
the internal parameters of the transistors. The net effect of this, however, is a large
amount of current in the form of a spike for the output current, as shown in Figure
C-15(b). To filter the transient current, a 0.01 IlF or 0.1 IlF ceramic disk capacitor
can be placed between the V cc and ground for each TTL IC. The lead for this
capacitor, however, should be as small as possible because a long lead results in a
large self-inductance, and that results in a spike on the V cc line [V = L (di/dt)].
This spike is called V cc bounce. The ceramic capacitor for each IC is referred to
as a decoupling capacitor. There is also a bulk decoupling capacitor, as described
next.
Bulk decoupling capacitor
If many IC chips change state at the same time, the combined currents
drawn from the board's V cc power supply can be massive and may cause a fluctuation of V cc on the board where all the ICs are mounted. To eliminate this, a relatively large decoupling tantalum capacitor is placed between the V cc and ground
lines. The size and location of this tantalum capacitor varies depending on the
number of ICs on the board and the amount of current drawn by each IC, but it is
APPENDIX C: IC TECHNOLOGY AND SYSTEM DESIGN ISSUES
741
common to have a single 22 !iF to 47 !iF capacitor for each of the 16 devices,
placed between the Vee and ground lines.
Crosstalk
Crosstalk is due to mutual inductance.
See Figure C-16. Previously, we discussed selfinductance, which is inherent in a piece of conductor. Mutual inductance is caused by two
electric lines running parallel to each other. The
mutual inductance is a function of!, the length
of two conductors running in parallel, d, the Figure C-16. Crosstalk (EMI)
distance between them, and the medium material placed between them. The effect of crosstalk can be reduced by increasing the
distance between the parallel or adjacent lines (in printed circuit boards, they will
be traces). In many cases, such as printer and disk drive cables, there is a dedicated ground for each signal. Placing ground lines (traces) between signal lines
reduces the effect of crosstalk. This method is used even in some ACT logic families where a Vee and a GND pin are next to each other. Crosstalk is also called
EM! (electromagnetic interference). This is in contrast to ES! (electrostatic interference), which is caused by capacitive coupling between two adjacent conductors.
Transmission line ringing
The square wave used in digital circuits is in
Ringing
reality made of a single fundamental pulse and
many harmonics of various amplitudes. When this
signal travels on the line, not all the harmonics
Buffer
respond in the same way to the capacitance, inductance, and resistance ofthe line. This causes what is
Series termination
called ringing, which depends on the thickness and
the length of the line driver, among other factors. To
reduce the effect of ringing, the line drivers are terminated by putting a resistor at the end of the line.
See Figure C-17. There are three major methods of
line driver termination: parallel, serial, and
Thevenin.
In serial termination, resistors of 30-50
Parallel termination
ohms are used to terminate the line. The parallel and Figure C-17. Reducing
Thevenin methods are used in cases where there is Transmissiou Line Ringing
a need to match the impedance of the line with the
load impedance. This requires a detailed analysis of the signal traces and load
impedance, which is beyond the scope of this book. In high-frequency systems,
wire traces on the printed circuit board (PCB) behave like transmission lines, causing ringing. The severity of this ringing depends on the speed and the logic family used. Table C-7 provides the length of the traces, beyond which the traces must
be looked at as transmission lines.
--{>----w.---LJ]l
742
Table C-7: Line Length Beyond Which
Traces Behave Like Transmission Lines
Logic Family
LS
S,AS
F,ACT
AS, ECL
FCT, FCTA
Line Length (in.)
25
11
8
6
5
(Reprinted by pennission ofIntegrated Device Technology,
copyright !DT 1991)
APPENDIX C: IC TECHNOLOGY AND SYSTEM DESIGN ISSUES
743
APPENDIXD
FLOWCHARTS AND
PSEUDOCODE
OVERVIEW
This appendix provides an introduction to writing flowcharts and
pseudocode.
745
Flowcharts
(Terminal)
If you have taken any previous
programming courses, you are probably
familiar with flowcharting. Flowcharts
use graphic symbols to represent different types of program operations. These
symbols are connected together into a
flowchart to show the flow of execution
of a program. Figure 0-1 shows some of
the more commonly used symbols.
Flowchart templates are available to help
you draw the symbols quickly and neatly.
Process
Pseudocode
Flowcharting has been standard
practice in industry for decades.
However, some find limitations in using
flowcharts, such as the fact that you can't
write much in the little boxes, and it is
hard to get the "big picture" of what the
program does without getting bogged
down in the details. An alternative to
using flowcharts is pseudocode, which
involves writing brief descriptions of the
flow of the code. Figures 0-2 through
0-6 show flowcharts and pseudocode for
commonly used control structures.
Subroutine
Input!
Output
Connector
o
Figure D-l. Commonly Used
Flowchart Symbols
+
Statement 1
Statement 1
Statement 2
Statement 2
•
Figure D-2. SEQUENCE Pseudocode versus Flowchart
746
Structured programming uses three basic types of program control structures: sequence, control, and iteration. Sequence is simply executing instructions
one after another. Figure D-2 shows how sequence can be represented in
pseudocode and flowcharts.
Figures D-3 and D-4 show two control programming structures: IF-THENELSE and IF-THEN in both pseudocode and flowcharts.
Note in Figures D-2 through D-6 that "statement" can indicate one statement or a group of statements.
Figures D-5 and D-6 show two iteration control structures: REPEAT
UNTIL and WHILE DO. Both structures execute a statement or group of statements repeatedly. The difference between them is that the REPEAT UNTIL structure always executes the statement(s) at least once, and checks the condition after
each iteration, whereas the WHILE DO may not execute the statement(s) at all
because the condition is checked at the beginning of each iteration.
IF (condition) THEN
Statement 1
ELSE
Statement 2
Statement 1
Statement 2
Figure D-3. IF THEN ELSE Pseudocode versus Flowchart
No
IF (condition) THEN
Statement
Statement
Figure D-4. IF THEN Pseudocode versus Flowchart
APPENDIX D: FLOWCHARTS AND PSEUDOCODE
747
+
Statement
REPEAT
Statement
UNTIL (condition)
No
Condition
?
Yes
Figure 0-5. REPEAT UNTIL Pseudocode versus Flowchart
9
WHILE (condition) DO
Statement
No
Condition
?
Yes
Statement
I
+
FIgure 0-6. WHILE DO Pseudocode versus Flowchart
Program 0-1 finds the sum of a series of bytes. Compare the flowchart versus the pseudocode for Program 0-1 (shown in Figure 0-7). In this example, more
program details are given than one usually finds. For example, this shows steps for
initializing and decrementing counters. Another programmer may not include
these steps in the flowchart or pseudocode. It is important to remember that the
purpose of flowcharts or pseudocode is to show the flow of the program and what
the program does, not the specific Assembly language instructions that accomplish
the program's objectives. Notice also that the pseudocode gives the same information in a much more compact form than does the flowchart. It is important to note
that sometimes pseudocode is written in layers, so that the outer level or layer
shows the flow of the program and subsequent levels show more details of how
the program accomplishes its assigned tasks.
748
Count = 5
Address
40H
Repeat
Add next byte
Increment address
Decrement counter
Until Count = 0
Count = 5
Address = 40H
~
Add one byte
Store Sum
Increment address
pointer
Decrement counter
No
Count
= O?
Yes
Store sum
Figure D-7. Pseudocode versus Flowchart for Program D-l
COUNTVAL
EQU S
COUNTREG
SET Ox20
SUM
SET Ox30
MOVLW COUNTVAL
MOVWF COUNTREG
LFSR
O,Ox40
WREG
CLRF
BS
ADDWF POSTINCO, W
DECF
COUNTREG,F
BNZ
BS
MOVWF SUM
;COUNT = S
iset aside location 20H for counter
iset aside location 30H for sum
;WREG = S
;load the counter
;load pointer. FSRO
;clear WREG
=
40H, RAM address
iadd RAM to WREG and increment FSRO
;decrement counter
;loop until counter
istore WREG in SUM
=
zero
Program D-l
APPENDIX D: FLOWCHARTS AND PSEUDOCODE
749
APPENDIX E.I
PIC18 PRIMER FOR
x86 PROGRAMMERS
x86
8-bit registers:
AL, AH, BL, BH,
CL, CH, DL, DH
16-bit (data pointer): BX, SI, DI
IP (16-bit)
Program Counter:
Input:
MOV DX,port addr
IN
AL,DX
PIC18
WREG and up to
256 RAM locations in Access Bank
TBLPTR
PC (21-bit)
MOVFW PORTx ; (x
=
A,B, .. G)
Output:
MOV
OUT
DX,port addr
DX,AL
MOVWF PORTx ; (x = A,B, .. G)
Loop:
Stack pointer:
DEC CL
JNZ TARGET
DECF MyReg,F
BNZ TARGET
SP (l6-bit)
SP (21-bit)
As we PUSH data onto the
stack, it decrements the SP.
Push increments the SP.
(Used exclusively for saving PC)
As we POP data from the stack,
Pop decrements the SP.
it increments the SP.
(Used exclusively for retrieving PC)
Data movement:
From the code segment:
MOV AL,CS: [51]
From the data segment:
MOV AL, lSI]
TBLRD
MOVFW FSRx
From RAM:
To RAM:
750
MOV AL, [51]
(Use SI, DI, or BX only.)
MOVFW FSRx
MOV
MOVWF FSRx
lSI] ,AL
APPENDIX E.2
PIC18 PRIMER FOR
8051 PROGRAMMERS
8-bit registers:
8051
A, B, RO, RI, ..... R7
16-bit (data pointer):
Program Counter:
Input:
MOV A,Pn
PIC18
WREG and up to 256 RAM
locations in Access Bank
DPTR
PC (l6-bit)
TBLPTR
PC (2l-bit)
(n=O - 3)
MOVFW PORTx ; (x = A,B, .. G)
(n=O - 3)
MOVWF PORTx ; (x = A,B, .. G)
Output:
MOV Pn,A
Loop:
DJNZ R3, TARGET
(Using RO-R7)
Stack pointer:
DECF MyReg,F
BNZ TARGET
SP (8-bit)
SP (2 I-bit)
As we PUSH data onto the
stack, it increments the SP.
Push increments the SP.
(U sed exclusively for saving PC)
As we POP data from the
stack, it decrements the SP.
Data movement:
From the code segment:
MOVC A,@A+PC
From the data segment:
MOVX A,@DPTR
Pop decrements the SP.
(Used exclusively for retrieving PC)
From RAM:
MOV A, @RO
(Use RO or RI only)
To RAM:
MOV @RO,A
(Use RO or RI only)
TBLRD
MOVFW FSRx
MOVFW FSRx
MOVWF FSRx
APPENDIX E: 8051 PRIMER FOR X86 PROGRAMMERS
751
APPENDIXF
ASCII CODES
Ctt"l
A@
AA
AB
AC
AD
AE
AF
AG
AH
AI
AJ
AK
AL
All
AN
AO
Ap
AQ
AR
AS
AT
AU
AU
AW
AM
~
AZ
A[
A,
A]
AA
A
752
Dec
Hex
II
1
2
3
4
5
6
7
8
9
111
11
12
13
14
15
16
17
18
19
211
21
22
23
24
25
26
27
28
29
311
31
1111
111
112
113
114
115
116
117
118
119
IIA
liB
IIC
liD
liE
IIF
111
11
12
13
Ch
g
I!I
•
•
~
~
•
C
c
(;]
/I
V
~
/I
!CO
10~
t
!!
14
'II
15
16
17
18
19
lA
18
lC
lD
lE
IF
11
-1
t
~
+
<L
~
;.
•
Code
NUL
SOH
STM
ETM
EOT
ENQ
ACK
BEL
BS
HT
LF
UT
FF
CR
SO
SI
DLE
DCl
DC2
DC3
DC4
NAK
SYN
ETB
CAN
Ell
SUB
ESC
FS
GS
RS
US
Dec
Hex
32
33
34
35
36
37
38
39
411
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
211
21
22
23
24
25
26
27
28
29
2A
28
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
38
3C
3D
3E
3F
Ch
Dec
Hex
Ch
.
64
65
66
67
68
69
70
71
<
?2
)
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
911
91
92
93
94
95
40
41
42
43
44
45
46
47
48
49
4A
48
4G
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
58
5C
5D
5E
5F
.
!
II
$
%
II<
*
+
,
-
.
/
0
1
2
3
4
5
6
7
8
9
:
;
<
~
>
?
Dec
Hex
I!
96
A
8
C
D
E
F
G
H
I
J
K
L
97
98
99
11l1l
1111
1112
103
1114
105
1116
1117
108
1119
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
60
61
62
63
64
65
66
67
68
69
6A
68
6C
6D
6E
6F
71l
71
II
N
0
P
Q
R
S
T
U
U
W
M
Y
Z
,
[
]
A
?2
73
74
75
76
Ch
·
a
b
c
d
e
f
g
h
i
j
k
1
~
n
0
p
q
.
s
t
u
u
??
w
78
79
7A
78
7G
7D
7E
7F
x
y
z
{
••
>
"
Dec
Hex
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
80
81
82
83
84
85
86
87
88
89
8A
8D
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9D
9C
9D
9E
9F
Ch
~
0
e
a
a
a
,e
~
e
e
i
i
i
A
A
E
'"
IE
6
0
6
a
il
Y
0
(j
¢
£
¥
PIs
f
APPENDIX F: ASCII CODES
Dec
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
191i1
191
Hex
Ch
A0
Ai
A2
A3
A4
A5
A6
A7
A8
A9
AA
AD
AC
AD
AE
AF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DD
DC
DD
DE
DF
a
i
6
U
fi
.
N
"i.
r
,
~
!Ii
i
«
»
§!
*
III
III
I
1
~
II
n
~
:I
II
i1
!J
u
~
1
Dec
192
193
194
195
196
197
198
199
21i11i1
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
Hex
Ch
Dec
Hex
Ch
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CD
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
L
224
225
226
227
228
229
2311
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
a
.L
T
~
-
+
~
II
I!
Ii
!!
"I~
~
n
"±
u
or
n
u
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f
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2
I
753
APPENDIXG
ASSEMBLERS, DEVELOPMENT
RESOURCES, AND SUPPLIERS
This appendix provides various Microchip Corp.
sources for PIC 18 assemblers and trainers. www.microchip.com
In addition, it lists some suppliers for chips
and other hardware needs. While these are Custom Computer Services Inc
all established products from well-known www.ccsinfo.com
companies, neither the authors nor the publisher assumes responsibility for any problem that may arise with any of them. You
are neither encouraged nor discouraged
from purchasing any of the products mentioned; you must make your own judgment
in evaluating the products. This list is sim- Figure G-l. Suppliers of
ply provided as a service to the reader. It Assemblers and Compilers
also must be noted that the list of products
Microchip Corp.
is by no means complete or exhaustive.
www.microchip.com
PIC18 assemblers
The PIC 18 assembler is provided by
Microchip and other companies. Some of
the companies provide shareware versions
of their products, which you can download
from their Web sites. However, the size of
code for these shareware versions is limited
to a few KB. Figure G-I lists some suppliers of assemblers.
www.MicroDigitaIEd.com
Custom Computer Services Inc.
www.ccsinfo.com
RSR Electronics
www.elexp.com
PIC18 trainers
There are many companies that produce and market PICI8 trainers. Figure
G-2 provides a list of some of them.
Figure G-2. Trainer Suppliers
754
Parts Suppliers
Figure G-3 provides a list of suppliers for many electronics parts.
RSR Electronics
Electronix Express
365 Blair Road
Avenel, NJ 0700 I
Fax: (732) 381-1572
Mail Order: 1-800-972-2225
In New Jersey: (732) 381-8020
www.elexp.com
Altex Electronics
11342 IH-35 North
San Antonio, TX 78233
Fax: (210) 637-3264
Mail Order: 1-800-531-5369
www.altex.com
Digi-Key
1-800-344-4539 (1-800-DIGI-KEY)
Fax: (218) 681-3380
www.digikey.com
Radio Shack
www.radioshack.com
JDR Microdevices
1850 South 10th St.
San Jose, CA 95112-4108
Sales 1-800-538-5000
(408) 494-1400
Fax: 1-800-538-5005
Fax: (408) 494-1420
www.jdr.com
Mouser Electronics
958 N. Main St.
Mansfield, TX 76063
1-800-346-6873
www.mouser.com
Jameco Electronic
1355 Shoreway Road
Belmont, CA 94002-4100
1-800-831-4242
(415) 592-8097
Fax: 1-800-237-6948
Fax: (415) 592-2503
www.Jameco.com
B. G Micro
P. O. Box 280298
Dallas, TX 75228
1-800-276-2206 (orders only)
(972) 271-5546
Fax: (972) 271-2462
This is an excellent source ofLCDs, ICs,
keypads, etc.
www.bgmicro.com
Tanner Electronics
1100 Valwood Parkway, Suite # I 00
Carrollton, TX 75006
(972) 242-8702
www.tannerelectronics.com
Figure G-3. Electronics Suppliers
APPENDIX G: ASSEMBLERS, DEVELOPMENT RESOURCES, AND SUPPLIERS
755
APPENDIXH
DATA SHEETS
756
PIC 18F2480/2580/4480/4580
25.0
INSTRUCTION SET SUMMARY
PIC18F248012580/4480/4580 devices incorporate the
standard set of 75 PIC18 core instructions, as well as
an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software
stack. The extended set is discussed later in this
section.
25.1
Standard Instruction Set
The standard PIC18 instruction set adds many
enhancements to the previous PICmicro® instruction
sets, while maintaining an easy migration from these
PICmicro instruction sets. Most instructions are a
single program memory word (16 bits), but there are
fOUf instructions that require t.No program memory
locations.
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
Byte-oriented operations
Bit-oriented operations
Literal operations
Control operations
The PIC18 instruction set summary in Table 25-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 25-1 shows the opcode field
descriptions.
Most byte-oriented instructions have three operands:
1.
2.
The file register (specified by 'f)
The destination of the result (specified by 'd')
3.
The accessed memory (specified by 'a')
The file register deSignator 'f specifies which file
register is to be used by the instruction. The destination
designator 'd' specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in
the W'REG register. If'd' is one, the result is placed in
the file register specified in the instruction.
All bit-oriented instructions have three operands:
1.
The file register (specified by 'f)
2.
3.
The bit in the file register (specified by 'b')
The accessed memory (specified by 'a')
The literal instructions may use some of the following
operands:
A literal value to be loaded into a file register
(specified by'k')
The desired FSR register to load the literal value
into (specified by 'f)
No operand required
(specified by '-'I
The control instructions may use some of the following
operands:
A program memory address (specified by 'n')
The mode of the CALL or RETURN instructions
(specified by's')
The mode of the table read and table write
instructions (specified by 'm')
No operand required
(specified by'-')
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the 4 MSbs are 'l'S. If
this second word is executed as an instruction (by
itself), it will execute as a NOP.
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruction. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP.
The double-word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 Jls. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 ).ls.
Two-word branch instructions (if true) would take 3 ).ls.
Figure 25-1 shows the general formats that the instructions can have. AU examples use the convention 'nnh'
to represent a hexadecimal number.
The Instruction Set Summary, shown in Table 25-2,
lists the standard instructions recognized by the
Microchip MPASMHA Assembler.
Section 25.1.1 "standard Instruction Set" provides
a description of each instruction.
The bit field deSignator 'b' selects the number of the bit
affected by the operation, while the file register designator 'f represents the number of the file in which the
bit is located.
@2004Microchip Technology Inc.
APPENDIX H: DATA SHEETS
Preliminary
DS39637 A-page 361
757
PIC18F2480/2580/4480/4580
TABLE 25-1'
OPCODE FIELD DESCRIPTIONS
Field
Description
RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a
a = 1: RAM bank Is specified by BSR register
Bit address within an 8-bit file register (0 to 7).
Bank Select Register. Used to select the current RAM bank.
bbb
BSR
e,
DC,
z,
00, N
d
deBt
f
f
f
GI.
k
label
mm
-.--.-
n
PC
PCL
PCH
PCLATH
PCLATU
PI5
PRODH
PRODL
s
TBLPTR
TABLAT
TO
TOS
u
HDT
WREG
x
z,
z,
l~
[text]
(text)
ALU status bits: Carry, Digit Carry, Zero, Overflow, Nej:Jative.
Destination select bit
d =0: store result in WREG
d = 1: store result in file register f
Destination: either the 'lNREG register or the specified register file location.
B-bit Register file address (OOh to FFh). or 2-bil FSR designator (Oh to 3h).
12-bit Register file address (OOOh to FFFh), This is the source address.
12-bit Register file address (OOOh to FFFh). This Is the destination address.
Global Interrupt Enable bit.
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value)
label name
The mode of the TBlPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
No change to register (such as TBlPTR with table reads and writes)
Post-Increment register (such as TBLPTR with table reads and writes)
Post-Decrement register (such as TBlPTR with table reads and writes)
Pre-Increment register (such as TBlPTR with table reads and writes)
The relative address (2's complement number) for relative branch instructions or the direct address for
GalVBranch and Return instructions
Program Counter.
Program Counter low Byte.
Program Counter High Byte.
Program Counter High Byte latch.
Pr().9_ram Counter Upper Byte latch.
Power-down bit.
Product of Multiply High Bvte.
Product of Multiply low Byte.
Fast Gall/Return mode select bit
s 0; do not update into/from shadow registers
s =~: certain registers loaded into/from shadow registers (Fast mode)
21-bit Table Pointer (points to a Program Memory location).
S-bit Table latch.
Time-out bit.
TOP-Of-Stack.
Unused or unchanged.
Watchdog Timer.
\l\k)rking register (accumulator).
Don't care ('0' or '~'). The assembler will generate code with x o. It is the recommended form of use for
compatibility with all Microchip software tools.
7-bit offset value for Indirect addressing of register files (source).
=
=
7-bit offset value for indirect addressing of register files (destination).
Optional argument.
Indicates an indexed address.
The contents of text.
[expr] <n>
::;~~ifies
bit n of the register indicated by the pointer expr.
-+
Asslgned
to.
< >
E
Register bit field.
In the set of.
italics
User defined term (font is Courier).
0839637 A-page 362
758
Preliminary
© 2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580
FIGURE 25-1:
GENERAL FORMAT FOR INSTRUCTIONS
Example Instruction
Byte..oriented file register operations
15
10
9
o
8 7
ADDWF MYREG,
f(FILE #)
w,
B
d =0 for result destination to be WREG register
d
a
a
f
=1 for result destination to be file register (f)
0 to force Access Bank
=1 for BSR to select bank
=8-bit file register address
Byte to Byte move operations (2-word)
15
15
MOVFF MYREGl, MYREG2
f (Source FILE #)
I
0
12 11
1111
I
0
12 11
IOPCODE
f (Destination FILE #)
I
=12·bit file register address
f
Bit..oriented file register operations
151211987
a I
I OPCODE I b (BIT#)I
b
a
a
f
o
BSF MYREG, bit, B
f (FILE #)
=3-bit position of bit in file register (f)
=0 to force Access Bank
=1 for BSR to select bank
=8-bit file register address
literal operations
15
8
I
o
7
OPCODE
MOVLW
k (literal)
I
7Fh
k = 8-bit immediate value
Control operations
CALL. GOTO and Branch operations
15
o
8 7
n<7:0>
OPCODE
15
(I~eral)
o
12 11
n<19:8> (literal)
11~~
n
GOTO Label
=2O-bit immediate value
870
15
I sI
OPCODE
15
12 11
llll
S
15
IOPCODE
15
OPCODE
CALL MYFUNC
n<7:0> (literal)
0
n<19:8> (literal)
I
=Fast bit
11 10
0
BRAMYFUNC
n<10:0> (literal)
8 7
I n<7:0> (literal)
© 2004 Microchip Technology Inc.
APPENDIX H: DATA SHEETS
0
Preliminary
BC MYFUNC
OS39637 A-page 363
759
PIC 18F2480/2580/4480/4580
TABLE 25-2"
PIC18FXXXX INSTRUCTION SET
Mnemonic,
Operands
16-Bit Instruction Word
Description
Cycles
MSb
LSb
status
Affected
Notes
BYTE.QRIENTED OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF
I,
I,
I,
I,
I,
I,
I,
I,
I,
f,
f,
I,
I,
I,
I,
I,
d, a
d, a
d, a
a
d, a
a
a
a
d, a
d, a
d, a
d, a
d, a
d, a
d, a
d, a
f51 fd
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
I,
I,
I,
f,
f,
a
a
a
d,
d,
t, d,
f, d,
I, a
I, d,
SUBWF
SUBWFB
I, d, a
I, d, a
SWAPF
TSTFSZ
XORWF
f, d, a
I, a
I, d, a
a
a
a
a
a
Add WREG and I
Add WREG and Carry bit to I
AND WREG with I
Clear f
Complement f
Compare I with WREG, skip =
Compare f with WREG, skip>
Compare I with WREG, skip <
Decrement f
Decrement f, Skip jf 0
Decrement f, Skip if Not 0
Increment f
Increment f, Skip if 0
Increment f, Skip if Not 0
Inclusive OR WREG with f
Movef
Move f5 (source) to
1st word
fd (destination)2nd word
Move WREG to I
Multiply WREG with I
Negate f
Rotate Left I through Canry
Rotate Left I (No Canry)
Rotate Right Ithrough Carry
Rotate Right I (No Canry)
Set I
Subtract ffrom WREG with
borrow
Subtract WREG from f
Subtract WREG Irom I with
borrow
Swap nibbles in f
Test f, skip if 0
Exclusive OR WREG with t
ffff
ffff
ffff C, DC, Z, OV, N 1,2
ffff C, DC, Z, OV, N 1,2
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
1,2
2
1,2
4
None
None
4
1,2
None
ffff C, DC, Z, OV, N 1,2,3,4
f f f f None
1,2,3,4
f f f f None
1,2
f f f f C, DC, Z, OV, N 1,2,3,4
f t f f None
4
f f f f None
1, 2
f f f f Z, N
1,2
1
f f f f Z, N
ffff None
ffff
ffff None
ffff None
1,2
ffff C, DC, Z, OV, N
ffff C,Z,N
1,2
ffff Z, N
ffff C, Z, N
ffff Z, N
ffff None
1,2
ffff C, DC, Z, OV, N
llda
10da
ffff
ffff
ffff C, DC, Z, OV, N 1,2
ffff C, DC, Z, OV, N
1
0011 10da
1 (2 or3) 0110 Olla
1
0001 10da
ffff
ffff
ffff
ffff None
ffff None
ffff Z, N
1
1
1
1
1
1 (2 or 3)
1 (2 or3)
1 (2 or3)
1
1 (20r3)
1 (20r3)
1
1 (20r3)
1 (20r3)
1
1
2
0010
0010
0001
Dlda
OOda
Olcta
0110
lOla
0001
0110
11da
0011
11da
lOda
1
1
1
1
1
1
1
1
1
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101
ffff
lIla
OOla
110a
01da
01da
Dada
OOda
100a
Olda
1
1
0101
0101
GOla
0110 OlGa
0110 GOGa
0000 aIda
0010 Ilda
0100 llda
0010 lOda
GOda
GOda
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
tfff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffft
ffff
ffff
ffff
Z, N
Z
Z, N
4
1, 2
Note 1:
When a Port register IS modified as a function of Itself (e.g., MOVF PORTE, I, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is
driven low by an external device, the data will be written back with a '0'.
2:
If this instruction is executed on the TMRO register (and where applicable, 'd' ;;;: 1), the prescaler will be cleared
if aSSigned.
3:
If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4:
Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word ofthe instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
5:
If the table write starts the write cycle to internal memory, the write will continue until terminated.
DS39637 A-page 364
760
Preliminary
© 2004 Microchip Technology Inc.
PIC 18F2480/2580/4480/4580
TABLE 25-2'
PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-8it Instruction Word
Mnemonic,
Operands
Description
Cycles
MSb
LSb
Status
Notes
Affected
BIT-ORIENTED OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a
f,
f,
f,
f,
a
b, a
b, a
d, a
b,
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
1
1
1 (2 or 3)
1 (2 or3)
1
1001 bbba
1000 bbba
0111
bbba
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
2
1110
0010
1110
1110
0110
0011
1110
0111
1110
1110
0101
1011 bbba
1010 bbba
None
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
mum None
None
None
None
None
1,2
1,2
3,4
3,4
1,2
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
n
n
n
n
n
n
n
n
n
n, S
CLRWDT
DAW
GOTO
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
RETLW
RETURN
SLEEP
Note 1:
n
-
-
n
S
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine1 st word
2nd word
Clear Watchdog TImer
Decimal Adjust WREG
Go to address 1st word
2nd word
No Operation
No Operation
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device Reset
Return from interrupt enable
1110
0100
1101
Orum
1110
0000
lIDs
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1110
1111
1
1
2
1
1
1
1
2
1
2
0001
0000
0000
1110
1111
0000
1111
0000
0000
1101 1rum
0000 0000
0000 0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
None
None
None
None
None
None
kkkk
None
None
kkkk None
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
nrum
1111
0001
1111
OOOs
TO.PD
C
None
None
None
None
None
None
All
GIEIGIEH,
PEIE/GIEL
None
None
TO,PD
4
0000 1100 kkkk kkkk
0000 0000 0001 001s
0000 0000 0000 0011
When a Port register IS modified as a function of Itself (e,g., MOVF PORTE, 1 0), the value used Will be that
value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is
driven low by an external device, the data will bewritlen back with a '0'.
k
S
Return with literal in WREG
Return from Subroutine
Go into Standby mode
2
2
1
J
= 1), the prescaler will be cleared
2:
If this instruction is executed on the TMRO register (and where applicable, 'd'
if assigned.
3:
If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOE
4:
Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
5:
Ifthe table write starts the write cycle to internal memory, the write will continue until terminated.
© 2004 Microchip Technology Inc.
APPENDIX H: DATA SHEETS
Preliminary
D839637A-page 365
761
PIC18F2480/2580/4480/4580
TABLE 25·2'
PIC18FXXXX INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
16-Bit Instruction Word
Description
Cycles
LITERAL OPERATIONS
ADDLW
k
Add literal and WREG
1
ANDLW
k
AND literal with VVREG
1
IORLW
k
Inclusive OR literal with WREG 1
LFSR
t, k
Move lITeral (12-bit) 2nd word
2
to FSR(t)
1st word
Move literal to BSR<3:0>
MOVLB
k
1
MOVLW
k
Move lITeral to WREG
1
MULLW
k
Multiply literal with WREG
1
RETLW
k
Return with literal in WREG
2
SUBLW
k
Subtract VVREG from literal
1
XORLW
k
Exclusive OR literal with VVREG 1
DATA MEMORY .. PROGRAM MEMORY OPERATIONS
TBLRD·
Table Read
2
TBLRO"'+
Table Read with post-increment
TBLRD·Table Read with post-decrement
TBLRO+*
TBLWrTBLWT*+
TBLWT·TBLWT+·
Note 1:
kkkk
kkkk
kkkk
kkkk
C. DC. Z, OV, N
Z, N
Z, N
OOff
kkkk
None
0000 kkkk
0000 0001 0000
0000 1110 kkkk
0000 1101 kkkk
kkkk
kkkk
kkkk
None
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
1111
0000 1100
0000 1000
0000 1010
kkkk
Notes
None
None
None
C, DC, Z, OV, N
Z, N
0000 0000 0000
1000 None
0000 0000 0000
1001 None
0000 0000 0000
1010 None
0000 0000 0000
1011 None
Table Read with pre-increment
Table Write
2
0000 0000 0000
1100 None
5
Table Write with post-increment
0000 0000 0000
1101 None
5
Table Write with post-decrement
0000 0000 0000
1110 None
5
Table Write with pre-increment
0000 0000 0000
1111 None
5
When a Port register IS modified as a function of itself (e,g., MOVF PORTE, 1, 0), the value used Will be that
value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is
driven low by an external device, the data will be written back with a '0'.
2:
If this instruction is executed on the TMRO register (and where applicable, 'd' = 1), the prescaler will be cleared
if assigned.
3:
If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4:
Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits, This ensures that all
program memory locations have a valid instruction
5:
If the table write starts the write cycle to internal memory, the write will continue until terminated.
OS39637 A-page 366
762
Affected
0000 1111 kkkk
0000 1011 kkkk
aooo 1001
1110 1110
Status
LSb
MSb
Preliminary
© 2004 Microchip Technology Inc.
PIC 18F2480/2580/4480/4580
25.1.1
STANDARD INSTRUCTION SET
ADDLW
ADD Literal to W
ADDWF
Syntax:
ADDLW
Syntax:
ADDWF
Operands:
os: k::;; 255
Operands:
0=::;f:5255
Operation:
f'N)+k~W
k
de 10,11
status Affected:
N, OV, C, DC, Z
I
Operation:
0N> + (f) ~ dest
Status Affected:
N,
av, C, DC, Z
The contents ofW are added to the
8-bit literal 'k' and the result is placed
Encoding:
I
0010
InW.
Description:
0000
I 1111
kkkk
kkkk
\M:lrds:
Cycles:
Q
Cycle Activity:
01
I
Decode
02
Read
Process
Hteral 'k'
Data
ADDLW
03
I WrIte to W
ISh
25h
ffff
ffff
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f:.:; 95 (5Fh). See
Section 26.2.3 ''Syte-Oriented and
Btt-Onented Instructions in Indexed
Literal Offset Mode" for details.
After Instruction
=
I Oida
Add Wto register 'f. If 'd' is '0', the
result is stored in W. If'd' Is '1', the
result is stored back in register 'f
(default).
If 'a' is '0', the Access Bank is selected.
If 'a' is '1', the BSR is used to select the
GPR bank (default).
04
Before Instruction
W
10h
W
f {,d {,a}}
a E [0,1]
Encoding:
Description:
ADDWlof
Words:
Cycles:
Q Cycle Activity:
02
01
ADDWF
04
03
REG,
0,
0
Before Instruction
W
REG
After Instruction
W
REG
Note:
17h
OC2h
OD9h
OC2h
j\J] PIG1a in~s ",ay take. an optiQnal:I.~.I·''lIumer\t.pl'$Cedil1!lthe' instrucli,mmnelT¥lliieJof lISoin
symllo/ie addresSin ' . ~ a Jall<lll" g~ .I!)e il]siruCtiOR format th.n:~s: {labii~ ihSIr'1Ji:Ii06 ~g~ITeIlI(.s):
© 2004 Microchip Technology Inc.
APPENDIX H: DATA SHEETS
Preliminary
D839637 A-page 367
763
PIC18F2480/2580/4480/4580
ADD Wand Carry bit to f
ADDWFC
Syntax:
ADDWFC
Operands:
0=:;1::;;255
dE [0,1J
a E [0,1J
f I,d {,a))
Operation:
\IN) + (f) + (C)
Status Affected:
N,QV, C, DC, Z
~
dest
Encoding:
I
Description:
Add W, the Carry flag and data memory
0010
I
ANDLW
OOda
I
fffE
fEfE
location 'f. If'd' is '0', the result is
placed in W. If'd' is '1', the result is
placed in data memory
I
AND Literal with W
Syntax:
ANDLW
Operands:
Osk:;255
Operation:
0N) .AND. k
status Affected:
N,Z
Encoding:
I
Description:
0000
k
-4
W
I 1011
kkkk
kkkk
Words:
Cycles:
Q Cycle Activity:
location 'f.
If 'a' is '0', the Access Bank is selected.
If 'a' is '1', the BSR is used to select the
GPR bank (default).
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f:5 95 (SFh). See
Section 25.2.3 "Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode" for details.
02
01
I
Decode
Read literal
.
'k'
I
ANOLW
Before Instruction
W
After Instruction
W
03
Process
Data
04
I Write to W
05Fh
A3h
03h
IJIvtlrds:
Cycles:
Q Cycle Activity:
01
02
AODWFC
04
03
REG,
0,
1
Before Instruction
Carry bit
REG
=
W
1
02h
4Dh
After Instruction
Carry bit
REG
0
02h
W
SOh
DS39637 A-page 368
764
Preliminary
I
The contents of Ware ANCed with the
a-bit literal 'k'. The result is placed in W.
© 2004 Microchip Technology Inc.
PIC 18F2480/2580/4480/4580
ANDWwlth f
BC
Syntax:
ANDWF
Syntax:
BC
Operands:
0:5fs255
dE {0,11
a E [0,11
Operands:
-1285n5127
Operation:
if Carry bit is '1'
(PC) + 2+ 2n -+ PC
status Affected:
None
ANDWF
f {,d {,a}}
Operation:
ry./) .AND. (Q --> dest
Status Affected:
N,Z
Encoding:
Description:
I
0001
I
01da
I
Branch If Carry
!
Encoding:
'ff'
ffff
If 'a' is '0' and the extended instruction
Section 26.2.3 ''Syte-Oriented and
Q3
Q2
Ql
Q4
ANDWF
REG,
0,
Cycles:
1(2)
Cycle Activity:
If Jump:
Q
Q1
Q2
Q3
Q4
Decode
Read literal
'n'
No
operation
Process
Data
\/Vrite to PC
No
operation
No
operation
No
operation
If No Jump.
Q2
Q3
Q4
Read literal
Process
Data
No
operation
Ql
Decode
I.
0
HERE
PC
Be
5
address (HERE)
After Instruction
If Carry
02h
C2h
PC
If Carry
PC
APPENDIX H: DATA SHEETS
'n'
Before Instruction
17h
C2h
© 2004 Microchip Technology Inc.
nnnn
1
I
Before Instruction
W
REG
After Instruction
W
REG
I nnnn
Words:
Vlbrds:
Q Cycle Activity:
0010
If the Carry bit is '1', then the program
wilt branch.
The 2'8 complement number '2n' is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
Bit-Oriented Instructions In Indexed
Literal Offset Mode" for details.
Cycles:
I
1110
Description:
The contents of Ware AND'ed with
register T. If 'd' is '0', the result is stored
in W. If'd' is '1', the result is stored back
in register 'f (default).
If 'a' is '0', the Access Bank is selected.
It 'a' is '1', the BSR is used to select the
GPR bank (default).
set is enabled, this Instruction operates
In Indexed Literal Offset Addressing
mode whenever f $; 95 (5Fh). See
n
Preliminary
l'
address (HERE + 12)
0;
address (HERE + 2)
0539637 A-page 369
765
PIC18F2480/2580/4480/4580
BH Clear!
BCF
Syntax:
BCF
Operands:
05f:5255
OSh::;;?
a E [0,11
f, b {,a)
o ~ f<b>
status Affected:
None
Encoding:
I
Description:
Bit 'b' in register 'f is cleared.
BN
·128:5n5127
Operation:
if Negative bit is '1'
I bbba
ffff
Description:
Words:
1
Cycles:
1(2)
If 'a' is '0' and the extended instruction
in Indexed Literal Offset addressing
Seetion 26.2.3 "Byte-Oriented and
Btt-Oriented Instructions in Indexed
Uteral Offset Mode" for details.
\l\brds:
Cycles:
Cycle Activity:
If Jump:
01
Q
Oecode
Q Cycle Activity:
03
02
03
04
Read literal
'n'
Process
Data
Write to PC
No
No
No
No
operation
operation
operation
02
03
Read literal
Process
Data
04
No
operation
If No Jump:
01
I
BeF
Before Instruction
FLAG_REG =C7h
After Instruction
FLAG_REG =47h
Decode
I.
'n'
HERE
PC
JUmp
address (HERE)
l'
address
If Negative
Preliminary
(Jump)
Q'
PC
766
BN
operation
Before Instruction
After Instruction
If Ne~agve
0539637 A-page 370
nnnn
If the Negative bit is '1', then the
program will branch.
The 2'6 complement number '2n' is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n, This instruction is then a
two-cycle Instruction.
set is enabled, this instruction operates
mode whenever f::; 95 (SFh). See
PC
I 1110 I 0110 I nnnn
Encoding:
ffff
-4
None
status Affected:
If 'a' is '0', the Access Bank is selected.
If 'a' is '1', the BSR is used to select the
GPR bank (default).
01
n
Syntax:
Operands:
(PC) + 2 + 2n
Operation:
1001
Branch if Negative
BN
address (HERE + 2)
@
2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580
BNC
Branch if Not Carry
Syntax:
BNC
Operands:
~128sn$127
jf Carry bit is '0'
Operation:
(PC) + 2 + 2n
~
Status Affected:
None
I
Description:
If the Carry bit is '0', then the program
!
0011
I
nnnn
nnnn
BNN
Operands:
~128::;;ns127
Operation:
jf Negative bit is '0'
(PC) + 2 + 2n -? PC
Status Affected:
None
Encoding:
I
instruction
1
Words:
1
Cycles:
1(2)
Cycles:
1(2)
Q Cycle Activity:
Q Cycle Activity:
If Jump:
If Jump:
01
02
03
04
Read literal
'n'
Process
Data
Vlh"ite to PC
No
operation
No
No
operation
operation
No
operation
02
03
Q4
If No Jump:
Q1
HERE
~
BNe
Jump
Q1
Decode
PC
If Carry
PC
Q3
04
Process
Data
Write to PC
No
No
No
operation
operation
operation
02
03
04
No
HERE
~
BNN
Jump
Before Instruction
After Instruction
If Negative
0;
address \ Jump)
1;
address (HERE + 2)
@2004MicrochipTechnology Inc.
APPENDIX H: DATA SHEETS
address (HERE)
PC
address (HERE)
PC
Q2
Read literal
'n'
operation
If No Jump.
Q1
Before Instruction
After Instruction
If Carry
nnnn
The 2's complement number '2n' is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two--cycle instruction.
\!\brds:
Decode
I 0111 I nnnn
1110
If the Negative bit is '0', then the
program will branch.
Description:
will branch.
The 2's complement number '2n' is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two~cycle
n
Syntax:
PC
Encoding:
1110
Branch if Not Negative
BNN
n
PC
IfNe~agve
Preliminary
0;
address (Jump)
1;
address (HERE + 2)
DS39637 A-page 371
767
PIC18F2480/2580/4480/4580
BNOV
Branch if Not OVerflow
BNZ
Syntax:
BNOV
Syntax:
BNZ
Operands:
-128$n:5127
Operands:
-128:5ns127
Operation:
if Overflow bit is '0'
(PC) ... 2'" 2n ~ PC
Operation:
if Zero bit is '0'
(PC) ... 2+ 2n 4 PC
status Affected:
None
Encoding:
I
n
j
nnnn
nnnn
I
Encoding:
Description:
The 2'5 complement number '2n' is
1(2)
I nnnn
nnnn
Words:
1
Cycles:
1(2)
Q Cycle Activity:
Q Cycle Activity:
If Jump:
If Jump:
01
02
03
04
01
02
03
04
Decode
Read literal
Write to PC
Decode
Read literal
Process
Data
Write to PC
'n'
Process
Data
No
No
No
No
No
No
No
operation
operation
operation
No
operation
operation
operation
operation
operation
02
03
04
02
03
Q4
'n'
If No Jump:
If No Jump:
01
Wrru>Jo;
BNOV Jump
HERE
01
Wrru>Jo;
Before Instruction
PC
PC
If Overflow
PC
0539637 A~page 372
BNZ
HERE
Jump
Before Instruction
PC
address (HERE)
After Instruction
If Overflow
768
0001
The 2's complement number '2n' is
added to the pc. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
PC ... 2 ... 2n. This instruction is then a
two-cycle instruction.
Cycles:
I
1110
If the Zero bit is '0', then the program
will branch.
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
\M:lfds:
n
None
Status Affected:
I 0101
1110
if the Overflow bit is '0', then the
program will branch.
Description:
Branch if Not Zero
address (HERE)
After Instruction
If Zero
0;
PC
address (Jump)
1;
If Zero
PC
address (HERE + 2)
Preliminary
0;
address {Jump)
1;
address (HERE + 2)
© 2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580
BRA
Unconditional Branch
Syntax:
BRA
Operands:
·1024$n:::;1023
Operation:
(PC) + 2 + 2n
Status Affected:
None
I
Encoding:
Description:
BSF
n
I
1101
4
BitSetf
Syntax:
BSF
Operands:
Osf$255
Osbs7
a E [0,11
PC
Onnn
I
nnnn
I
nnnn
Add the 2's complement number '2n' to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
I
1 --+ f<b>
Operation:
status Affected:
I
Description:
Bit 'b' in register 'f is set.
I
bbba
I
ffff
I
I
ffff
GPR bank (default).
If 'a' is '0' and the extended Instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f s 95 (SFh). See
Section 26.2.3 "Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode" for details.
2
Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
V\ttite to PC
'n'
Process
Da1a
No
No
operation
No
No
VVords:
operation
operation
Cycles:
operation
1000
If'a' is '0', the Access Bank is selected.
If 'a' is '1', the BSR is used to select the
two-cycle instruction.
Q
None
Encoding:
\l\brds:
Cycles:
f, b La)
Q Cycle Activity:
~
BRA
HERE
Q2
Q1
Jump
Q3
Q4
Before Instruction
PC
address (HERE)
After Instruction
PC
address (Jump)
aSF
Before Instruction
FLAG_REG
OAh
After Instruction
FLAG_REG
© 2004 Microchip Technology Inc.
APPENDIX H: DATA SHEETS
Preliminary
8Ah
0839637A-page 373
769
PIC18F2480/2580/4480/4580
BTFSC
B~
Syntax:
BTFSC f, b La]
Test File, Skip if Clear
Syntax:
BTFSS f, b {,a}
Operands;
o 5 f::;; 255
Operands:
O~fs255
BTFSS
Bit Test File, Skip if Set
O:S:b<7
E [O,fl
Os:bs:7
8E [0,1]
a
Operation:
skip if (f<b»
Status Affected:
None
Encoding:
I
I
1011
=0
fEff
ffff
bbba
If bit 'b' in register 'f is '0', then the next
instruction is skipped. If bit 'b' is '0', then
the next instruction fetched during the
Description:
Operation:
skip jf (f<b»
Status Affected:
None
Encoding:
I
ffff
bbba
fEff
If bit 'b' in register 'f is '1', then the next
Instruction is skipped. If bit 'b' is '1', then
the next instruction fetched during the
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle instruction.
Description:
current instruction execution is discarded
and a NOP is executed instead, making
this a two-cycle Instruction.
If 'a' is '0', the Access Bank is selected. If
'a' is '1', the BSR is used to select the
GPR bank (default).
If 'a' is '0' and the extended instruction set
is enabled, this instruction operates in
Indexed literal Offset Addressing
mode whenever f::; 95 (5Fh).
If 'a' is '0', the Access Bank is selected. If
See Section 26.2.3 "Byte-Oriented and
'a' is '1', the 8SR is used to select the
GPR bank (default).
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f:S: 95 (SFh).
See Section 25.2.3 "Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode" for details.
Literal Offset Mode" for details.
Btt-Oriented InstrucUons in Indexed
\fI.brds:
1
Words:
Cycles:
f(2)
Cycles:
Note:
1
f(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
3 cycles if skip and followed
by a 2-word instruction.
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
BTFSC
FLAG,
1,
HERE
FALSE
0
FALSE
TRUE
PC
PC
address (HERE)
If FLAG<1>
PC
PC
DS39637 A-page 374
FLAG, 1, 0
Before Instruction
0·
address
f·
address (HERE)
After Instruction
IfFLAG<1>
After Instruction
IfFLAG<1>
BTFSS
TRUE
Before Instruction
770
I
1010
=1
PC
(TRUE)
IfFLAG<1>
PC
address (FALSE)
Preliminary
0·
address (FALSE)
f·
address (TRUE)
© 2004 Microchip Technology Inc.
PIC 18F2480/2580/4480/4580
Btt Toggle f
BTG
BOV
Branch if OVerflow
n
Syntax:
BTG t, b (,a)
Syntax:
BOV
Operands:
0::;;f::;;255
Dsb<7
a e (0,1J
Operands:
-128::;::n:-:;;127
Operation:
if Overflow bit is '1'
Operation:
(f<b»
status Affected:
None
Encoding:
Description:
I
(PC) + 2 + 2n --+ PC
--+ f<b>
0111
I
bbba
ffff
ffff
status Affected:
None
Encoding:
I
Description:
Bit 'b' in data memory location 'f Is
inverted.
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
Section 26.2.3 "Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode" for details.
I 0100 I
nnnn
nnnn
The 2's complement number '2n' is
added 10 the PC. Since the PC will
have incremented to fetch lhe next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two..cycle instruction.
If'a' is '0', the Access Bank is selected.
If'a' is '1', the BSR is used to select the
GPR bank (defau.).
in Indexed Literal Offset Addressing
mode whenever f s; 95 (SFh). See
1110
If the Overflow bit is '1', then the
program will branch.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
\l\brds:
01
02
03
04
Cycles:
Decode
Read literal
Process
Data
Write to PC
No
No
No
No
operation
operation
operation
operation
'n'
Q Cycle Activity:
01
03
© 2004 Microchip Technology Inc.
APPENDIX H: DATA SHEETS
Preliminary
OS39637A-page 375
771
PIC18F2480/2580/4480/4580
BZ
Branch if Zero
Subroutine Call
CALL
n
Syntax:
BZ
Syntax:
CALL k {,s}
Operands:
-128s: n:s; 127
Operands:
O:s; k:s; 1048575
Operation:
if Zero bit is '1'
(PC) + 2 + 2n -4 PC
Operation:
Status Affected:
None
Encoding:
I
I 0000 I
1110
se 10,1)
nnnn
(PC) + 4.00..7 TOS,
k -4 PC<20:1 >,
ifs 1
=
nnnn
(W)-.WS,
(Status) ~ STATUSS,
If the Zero bit is '1', then the program
will branch.
Description:
The 2'$ complement number '2n' is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
(BSR) -. BSRS
Status Affected:
None
Encoding:
1st word (k<7:0»
1110
2nd word(k<19:8»
1111
2
Cycles:
2
If Jump:
Q2
Q3
Q4
Read literal
Process
Write to PC
'n'
Data
No
No
No
No
operation
operation
operation
operation
If No Jump
Q2
Q1
~
Q3
HERE
BZ
Q4
Q Cycle Activity:
PC
address (HERE)
PC
If Zero
PC
Q1
Q2
Q3
Q4
Decode
Read literal
'k'<7:0>,
Push PC to
Read literal
'k'<19:8>,
Write to PC
stack
Jump
Before Instruction
After Instruction
If Zero
kkkk,
kkkk,
Words:
1(2)
Q1
kkkk
Subroutine call of entire 2-Mbyte
memory range. First, return address
(PC + 4) is pushed onto the return
stack. If's' = l, the W, Status and BSR
registers are also pushed into their
respective shadow registers, WS,
STATUSS and BSRS. If's' = 0, no
update occurs (defauH). Then, the
20-bit value 'k' is loaded into PC<20:1>.
CALL is a two-cycle instruction.
Q Cycle Activity:
Decode
k,kkk
Description·
Vl.brds:
Cycles:
1108
k19 kkk
No
No
No
No
operation
operation
operation
operation
1;
HERE
address (Jump)
0;
address (HERE + 21
CALL
THERE, 1
Before Instruction
PC
address (HERE)
After Instruction
PC
TOS
ws
BSRS
STATUSS=
OS39637 A-page 376
772
Preliminary
address (THERE)
address (HERE + 4)
W
BSR
Status
© 2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580
CLRF
Clear f
Syntax:
CLRF
Operands:
Osf:;;255
a E [0,1)
f La}
CLRWDT
Clear Watchdog Timer
Syntax:
CLRWDT
Operands:
None
Operation:
OOOh
~WDT,
Operation:
OOOh~f
status Affected:
Z
Encoding:
\
Status Affected:
TO,PD
Description:
Clears the contents of the specified
register.
If 'a' is '0', the Access Bank is selected.
If 'a' is '1', the BSR is used to select the
GPR bank (default).
Encoding:
I
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f:;; 95 (SFh). See
Words:
OOOh --4 WDT postscaler,
1 ~TO,
1->Z
1 ...... PO
0110
I lOla I
ffff
ffff
Description:
0000
0000
0000
0100
CLRWDT instruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits TO
and PO are set.
Cycles:
Q Cycle Activity:
Section 26.2.3 "Byte-Oriented and
Q1
Q2
Bit-Oriented InstrucUons in Indexed
Literal Offset Mode" for details.
V\obrds:
CLRWDT
Cycles:
Before Instruction
VVDT Counter
After Instruction
WDT Counter
WDT Postscaler
TO
PD
CLRF
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
@
?
OOh
o
1
1
SAh
OOh
2004 Microchip Technology Inc.
APPENDIX H: DATA SHEETS
Preliminary
OS39637A-page 3n
773
PIC 18F2480/2580/4480/4580
COMF
Complement f
Syntax:
COMF
Operands:
O:sfs;255
Compare f
CPFSEQ
f {.d (.a)}
Operation:
CPFSEQ
0$;f:5:255
a E [0,11
N,Z
Encoding:
!
Description:
(Q- (W),
if (Q = (W)
(unsigned comparison)
Operation:
s~p
(1) .... dest
status Affected:
0001
W, Skip if f = W
f(,a)
Syntax:
Operands:
dE (0,1(
a E [0,1]
w~h
status Affected:
I llda
ffff
ffff
The contents of register 'f are
complemented. If 'd' is '1', the result is
stored InW.lf'd' is '0', the result is
stored back in register 'f (default).
Encoding:
Description:
None
I
I
OllO
001.
I
I ffff I
ffff
Compares the contents of data memory
location 'f to the contents of W by
performing an unsigned subtraction.
=
If 'f W, then the fetched instruction is
discarded and a NO? is executed
instead, making this a two-cycle
instruction.
If'a' is '0', the Access Bank is selected.
If's' is '0', the BSR is used to select the
GPR bank (default).
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f s: 95 (SFh). See
If 'a' is '0', the Access Bank is selected.
If's' is '1', the BSR is used to select the
GPR bank (default).
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f::; 95 (SFh). See
Section 25.2.3 "Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode" for details.
W:>rds:
Section 26.2.3 "Byte...()riented and
Cycles:
Bit..()riented Instructions in Indexed
literal Offset Mode" for details.
a Cycle Activity:
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
COMF
Before Instruction
REG
After Instruction
REG
=
W
REG,
0,
0
13h
13h
ECh
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
CPFSEQ REG, 0
HERE
NEQUAL
EQUAL
Before Instruction
PC Address
HERE
?
?
W
REG
After Instruction
If REG
PC
If REG
PC
D839637 A~page 378
774
Preliminary
•
W;
Address (EQUAL)
W;
Address (NEQUAL)
© 2004 Microchip Technology Inc.
PIC 18F2480/2580/4480/4580
Compare f with W, Skip if f > W
CPFSGT
Syntax:
CPFSGT
Operands:
o 0:; f:o;255
f{,a}
a E [0,11
en - (W),
Operation"
skip if (f) ;>0 r,:N)
(unsigned comparison)
status Affected"
None
Encoding:
I
Description:
I 010a I
0110
ffff
ffff
Compares the contents of data memory
location 'f to the contents of the W by
performing an unsigned subtraction,
I
CPFSLT
Compare f w~h W, Skip iff < W
Syntax:
CPFSLT
Operands:
05f5255
a E [0,11
Operation:
(Q - (W),
skip if (f) <: 0N)
(unsigned comparison)
status Affected:
None
Encoding·
I
ffff
Words:
1
If 'a' is '0', the Access Bank is selected.
If'a' iS'l', the BSR is used to select the
Cycles:
1(2)
Note:
Section 25.2.3 "Byte-Oriented and
Bit·Oriented Instructions in Indexed
Literal Offset Mode" for details.
ffff
Compares the contents of data memory
location 'f to the contents of W by
performing an unsigned subtraction.
If the contents of 'f are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If 'a' is '0', the Access Bank is selected.
If 'a' is '1', the BSR is used to select the
GPR bank (default).
If the contents of 'f are greater than the
mode whenever f s 95 (SFh). See
I OOOa I
Description:
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
GPR bank (default).
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
ouo
f{,a}
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
VVords
Cycles:
1(2)
Note:
3 cycles if skip and followed
by a 2-word instruction.
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
NGREATER
GREATER
CPFSGT REG, 0
Before Instruction
PC
W;
<
W;
No
No
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
NLESS
LESS
Before Instruction
PC
W
After Instruction
If REG
PC
If REG
PC
?
>
No
operation
~
Address (HERE)
W
After Instruction
If REG
PC
If REG
PC
No
operation
CPFSLT REG, 1
Address (HERE)
?
W;
Address (LESS)
W;
Address (NLESS)
Address (GREATER)
Address (NGREATER)
© 2004 Microchip Technology Inc.
APPENDIX H: DATA SHEETS
Preliminary
DS39637 A-page 379
775
PIC18F2480/2580/4480/4580
DECF
Decrementf
DAW
Decimal Adjust W Register
Syntax:
DAW
Syntax:
DECF f (,d Ca)}
Operands:
None
Operands:
Osfs255
dE 1°,1]
If [W<3:0> >9J or [DC = 11 then
Operation:
(W<3:0» + 6
~
a E [0,11
W<3:0>;
Operation:
(f)-1
(W<3:0» --+ W<3:0>;
Status Affected:
C, DC, N, OV, Z
If [W<7:4> ;.91 or [e = IJ then
0N<7:4» + 6 --+ W<7:4>;
C = 1;
Encoding:
I
Description:
Decrement register
(W<7:4» --+ W<7:4>;
Status Affected:
C
Encoding:
I
0000
I 0000 I
0000
0111
DAW adjusts the eight-bit value in W,
resulting from the ear1ier addition of two
variables (each in packed BCD format)
and produces a correct packed BCD
result.
I Oida I
'r.
ffff
I
ffff
If 'd' is '0', the
Section 25.2,3 "Byte..Qriented and
Bit..Qriented Instructions in Indexed
VVords:
Literal Offset Mode" for details.
Cycles:
Words:
Q Cycle Activity:
01
I
0000
result is stored in W. If 'd' is '1', the
result is stored back in register 'f
(default).
If 'a' is '0', the Access Bank is selected.
If'a' is '1', the BSR is used to select the
GPR bank (default).
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f s; 95 (5Fh). See
else
Description:
~dest
else
Decode
02
03
04
Read
Process
Dais
write
register W
Cycles:
Q Cycle Activity:
W
02
01
04
03
Example 1·
DAW
Before Instruction
W
C
DC
After Instruction
W
C
DC
Example 2:
A5h
DECF
0
0
Before Instruction
OSh
Z
After Instruction
CNT
1
0
CNT,
1,
0
01h
0
CNT
OOh
Z
1
Before Instruction
W
C
DC
After Instruction
W
34h
C
DC
0
DS39637 A-page 380
776
CEh
0
0
1
Preliminary
© 2004 Microchip Technology Inc.
PIC 18F2480/2580/4480/4580
Decrement f, Skip if 0
DECFSZ
Syntax:
DECFSZ
Operands:
0:;f:;255
dE (O,lJ
f (.d
Decrement f, Skip if not 0
DCFSNZ
(.all
Syntax:
DCFSNZ
operands'
05:f$255
aE (O,lJ
(f) -1 ....... dest.
skip if result = 0
status Affected:
None
I
Encoding:
Description:
0010
Operation:
Illda I
ffff
I
ffff
The contents of register 'f are
decremented. If 'd' is '0', the result is
placed in W. If 'd' is '1', the result is
placed back in register 'f (default).
(f) - 1 --+ dest,
skip jf result :;c 0
Status Affected:
None
Encoding:
I
If 'a' is '0', the Access Bank is selected.
If 'a' is '1', the BSR is used to select the
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f:::; 95 (5Fh). See
Section 26.2.3 "Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode" for details.
Section 26.2.3 "Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode" for details.
1
1
Words:
1{2)
Cycles:
3 cycles if skip and followed
ffff
If 'a' is '1', the BSR is used to select the
GPR bank (default).
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f:::; 95 (5Fh). See
1(2)
I
If 'a' is '0', the Access Bank is selected.
GPR bank (default).
Note:
ffff
If the result is not '0', the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
and a NOP is executed instead, making
it a two-cycle instruction.
Cycles:
Illda I
0100
The contents of register 'f are
decremented. If 'd' is '0', the result is
placed in W. If'd' is '1', the result is
placed back in register 'f' (default).
Description:
If the result is '0', the next instruction
which Is already fetched is discarded
'JI.tlrds:
{,d {,all
dE (O,lJ
a E [0,1)
Operation:
f
Note:
by a 2-word instruction.
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
01
02
03
04
01
02
03
04
If skip:
If skip and followed by 2-word instruction:
No
No
No
No
Q1
02
03
04
operation
operation
operation
operation
No
No
No
No
operation
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
DECFSZ
CNT,
GOTO
LOOP
1,
1
Before Instruction
PC
Before Instruction
TEMP
After Instruction
TEMP
Address (HERE)
After Instruction
CNT
CNT-1
O·
IfCNT
PC
IfCNT
PC
A'ddress (CONTINUE)
::f.:
APPENDIX H: DATA SHEETS
TEMP-1,
O·
PC
Address (HERE + 2)
If TEMP
PC
Preliminary
TEMP, 1, 0
?
IfTEMP
C>,
© 2004 Microchip Technology Inc.
DCFSNZ
HERE
ZERO
NZERO
CONTINUE
A'ddress (ZERO)
:;c
o
A'ddress (NZERO)
DS39637A-page 381
777
PIC18F2480/2580/4480/4580
Increment f
GOTO
Unconditional Branch
INCF
Syntax:
GOTO k
Syntax:
INCF
Operands:
0 :0::; k ::; 1048575
Operands:
Operation"
k
O::;fs255
dE [O,1[
Status Affected
None
~
PC<20: 1>
a E [0,1J
Operation:
Encoding:
1st word (k<7:0»
1110
1111
k.,kkk
kkkko
2nd word(k<19:8»
1111
k:9 kkk
kkkk
kkkks
Description:
(f) + 1
status Affected:
GOTO allows an unconditional branch
Encoding:
Description"
anywhere within entire
2-Mbyte memory range. The 20-bit
value 'k' is loaded into PC<20:1 >
GOTO is always a two-cycle
instruction.
Words:
2
Cycles:
2
Q
~
dest
C, DC, N, OV, Z
I
0010
!
ffff
lOda
Uff
The contents of register Tare
incremented. If 'd' is '0', the result is
placed in W. If'd' is '1', the result is
placed back in register T (default).
If 'a' is '0', the Access Bank is selected.
If 'a' is '1', the BSR is used to select the
GPR bank (default).
If'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f s 95 (SFh). See
Section 25.2.3 "Byte-Oriented and
Cycle Activity:
02
03
04
Read literal
'k'<7:0>,
No
operation
Read literal
'k'<19:8>,
No
No
No
No
operation
operation
operation
operation
01
Decode
f {,d {,all
Vl/rite to PC
Bit-Oriented Instructions in Indexed
Literal Offset Mode" for details.
Words:
Cycles:
Q
Cycle Activity:
02
01
GOTO THERE
04
03
After Instruction
Address (THERE)
PC =
INCF
Before Instruction
CNT
0539637 A-page 382
778
Preliminary
1,
0
FFh
Z
0
C
DC
?
After Instruction
CNT
CNT,
?
Z
DOh
1
C
1
DC
1
© 2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580
INCFSZ
Increment f, Skip if 0
Syntax:
INCFSZ
Operands:
0$f$255
Increment f, Skip if not 0
INFSNZ
f {,d {,a)}
INFSNZ
Operands:
0:5f:5255
de ]0,1]
a E [0,11
dE (0,1]
aE
[0,1]
(f) + 1 ~dest,
skip if result ;to 0
Operation:
(f) + 1 -4 dest,
skip if result 0
Operation:
status Affected:
None
status Affected:
None
Encoding:
I
=
I
Encoding:
Description:
OOll
I
llda
ffff
ffff
The contents of register 'f are
incremented. If 'd' is '0', the result is
which is already fetched is discarded
and a NOP is executed instead, making
it a two·cycle instruction.
If 'a' is '0', the Access Bank is selected.
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f:5 95 (SFh). See
and
Literal Offset Mode" for details.
1
VVords:
1(2)
Note:
I ffff
If 'a' is '0' and the extended instruction
set is enabled, this Instruction operates
in Indexed Literal Offset Addressing
mode whenever f:5 95 (5Fh). See
Section 25.2.3 "Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode" for details.
Bit..()riented Instructions in Indexed
'v\tIrds:
ffff
If 'a' is '0', the Access Bank is selected.
If 'a' is '1.', the BSR is used to select the
GPR bank (default).
If 'a' is '1', the BSR is used to select the
GPR bank (default).
"Byte~riented
I 1.0da I
If the result is not' 0', the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making n a two-cycle
instruction.
If the result is '0', the next instruction
Section 25.2.3
0100
The contents of register 'f are
incremented. If 'd' is '0', the result is
placed in W. If'd' is 'I', the result is
placed back in register 'f (default).
Description:
placed in W.lf'd' is '1', the result is
placed back in register 'f (default).
Cycles:
f {,d loa))
Syntax:
Cycles:
1(2)
3 cycles if skip and followed
by a 2-word instruction.
Note:
3 cycles if skip and followed
by a 2-word instruction.
01
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
No
No
No
No
No
No
No
No
operation
operation
operation
operation
operation
operation
operation
operation
HERE
NZERO
ZERO
Before Instruction
PC
After Instruction
CNT
IfCNT
PC
IfCNT
PC
•
@
INCFSZ
CNT, 1., 0
HERE
ZERO
NZERO
Before Instruction
PC
After Instruction
REG
If REG
PC
If REG
PC
Address (HERE)
CNT+ 1
•
0;
Address (ZERO)
0;
Address (NZERO)
2004 Microchip Technology Inc.
APPENDIX H: DATA SHEETS
Preliminary
INFSNZ
REG, 1,
0
Address (HERE)
REG+ 1
0;
Address (NZERO)
0;
Address (ZERO)
D539637A-page 383
779
PIC 18F2480/2580/4480/4580
Inclusive OR Literal with W
IORLW
Inclusive OR W with f
IORWF
Syntax:
IORLW k
Syntax:
IORWF
Operands:
Osks255
Operands:
Operation:
(IN) .OR. k
Status Affected:
N,Z
Osfs:255
dE [0,11
a e [0,1]
Operation:
(IN) .OR.
Status Affected:
N,Z
The contents of Ware ORed with the
eight-bit literal 'k', The result is placed
Encoding:
J
inW
Description:
Inclusive OR W with register 'r. If 'd' is
'0', the result is placed In W. If 'd' is '1',
the result is placed back in register 'f
(default).
Encoding:
Description:
I
0000
~
I
W
1001
kkkk
kkkk
\l\brds:
Cycles:
Q Cycle Activity:
I
01
02
03
Decode
Read
literal 'k'
Process
IORLW
Before Instruction
W
After Instruction
W
Data
0001
f (,d (,a})
m.... des!
) Doda )
ffff
ffff
If 'a' is '0', the Access Bank is selected.
If 'a' is '1', the BSR is used to select the
GPR bank (default).
04
I Write to W
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ~ 95 (SFh), See
35h
Section 26.2.3 "Byte..()riented and
Bit..()riented Instructions in Indexed
9Ah
Literal Offset Mode" for details.
BFh
Words:
CyCles:
Q Cycle Activity:
01
02
IORWF
Before Instruction
RESULT =
W
RESULT, 0, 1
13h
91h
After Instruction
RESULT
W
OS39637 A~page 384
780
Preliminary
13h
93h
© 2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580
Load FSR
MOVF
Syntax:
LFSR f, k
syntax:
MOVF
Operands:
o ~ f:::; 2
operands"
0::::;f::::;255
Operation:
k
status Affected:
None
LFSR
Movef
O::::;k::::;4095
~
de [O,1[
a
FSRf
Operation:
The 12-bit literal 'k' is loaded into the
file select register pointed to by T.
WJrds:
2
Cycles:
2
Description:
Q Cycle Activity:
02
03
04
Read literal
'k'MSB
Process
Write
Data
literal 'k'
Read literal
'k'LSB
~
LFSR 2,
After Instruction
FSR2H
FSR2L
Process
Data
ASh
OOda
I
fEfE
I
fEff
I
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f S 95 (5Fh). See
Section 26.2.3 "Byte..()riented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode" for details.
write literal
'k' to FSRfL
3ABh
03h
I
0101
The contents of register 'r are moved to
a destination dependent upon the
status of 'd'. If'd' is '0', the result is
placed in W. If 'd' is '1', the result is
placed back in register 'f' (default).
Location 'f can be anywhere in the
256-byte bank.
If 'a' is '0', the Access Bank is selected.
If 'a' is '1', the BSR is used to select the
GPR bank (default).
MSBto
FSRfH
Decode
[0,11
N,Z
I
Encoding:
Description:
E
f -+ dest
Status Affected:
Encoding:
01
Dewde
f Ld La)}
Words:
Cycles:
Q Cycle Activity:
I
01
02
03
04
Decode
Read
register 'f
Process
Write W
MOVF
Before Instruction
REG
W
After Instruction
REG
W
@2004MicrochipTechnology Inc.
APPENDIX H: DATA SHEETS
Preliminary
Data
REG,
0,
°
22h
FFh
22h
22h
D539637 A-page 385
781
PIC18F2480/2580/4480/4580
MOVFF
Move f to f
Syntax:
Operands:
MOVLB
Move Literal to Low Nibble in BSR
MOVFF fs.fd
Syntax:
MOVLW k
0 s: f8 S; 4095
AS: fd ~A095
Operands:
O::;;k~255
Operation:
(f8) --+ fd
status Affected:
None
Encoding:
Operation:
k
status Affected:
None
Encoding:
I
Description:
1st word (source)
1100
1111
2nd word (destin.)
fiff
ffff
ffffs
ffff
ffff
ffffd
, ,
The contents of source register fs are
moved to destination register 'fd"
Description:
Location of source 'fs' can be anywhere
in the 4096-byte data space (OOCh to
-4
BSR
0000
I 0001
kkkk
kkkk
The eight-bit literal 'k' is loaded into the
Bank Select Register (B5R). The value
of BSR<7:4> always remains '0',
regardless of the value of k 7:k4.
Words:
Cycles:
FFFh) and location of destination 'fd'
can also be anywhere from OOOh to
FFFh.
Either source Of destination can be W
(a useful special situation).
MOVFF is particularly useful for
transferring a data memory location to a
peripheral register (such as the transmit
buffer or an 110 port).
The MOVFF instruction cannot use the
pel, TOSU, TaSH or TOSL as the
destination register
VIobrds:
2
Cycles:
2(3)
MOVLB
Before Instruction
BSR Register
After Instruction
8SR Register
5
02h
05h
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
Process
register 'f
Data
No
operation
No
operation
register 'f
(src)
Decode
No
operation
(dest)
No dummy
read
MOVFF
VVl'ite
REG1, REG2
Before Instruction
REG1
REG2
33h
REG2
33h
0539637 A-page 386
782
33h
11h
After Instruction
REG1
Preliminary
© 2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580
MOVLW
MOVWF
Move Literal to W
MoveWlof
Syntax:
MOVLW k
Syntax:
MOVWF
Operands:
O~k::;;255
Operands:
Operation:
k~W
0::;;f::::255
a E (0,1]
Status Affected:
None
Encoding:
I
Description:
The eight·bit literal 'k' is loaded Into W
0000
I
lUO
I
kkk<
I
kkkk
(!N) ~ f
Status Affected:
None
Encoding:
I 0110
Descr'lption:
1
IMlrds:
I
Operation:
Cycles:
Q Cycle Activity:
01
I
Decode
02
03
Read
Process
Dala
literal 'k'
MOVLW
ffff
lIla
ffff
Move data from W to register T.
Location 'f can be anywhere in the
256-byte bank.
If 'a' is '0', the Access Bank is selected.
If 'a' is '1', the BSR is used to select the
GPR bank (default).
04
I Wlite to W
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f s;; 95 (SF h). See
Section 26.2.3 "Byte..oriented and
Bit..oriented Instructions in Indexed
Literal Offset Mode" for details.
SAh
After Instruction
W
f{.a}
5Ah
Words:
cycles:
Q Cycle Activity:
01
MOVWF
REG,
0
Before Instruction
W
REG
After Instruction
W
REG
@
2004 Microchip Technology Inc.
APPENDIX H: DATA SHEETS
Preliminary
4Fh
FFh
4Fh
4Fh
0839637 A~page 387
783
PIC 18F2480/2580/4480/4580
MULLW
Multiply LHeral wHh W
Syntax:
MULLW
Operands:
O:sk$255
Operation:
(IN) )( k ~ PRODH:PRODl
Multiply W with f
MULWF
k
Syntax:
MULWf
Operands:
0$f$255
f{,a}
a E (0,1)
(W) x (Q -> PRODH:PRODL
Status Affected:
None
Operation:
Encoding:
I 0000 I 1101 I kkkk I kkkk
Status Affected:
None
Encoding:
I 0000 I 001a I
Description:
An unsigned multipUcatlon is carried
out between the contents of Wand the
8-bit literal 'k'. The 16-bit result is
placed in the PRODH:PRODL register
pair. PRODH contains the high byte.
Description:
W is unchanged.
None of the status flags are affected.
Note that neither overflow nor carry is
possible in this operation. A zero result
is possible but not detected.
Cycles:
Q Cycle Activity:
Q2
Read
Q1
literal 'k'
.wmJ>IL
Before Instruction
W
PRODH
PRODL
After Instruction
W
PRODH
PRODL
MULLW
Q3
Q4
Process
Data
Write
registers
PRODH:
PRODL
OC4h
E2h
?
?
I
ffff
Note that neither overflow nor eany is
possible in this operation. A zero
result is possible but not detected.
If 'a' is '0', the Access Bank is
selected. If 'a' is '1', the BSR is used
to select the GPR bank (default).
If 'a' is '0' and the extended
instruction set is enabled, this
instruction operates in Indexed Literal
Offset Addressing mode whenever
f.,; 95 (5Fh). See Section 26.2.3
''Syte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode" for details.
V\brds:
Decode
ffff
An unsigned multiplication is earried
out between the contents of Wand the
register file location T. The 16~bit
result is stored in the PRODH:PRODL
register pair. PRODH contains the
high byte. Both Wand 'f' are
unchanged.
None of the status nags are affected.
Words:
Cycles:
a Cycle Activity:
=
E2h
ADh
08h
Q1
Q2
Q3
Q4
Decode
Read
register'r
Process
Data
write
registers
PRODH:
PRODL
MULWF
REG,
1
Before Instruction
W
REG
PRODH
PRODL
After Instruction
D539637A-page 388
784
Preliminary
C4h
B5h
?
?
W
C4h
REG
PRODH
PRODL
B5h
BAh
94h
© 2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580
NEGF
Negate f
Syntax:
NEGF
Operands:
O:o;f:5255
a E [0,1)
(f) +
Operation:
f{,a}
1 -d
Status Affected:
N,
av,
Encoding:
I
0110
Description
Location 'f is negated using two's
complement. The result is placed in the
data memory location 'f,
C, DC, Z
I 110. I
ffff
I
ffff
If 'a' is '0', the Access Bank is selected.
If 'a' is '1', the BSR is used to select the
GPR bank (default).
I
NOP
No Operation
Syntax:
NOP
Operands:
None
Operation:
No operation
Status Affected:
None
Encoding:
Description:
No operation.
Words:
Cycles:
Q Cycle Activity:
01
02
03
04
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f:5 95 (5Fh). See
Section 25.2.3 "Byte-Oriented and
Bit-Orlented Instructions in Indexed
Literal Offset Mode" for details.
None.
W:lrds:
Cycles:
Q Cycle Activity:
01
02
NEGF
03
04
REG, 1
Before Instruction
REG
OOll lno 13Ah]
After Instruction
REG
1100 OllO IC6h]
© 2004 Microchip Technology Inc.
APPENDIX H: DATA SHEETS
Preliminary
DS39637 A~page 389
785
PIC 18F2480/2580/4480/4580
POP
Pop Top of Return Stack
PUSH
Push Top of Return Stack
PUSH
Syntax:
POP
Syntax:
Operands:
None
Operands:
None
Operation:
(TOS)
Operation:
(PC'" 2)
Status Affected:
None
status Affected:
None
Encoding:
I
I
Encoding:
Description;
-4
0000
bit bucket
I
0000
I
0000
0110
The TOS value is pulled off the return
stack and is discarded. The TOS value
then becomes the previous value that
was pushed onto the return stack.
This instruction is provided to enable
the user to property manage the return
stack to incorporate a software stack.
\/'I,brds:
Description:
--j.
0000
TOS
I 0000
0000
0101
The PC + 2 is pushed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows implementing a
software stack by modifying TOS and
then pushing it onto the return stack.
Words:
Cycles:
Cycles:
Q Cycle Activity:
~
POP
GOTO
Stack (1 level down)
02
03
PUSH
PC + 2 onto
return stack
No
04
No
operation
operation
~
NEW
PUSH
Before Instruction
TOS
PC
Before Instruction
TOS
01
Decode
0031A2h
014332h
345Ah
0124h
After Instruction
PC
TOS
After Instruction
TOS
PC
0539637 A~page 390
786
014332h
NEW
stack (1 level down)
Preliminary
0126h
0126h
345Ah
© 2004 Microchip Technology Inc.
PIC 18F2480/2580/4480/4580
RCALL
Relative Call
n
RESET
Reset
Syntax:
RESET
Syntax:
RCAlL
Operands:
·1024S:n s: 1023
Operands:
None
Operation:
(PC) + 2 ~ TOS,
(PC) +2 + 2n 4 PC
Operation:
Reset all registers and flags that are
affected by a MCLR Reset.
Status Affected:
None
Encoding:
I
Description:
~101
I Innn I nnnn
nnnn
Subroutine call with a jump up to 1K
from the current location. First, return
address (PC + 2) is pushed onto the
stack. Then, add the 2's complement
number '2n' to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
status Affected:
All
Encoding:
I
Description:
I 0000 I
Ull
1111
Words:
Cycles:
Q Cycle Activity:
I
Q1
Q2
Q3
Q4
Decode
51art
No
operation
No
Reset
Vvtlrds:
Cycles:
0000
This instruction provides a way to
execute a MCLR Reset in software.
2
operation
RESET
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
'n'
Process
\Mite to PC
After Instruction
Registers =
Flags·
=
Reset value
Reset Value
Data
PUSH PC to
No
stack
No
No
No
operation
operation
operation
operation
HERE
RCALL Jump
Before Instruction
Address (HERE)
PC =
After Instruction
Address (Jump)
PC =
TOS
Address (HERE + 2)
=
@
2004 Microchip Technology Inc.
APPENDIX H: DATA SHEETS
Preliminary
DS39637A~page 391
787
PIC 18F2480/2580/4480/4580
RETFIE
Return Literal to w
RETLW
Return from Interrupt
Is)
Syntax:
RETFIE
Syntax:
RETlW k
Operands:
se [0,11
Operands:
O~k~255
Operation:
(TOS) ~ PC,
1 --+ GIEIGIEH or PEIE/GIEL,
Operation:
k-l-W,
ifs
(TOS)~PC,
=1
PClATU, PCLATH are unchanged
0NS)~W,
(STATUSS) ~ Status,
(BSRS) ~ BSR,
PCLATU, PCLATH are unchanged.
status Affected:
GIEIGIEH, PEIElGIEL,
I
Description:
Return from Interrupt Stack Is popped
I
0000
I
I
0001
None
Encoding:
I
Description:
Encoding:
0000
Status Affected:
OOOs
and Top-of-stack (TOS) is loaded into
the PC. Interrupts are enabled by
setting either the high Of low priority
global interrupt enable bit. If's' =1, the
contents afthe shadow registers, WS,
STATUSS and BSRS, are loaded into
Cycles:
2
Q Cycle Activity:
03
04
No
No
poppe
operation
operation
from stack
Set GIEH or
GIEL
No
operation
No
No
No
operation
operation
operation
RETFIE
After Interrupt
PC
W
BSR
status
GIEIGIEH, PEIElGIEL
OS39637 A-page 392
788
I
kkkk
I
kkkk
Q Cycle Activity:
01
Decode
02
03
Q4
Read
literal 'k'
Process
Data
POP PC
from stack,
Write to W
No
No
No
No
operation
operation
operation
operation
~
CALL
02
01
Decode
1100
2
Cycles:
Status and BSR. If's' =0, no update of
these registers occurs (default).
1
I
Words:
their corresponding registers, W,
\!\brds:
0000
W is loaded with the eight-bit literal 'k'.
The program counter is loaded from the
top of the stack (the retum address).
The high address latch (PCLATH)
remains unchanged.
TABLE
TABLE
ADDWF PCL
RETLW kO
RETLW k1
W contains table
offset value
W now has
table value
W ~ offset
Begin table
1
RETLW kn
TOS
WS
BSRS
STATUSS
1
Before Instruction
W
After Instruction
W
Preliminary
End of table
07h
value of kn
© 2004 Microchip Technology Inc.
PIC 18F2480/2580/4480/4580
Return from Subroutine
RETURN
Ro_ Left f through Carry
RLCF
Syntax:
RETURN {s}
Syntax·
Operands:
sE
Operands:
Operation:
(0,1)
RLCF
dE (0,11
(0,11
(TOS) .... PC,
aE
ifs =1
(WS) .... W,
None
Encoding:
I
Description:
0000
(f<n» ~dest<n + 1>,
(1<7» --+ C,
(C) ~ desl<O>
Operation:
(STATUSS) ~ status,
(BSRS) ~ BSR,
PCLATU, PC LATH are unchanged
Status Affected:
I 0000 I
0001
I
OOls
I
Status Affected:
C,N,Z
Encoding:
I
Description:
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
's'= 1, the contents of the shadow
registers, WS, STATUSS and BSRS,
are loaded into their corresponding
registers, W, status and BSR. If
's' 0, no update of these registers
occurs (default).
1
Cycles:
2
02
03
04
No
operation
Process
Data
POP PC
from stack
No
No
No
No
operation
operation
operation
operation
Decode
I Dlda I
ffff
ffff
If's' is '0' and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f ::;95 (5Fh). See Section 25.2.3
Q Cycle Activity:
01
OOH
The contents of register 'f are rotated
one bit to the left through the Carry
flag. If 'd' is '0', the result is placed in
W. If 'd' is '1', the result is stored back
in register 'f (default).
If 'a' is '0', the Access Bank Is
selected. If 'a' is '1', the BSR is used to
select the GPR bank (default).
=
I,/\brds:
f {,d {,all
O~f::;:255
"Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode" for details.
@~r-r-eg-i-st-er-f--'h
Words:
Cycles:
Q Cycle Activity:
RETURN
01
After Interrupt
PC
=TOS
~
RLCF
Before Instruction
REG
C
After Instruction
REG
W
C
© 2004 Microchip Technology Inc.
APPENDIX H: DATA SHEETS
Preliminary
REG, 0, 0
1110 0110
°
lll0 0110
1100 1100
1
OS39637 A~page 393
789
PIC18F2480/2580/4480/4580
Ro_ Left f (No Carry)
RLNCF
RLNCF
Syntax:
Operands:
Rotate Right f through Carry
RRCF
f{,d {,a}}
0::;;f::;;255
Synta)(;
RRCF
Operands:
0::; f::; 255
dE [0,1)
a e [0,1)
dE [0,1)
a€
Operation:
(f<n»
~
dest<n + 1>,
(f<7»
-4
dest<O>
status Affected:
N,Z
Encoding:
I
Description:
0100
f I,d La})
I Olda I
ffEE
ffff
The contents of register 'f are rotated
one bit to the left. If 'd' is '0', the result
is placed in W. If 'd' is 'I', the result is
stored back in register 'f (default).
status Affected:
C,N,Z
Encoding:
I
Description:
If'a' Is '0', the Access Bank is selected.
If'a' is '1', the BSR is used to select the
GPR bank (default).
set Is enabled, this instruction operates
in Indexed literal Offset Addressing
mode whenever f s: 95 (5Fh). See
Section 26.2.3 "Byle-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode" for details.
register f
0011
I Ooda
Hff
ffff
The contents of register 'f are rotated
one bit to the right through the Carry
flag. If 'd' is '0', the result is placed in W.
If'd' Is '1', the result is placed back in
register 'f (default).
If 'a' is '0', the Access Bank is selected.
If 'a' is '1', the BSR is used to select the
GPR bank (default).
If 'a' is '0' and the extended instruction
rl
[0,1]
(f<n» -4 dest<n -1 >,
(f<O» --+ C,
(C) --+ dest<7>
Operation:
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Inde)(ed literal Offset Addressing
mode whenever f::; 95 (5Fh). See
Section 26.2.3 "Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode" for details.
b
cill:I
\l\brds:
register f
Cycles:
h
Words:
Q Cycle Activity:
Cycles:
Q Cycle Activity:
Q2
Ql
~
RLNCF
1010 1011
~
After Instruction
REG
Q4
REG, 1, 0
Before Instruction
REG
Q3
RRCF
REG, 0, 0
Before Instruction
0101 0111
REG
C
1110 0110
0
After Instruction
REG
W
C
DS39637 A~page 394
790
Preliminary
1110 0110
0111 0011
0
© 2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580
RRNCF
Rotate Right I (No Carry)
SETF
Set I
Syntax:
RRNCF
Syntax:
SETF
Operands:
O~f:;;255
Operands:
O:s f::;: 255
a E [0,11
Operation:
FFh --.. f
f {,d {,a}}
dE [0,11
a E [0,11
Operation:
(f<:n»
---J.
dest<n - 1>,
(f<O» -+ dest<7>
Status Affected:
N,Z
0110
I IOOa I
fHf
I ffff
The contents of the specified register
are set to FFh.
The contents of register 'f' are rotated
one bit to the right. If 'd' is '0', the result
If 'a' is '0', the Access Bank is selected.
If 'a' is '1', the BSR is used to select the
is placed in W If 'd' is '1', the result is
placed back in register 'f (default).
GPR bank (default),
If'a' is '0' and the extended instruction
If 'a' is '0', the Access Bank will be
selected, overriding the BSR value. If'a'
is '1', then the bank will be selected as
per the BSR value (default).
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f::; 95 (SFh). See
set is enabled, this instruction operates
EftE
Section 25.2.3 "Byte-Oriented and
I
Description:
I
ftft
I
I
Description"
OOda
I
None
Encoding:
Encoding:
0100
I
status Affected:
f {,a}
in Indexed Literal Offset Addressing
mode whenever f::;; 95 (SFh). See
Section 25.2.3 "Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode" for details.
Words:
Cycles:
Bit-Oriented Instructions in Indexed
Literal Offset Mode" for details.
c:1
register f
b
Words:
Cycles:
SETF
Before Instruction
REG
After Instruction
REG
Example 1"
RRNCF
Before Instruction
REG
REG,
l,
0
0,
0
REG,l
5Ah
FFh
1101 0111
After Instruction
REG
!;l!;!i!mple ;;::
1110 1011
RRNCF
Before Instruction
W
REG
After Instruction
W
REG
REG,
?
1101 0111
11lO 1011
1101 0111
© 2004 Microchip Technology Inc.
APPENDIX H: DATA SHEETS
Preliminary
DS39637A~page 395
791
PIC 18F2480/2580/4480/4580
SLEEP
Enter Sleep mode
SUBFWB
Syntax:
SLEEP
Syntax:
Operands:
None
Operands:
Operation:
OOh --+ WDT,
o ----j. WDT postscaler,
SUBFWB
a € to,1]
N, OV, C, DC, Z
Encoding:
I
Description:
The Power-Down status bit (PO) is
cleared. The Time-out status bit (TO)
is set. Watchdog Timer and its
postscaler are cleared.
Subtract register 'r and Carry flag
(borrow) from W (2'8 complement
method). If 'd' is '0', the result is stored
in W. If'd' is '1', the result is stored in
register'f (default).
The processor is put into Sleep mode
with the oscillator stopped.
If'a' is '1', the BSR is used to select the
----j.
PO
Status Affected:
TO,PD
Encoding:
I 0000 I 0000 I 0000 I OOll I
0101
I
Olda
I
HEf
ffff
If'a' is '0', the Access Bank is selected.
GPR bank (defau~).
1
If 'a' is '0' and the extended instruction
Cycles:
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f::; 95 (SFh). See
Q Cycle Activity:
QI
~
Q2
Q3
SLEEP
Before Instruction
TO = ?
PD = ?
After Instruction
TO
1t
PO =
a
t
(C) --> des!
(W) - (Q -
status Affected:
o
W::lrds:
f (,d (,a))
0;5;1$255
dE (0,1)
Operation:
1--+TO,
Description:
Subtract f from W with Borrow
04
Section 26.2.3 "Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode" for details.
Words:
Cycles:
Q Cycle Activity:
01
Example 1·
Q2
Q3
SUBFWB
Q4
REG, 1, 0
Before Instruction
IfWDT causes wake-up, this bit is cleared.
REG
3
W
C
2
1
After Instruction
REG
W
FF
2
C
o
o
Z
1
; resuH is negative
N
Example 2·
SUBFWB
REG, 0, 0
Before Instruction
REG
2
W
C
5
1
After Instruction
REG
W
C
Z
N
Example 3
2
3
1
o
o
; resuH is positive
SUBFWB
REG, 1, 0
Before Instruction
REG
W
C
After Instruction
o
REG
o
W
C
Z
N
OS39637 A-page 396
792
Preliminary
1
2
2
1
1
o
; resuH is zero
© 2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580
SUBLW
Subtract W from Literal
SUBWF
Subtract W from f
Syntax:
SUBLW k
Syntax:
SUBVIIF
Operands:
Os:ks:255
Operands:
Operation:
k-(W)
0::;;f$255
d € [0,1J
status Affected:
N, OV, C, DC, Z
Encoding"
I 0000 I 1000 I kkkk I kkkk
Description:
~W
a e [0,11
W is subtracted from the eight-bit
literal 'k'. The result is placed in W.
'v\brds:
N, OV, C, DC, Z
Encoding:
I 0101 I llda
Q Cycle Activity:
Example 1:
03
SUBLW
Q4
C
After Instruction
W
C
Z
N
Example 2'
C
After Instruction
W
C
Z
N
Example 3:
Before Instruction
W
C
After Instruction
W
set is enabled, this instruction operates
in Indexed literal Offset Addressing
mode whenever f s 95 (5Fh). See
Section 26.2.3 "Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode" for detaUs.
01 h
?
01h
1
; result is positive
0
0
SUBLW
02h
Words:
Cycles:
Q Cycle Activity;
02h
?
OOh
1
; result is zero
1
0
SUBLW
Example 1:
REG
02h
W
C
REG
FFh; (2'6 complement)
; result is negative
Z
0
1
REG, 1, 0
3
2
?
After Instruction
?
o
SUBWF
Before Instruction
03h
C
N
ffff
If'a' is '0' and the extended instruction
02h
Before Instruction
W
ffff
Subtract W from register 'f (2'5
complement method). If'd' is '0', the
result is stored in W. If 'd' is '1', the
result is stored back in register 'f
(default).
If'a' is '0', the Aocess Bank is selected,
If'a' is '1', the B5R is used to select the
GPR bank (default).
Before Instruction
W
des1
(Q - (W)
status Affected:
Cycles:
02
~
Operation:
Description:
01
f {,d {,a}}
1
W
2
C
1
0
0
Z
N
Example 2:
SUBWF
; result is positive
REG, 0, 0
Before Instruction
REG
W
2
2
C
?
After Instruction
REG
W
C
Z
N
Example 3'
2
0
1
1
0
SUBWF
; result is zero
REG, 1, 0
Before Instruction
REG
W
1
2
C
?
After Instruction
REG
FFh ;(2's complement)
W
2
0
0
1
C
Z
N
© 2004 Microchip Technology Inc.
APPENDIX H: DATA SHEETS
Preliminary
; result is negative
0539637 A·page 397
793
PIC18F2480/2580/4480/4580
SUBWFB
Subtract W from f with Borrow
Syntax:
SUBWFB
Operands:
O~f$:255
Swap!
SWAPF
f I,d {,a}}
Syntax:
SWAPF f {,d {,a}}
Operands:
0::;fS:255
dE [0,1]
a E [0,1]
dE [0,1]
aE
[0,1]
(C) -4 desl
Operation:
(f) - (W) -
Status Affected:
N, OV, C, DC, Z
Encoding:
I
Description:
0101
I
10da
I
Operation:
ffff
ffff
Subtract Wand the Carry flag (borrow)
from register T (2's complement
method). It'd' is '0', the result is stored
in W. If 'd' is '1', the result is stored back
in register 'f (default).
I
(f<3:0»
~
dest<7:4>,
(f<7:4»
~
dest<3:0>
Status Affected:
None
Encoding:
I
Description:
If 'a' is '0', the Access Bank is selected.
If 'a' is '1', the BSR is used to select the
GPR bank (default).
0011
I 10da I
ffff
ffff
The upper and lower nibbles of register
'f are exchanged. If 'd' is '0', the resull
is placed in W. If 'd' is '1', the result is
placed in register 'f (default).
If 'a' is '0', the Access Bank is selected.
If'a' iS'l', the BSR is used to select the
GPR bank (default).
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f s 95 (5Fh). See
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed litera! Offset Addressing
mode whenever f s: 95 (5Fh). See
Section 26.2.3 "Byte-Oriented and
Bit-Orlented Instructions in Indexed
Section 25.2.3 "Byte-Oriented and
Bit-Oriented Instructions in Indexed
literal Offset Mode" for details.
Literal Offset Mode" for details.
Words:
Words:
Cycles:
Cycles:
Q Cycle Activity:
Q2
Q1
!;,~ilIIlRI!ill'
Before Instruction
REG
W
C
After Instruction
REG
W
C
Z
N
SUBWFB
Before Instruction
REG
W
C
After Instruction
REG
1,
(0001 1001)
( 0000 1101)
OCh
ODh
1
0
0
(oooo
SUBWFB
03h
OEh
1
F5h
Q4
0
19h
ODh
1
SUBWFB
El!S!ml2l§:2:
Before Instruction
REG
1Bh
1Ah
W
C
0
After Instruction
REG
18h
W
OOh
C
1
Z
1
N
0
!;1Sii!1II~I~J
REG,
Q3
SWAPF
Before Instruction
REG
After Instruction
REG
1011)
( 0000 1101)
REG, 1, 0
53h
35h
; result is positive
REG,
0,
0
(0001 1011 )
(0001 1010 )
(0001 1011)
; result is zero
REG, 1,
( 0000 0011)
(0000 1101)
(1111 OIOO)
; [2's comp)
W
C
Z
N
DS39637 A~page 398
794
OEh
0
0
1
(0000 1101)
; result is negative
Preliminary
© 2004 Microchip Technology Inc.
I
PIC18F2480/2580/4480/4580
TBLRD
Table Read
Syntax:
TBLRD
Operands:
None
Operation:
ifTBLRO .,
(Prog Mem (TBLPTR» ~ TABLAT;
TBLPTR - No Change;
ifTBLRD *+,
(Prog Mem (TBLPTR» -4 TABLAT;
(TBLPTR) + 1 .....,. TBLPTR;
ifTBLRD *-,
(Prog Mem (TBLPTR» .....,. TABLAT;
(TBLPTR) - 1 .....,. TBLPTR;
ifTBLRD +*,
(TBLPTR) + 1 -4 TBLPTR;
(Prog Mem (TBLPTR)) .....). TABLAT;
status Affected:
(~;
*+; *-; +*)
TBLRD
Table Read (Continued)
Example 1:
TBtRD
TABLAT
TBLPTR
0000
0000
0000
55h
OOA356h
34h
MEMORY(OOA356h)
After Instruction
TABLAT
TBLPTR
Example 2-
34h
OOA357h
TBLRO
Before Instruction
TABLAT
TBLPTR
MEMORY(01A357h)
MEMORY(01A358h)
After Instruction
TABLAT
TBLPTR
None
Encoding:
*+
Before Instruction
+*
OAAh
01A357h
12h
34h
34h
01A358h
10nn
nn",Q >
~l
~2
~3
Description:
.,
>.
>.
ThiS instructIOn IS used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer, called Table
Pointer (TBLPTR), is used.
The TBlPTR (a 21~bit pointer) pOints to
each byte in the program memory. TBlPTR
has a 2*Mbyte address range.
TBlPlR{O] 0: least Significant Byte of
Program Memory 1J\brd
TBlPlR[Oj 1: Most Significant Byte of
Program Memory VIA:lrd
The TBLRD instruction can modify the value
of TBlPTR as follows:
=
=
no change
post~increment
post-decrement
pre-increment
\M::)rds:
Cycles:
2
Q Cycle Activity:
01
02
03
04
Decode
No
No
No
operation
No operation
(Read Program
Memory)
operation
operation
No
No
No operation
operation
operation (Wite TABLAT)
© 2004 Microchip Technology Inc.
APPENDIX H: DATA SHEETS
Preliminary
OS39637 A-page 399
795
PIC18F2480/2580/4480/4580
TBLWT
Table Write
TBLWT
Table Write (Continued)
Syntax:
TBLWT (*; .+; *-; +*)
Example ,.
TELWI' *+;
Operands:
None
Operation:
if TBlWT*,
(TABLAT)
-4
Before Instruction
TABLAT
55h
OOA356h
TBLPTR
HOLDING REGISTER
(OOA356h)
FFh
After Instructions (table write completion)
TABLAT
55h
TBLPTR
OOA357h
HOLDING REGISTER
(OOA356h)
55h
Holding Register;
TBLPTR - No Change;
if TBlWT*+,
(TABLAT) -4 Holding Register;
(TBLPTR) + 1 -4 TBLPTR;
if TBlVlfr-,
(TABLAT) -4 Holding Register;
(TBLPTR) - 1 ..., TBLPTR;
Example 2:
ifTBlWf+*,
(TBLPTR) + 1
(TABLAT)
status Affected:
-4
-4
TBLPTR;
Holding Register;
None
Encoding:
0000
0000
0000
~l
~2
~3
Description:
.
lInn
nn",O
.-'.
.'
ThIs Instruction uses the 3 LSBs of the
TBLPTR to determine which of the
a holding registers the TABLAT is written to.
TELWI' +*;
Before Instruction
TABLAT
34h
TBLPTR
01389Ah
HOLDING REGISTER
FFh
(01389Ah)
HOLDING REGISTER
(01389Bh)
FFh
After Instruction (table write completion)
TABLAT
34h
TBLPTR
01389Bh
HOLDING REGISTER
FFh
(01389Ah)
HOLDING REGISTER
(01389Bh)
34h
The holding registers are used to program
the contents of Program Memory (P.M.).
(Refer to Section 6.0 "Flash Program
Memory" for additional details on
programming Flash memory.)
The TBlPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-MBtye address range. The LSb of
the TBLPTR selects which byte ofthe
program memory location to access.
=0:
Least Significant Byte
of Program Memory
Word
TBLPTR(O] 1: Most Significant Byte of
Program Memory Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
TBLPTR(O]
=
no change
post-increment
post-decrement
pre-increment
IJI..brds:
Cycles:
2
Q Cycle Activity:
Q1
Decode
Q2
Q3
Q4
No
No
No
operation operation operation
No
No
No
No
operation operation operation operation
(Write to
(Read
TABLAT)
Holding
Register)
D539637 A-page 400
796
Preliminary
© 2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580
TSTFSZ
Test f, Skip if 0
XORLW
Exclusive OR Literal with W
Syntax:
TSTFSZ f (.a)
Syntax:
XORLW k
Operands:
0:;;f:5255
Operands:
Osks255
a E [0,11
Operation:
skip jff =0
0N) XOR k
Operation:
status Affected:
N.Z
Status Affected:
None
Encoding:
I
Encoding:
I 0000 I 1010 I kkkk
Description:
0110
I Olla
Efff
ffff
If 'f - 0, the next instruction fetched
during the current instruction execution
is discarded and a Nap is executed,
making this a two-cycle instruction.
If 'a' is '0', the Access Bank is selected.
If 'a' is '~', the BSR is used to select the
GPR bank (default).
~W
I
kkkk
The contents of Ware XORed with
the 8~bit literal 'k', The result is placed
inW.
Description:
Words:
Cycles:
Q Cycle Activity:
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed literal Offset Addressing
mode whenever f s: 95 (SFh). See
I
01
02
03
Decode
Read
literal 'k'
Process
Data
XORLW
Section 26.2.3 "Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode" for details.
04
I Write to W
OAFh
Before Instruction
W
B5h
After Instruction
V\tlrds:
W
Cycles:
1Ah
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
01
04
03
02
If skip:
No
No
No
No
operation
operation
operation
operation
No
No
No
No
operation
operation
operation
operation
HERE
NZERO
ZERO
TSTFSZ
CNT, 1
Before Instruction
PC
Address (HERE)
After Instruction
IfCNT
PC
IfCNT
PC
@
OOh.
"*
Address (ZERO)
OOh,
Address (NZERO)
2004 Microchip Technology Inc.
APPENDIX H: DATA SHEETS
Preliminary
DS39637 A·page 401
797
PIC18F2480/2580/4480/4580
XORWF
Exclusive OR W with f
Syntax:
XORWF
Operands:
0;:;;f$255
f (,d La))
dE [0,11
E [0,11
a
Operation:
(W) .xOR. (Q
status Affected:
N,Z
Encoding:
I
Description:
0001
-4
des!
I lOda I
ffff
ffff
I
Exclusive OR the contents of Wwith
register 'f. If'd' is '0', the result is stored
in W. If'd' is '1', the result is stored back
in the register 'f (default).
If 'a' is '0', the Access Bank is selected,
If'a' iS'l', the BSR is used to select the
GPR bank (default).
If 'a' is '0' and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f:::; 95 (5Fh). See
Section 26.2.3 "Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode" for details.
'II'IA:lrds:
Cycles:
Q Cycle Activity:
01
02
XORWF
03
04
REG, 1, 0
Before Instruction
REG
W
AFh
B5h
After Instruction
REG
W
DS39637A-page 402
798
lAh
BSh
Preliminary
© 2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580
25.2
Extended Instruction Set
A summary of the instructions in the extended instruction set is provided in Table 25-3. Detailed descriptions
are provided in Section 25.2.2 "Extended Instruction
Set". The opcode field descriptions in Table 25-1 apply
to both the standard and extended PIC18 instruction
sets.
In addition to the standard 75 instructions afthe PIC18
instruction set, PIC18F248012580/4480/4580 devices
also provide an optional extension to the core CPU
functionality. The added features include eight addi-
tional instructions that augment indirect and indexed
addressing operations and the implementation of
set
Note:
The insfruCtion"
extension and the
IndexOd Literal; ~t Addressing mode
Indexed Literal Offset Addressing mode for many afthe
standard PIC18 instructions.
~re:~s!e~ed 1c?~ pptirniZing applications
written in-G;' the user may likely never use
The additional features are disabled by default. To
ftlese 4nstrUCtfoos directly
enable them, users must set the XINST configuration
Th~
in assembler.
sYr!tOl<: ~ ;tj1~;': commands
is provided :,!S. ~ r.t,reO<:<! W.users who may be
revitlVl1ng, ~de:)bat !las been generated
bit.
The instructions in the extended set can all be
classified as literal operations, which either manipulate
byacoropUer,
the File Select Registers or use them for indexed
addressing. Two of the instructions, ADDFSR and
25.2.1
SUBFSR, each have an additional special instantiation
for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.
.•
EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed arguments, using one of the File Select Registers and some
offset to specify a source or destination register. When
an argument for an instruction serves as part of
indexed addressing, it is enclosed in square brackets
("[ ]"). This is done to indicate that the argument is used
as an index or offset. MPASMTM Assembler will flag an
error if it determines that an index or offset value is not
bracketed.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in byteoriented and bit-oriented instructions. This is in addition
to other changes in their syntax. For more details, see
Section 25.2.3.1 "Extended Instruction Syntax with
standard PIC18 Commands".
dynamic allocation and de-allocation of software
stack space when entering and leaving
subroutines
function pointer invocation
software stack Pointer manipulation
manipulation of variables located in a software
stack
II/ote.:.
In the past, sqt!8re brackets have been
used to :~,' optiQnal arguments in the
PIC18 'and earli~r_ instruction sets. In this
text and gpj"g forward, optional arguments
are denoted.by braces ,0").
TABLE 25-3'
EXTENSIONS TO THE PIC18 INSTRUCTION SET
16-Bit Instruction Word
Mnemonic,
Operands
ADDFSR
ADDULNK
CALLW
MOVSF
zS, fd
zS,
PUSHL
k
SUBFSR
SUBULNK
t, k
k
Cycles
MSb
t, k
k
MOVSS
@
Description
~
Add literal to FSR
Add literal to FSR2 and return
Call subroutine using WREG
Move Zs (source) to 1st word
fd (destination) 2nd word
Move Zs (source) to 1st word
zd (destination)2nd word
store literal at FSR2,
decrement FSR2
Subtract literal from FSR
Subtract literal from FSR2 and
return
2004 Microchip Technology Inc,
APPENDIX H: DATA SHEETS
1
2
2
2
2
1
1
2
Preliminary
1110
1110
0000
1110
1111
1110
1111
1110
1110
1110
LSb
ffkk kkkk
Status
Affected
1000
1000
0000
1011
Ozzz
zzzz
ffff
ffff
ffff
1011
xxxx
1010
lzzz
xzzz
zzzz
zzzz
None
kkkk
kkkk
None
1001
1001
ffkk
11kk
kkkk
kkkk
None
None
l1kk kkkk
0001 0100
None
None
None
None
D839637 A~page 403
799
PIC18F2480/2580/4480/4580
25.2.2
EXTENDED INSTRUCTION SET
ADDFSR
Add LHeral to FSR
Syntax:
ADDFSR
Operands:
o sk:::;63
fE (0,1,21
FSR(fj + k --> FSR(O
Operands:
None
Operation:
Status Affected:
f, k
The 6-bit literal 'k' is added to the
contents ofthe FSR specified by T.
Description"
VVords:
Cycles:
Add Literal to FSR2 and Return
Syntax:
Operation:
ADDULNK k
Osks:63
FSR2 + k ~ FSR2,
Status Affected:
None
PC
11110 1,000 I ftkk I kkkk
Encoding:
ADDULNK
Encoding:
Description:
=(TOS)
1,110 1,000
llkk
kkkk
The 6~bit literal 'k' is added to the
contents of FSR2. A RETURN is then
executed by loading the PC with the
TOS.
1
1
The instruction takes two cycles to
execute; a NOP is performed during the
Q Cycle Activity:
01
second cycle.
This may be thought otas a special case
of the ADDFSR instruction, where f =3
(binary 'll'); it operates only on FSR2.
ADDFSR 2.
Before Instruction
FSR2
03FFh
After Instruction
FSR2
23h
Words:
1
Cycles:
2
Q Cycle Activity"
0422h
01
02
Q3
04
Decode
Read
literal 'k'
Process
Wite to
No
No
Data
No
FSR
No
Operation
Operation
Operation
Operation
ADDULNK 23h
Before Instruction
FSR2
PC
TOS
03FFh
0100h
02AFh
After Instruction
Note:
0422h
PC
TOS
02AFh
TOS-1
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).
0539637 Awpage 404
800
FSR2
Preliminary
© 2004 Microchip Technology Inc.
PIC 18F2480/2580/4480/4580
CALLW
Subroutine Call Using WREG
Syntax:
Operands:
Operation:
MOVSF
Move Indexed to f
CALLW
Syntax:
MOVSF {Zs}, fd
None
Operands:
0 ~ Zs ~ 127
(PC + 2) -4 TOS,
0N) --+ pel,
(PC LATH) --+ PCH,
Operation:
((FSR2) + Zs)
status Affected:
None
O.$fd~4095
(PCLATU) -; PCU
status Affected:
None
Encoding:
I
Description
0000
I
0000
I
0001
0100
I
1st word (source)
1110
1111
2nd word (destin.)
Description:
update W, status or BSR.
Cycles:
2
01
02
03
04
Push PC to
stack
No
No
Read
WREG
No
No
No
operation
operation
operation
operation
Words:
2
Cycles:
2
operation
PCLATU
CALLW
PCLATH
PCLATU
W
01
02
03
04
Decode
Determine
source addr
Determine
source addr
Read
source reg
No
No
operation
operation
Write
register T
(des!)
Decode
address (HERE)
= 10h
= OOh
After Instruction
PC
TOS
ffffd
Q Cycle Activity:
Before Instruction
W
zzzz"
ffff
If the resultant source address points to
an indirect addressing register, the
value returned will be OOh.
Decode
PC
PCLATH
ozzz
ffff
The MOVS F instruction cannot use the
PCl, TOSU, TOSH or TOSl as the
destination register.
Q Cycle Activity:
HERE
1011
The contents of the source register are
moved to destination register 'fd'. The
actual address of the source register is
determined by adding the 7-bit literal
offset 'Zs' in the first word to the value of
FSR2. The address of the destination
register is specified by the 12-bit literal
'fd' in the second word. Both addresses
can be anywhere in the 4096-byte data
space (oaOh to FFFh).
Unlike CALL, there is no option to
1
fd
Encoding:
First, the return address (PC + 2) is
pushed onto the Tetum slacle Next, the
contents ofW are written to pel; the
existing value is discarded. Then, the
contents of PCLATH and PCLATU are
latched into PCH and PCU,
respectively. The second cycle is
executed as a NOP instruction while the
new next instruction is fetched.
\M)rds
-4
No dummy
read
06h
001006h
address (HERE + 2)
10h
OOh
06h
~
MOVSF
[05h] ,
REG2
Before Instruction
FSR2
Contents
of85h
REG2
SOh
33h
11h
After Instruction
FSR2
Contents
of85h
REG2
© 2004 Microchip Technology Inc.
APPENDIX H: DATA SHEETS
Preliminary
SOh
33h
33h
DS39637 A-page 405
801
PIC18F2480/2580/4480/4580
MOVSS
Nk>ve Indexed to Indexed
PUSHL
Syntax:
MOVSS [zJ, [zdl
O:S"zs :S:127
Syntax:
PUSHL k
Operands:
0:s;ks:255
Operation:
k ~(FSR2),
FSR2 - 1~ FSR2
Operands:
O::;Zd:S 127
Operation:
«FSR2) + zs) --.,. «FSR2) + zd)
Status Affected:
None
Encoding:
1st word (source)
status Affected: None
1110
111.1
2nd word (dest.)
store Lileral at FSR2, Decrement FSR2
r--,-,,-,--rl-'-O-'-O-'-k~k~k~k-'I~k~k~kk-'I
Encoding:
Ion
lzzz
zz:zzs
xxxx
xzzz
zzzzd
Description:
The contents of the source register are
Description
moved to the destination register. The
addresses of the source and destination
registers are determined by adding the
7-bit literal offsets 'zs' or '-ld',
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4Q96..byte data memory space
(OOOh to FFFh),
The B~bit literal 'k' is written to the data
memory address specified by FSR2. FSR2 is
decremented by 1 after the operation.
This instruction allows users to push values
onto a software stack.
Words:
Cycles:
Q Cycle Activity:
Q4
Ql
The MOVSS instruction cannot use the
pel, TOSU, TaSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value retumed will be DOh. If the
resultant destination address points to
an indirect addressing register, the
instruction will execute as a NO P.
2
2
\I\.obrds:
Cycles:
PUSHL
08h
Before Instruction
FSR2H:FSR2L
Memory (01 ECh)
01ECh
OOh
After Instruction
FSR2H:FSR2L
Memory (01 ECh)
01EBh
08h
Q Cycle Activity:
01
Q2
Q3
04
Decode
Determine
source addr
Decode
Determine
dest addr
Determine
source addr
Determine
dest addr
Read
source reg
Write
to dest reg
~
MOVSS
Before Instruction
FSR2
Contents
of85h
Contents
ofB6h
After Instruction
FSR2
Contents
ofBSh
Contents
ofB6h
DS39637A-page 406
802
[OSh] ,
[06h]
SOh
33h
l1h
80h
33h
33h
Preliminary
© 2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580
SUBFSR
Subtract Literal from FSR
SUBULNK
Subtract Uteral from FSR2 and Relurn
Syntax:
SUBFSR f, k
Operands:
o s k::;; 63
Syntax;
Operands:
Operation:
SUBULNK k
0 $; k ::;: 63
IE [0,1,2]
Operation:
FSR2 - k ....,. FSR2
(TOS) .... PC
FSRf - k....,. FSRf
status Allected:
Encoding:
None
status Affected: "N"'o"ne"---_.-_ _--,-____- r -______,
1"110 1"00" I ffkk I kkkk
Encoding:
I 1110 I
The 6-bit literal 'k' is subtracted from
Description:
The 6-bit literal 'k' is subtracted from the
Description:
llkk
k.k.kk
contents of the FSR2. A RETURN is then
executed by loading the PC with the TOS.
the oontentsofthe FSR specified
by T.
The instruction takes two cycles to execute;
'v\Qrds:
Cycles:
Q Cycle Activity:
01
1001
02
03
a NOP is performed during the second cycle.
This may be thought of as a special case of
the SUBFSR instruction, where f = 3 (binary
04
'11'); it operates only on FSR2.
1
Words:
Cycles:
2
Q Cycle Activity:
~
Before Instruction
FSR2
After Instruction
=
FSR2
SUBFSR 2, 23h
04
02
Read
register 'f'
No
No
No
No
Operation
Operation
Operation
Operation
03FFh
03DCh
03
Process
01
Decode
Data
Wite to
destination
SUBULNK 23h
WJIU>io;
Before Instruction
FSR2
PC
After Instruction
FSR2
PC
© 2004 Microchip Technology Inc.
APPENDIX H: DATA SHEETS
Preliminary
03FFh
0100h
03DCh
(TOS)
OS39637A-page 407
803
PIC 18F2480/2580/4480/4580
25.2.3
Note:
BYTE-ORIENTED AND
BIT-ORIENTED INSTRUCTIONS IN
INDEXED LITERAL OFFSET MODE
Enabling
the
P1C18
instruction
set
extension may cause legacy applications
to behave erratically or fail entirely.
In addition to eight new commands in the extended set,
enabling the extended instruction set also enables
Indexed Literal Offset Addressing mode (Section 5.6.1
"Indexed Addressing with Literal Offset"). This has
a significant impact on the way that many commands of
the standard PIC18 instruction set are interpreted
When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations:
either as a location in the Access Bank (a = 0), or in a
GPR bank designated by the BSR (a = 1). When the
extended instruction set is enabled and a = 0, however,
a file register argument of 5Fh or less is interpreted as
an offset from the pointer value in FSR2 and not as a
literal address, For practical purposes, this means that
all instructions that use the Access RAM bit as an
argument - that is, all byte-oriented and bit-oriented
instructions, or almost half of the core PIC18 instructions
- may behave differently when the extended instruction
set is enabled.
25.2.3.1
Extended Instruction Syntax with
Standard PIC18 Commands
When the extended instruction set is enabled, the file
register argument, 'f, in the standard byte-oriented and
bit-oriented commands is replaced with the literal offset
value, 'k'. As already noted, this occurs only when 'f is
less than or equal to 5Fh. V\lhen an offset value is used,
As with
it must be indicated by square brackets ("[
the extended instructions, the use of brackets indicates
to the compiler that the value is to be interpreted as an
index or an offset. Omitting the brackets, or using a
value greater than 5Fh within brackets, will generate an
error in the MPASMTM Assembler.
n.
If the index argument is properly bracketed for Indexed
Uteral Offset Addressing, the Access RAM argument is
never specified; it will automatically be assumed to be
'0' This is in contrast to standard operation (extended
instruction set disabled) when 'a' is set on the basis of
the target address. Declaring the Access RAM bit in
this mode will also generate an error in the MPASM
Assembler.
The destination argument, 'd', functions as before.
In the latest versions of the MPASM assembler,
language support for the extended instruction set must
be explicitly invoked. This is done with either the
command line option, /y, or the PE directive in the
source listing,
When the content of FSR2 is OOh, the boundaries of the
Access RAM are essentially remapped to their original
values. This may be useful in creating backward
compatible code. If this technique is used, it may be
necessary to save the value of FSR2 and restore it
when moving back and forth between 'C' and assembly
routines in order to preselVe the Stack Pointer. Users
must also keep in mind the syntax requirements of the
extended instruction set (see Section 25.2.3.1
"Extended Instruction Syntax with Standard PIC18
Commands").
It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular,
users who are not writing code that uses a software
stack may not benefit from using the extensions to the
instruction set.
Although the Indexed Uteral Offset Addressing mode
can be very useful for dynamic stack and pointer
manipulation, it can also be very annoying if a simple
arithmetic operation is carried out on the wrong
register. Users who are accustomed to the PIC18
programming must keep in mind that, when the
extended instruction set is enabled, register addresses
of 5Fh or less are used for Indexed Literal Offset
Addressing.
Additionally, the Indexed Literal Offset Addressing
mode may create issues with legacy applications
written to the PIC18 assembler, This is because
instructions in the legacy code may attempt to address
registers in the Access Bank below 5Fh. Since these
addresses are interpreted as literal offsets to FSR2
when the instruction set extension is enabled, the
application may read or write to the wrong data
addresses.
Representaflve examples of typical byte-oriented and
bit-oriented instructions in the Indexed Uteral Offset
Addressing mode are provided on the following page to
show how execution is affected. The operand
conditions shown in the examples are applicable to all
instructions of these types.
DS39637A-page 408
804
25.2.4
CONSIDERATIONS WHEN
ENABLING THE EXTENDED
INSTRUCTION SET
When porting an application to the PIC18F2480/25801
4480/4580, it is very important to consider the type of
code A large, re-entrant application that is written in 'C'
and would benefit from efficient compilation will do well
when using the instruction set extensions. Legacy
applications that heavily use the Access Bank will most
likely not benefit from using the extended instruction
set
Preliminary
© 2004 Microchip Technology Inc.
PIC18F2480/2580/4480/4580
Bit Set Indexed
(Indexed LHeral Offset mode)
ADD W to Indexed
(Indexed LHeral Offset mode)
BSF
Syntax:
AOOWF
Syntax:
BSF [k], b
Operands:
0:;;; k:::.;95
dE [0,1]
a", 0
Operands:
0::;;; f:::.; 95
O:s:bs:7
Operation:
0N) + «FSR2) + k)
ADDWF
[k] {,d)
--J.
dest
Status Affected: N, OV, C, DC, Z
Encoding:
I
0010
Description:
INords:
DidO
I
kkkk
kkkk
I
a
=0
Operation:
1
-4
Status Affected:
None
Encoding:
I
The contents of Ware added to the contents
of the register indicated by FSR2, offset by the
Description:
value 'k'.
Words:
If 'd' is '0', the result is stored in W. If 'd' iS'l',
the result is stored back in register 'r (default).
Cycles:
«FSR2 + k»<b>
I bbbo I kkkk
1000
I
kkkk
Bit 'b' afthe register indicated by FSR2,
offset by the value 'k', is set.
1
Cycles:
Q Cycle Activity:
Q2
Q1
ADDWF
Q3
Q4
Before Instruction
FLAG OFST
FSR2Contents
[OFST} ,0
Before Instruction
W
OFST
FSR2
Contents
ofOA2Ch
After Instruction
W
Contents
ofOA2Ch
OAh
OAOOh
55h
ofOAOAh
17h
2Ch
After Instruction
Contents
OAOOh
ofOAOAh
OSh
20h
37h
20h
Set Indexed
(Indexed Literal Offset mode)
SETF
Syntax:
SETF [k]
Operands:
O:s;k:s;95
Operation:
FFh
Status Affected:
None
Encoding:
I
Description:
The contents ofthe register indicated by
-4
«FSR2) + k)
0110
I 1000 I
kkkk
I kkk' I
FSR2, offset by 'k', are setta FFh.
1
Words:
Cycles:
Q Cycle Activity:
I
Ql
Q2
Decode
Read 'k'
SETF
Before Instruction
OFST
FSR2
Contents
ofOA2Ch
After Instruction
Contents
ofOA2Ch
@
2004 Microchip Technology Inc.
APPENDIX H: DATA SHEETS
Preliminary
Q4
Q3
Process
\Nri1.
Data
register
[OFSTj
2Ch
OAOOh
OOh
FFh
0539637 A~page 409
805
PIC18F2480/2580/4480/4580
25.2.5
SPECIAL CONSIDERATIONS WITH
MICROCHIP MPLAB® IDE TOOLS
The latest versions of Microchip's software tools have
been designed to fully support the extended instruction
set of the PIC18F248012580/4480/4580 family of
devices. This includes the MPLAB C18 C compiler,
MPASM assembly language and MPLAB Integrated
Development Environment (IDE).
When selecting a target device for software development, MPLAB IDE will automatically set default configuration bits for that device. The default setting for the
XINST configuration bit is '0', disabling the extended
instruction set and Indexed Literal Offset Addressing
mode. For proper execution of applications developed
to take advantage of the extended instruction set,
To develop software for the extended instruction set,
the user must enable support for the instructions and
the Indexed Addressing mode in their language tool(s).
Depending on the environment being used, this may be
done in several ways:
A menu option, or dialog box within the
environment, that allows the user to configure the
language tool and its settings for the project
A command line option
A directive in the source code
These options vary between different compilers,
assemblers and development environments. Users are
encouraged to review the documentation accompanying their development systems for the appropriate
information.
XINST must be set during programming.
DS39637A-page 410
806
Preliminary
© 2004 Microchip Technology Inc.
INDEX
A
Accumulator.
SeeWREG
ADC
ADCONO register, 507
ADCONI register, 508
ADFM bit and data formatting,
block diagram,
506
conversion time,
510
features,
505
interrupt programming,
513
interrupt programming in C,
polling programming in C, 513
steps in polling programming,
ADC devices
analog input, 504
block diagram,
500
connection, 500
conversion signals, 504
501
conversion time,
data output, 502
parallel vs. serial, 502
reference voltage, 50 I
resolution, 501
Addition in the PIC 18,
156
Address bus, 14, 15
Addressing modes
bit addressing,
214
direct addressing mode,
195
immediate addressing mode,
register indirect addressing mode,
INDFx registers, 199,202
LFSR instruction, 199
look-up table in RAM, 212
PLUSWx registers,
202
POSTDECx registers,
202
POSTINCx registers,
202
PREINCx registers,
202
ROM addressing mode.
See Table processing
AND gate,
9
Arithmetic instructions
ADDLW,
41, 156,682
INDEX
509
514
511
194
199
ADDLWC, 157
49,156,683
ADDWF,
ADDWFC, 684
DAW,
159,696
DECF,
196, 698
DECFSNZ, 699
DECFSZ, 196, 699
INCF,
196,701
INCFSNZ, 702
INCFSZ,
701
MULLW,
163,706
MULWF,
707
NEGF,
707
SUBFWB, 162,713
SUBLW,
161,713
SUBWF,
714
SUBWFB, 162,715
ASCII, 7, 8
ASCII numbers,
184
ASCII table, 752
ASCII to packed BCD conversion, 186
ASCII to packed BCD conversion in C, 272
asm file,
70, 71
Assembler directives
DB (define byte), 205
EXTERN, 241
GLOBAL, 241
INCLUDE, 237
LIST,
313
LOCAL,
235
MACRO, 234
NOEXPAND/EXPAND, 237
Assemblers, 754-755
Assembly language, 67
70
assembling and linking,
negative values,
350
structure of, 68
B
Bank switching,
219
BSR register,
219
destination select bit, d ,
196, 222
MOVFF instructions,
223
RAM access bit, a, 219,221
BCD number systems,
158, 159
BCD addition and correction,
160
807
packed BCD,
158
unpacked BCD,
158
BCD to ASCII conversion, 230
Binary (hex) to ASCII conversion, 231
Binary (hex) to ASCII conversion in C, 276
Binary numbers,
2
addition,
6
representation,
3
Bit,
13
Bit instructions
BCF, 144,214,687
BSF, 143, 214, 690
146,214,690
BTFSC,
BTFSS,
146,214,691
BTG, 146,214,691
Branch instructions
BC, 687
BN, 687
105,688
BNC,
BNN,
688
689
BNOV,
BNZ,
100,689
BOV, 689
BRA,
108, 690
BTFSC,
690
BTFSS,
691
BZ, 104,692
calculating the short branch,
CPFSEQ, 695
CPFSGT, 696
CPFSLT,
696
DECFSNZ, 699
DECFSZ, 699
GOTO,
700
GOTO (long branch),
108
lNCFSZ,
701
lNFSNZ,
702
NOP,708
RESET,
709
SLEEP,
712
TSTFSZ,
717
Buffers,
733
Bus, 14
Byte, 13
808
107
c
C (carry flag), 58
C programming.
See Program the PIC 18 in C
Call instructions
and the role of the stack, 112
CALL,
110,692
RCALL,
115, 709
RETFIE,
709
RETLW,
710
RETURN, 710
Capture mode
block diagram,
580
measuring pulse period,
580
measuring pulse width,
582
programming,
581,583
programming in C, 581, 584
steps for programming,
579
CCP
Capture mode programming,
579
CCP and timers,
570
CCP pins, 572
CCP registers,
570
CCPlIF flag bit,
573
compare mode programming,
574
modules,
570
PWM programming,
586
T3CCP2:T3CCP1 bits,
573
Checksum subroutine, 227
Checksum subroutine in C, 274
Compare instructions
CPFSEQ, 175
CPFSGT,
174
CPFSLT,
176
Compare mode
block diagram,
575
programming,
576, 577
programming in C, 576
steps for programming,
575
Complement instructions
BTG, 146
COMF,
54, 174
NEGF,
174
Control bus, 14
Conversion
binary to decimal, 3
binary to hex,
4
decimal to binary,
decimal to hex,
hex to binary,
hex to decimal,
CPU, 14, 15
Crosstalk,
742
Currents,
739
dynamic,
739
static,
739
2
4
4
5
o
DAC interfacing
converting output to voltage,
517
generating a sine wave,
517
MC1408 and DAC0808, 516
operation, 516
programming,
519
programming in C, 520
Daisy chain, 723
Data bus,
14
Data in the PIC
data type, 61
representation,
61
DC (digital carry flag),
58
DC motor interfacing
bidirectional control,
652
H-bridge control, 653, 654
operation, 651
programmmg,
655
unidirectional control,
652
using ECCP
665
bidirectional control,
connection to PIC 18,
666
programming,
668
programming in C,
668
using optoisolator, 657
connection to PICI8,
658
programming,
659
programming in C,
660,661,662
using PWM, 657
connection to PIC 18,
663
programming,
663
programming in C,
664
using the L293,
655
connection to PIC 18,
656
programming,
656
INDEX
Decoders,
12
Decrement instructions
DECF,
54
DECFSZ, 98
Division in the PIC18,
application for,
164
OS 1306 RTC interfacing
I-Hz pin programming,
address map, 611
alarm mask bits,
625
alarm programming, 626
alarm programming in C,
alarms and interrupts,
block diagram,
610
connection to PIC 18,
importance of WP-bit,
pins, 608
programmmg,
616
programming in C, 619
serial mode selection,
time and date,
611
163
622
628
622,623
612,614
610
610
E
ECCP
capture mode programming,
compare mode programming,
ECCP and timers, 594
ECCP pins, 592, 665
ECCP registers,
593, 594
ECCPIIF flag bit, 594
modules,
570
programmmg,
668
programming in C, 668
PWM programming,
597
ECCP Capture mode
programmmg,
596
programming in C, 596
steps for programming,
595
ECCP Compare mode
programming,
595
programming in C, 595
steps for programming,
594
ECCPPWM
steps for programming,
597
EEPROM data memory
between Flash programming,
595
595
559
809
between Flash programming in C, 562
programming in C, 561
read programming, 557
size, 555
write programming, 556
F
Fan-out,
732, 734, 738
File instructions
ADDWF, 49, 156, 683
ADDWFC, 684
ANDWF,
171,685
CLRF,
694
COMF,
54,174,694
CPFSEQ,
175,695
CPFSGT,
174,696
CPFSLT,
176,696
DECF,
54,196,698
DECFSNZ, 699
DECFSZ, 196,699
INCF,
196,701
INCFSNZ, 702
701
INCFSZ,
10RWF,
171,703
MOVF,
55
56,223,705
MOVFF,
MOVWF, 48, 706
MULWF,
707
NEGF,
174,707
RLCF,
180,710
RLNCF,
179, 711
RRCF,
180,711
RRNCF,
179,711
SETF,
712
SUBFWB, 162,713
SUBWF,
714
SUBWFB, 162,715
SWAPF,
183,716
TSTFSZ,
717
XORWF,
172,718
File register
access bank, 46
general purpose registers, 44
memory allocation, 43
special function registers, 43
vs. EEPROM,
44
810
Flash program memory,
539
between RAM programming,
546
boundaries, 542
EECON I register, 541
EECON2 register, 542
erase programming, 548, 549
erase programming in C, 552, 553
read programming, 545
read programming in C,
551
write programming, 544, 545
write programming in C, 551, 553
writing data to Flash,
540, 542
Flip-flops,
12
Flowcharts, 746
G
Gigabyte,
13
Ground bounce,
740
H
Harvard architecture in PIC, 79
Hex file,
316
Hexadecimal numbers,
4
addition,
7
subtraction, 7
I/O in the PIC 18
bit -addressabiJity, 143
ports in the PIC 18 family,
programming ports, 130
RAW (Read-After-Write),
reading PORTx vs. LATx,
role of TRISx registers,
status upon reset, 141
I/O ports
reading input pin, 735
writing to the ports, 736
IC technology, 726-731
Idle mode,
740
Instruction syntax
destination select bit, d ,
RAM access bit, a, 219
Instructions
131
140
151
131,134
196
bit instructions.
See also Bit instructions
examples, 676
syntax,
674
byte-oriented instructions.
See also File instructions
examples, 679
syntax,
678
control instructions.
See Branch instructions &
Call instructions
instructions using a literal value.
See also Literal instructions
examples, 677
syntax,
677
16-bit format,
675
syntax,
681
table read and write instructions.
See also Table processing
syntax,
680
INTCON register
OlE bit,
427
OlEH and GIEL bits,
456
INTOIE bit, 439
INTOIF flag bit,
439
PEIE bit,
427
RBIE bit, 449
RBIF flag bit,
449
TMROIE bit, 429
TMROIF flag bit, 338, 429
INTCON3 register
INTlIE bit, 439
INTI IF flag bit,
439
INT2IE bit, 439
INT2 IF flag bit,
439
Interrupts
C programming,
435
enabling and disabling,
426
executing an interrupt,
425
fast context saving, 466
INTCON register, 427
interrupt inside an interrupt,
465
interrupt latency,
466
interrupt service routine (ISR),
424
interrupt vector table,
425
INTx interrupt programming,
439
negative edge-triggered, 442
INDEX
sampling, 444
PORTB-change interrupt programming, 449
priorities, 454, 456
software interrupts, 467
sources of interrupts,
425
associated registers,
455
timer interrupt programming, 429, 435, 463
USART interrupt programming, 445, 463
vs. polling, 424
Inverter,
10
Inverters,
727, 728
IPR I register
RCIP bit,
455
TMRlIP bit, 455
TMR2IP bit, 455
TXIP bit,
455
K
Keyboard interfacing
connection to PICI8,
debounce, 490
determining a key press,
determining a key press in
flow chart, 489,495
interrupt key detection,
scanning key detection,
Kilobyte,
13
487,488
490
C,
492
487
494
L
LCD interfacing
addressing display RAM, 480
C programming,
483
command codes,
475,481
data sheet, 480
operation, 474
pin descriptions,
474
sending data using table processing, 482
sending data with busy flag,
477
sending data with time delay,
476
signal timing diagrams,
479
vendors,
482
Linking,
71
Literal instructions
ADDLW,
682
IORLW,
702
811
LFSR,
704
MOVF,
704
705
MOVLB,
MOVLW, 705
SUBLW,
713
XORLW,
718
Logic instructions
ANDLW,
171,685
ANDWF,
171,685
CLRF,
694
CLRWDT, 694
COMF,
694
IORLW,
171,702
IORWF,
171,703
RLCF,
710
RLNCF,
711
RRCF,
711
RRNCF,
711
SETF,
712
XORLW,
172,718
XORWF,
172,718
Loop instructions
BTFSC,
214
BTFSS,
214
DECFSZ, 196
Looping in the PIC 18
BNZ,
100
BTFSC,
146
BTFSS,
146
DECFSZ, 98
1st file, 70, 72
M
Macros,
234
INCLUDE directive,
237
LOCAL directive, 235
MACRO definition, 234
macros vs. subroutines,
240
NOEXPAND/EXPAND directives, 237
MAX232,
395
MAX233,
396
Megabyte,
13
Microcontroller,
24
choosing a microcontroller, 26
for embedded systems,
25
mechatronics and microcontrollers, 27
812
other microcontrollers,
34
versus mICroprocessor,
24
24
Microprocessor,
embedded applications,
25
pipe lining, 117
Modules,
240
EXTERN directive, 241
GLOBAL directive, 241
linking modules together, 243
writing modules,
240
MOVE instructions
MOVF,
55, 704
MOVFF,
56, 705
MOVLB, 705
MOVLW, 41,705
MOVWF, 48, 706
MPLAB simulator, 87,223
MSSP,612
RTC programming, 616
RTC programming in C, 619
setting the date of RTC,
615
setting time of RTC, 614
SSPCONI register, 613
SSPSTAT register, 613
Multiplication in the PICI8, 163
Multistage execution in the PICI8,
N
N (negative flag),
NAND gate, 10
Nested loop, 102
for delay,
121
Nibble, 13
NOR gate,
10
58
o
obj file,
70
One's complement, 7
Open collectors,
731
Open drain gates,
731
Optoisolator interfacing,
connection to PICI8,
DC motor control, 657
packages, 641
OR gate,
9
640
641
123
OV (overflow flag), 58
in signed number operations,
168
p
Packed BCD to ASCII conversion, 185
Packed BCD to ASCII conversion in C, 272
PIC Assembler
file types, 71
rules for labels,
66
PIC microcontroller, 28
addressing modes, 194
bank switching,
219
brief history, 28
features,
29
data RAM and EEPROM,
33
1/0,
34
peripherals,
34
program memory, 32
PIC trainer, 34
PIC 18F458/452
configuration registers,
background debugger,
brown-out detection,
C programming, 315
clock source,
305
CONFIG directive,
power-up timer, 309
RB5 and PGM pin,
stack overflow, 311
watchdog timer, 310
pin connections,
300
ports,
303
reset state, 30 I
trainer,
325
PICkit 2 and testing,
troubleshooting tips,
PICkit 2 programmer, 327
test program in Assembly,
test program in C, 329
PIE I register
ADIE bit, 513
RCIE bit, 445
TXIE bit, 445
PIR I register
ADIF flag bit,
513
CCPlIF flag bit,
573
INDEX
304
311
308
308
311
327
330
328
RCIF flag bit,
401
TMRlIF flag bit, 353,429
TMR2lF flag bit, 373,429
TMR31F flag bit, 377
TXIF flag bit,
401
P1R2 register
ECCPlIF flag bit, 594
P1R3 register
TMR3 IF flag bit, 429
Port A, 135
alternate functions, 137
Port B, 136
alternate functions, 137
Port C, 137
alternate functions, 139
Port D, 138
alternate functions, 139
Port E, 139
Power dissipation,
739
Program counter in the PI C, 73
and the memory map,
73
upon applying power,
75
while executing a program, 77
Program ROM
executing from,
77
placing code in,
75
width in the PIC 18, 77
Program the PICI8 in C
ADC,
513,514
capture mode,
581,584
compare mode,
576
configuration registers,
315
DAC,
520
data conversion,
271
data RAM allocation,
286
#pragma directive,
289
overlay storage class,
291
data serialization, 277
data types, 252
long,
256
short long, 256
signed char,
255
signed int, 256
unsigned char,
253
unsigned int,
255
DC motor, 660
DC motor with ECCP,
668
813
DC motor with PWM,
ECCP compare,
595
EEPROM, 561
Flash,
551
1/0 programming, 259
bit-addressable I/O,
byte size I/O,
259
interrupts, 435
keyboard, 492
LCD,
483
logic operations,
267
program ROM allocation,
near and far code, 282
pragma directive, 283
RTC,619
RTC alarms, 628
sensors,
524
time delay, 257
TimerO and Timer!, 362
as counters,
368
USART,
414
Pseudocode, 746
PWM
block diagram,
591
duty cycle, 586,588,591
period,
586
programmmg,
590
programming in C, 590
steps for programming,
timing diagram,
591
664
261
S
280
589
R
RAM, 13,15
RCON register
IPEN bit,
455
Reed switch, 640
Relay interfacing
driving a relay,
638
electromechanical relays,
motor control,
637
programmmg,
638
solid-state relays, 639
RISC architecture
features,
84
in PIC,
84
ROM, 13,15
814
Rotate instructions
RLCF,
180
RLNCF,
179
RRCF,
180
RRNCF,
179
636
Semiconductor memory
capacity,
530
DRAM,
537
organization,
538
packaging issues, 537
EEPROM, 534
EPROM,
532
Flash,
534
Mask ROM, 535
NV-RAM, 536
organization, 530
PROM,
532
RAM,
535
ROM,
532
speed,
531
SRAM,
535
UV-EPROM,
532
Sensor interfacing
connection to PIC 18,
523
LM34 and LM35, 521
programming,
524
programming in C, 524
signal conditioning, 522
temperature sensors, 521
Serial communication
asynchronous,
389,390
COM ports, 394
data framing,
390
DTE and DCE classifications,
handshaking signals,
392
PIC 18 support.
See USART
RS232 standards, 391
simplex and duplex, 389
synchronous,
389
transfer rate, 391
vs. parallel communications,
Serializing data,
181
Signed numbers,
166
392
388
overflow problem, 168
Source file, 71
Special Function Registers, 197
SPI communications
SPI bus,
604
steps for reading
multiple bytes,
607
single byte,
606
steps for writing
multiple bytes,
605
single byte,
605
vs. parallel communications,
604
Stack in the PIC 18, 110
upper limit, 114
using memory banks,
233
Stack instructions
POP, 111, 708
PUSH,
III, 708
STATUS register,
57
bit addressing,
217
58
carry flag (C),
digital carry flag (DC),
58
for decision making,
60
impact of instructions on, 58, 60
negative flag (N), 58
overflow flag (OY), 58
zero flag (Z),
58
Stepper motor interfacing
4-step sequence,
643
8-step sequence,
646
calculating steps per second,
645
connection to PICI8,
645
holding torque,
646
interfacing with optoisolator,
649
motor speed, 646
operation, 642
programming,
644, 649
programming in C, 650
step angle, 643
steps per rotor tooth,
645
unipolar vs. bipolar, 647
using transistors as drivers, 647
wave drive sequence,
646
Structured programming,
747
Subtraction in the PICI8,
161
role of C and N,
163
INDEX
T
Table processing,
205
look-up table and RETLW instruction, 209
TABLAT register, 206
TBLPTR register, 206
TBLRD*, 716
TBLRD*-, 206,716
TBLRD* instruction,
206
TBLRD*+, 716
TBLRD*+ instruction,
206
TBLRD+*, 716
TBLRD+* instruction,
206
TBLWRT instruction,
213
TBLWT*, 717
TBLWT*-, 717
TBLWT*+, 717
TBLWT+*, 717
Terabyte,
13
Time delay
branch penalty,
118
calculation for PIC 18,
117, 120
instruction cycle time,
118
programming in C, 257
using nested loops, 121
Timer registers,
336
TimerO
16-bit programming,
339
delay calculations, 342
finding register values, 343, 345
prescaler and long time delay,
346
8-bit programming, 348
as a counter, 355
block diagram,
339
C programming,
362
as a counter,
368
interrupt programming,
430, 460
interrupt programming in C,
435, 463
TOCON register,
336
TOCS and clock source,
337
TOCS bit, 355
TMROIF flag,
338
Timer!
and compare mode, 577
block diagram,
352
C programming,
362
as a counter,
368
815
interrupt programming,
432, 460
interrupt programming in C, 435, 463
TI CON register,
353
TMRllF flag,
353
using an external crystal, 357
Timer2
and PWM, 589
block diagram,
373
T2CON Register, 374
TMR2IF flag,
373
Timer3,
376
and compare mode, 573
block diagram,
378
T3CON register, 377
TMR3IF flag,
377
Transient current,
741
Transistors, 726, 727
Transmission line ringing,
742
9, 734
Tri-state buffer,
TTL technology,
729, 730
Two's complement, 7
u
USART
baud rate error calculation, 408
block diagram,
413
C programming,
414
connecting to MAX232,
395
connecting to MAX233,
396
duplex programming,
412
interrupt programming,
446
interrupt programming in C, 447, 463
PIRI register,
402
quadrupling the baud rate, 405
RCIF flag, 401,404,445
RCREG register,
399
RCSTA register,
400
receiver programming,
404
RX and TX pins, 395
SPBRG register and baud rate,
397
transmitter programming, 402
TXIF flag, 40 I, 403, 445
TXREG register,
399
TXSTA register,
399
816
w-z
Wire wrapping,
722
Word, 13
WREG (working register),
WREG instructions
ADDLW,
41,156,682
ADDLWC, 157
ADDWF, 49,156,683
ADDWFC, 684
ANDLW,
171,685
ANDWF,
171,685
DAW,
696
IORLW,
702
IORWF,
171,703
MOVLW, 55,705
MOVWF, 48, 706
MULLW,
163,706
MULWF,
707
ORLW,
171
SUBFWB, 162
SUBLW,
161,713
SUBWF,
713
SUBWFB, 162,715
XORLW,
172,718
XORWF,
172,718
XOR gate,
10
Z (zero flag), 58
40
Muhammad Irfan