JAIN UNIVERSITY Declared as Deemed-to-be Univ ersity u/s 3 of the UGC Act 1956 4TH SEMESTER HDL LABORATORY MANUAL 12ECL47 Department of Electronics and Communication Engineering School of Engineering & Technology Jain Global campus, Kanakapura Taluk, Ramanagar District -562112 Karnataka, INDIA 2017-2018  HDL LAB MANUAL 2017-18 Course Description This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable test bench. Structural, Register Transfer Level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the Advanced VLSI course. Digital Logic Design Using Verilog: This course prepares students to implement Verilog modeling of digital logic. Students learn Verilog constructs and hardware modeling techniques. The course covers Verilog language elements and data types. Students tackle key challenges and learn structural, dataflow and behavioral modeling in Verilog, including common constructs and coding considerations. Instruction in the coding and testing of digital logic includes examples of combinational circuits (gates, mux/demux, encoders/decoders, and Boolean expression), sequential circuits (latches, flip-flops, shift registers, counters, RAMs and ROMs), and complex logic (flavors of ALU and FSM) Designing Xilinx FPGAs: This course is a practical introduction to programmable logic designs with Xilinx FPGAs Using several examples and design techniques, students will be taken through a complete PLD design. Upon completion of the course, students should be able to complete a design with Xilinx FPGAs, and understand the design and timing reports. Topics include a logic design process review, design software, Xilinx CPLDs and FPGAs architecture, design techniques and optimizing. Lab Descriptions The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. You will write, synthesize, simulate, and  ECE Dept. SET-JU Page 2 HDL LAB MANUAL 2017-18 implement all the labs. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. Course Objectives Upon completion of this course, students will be able to: Understand VHDL syntax and coding styles relevant to logic design Write VHDL RTL hardware designs using good coding practices Understand the synthesizable subset of VHDL Understand problematic issues in coding hardware Use types, overloading, and conversion functions from standard VHDL packages (std_logic_1164, numeric_std, and std_logic_arith) Write simple transaction-based testbenches using subprograms Use your VHDL simulation and synthesis tools Introduction to Field Programmable Gate Arrays (FPGAs) A FPGA is a Field Programmable Gate Array; basically an array of generic gates to perform any logic function. Many FPGAs simply use small blocks of memory, called CLBs (Combinational Logic Blocks), to look up the answer to equations of 4 or 5 variables. In the past, AND and OR gates would be interconnected to solve equations; but this has been replaced with CLB's as they are more flexible and can be used as memory blocks. As not all equations have as little as 4 variables; typical designs will be spread over several CLBs; requiring signals to be routed between the CLBs. Just how much circuitry there is, and how fast it will run, in a particular FPGA, depends upon the speed of CLBs, the amount of resources for routing signals between CLBs, and how well a design can be "laid out" or optimized. Newer FPGAs are tailored for specific circuits. The Cyclone II FPGA, which is in our  ECE Dept. SET-JU Page 3 HDL LAB MANUAL 2017-18 labs, has hardware multipliers and adders, which run at 250MHz, allowing ultra signal processing circuits to be built. Configurable interconnects are provided between the chip resources (CLBs, hardware multipliers and memory blocks for the Cyclone II FPGA). The logic, circuitry, and interconnects in the architecture are configured by uploading a programming file to the FPGA chip. This property makes the FPGA chip very flexible since it is able to realize different digital circuits by uploading a different programming file. FPGAs are different that microprocessors or microcontrollers because the designer is able to change the hardware realized by the chip by programming it. Since hardware is always faster than software FPGAs allow hardware to be built with nearly the speed of software development. FPGA design steps Writing an HDL description ("design entry"). HDL is a class of high-level languages which is used to define how the device should work. It can be thought about as a programming language, though significantly different from the conventional programming languages. The most frequently used hardware description languages are VHDL and Verilog. Writing a test environment. It is almost impossible to create a fully correct HDL design at once. Therefore, it should be tested for possible errors. Whereas in the area of software development a program can be tested by simply running it, testing FPGA design involves writing a dedicated test environment. Test environment can be written in HDL (VHDL/Verilog), or in SystemC (SystemC is a special class library for C++ with the support for hardware signal simulation). A test environment usually includes a behavioral model, which is a higher-level, non-synthesizable device description used to verify HDL design correctness. Behavioral simulation is used to verify the HDL description against the corresponding behavioral model (using test environment). Most design errors are fixed at this stage. Synthesis is an automated process of converting a high-level HDL description to a machine-readable circuit description (a so-called netlist). Although synthesis of a  ECE Dept. SET-JU Page 4 HDL LAB MANUAL 2017-18 correctly written HDL code shouldn't be a problem, some errors uncaught by behavioral simulation can appear at this stage. Implementation is a process of converting netlist to an FPGA configuration bit stream (tailored for specific FPGA device). Post-implementation simulation is used to verify the implemented design (taking switching and propagation delays into account) against the behavioral model. This step can be omitted for simple designs. Testing a produced bit stream in hardware. FPGA design is impossible without specialized vendor-specific EDA (electronic design automation) tools: Xilinx ISE (Integrated Software Environment) for Xilinx FPGAs, Quartus II for Altera devices, Libero for Actel devices. Tool Overview Xilinx ISE (Integrated Software Environment) The ISE® design flow comprises the following steps: design entry, design synthesis, design implementation, and Xilinx® device programming. Design verification, which includes both functional verification and timing verification, takes places at different points during the design flow. FPGA Design Flow Overview  ECE Dept. SET-JU Page 5 HDL LAB MANUAL 2017-18 1. Design Entry: allows the designer to enter a hardware design specification using: Hardware Description Language: such as VHDL or Verilog (we use VHDL) Schematic Entry: by connecting blocks of ranging complexity. It can be used to interconnect simple components such as simple logic gates, or to interconnect previously created hardware modules. Procedure: Create an ISE project as follows: Create a project. Create files and add them to your project, including a user constraints (UCF) file. Add any existing files to your project. Assign constraints such as timing constraints, pin assignments, and area constraints.  ECE Dept. SET-JU Page 6 HDL LAB MANUAL 2017-18 2. Functional Verification Circuit/Design Simulation: In order for a designer to verify the functionality of their design simulation is required. The simulation step ensures that the circuit operates in the expected manner. A simulator is fed with the design description files and waveforms describing the input values against time to the circuit under test. The simulator then produces the logic values that will appear on the circuit outputs as waveforms also against time. You can verify the functionality of your design at different points in the design flow as follows: Before synthesis, run behavioral simulation (also known as RTL simulation). After Translate, run functional simulation (also known as gate-level simulation), using the SIMPRIM library. After device programming, run in-circuit verification. 3. Design Synthesis You can synthesize your design once design files have been created. The synthesis process will check code syntax and analyze the hierarchy of your design which ensures that your design is optimized for the design architecture you have selected. The resulting netlist is saved to an NGC  ECE Dept. SET-JU Page 7 HDL LAB MANUAL 2017-18 file (for Xilinx® Synthesis Technology (XST)) or an EDIF file (for Precision, or Synplify/Synplify Pro). The synthesis process can be used with the following synthesis technology tools. Select one of the following for information about running your synthesis tool: Xilinx Synthesis Technology (XST) Precision from Mentor Graphics Inc. Synplify and Synplify Pro from Synplicity Inc. 4. Design Implementation Implement your design as follows: Implement your design, which includes the following steps: o Translate o Map Place and Route Review reports generated by the Implement Design process, such as the Map Report or Place & Route Report, and change any of the following to improve your design: Process properties o Constraints Source files Synthesize and implement your design again until design requirements are met. Timing Verification Timing Analysis: It gives an accurate indication of how fast the circuit runs, and if speed and timing constraints can be met. Electronic circuits always have speed requirements to be met and being able to ballpark how fast a design works without having to build and measure it greatly speeds up design time.  ECE Dept. SET-JU Page 8 HDL LAB MANUAL 2017-18 You can verify the timing of your design at different points in the design flow as follows: Run static timing analysis at the following points in the design flow: o After Map o After Place & Route Run timing simulation at the following points in the design flow: o After Map (for a partial timing analysis of CLB and IOB delays) After Place and Route (for full timing analysis of block and net delays) Xilinx Device Programming Programming the FPGA: In this step the programming file is uploaded to the FPGA chip to realize the design. The circuit can be physically tested afterwards by applying inputs and observing outputs Program your Xilinx device as follows: Create a programming file (BIT) to program your FPGA. Generate a PROM or ACE file for debugging or to download to your device. Optionally, create a JTAG file. Use iMPACT to program the device with a programming cable. DIFFERENT SIMULATORS AND SYNTHESIS USED IN DIGITAL DESIGN Simulators: Simulator Company Language ModelSim Mentor Graphics VHDL-2002, V2001, SV2005 ISE Simulator Xilinx VHDL-93, V2001 VCS Synopsys VHDL-2002, V2001, SV2005 Quartus II Simulator Altera VHDL-1993, V2001, SV2005 Verilog-XL Cadence V1995 Verilogger Synapticad V2001,V1995 Silos Simucad Design Automation V1995 Synthesis Tool: Company Tool Cadence RTL Compiler Synopsys Design Compiler Xilinx Synplicity Synplify  ECE Dept. SET-JU Page 9 HDL LAB MANUAL 2017-18 Outcome: Skills Gained from Course After completing this Course, Student will know how to: Implement the VHDL/Verilog portion of coding for synthesis o Identify the differences between behavioral and structural coding styles o Distinguish coding for synthesis versus coding for simulation o Use scalar and composite data types to represent information o Use concurrent and sequential control structure to regulate information flow o Implement common VHDL constructs (Finite State Machines [FSMs], RAM/ROM data structures) Simulate a basic VHDL design o Write a VHDL test bench and identify simulation-only constructs Identify and implement coding best practices o Optimize VHDL code to target specific silicon resources within the Xilinx FPGA Create and manage designs within the ISE software environment Learn VHSIC Hardware Description Language (VHDL) Synthesis of Digital Hardware Modeling of Complex Digital Systems Test bench Development Learn about FPGA design concepts and practices and how VHDL can be applied  ECE Dept. SET-JU Page 10 HDL LAB MANUAL 2017-18 Hardware- overview SPARTAN -3 FPGA from XILINX  ECE Dept. SET-JU Page 11 HDL LAB MANUAL 2017-18 Xilinx Spartan Implementation Configurable Logic Blocks are connected by programmable interconnect, configuration of which is controlled by SRAM It is unlimited reprogram ability  ECE Dept. SET-JU Page 12 JAIN UNIVERSITY Declared as Deemed-to-be Univ ersity u/s 3 of the UGC Act 1956 School of Engineering and Technology DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING SIXTH SEMESTER (Batch-1) HDL Laboratory (ECL-68) SI Title of experiment Sub Group O=10 P =20 R=10 DOE DOS SIGN NO P CYCLE -1 EXPERIMENTS AND NAND WEEK-1 1. Basic gates OR NOR XOR XNOR ALL gates 2. Multiplexer 2:1 MUX 4:1 MUX WEEK-2 8:1 MUX 3. De Multiplexer 1:2 DEMUX 1:4 DEMUX 1:8 DEMUX 4. Encoder Without Priority 8:3 4:2 WEEK-3 5. Encoder With Priority 8:3 4:2 6. Decoder 3:8 2:4 WEEK-4 7. Binary to Gray conversion 4 bit 8. Gray to Binary conversion 4 bit 9. Comparator 1 bit 4 bit WEEK-5 10. ALU 8 Bit 32 Bit 11. Adder Half Adder Full Adder WEEK-6 Half 12. Subtractor Subtractor Full Subtractor 13. WEEK-7 Lab Test 1  CYCLE -2 EXPERIMENTS D Flip Flop 14. Flip Flop T Flip Flop SR Flip Flop JK Flip Flop BCD 15. U/Down Counter Counter WEEK9 Binary Up/Down Counter CYCLE -3 EXPERIMENTS --Hardware Interfacing Experiments Sine Generation of different Waveform 16. Square WEEK-10 waveforms using DAC waveform Triangular Waveform 17. 16X2 LCD interface Stepper Motor speed and direction Control WEEK-11 18. Control external lights using relays 19. LAB TEST 2 WEEK-12 REVISION WEEK-13 GRAND TOTAL AVERAGE  JAIN UNIVERSITY Declared as Deemed-to-be Univ ersity u/s 3 of the UGC Act 1956 School of Engineering and Technology DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING SIXTH SEMESTER (Batch-2) HDL Laboratory (ECL-68) SI Title of experiment Sub Group O P R DOE DOS SIGN NO =10 =20 =10 CYCLE -1 EXPERIMENTS AND NAND OR WEEK-1 1. Basic gates NOR XOR XNOR ALL gates 2. Multiplexer 2:1 MUX 4:1 MUX WEEK-2 8:1 MUX 3. De Multiplexer 1:2 DEMUX 1:4 DEMUX 1:8 DEMUX 4. Encoder Without Priority 8:3 4:2 WEEK-3 5. Encoder With Priority 8:3 4:2 6. Decoder 3:8 2:4 WEEK-4 7. Binary to Gray conversion 4 bit 8. Gray to Binary conversion 4 bit 9. Comparator 1 bit 4 bit WEEK-5 10. ALU 8 Bit 32 Bit 11. Adder Half Adder Full Adder WEEK-6 12. Subtractor Half Subtractor Full Subtractor 13. WEEK-7 Lab Test 1  CYCLE -2 EXPERIMENTS D Flip Flop 14. Flip Flop T Flip Flop WEEK-8 SR Flip Flop JK Flip Flop BCD 15. U/Down Counter WEEK9 Counter Binary Up/Down Counter CYCLE -3 EXPERIMENTS --Hardware Interfacing Experiments Generation of different Sine Waveform WEEK-10 16. Square waveform waveforms using DAC Triangular Waveform 16X2 LCD INTERFACE 17. WEEK-11 Stepper Motor speed and direction control 18. Control external lights using relays 19. LAB TEST 2 WEEK-12 REVISION WEEK-13 GRAND TOTAL AVERAGE  HDL LAB MANUAL 2017-18 Cycle-1 Experiments- Combinational Circuits  ECE Dept. SET-JU Page 15 HDL LAB MANUAL 2017-18 Logic gates Write HDL code to implement all Logic gates and verify. AIM: To design all the logic gates using dataflow modeling style and verify the functionalities along with their synthesis and simulation results. Design and Circuit diagram: Truth Table: INPUT OUTPUT A B y_not y_or y_and y_nor y_nand y_xor y_xnor 0 0 1 0 0 1 1 0 1 0 1 1 1 0 0 1 1 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 0 0 1 Output Expression y_not y_or A+B y_and AB y_nor + y_nand y_xor + y_xnor +AB NOT GATE VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity not1_gate is Port ( A : in STD_LOGIC;  ECE Dept. SET-JU Page 16 HDL LAB MANUAL 2017-18 Y : out STD_LOGIC); end not1_gate; architecture Behavioral of not1_gate is begin Y<= not A; end Behavioral; SYNTHESIS RESULTS: SIMULATION RESULTS: INPUT Test bench waveform: Output Waveform: AND GATE VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ANDD_GATE1 is Port ( A : in STD_LOGIC;  ECE Dept. SET-JU Page 17 HDL LAB MANUAL 2017-18 B : in STD_LOGIC; Y : out STD_LOGIC); end ANDD_GATE1; architecture Behavioral of ANDD_GATE1 is begin Y<= A and b; end Behavioral; SYNTHESIS RESULTS: SIMULATION RESULTS: INPUT Test bench waveform: Output Waveform: OR GATE  ECE Dept. SET-JU Page 18 HDL LAB MANUAL 2017-18 VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity or1_gate is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC); end or1_gate; architecture Behavioral of or1_gate is begin Y<= A or B; end Behavioral; SYNTHESIS RESULTS: SIMULATION RESULTS: INPUT Test bench waveform: Output Waveform:  ECE Dept. SET-JU Page 19 HDL LAB MANUAL 2017-18 NAND GATE VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nand_gate1 is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC); end nand_gate1; architecture Behavioral of nand_gate1 is begin Y<= A nand B; end Behavioral; SYNTHESIS RESULTS: SIMULATION RESULTS: INPUT Test bench waveform:  ECE Dept. SET-JU Page 20 HDL LAB MANUAL 2017-18 Output Waveform: N0R GATE VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity nor1_gate is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC); end nor1_gate; architecture Behavioral of nor1_gate is begin Y<= A nor B; end Behavioral; SYNTHESIS RESULTS: SIMULATION RESULTS:  ECE Dept. SET-JU Page 21 HDL LAB MANUAL 2017-18 INPUT Test bench waveform: Output Waveform: XOR GATE VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity XOR1_GATE is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC); end XOR1_GATE; architecture Behavioral of XOR1_GATE is begin Y<= A xor B;  ECE Dept. SET-JU Page 22 HDL LAB MANUAL 2017-18 end Behavioral; SYNTHESIS RESULTS: SIMULATION RESULTS: INPUT Test bench waveform: Output Waveform: XNOR GATE VHDL Code: library IEEE; ECE Dept. SET-JU Page 23  HDL LAB MANUAL 2017-18 use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity XNOR1_GATE is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Y : out STD_LOGIC); end XNOR1_GATE; architecture Behavioral of XNOR1_GATE is begin Y<= A xnor B; end Behavioral; SYNTHESIS RESULTS: SIMULATION RESULTS: INPUT Test bench waveform: Output Waveform:  ECE Dept. SET-JU Page 24 HDL LAB MANUAL 2017-18 All Logic gate VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity all_gates is Port ( A,B : in std_logic; y_not : out std_logic; y_or : out std_logic; y_and : out std_logic; y_nor : out std_logic; y_nand : out std_logic; y_xor : out std_logic; y_xnor : out std_logic); end all_gates; architecture Behavioral of all_gates is begin y_not <= not A; y_or <= A or B; y_and <= A and B; y_nor <= A nor B; y_nand <= A nand B; y_xor <= A xor B; y_xnor <= A xnor B; end Behavioral;  ECE Dept. SET-JU Page 25 HDL LAB MANUAL 2017-18 SYNTHESIS RESULTS: SIMULATION RESULTS: INPUT Test bench waveform:  ECE Dept. SET-JU Page 26 HDL LAB MANUAL 2017-18 Output Waveform: CONCLUSION/RESULT: Basic logic gates NOT, AND, OR, NOR, NAND, XOR, XNOR are designed in dataflow model and outputs are verified. 2. Multiplexer Write HDL code to implement 8:1Multiplexer and verify. AIM: To design a 8:1 multiplexer using behavioral model and verify its functionality using the test bench. Truth Table: INPUT OUTPUT SEL2 SEL1 SEL0 MUX_OUT 0 0 0 A 0 0 1 B 0 1 0 C 0 1 1 D 1 0 0 E 1 0 1 F 1 1 0 G 1 1 1 H  ECE Dept. SET-JU Page 27 HDL LAB MANUAL 2017-18 VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Mux8_1 is port ( SEL: in STD_LOGIC_VECTOR(2 downto 0); A,B,C,D,E,F,G,H :in STD_LOGIC; MUX_OUT: out STD_LOGIC); end Mux8_1; architecture behavioural of Mux8_1 is begin process (SEL,A,B,C,D,E,F,G,H) begin case SEL is when "000" => MUX_OUT <= A; when "001" => MUX_OUT <= B; when "010" => MUX_OUT <= C; when "011" => MUX_OUT <= D; when "100" => MUX_OUT <= E; when "101" => MUX_OUT <= F; when "110" => MUX_OUT <= G; when "111" => MUX_OUT <= H; when others => null; end case; end process; end behavioural; SYNTHESIS RESULTS:  ECE Dept. SET-JU Page 28 HDL LAB MANUAL 2017-18 SIMULATION RESULTS: INPUT Test bench waveform: Output Waveform:  ECE Dept. SET-JU Page 29 HDL LAB MANUAL 2017-18 3. De Multiplexer Write HDL code to implement 1:8 De-Multiplexers. AIM: To design a 1:8 De-Multiplexer and verify its functionality and check its simulation report. Truth Table: INPUT OUTPUT Enable S2 S1 S0 Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] 1 X X X 0 0 0 0 0 0 0 0 0 0 0 0 din 0 0 0 0 0 0 0 0 0 0 1 0 din 0 0 0 0 0 0 0 0 1 0 0 0 din 0 0 0 0 0 0 0 1 1 0 0 0 din 0 0 0 0 0 1 0 0 0 0 0 0 din 0 0 0 0 1 0 1 0 0 0 0 0 din 0 0 0 1 1 0 0 0 0 0 0 0 din 0 0 1 1 1 0 0 0 0 0 0 0 din VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;  ECE Dept. SET-JU Page 30 HDL LAB MANUAL 2017-18 entity demux1X8 is Port ( din : in std_logic; enable : in std_logic; sel : in std_logic_vector(2 downto 0); y : out std_logic_vector(7 downto 0)); end demux1X8; architecture Behavioral of demux1X8 is begin process(enable, din,sel) begin if(enable=’1’)then y<=(others=>’0’); else case sel is when "000" => y(0) <= din ; when "001" => y(1) <= din ; when "010" => y(2) <= din ; when "011" => y(3) <= din; when "100" => y(4) <= din ; when "101" => y(5) <= din ; when "110" => y(6) <= din ; when "111" => y(7) <= din ; when others => null; end case; end if; end process; end Behavioral; SYNTHESIS RESULTS:  ECE Dept. SET-JU Page 31 HDL LAB MANUAL 2017-18 SIMULATION RESULTS: INPUT Test bench waveform: Output Waveform: 4. Encoder without priority Write a HDL program for the 8 to 3 Encoder without priority and Verify. Truth Table: enable Din7 Din6 Din5 Din4 Din3 Din2 Din1 Din0 Dout2 Dout1 Dout0 1 X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 1 1  ECE Dept. SET-JU Page 32 HDL LAB MANUAL 2017-18 VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encoder8_3wpvh is Port ( enable : in std_logic; din : in std_logic_vector(7 downto 0); dout : out std_logic_vector(2 downto 0)); end encoder8_3wpvh ; architecture Behavioral of encoder8_3wpvh is begin process(enable,din) begin if (enable='1') then dout<="000"; else case din is when "00000001"=> dout<="000"; when "00000010"=> dout<="001"; when "00000100"=> dout<="010"; when "00001000"=> dout<="011"; when "00010000"=> dout<="100"; when "00100000"=> dout<="101"; when "01000000"=> dout<="110"; when "10000000"=> dout<="111"; when others => dout<="000"; end case; end if; end process; end Behavioral; SYNTHESIS RESULTS:  ECE Dept. SET-JU Page 33 HDL LAB MANUAL 2017-18 SIMULATION RESULTS: INPUT Test bench waveform: Output Waveform:  ECE Dept. SET-JU Page 34 HDL LAB MANUAL 2017-18 5. Encoder with priority Write a HDL program for the 8 to 3 Encoder with priority and Verify. Truth Table: enable Din7 Din6 Din5 Din4 Din3 Din2 Din1 Din0 Dout2 Dout1 Dout0 1 X X X X X X X X 0 0 0 0 X X X X X X X 1 0 0 0 0 X X X X X X 1 0 0 0 1 0 X X X X X 1 0 0 0 1 0 0 X X X X 1 0 0 0 0 1 1 0 X X X 1 0 0 0 0 1 0 0 0 X X 1 0 0 0 0 0 1 0 1 0 X 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 1 1 VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity pri_enc is Port ( enable : in std_logic; din : in std_logic_vector(7 downto 0); dout : out std_logic_vector(2 downto 0)); end pri_enc; architecture Behavioral of pri_enc is begin process(enable,din) begin if(enable='1')then dout<=(others=>'0'); else if(din(0)='1')then dout<="000"; elsif(din(1)='1')then dout<="001"; elsif(din(2)='1')then dout<="010"; ECE Dept. SET-JU Page 35  HDL LAB MANUAL 2017-18 elsif(din(3)='1')then dout<="011"; elsif(din(4)='1')then dout<="100"; elsif(din(5)='1')then dout<="101"; elsif(din(6)='1')then dout<="110"; elsif(din(7)='1')then dout<="111"; else dout<="000"; end if; end if; end process; end Behavioral; SYNTHESIS RESULTS: SIMULATION RESULTS: INPUT Test bench waveform:  ECE Dept. SET-JU Page 36 HDL LAB MANUAL 2017-18 Output Waveform:  ECE Dept. SET-JU Page 37 HDL LAB MANUAL 2017-18 6. Decoder Write HDL code to implement 2:4 Decoder and verify. Truth Table: enable Din1 Din0 Dout3 Dout2 Dout1 Dout0 1 X X 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 0 0 0 VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder2_4vh is Port ( enable : in std_logic; din : in std_logic_vector ( 1 downto 0 ); dout : out std_logic_vector ( 3 downto 0 )); end decoder2_4vh; architecture Behavioral of decoder2_4vh is begin process (enable,din) begin if(enable = '1')then dout <= "0000"; else case din is when "00" => dout <= "0001" ; when "01" => dout <= "0010" ; when "10" => dout <= "0100" ; when "11" => dout <= "1000" ; when others => dout <= "0000"; end case; ECE Dept. SET-JU Page 38  HDL LAB MANUAL 2017-18 end if; end process; end Behavioral; SYNTHESIS RESULTS: SIMULATION RESULTS: INPUT Test bench waveform: Output Waveform:  ECE Dept. SET-JU Page 39 HDL LAB MANUAL 2017-18 7. BINARY TO GRAY CONVERSION Write a HDL program for 4 bit Binary to Gray conversion and Verify. Truth Table: VHDL Code:  ECE Dept. SET-JU Page 40 HDL LAB MANUAL 2017-18 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity binarytogray is Port ( b : in std_logic_vector(3 downto 0); g : out std_logic_vector(3 downto 0)); end binarytogray; architecture Behavioral of binarytogray is begin process(b) begin g(3)<=b(3); g(2)<=b(3) xor b(2); g(1)<=b(2) xor b(1); g(0)<=b(1) xor b(0); end process; end Behavioral; SYNTHESIS RESULTS:  ECE Dept. SET-JU Page 41 HDL LAB MANUAL 2017-18 SIMULATION RESULTS: INPUT Test bench waveform: Output Waveform: 8. Gray to Binary conversion Write a HDL program for 4 bit Gray to Binary conversion and verify. Truth Table:  ECE Dept. SET-JU Page 42 HDL LAB MANUAL 2017-18 VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity graytobin is Port ( g : in std_logic_vector(3 downto 0); b : out std_logic_vector(3 downto 0)); end graytobin; architecture Behavioral of graytobin is begin process(g) begin b(3)<=g(3); b(2)<=g(3) xor g(2); b(1)<=g(3) xor g(2) xor g(1); b(0)<=g(3) xor g(2) xor g(1) xor g(0); end process; end Behavioral; SYNTHESIS RESULTS:  ECE Dept. SET-JU Page 43 HDL LAB MANUAL 2017-18 SIMULATION RESULTS: INPUT Test bench waveform: Output Waveform:  ECE Dept. SET-JU Page 44 HDL LAB MANUAL 2017-18 9. Comparator Write HDL code to implement 4-bit Comparator and verify. Truth Table: enable A B aeb agb alb 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 1 1 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 0 0 1 0 1 1 0 1 0 0 0 1 0 0 1 1 0 1 0 0 1 0 0 1 0 0 1 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 0 1 0 1 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 0 0 0 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 0 0 1 0 0 1 1 1 0 0 0 0 1 0 1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity comp is Port ( enable : in std_logic; : in std_logic_vector(3 downto 0); : in std_logic_vector(3 downto 0); aeb,agb,alb : out std_logic); end comp; architecture Behavioral of comp is begin process(enable,a,b) variable x,y,z:std_logic; begin if(enable='1')then  ECE Dept. SET-JU Page 45 HDL LAB MANUAL 2017-18 x:='0'; y:='0'; z:='0'; else if(a=b)then x:='1'; y:='0'; z:='0'; elsif(a>b)then x:='0'; y:='1'; z:='0'; else x:='0'; y:='0'; z:='1'; end if; end if; aeb<=x; agb<=y; alb<=z; end process; end Behavioral; SYNTHESIS RESULTS:  ECE Dept. SET-JU Page 46 HDL LAB MANUAL 2017-18 SIMULATION RESULTS: INPUT Test bench waveform: Output Waveform:  ECE Dept. SET-JU Page 47 HDL LAB MANUAL 2017-18 10. ALU Design a 8 bit ALU with minimum 8 operations using HDL Truth Table: A1 B1 OPCODE Y(16 Bit) 000 + 001 - 11111111(FFh) 11111111(FFh)) 010 or 011 AND 100 not 101 * 110 NAND 111 XOR entity alu is Port( a1,b1:in std_logic_vector(7 downto 0); opcode : in std_logic_vector(2 downto 0); Yout : out std_logic_vector(15 downto 0)); end alu; architecture Behavioral of alu is signal a: std_logic_vector( 15 downto 0); signal b: std_logic_vector( 15 downto 0); begin a<= "00000000" & a1; b<= "00000000" & b1; Yout<= a+b when opcode ="000" else a-b when opcode ="001" else a or b when opcode ="010" else a and b when opcode ="011" else not a when opcode ="100" else a1 * b1 when opcode ="101" else a nand b when opcode ="110" else a xor b; end Behavioral; SYNTHESIS RESULTS: SIMULATION RESULTS: INPUT Test bench and Output Waveform: Results:  ECE Dept. SET-JU Page 48 HDL LAB MANUAL 2017-18 11. ADDER Write a HDL code to describe the functions of a Full Adder using three modeling styles. Truth Table: A B Cin SUM Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 i. DATA FLOW DESCRIPTION VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FullAdder is Port ( a,b,cin : in std_logic; sum,cout : out std_logic); end FullAdder; architecture dtfl of FullAdder is begin sum <= a xor b xor cin; cout <= (a and b) or (b and cin) or (cin and a); end dtfl; ii. BEHAVIORAL DESCRIPTION VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Seq_Full is  ECE Dept. SET-JU Page 49 HDL LAB MANUAL 2017-18 Port ( A : in std_logic; B : in std_logic; Cin : in std_logic; Sum : out std_logic; Cout : out std_logic); end Seq_Full; architecture Behavioral of Seq_Full is begin process(A,B,Cin) begin if(A='0' and B='0' and Cin='0')then Sum<='0'; Cout<='0'; elsif(A='0' and B='0' and Cin='1')then Sum<='1'; Cout<='0'; elsif(A='0' and B='1' and Cin='0')then Sum<='1'; Cout<='0'; elsif(A='0' and B='1' and Cin='1')then Sum<='0'; Cout<='1'; elsif(A='1' and B='0' and Cin='0')then Sum<='1'; Cout<='0'; elsif(A='1' and B='0' and Cin='1')then Sum<='0'; Cout<='1'; elsif(A='1' and B='1' and Cin='0')then Sum<='0'; Cout<='1'; elsif(A='1' and B='1' and Cin='1')then Sum<='1'; Cout<='1'; end if; end process; end Behavioral;  ECE Dept. SET-JU Page 50 HDL LAB MANUAL 2017-18 STRUCTURAL DESCRIPTION VHDL Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FA is Port ( a,b,cin : in std_logic; sum,cout : out std_logic); end FA; architecture Behavioral of FA is component HA port (I1, I2 : in std_logic; x, y : out std_logic); end component; component orgate port (I1, I2 : in std_logic; x : out std_logic); end component; signal s0,c0,c1:std_logic; begin HA1 : HA port map (a,b,s0,c0); HA2 : HA port map (cin,s0,sum,c1); O1 : orgate port map (c0,c1,cout); end Behavioral; ---------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; ECE Dept. SET-JU Page 51  HDL LAB MANUAL 2017-18 use IEEE.STD_LOGIC_UNSIGNED.ALL; entity HA is Port ( I1 : in std_logic; I2 : in std_logic; x: out std_logic; y : out std_logic); end HA; architecture Behavioral of HA is begin x<= I1 xor I2; y <= I1 and I2; end Behavioral; ---------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity orgate is port ( I1: in std_logic; I2: in std_logic; x: out std_logic); end orgate; architecture Behavioral of orgate is begin x <= I1 or I2; end Behavioral; ---------------------------------------------------------------- 12. Subtractor i. DATA FLOW DESCRIPTION Half Subtractor VHDL Code: entity halfsub is port ( a,b : in std_logic; diff,borrow: out std_logic); end halfsub; architecture Behavioral of halfsub is begin diff <= a xor b; borrow<= (not a) and b; end Behavioral;  ECE Dept. SET-JU Page 52 HDL LAB MANUAL 2017-18 Full Subtractor Truth Table: A B Bin Difference Borrow 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 Difference =(A-B)-Bin entity fullsub is port ( a,b,bin: in std_logic; diff,borrow : out std_logic); end fullsub; architecture Behavioral of fullsub is begin diff<= a xor b xor bin; borrow <= (bin and (not(a xor b)))or ((not a) and b); end Behavioral; STRUCTURAL entity fullsub is port ( a,b,bin: in std_logic; diff,borrow : out std_logic); end fullsub; architecture Behavioral of FA is component HS ECE Dept. SET-JU Page 53  HDL LAB MANUAL 2017-18 port (I1, I2 : in std_logic; X, Y : out std_logic); end component; component orgate port (I1, I2 : in std_logic; X : out std_logic); end component; signal d0,b0,b1:std_logic; begin HS1 : HS port map (a,b,d0,b0); HS2 : HS port map (bin,d0,diff,b1); O1 : orgate port map (b0,b1,borrow); end Behavioral; ---------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity HS is Port ( I1 : in std_logic; I2 : in std_logic; : out std_logic; : out std_logic); end Hs; architecture Behavioral of Hs is begin <= I1 xor I2; <= (not I1) and I2; end Behavioral; ---------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity orgate is port ( I1: in std_logic; I2: in std_logic; x: out std_logic); end orgate; architecture Behavioral of orgate is begin <= I1 or I2; end Behavioral;  ECE Dept. SET-JU Page 54 HDL LAB MANUAL 2017-18 First Cycle Verilog Programmes 1. All Logic gate module all_gate(a,b, y_not, y_or, y_and, y_nor, y_nand, y_xor,y_xnor); input a; input b; output y_not, y_or, y_and, y_nor, y_nand, y_xor,y_xnor; assign y_or = a | b; assign y_and = a & b; assign y_not = ~ a; assign y_nand = ~( a & b ) ; assign y_nor = ~ (a | b); assign y_xor = a ^ b ; assign y_xnor = ~ (a ^ b); endmodule 2. 4:1 Multiplexer module MUX41V(A,B,C,D,sel, MUX_OUT); input A,B,C,D; input [1:0] sel; output MUX_OUT; reg MUX_OUT; always@(sel, A,B,C,D) begin case(sel) 2'd0 : MUX_OUT = A; 2'd1 : MUX_OUT = B; 2'd2 : MUX_OUT = C; 2'd3 : MUX_OUT = D; endcase end endmodule 3. 1:4 De Multiplexer module demux14v(din, sel, y); input [1:0] sel; input din; output [3:0] y; reg [3:0] y; always @(sel,din) case({din,sel}) 3'b100:y=4'b0001; 3'b101:y=4'b0010; 3'b110:y=4'b0100; ECE Dept. SET-JU Page 106  HDL LAB MANUAL 2017-18 3'b111:y=4'b1000; default:y=4'b0000; endcase endmodule 4. 4:2 Encoder without Priority module EWP(din,enable,dout); input [3:0] din; input enable; output [1:0] dout; reg [1:0] dout; always @(din,enable) begin if (enable == 1'b1) dout = 3'b00; else begin case (din) 4'b0001 : dout=2'b00; 4'b0010 : dout=2'b01; 4'b0100 : dout=2'b10; 4'b1000 : dout=2'b11; default : dout=2'b00; endcase end end endmodule 5. 4:2 Encoder with Priority module EP(DIN,DOUT,enable); input [3:0] DIN; output [1:0] DOUT; input enable; reg [1:0] DOUT; always @(DIN,enable) begin if(enable==1'b1) DOUT=2'b00; else begin casex (DIN) 4'bxxx1 : DOUT= 2'b00; 4'bxx10 : DOUT= 2'b01; 4'bx100 : DOUT= 2'b10; 4'b1000 : DOUT= 2'b11; default : DOUT= 2'b00; ECE Dept. SET-JU Page 107  HDL LAB MANUAL 2017-18 endcase end end endmodule 6. 2:4 Decoder module decoder2_4v(enable,din,dout); input enable; input [1:0] din; output [3:0] dout; reg [3:0] dout; always @(enable,din) begin if (enable==1'b1) begin dout=4'b0000; end else begin case(din) 2'b00 : dout=4'b0001; 2'b01 : dout=4'b0010; 2'b10 : dout=4'b0100; 2'b11 : dout=4'b1000; endcase end end endmodule 7. Comparator module comparator(a,b,en,aeb,agb,alb); input [3:0] a; input [3:0] b; input en; output aeb; output agb; output alb; reg aeb,agb,alb; always @(a,b,en) begin if (en==1) if(a==b) ECE Dept. SET-JU Page 108  HDL LAB MANUAL 2017-18 begin aeb=1; agb=0; alb=0; end else if(a>b) begin aeb=0; agb=1; alb=0; end else begin aeb=0; agb=0; alb=1; end else begin aeb=0; agb=0; alb=0; end end endmodule 8. Binary to Gray module bintogray(b,g); input [3:0] b; output [3:0] g; reg [3:0] g; always@(b) begin g[3]=b[3]; g[2]=b[3] ^ b[2]; g[1]=b[2] ^ b[1]; g[0]=b[1] ^ b[0]; end endmodule 9. Gray to Binary module gratobin(g,b); input [3:0] g; output [3:0] b; reg [3:0] b; ECE Dept. SET-JU Page 109  HDL LAB MANUAL 2017-18 always@(g) begin b[3]=g[3]; b[2]=g[3] ^ g[2]; b[1]=g[3] ^ g[2] ^ g[1]; b[0]=g[3] ^ g[2] ^ g[1] ^ g[0]; end endmodule 10.8 bit ALU module aluu(a,b,opcode,enable,y); input [7:0] a,b; input [3:0] opcode; input enable; output [15:0] y; reg [15:0] y; always@(a,b,enable,opcode) begin if(enable==1'b1) begin case (opcode) 4'b0001 : y = a + b; 4'b0010 : y = a - b; 4'b0011 : y = ~ a; 4'b0100 : y = a * b; 4'b0101 : y = a & b; 4'b0110 : y = a | b; 4'b0111 : y = ~(a & b); 4'b1000 : y = a ^ b; default: y=16'd0; endcase end else begin y=16'd0; end end endmodule 11.Full Adder module FA(a,b,cin,sum,cout); input a; input b; input cin; output sum; ECE Dept. SET-JU Page 110  HDL LAB MANUAL 2017-18 output cout; HA H1 (a,b,s0,c0); HA H2 (cin,s0,sum,c1); or_gate O1 (c0, c1, cout); endmodule module HA(a,b,s,c); input a,b; output s,c; xor (s,a,b); and (c,a,b); endmodule module or_gate(a,b,y); input a; input b; output y; assign y = a | b; endmodule ECE Dept. SET-JU Page 111  HDL LAB MANUAL 2017-18 Cycle-2 Experiments- Sequential Circuits 1 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 Flip Flop Verify the functionality of D Flip Flop using HDL AIM: To design a D-flip flop in behavioral model and testing the functionality using test bench RESET CLK D Q Qb 1 X X 0 1 0 1 0 0 1 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 entity D_ff is Port ( d : in std_logic; reset : in std_logic; clk : in std_logic; q,qb : inout std_logic); end D_ff; architecture Behavioral of D_ff is begin process(clk,reset) begin if(reset='1')then q <= '0'; elsif(clk'event and clk='1')then q <= d; end if; end process; qb <= not q; end Behavioral; SYNTHESIS RESULTS: SIMULATION RESULTS: INPUT Test bench and Output Waveform: Results: 2 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 Verify the functionality of T Flip Flop using HDL. RESET CLK T Q Qb 1 X X 0 1 0 1 0 Previous Q-0 Previous Qb-1 0 0 0 Previous Q-0 Previous Qb-1 0 1 1 Previous not(Q)-1 Previous not(Qb)-0 0 0 1 1 0 entity T_ff is Port ( clk : in std_logic; reset : in std_logic; t : in std_logic; q ,qb: inout std_logic); end T_ff; architecture Behavioral of T_ff is begin process(clk,reset) begin if reset='1' then q <= '0'; elsif(clk'event and clk='1')then if t='1' then q <= not q ; else q<=q; end if; end if; end process; qb <= not q ; end Behavioral; SYNTHESIS RESULTS: SIMULATION RESULTS: INPUT Test bench and Output Waveform: Results: 3 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 Verify the functionality of SR-Flip Flop using HDL RESET CLK S R Q Qb 1 X X X 0 1 0 1 0 0 Previous Q-0 Previous Qb-1 0 0 0 1 0 1 0 1 1 0 1 0 0 0 1 1 Z Z entity SR_ff is Port ( S : in std_logic; R : in std_logic; clk : in std_logic; reset : in std_logic; q,qb : out std_logic); end SR_ff; architecture Behavioral of SR_ff is begin process (clk,reset) variable temp : std_logic; begin if(reset='1')then temp := '0'; elsif(clk'event and clk='1')then if(S='0' and R='0')then temp := temp ; elsif(S='0' and R='1')then temp := '0' ; elsif(S='1' and R='0')then temp := '1' ; elsif(S='1' and R='1')then temp := 'Z' ; end if; end if; q <= temp; qb <= not temp; end process; end Behavioral; SYNTHESIS RESULTS: SIMULATION RESULTS: 4 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 INPUT Test bench and Output Waveform: Results: Verify the functionality of JK Flip Flop using HDL RESET CLK J K Q Qb 1 X X X 0 1 0 1 0 0 Previous Q-0 Previous Qb-1 0 0 0 1 0 1 0 1 1 0 1 0 0 0 1 1 Previous (not Q)-0 Previous (not Qb)-1 entity JK_ff is Port ( J : in std_logic; K : in std_logic; clk : in std_logic; reset: in std_logic; q : out std_logic; qb : out std_logic); end JK_ff; architecture JK_ff_arch of JK_ff is begin process(clk,reset) variable temp:std_logic; begin if(reset='1')then temp := '0'; elsif(clk'event and clk='1')then if(J='0' and K='0')then temp := temp ; elsif(J='0' and K='1')then temp := '0' ; elsif(J='1' and K='0')then temp := '1' ; elsif(J='1' and K='1')then temp := not temp ; end if; end if; q <= temp; qb <= not temp; end process; end JK_ff_arch; SYNTHESIS RESULTS: SIMULATION RESULTS: 5 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 INPUT Test bench and Output Waveform: Results: COUNTERS BCD UP/DOWN COUNTER entity BCD_counter is port(clk, updown, reset:in std_logic; count: out std_logic_vector( 3 downto 0)); end entity BCD_counter; architecture behaviour of BCD_counter is signal q: std_logic_vector(0 to 3); begin process(clk) begin if(Clk'event and Clk = '1') then if(updown = '1') then -- counting up if(reset = '1')then --initialize q<="0000"; -- reset to 0 else if (q<"1001") then q<=q+1; else q<="0000"; end if; end if; elsif(updown = '0') then --counting down if(reset = '1') then --initialize q<="1001"; --reset to 9 else if (q>"0000") then q<=q-1; else q<="1001"; end if; end if; end if; end if; 6 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 end process; count <= q; end behaviour; SYNTHESIS RESULTS: SIMULATION RESULTS: INPUT Test bench and Output Waveform: Results: BINARY UP/DOWN COUNTER entity binary_up_down_counter is port ( cout :out std_logic_vector (3 downto 0); up_down :in std_logic; -- up_down control for counter clk :in std_logic; -- Input clock reset :in std_logic ); end binary_up_down_counter; architecture behaviour of binary_up_down_counter is signal count :std_logic_vector (3 downto 0); begin process (clk, reset) begin if (reset = '1') then count <= (others=>'0'); elsif (rising_edge(clk)) then if (up_down = '1') then count <= count + 1; else count <= count - 1; end if; end if; end process; cout <= count; end behaviour; SYNTHESIS RESULTS: SIMULATION RESULTS: INPUT Test bench and Output Waveform: Results: 7 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 8 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 CYCLE 2 VERILOG T FF module D_ff(d,clk,reset,q,qb); input d; input clk; input reset; output q; output qb; reg q,qb; always@(posedge clk or posedge reset) begin if(reset==1'b1) begin q<=1'b0; qb<=1'b1; end else begin q<=d; qb<=~d; end end endmodule T FF module T_ff(clk,reset,t,q,qb); input clk; input reset; input t; output q; output qb; reg q,qb; always@(posedge clk) begin if (reset==1'b1) begin q=1'b0; qb=1'b1; end else 1 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 begin if(t==1'b1) q = ~q; else q = q; end qb=~q; end endmodule SR FF module SR_f_f(SR,clk,reset,q,qb); input [1:0] SR ; input clk,reset; output q,qb; reg q,qb; always@(posedge clk) begin if(reset==1'b1) q = 1'b0; else begin case (SR) 2'b00 : q = q ; 2'b01 : q = 1'd0 ; 2'b10 : q = 1'd1 ; 2'b11 : q = 1'dZ ; endcase end qb = ~ q; end endmodule JK FF module JK_ff(JK,clk,reset,q,qb); input [1:0] JK; input clk; input reset; output q,qb; reg q,qb; always@(posedge clk) 2 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 begin if (reset==1’b1) q = 1'd0 ; else begin case(JK) 2'b00 : q = q ; 2'b01 : q = 1'd0 ; 2'b10 : q = 1'd1 ; 2'b11 : q = ~ q ; endcase end qb = ~q; end endmodule 4 bit Binary UP/DOWN counter module counter(q,updown,reset, clock,count); output [3:0] q; input reset, clock, updown,count; reg [3:0] q; always @(posedge clock) if (reset) q = 0; else if (count) begin if (updown) q = q + 1; else q = q - 1; end endmodule 4 bit BCD UP/DOWN counter module BCD( count, updown, clk,rst, en ); output [3:0] count; input updown; input clk, rst, en; 3 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 reg [3:0] reg_cnt; reg [3:0] nxt_cnt; always @ ( posedge rst or posedge clk ) begin if ((rst == 1'b1)) reg_cnt <= 1'h0; else if ((en == 1'b1)) reg_cnt <= nxt_cnt; end always @ ( reg_cnt or updown ) begin if (updown ) if ((reg_cnt == 0)) nxt_cnt <= 4'b1001; else nxt_cnt <= (reg_cnt - 1); else if ((reg_cnt == 9)) nxt_cnt <= 1'h0; else nxt_cnt <= (reg_cnt + 1); end assign {count}=reg_cnt; endmodule 4 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 Cycle-3 Experiments- Hardware Interfacing 1. Write a VHDL code to control external lights using relays. Procedure: Make the connection between FRC9 of the FPGA board to the External light connector of the VTU card2. Make the connection between FRC1 of the FPGA board to the Dip switch connector of the VTU card2. Connect the downloading cable and power supply to the FPGA board. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial mode and select the respective BIT file and click program. Make the reset switch on (active low) and analyze the data. RELAY 1 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 2 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 VHDL CODING library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity extlight is Port ( cntrl1,cntrl2 : in std_logic; light : out std_logic); end extlight; architecture Behavioral of extlight is begin light<= cntrl1 OR cntrl2 ; end Behavioral; UCF file(User constraint) 2. Write a VHDL code to control speed, direction of Stepper motor. CLOCK DIVISION library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity clock_division is Port ( clk: in std_logic); end clock_division; architecture Behavioral of clock_division is signal clk_div : std_logic_vector(2 downto 0):= "000"; signal clk_int: std_logic; 3 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 begin process(clk) begin if rising_edge (clk) then clk_div <= clk_div + '1'; end if; end process; clk_int<=clk_div(2); end Behavioral; Stepper motor library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity STEPPERnew is Port ( dout : out std_logic_vector(3 downto 0); clk,reset: in std_logic; row:in std_logic_vector(1 downto 0); dir:in std_logic); end STEPPERnew; architecture Behavioral of STEPPERnew is signal clk_div : std_logic_vector(25 downto 0); signal clk_int: std_logic; signal shift_reg : std_logic_vector(3 downto 0); begin process(clk) begin if rising_edge (clk) then clk_div <= clk_div + '1'; end if; end process; clk_int<=clk_div(21) when row="00"else clk_div(19) when row="01"else clk_div(17) when row="10"else clk_div(15) ; process(reset,clk_int,dir) begin if reset='0' then shift_reg <= "1001"; elsif rising_edge(clk_int) then if dir='0' then shift_reg <= shift_reg(0) & shift_reg(3 downto 1); else 4 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 shift_reg<=shift_reg(2 downto 0) & shift_reg(3); end if; end if; end process; dout <= shift_reg; end Behavioral; UCF file(User constraint File) Write a VHDL code to generate different waveforms using DAC change the frequency and amplitude. Procedure: 1. Make the connection between FRC5 of the FPGA board to the DAC connector of the VTU card2. Make the connection between FRC1 of the FPGA board to the Dip switch connector of the VTU card2. Connect the downloading cable and power supply to the FPGA board. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial mode and select the respective BIT file and click program. Make the reset switch on (active low) and analyze the data. MATLAB CODE FOR SINE VALUES x=0:2:360; y =128+128*sin(x*pi/180); z=fix(y); RUN+ IN RESULT TYPE THE FOLLOWING csvwrite('csvlist.dat',z) type csvlist.dat 5 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 i. SINE Waveform VHDL CODING LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SINE IS PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; dac_out : OUT STD_LOGIC_VECTOR(0 to 7)); END SINE; ARCHITECTURE BEHAVIORAL OF SINE IS SIGNAL C1:STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL I :INTEGER RANGE 0 TO 179; TYPE SINE IS ARRAY (0 TO 179) OF INTEGER RANGE 0 TO 255; CONSTANT VALUE:SINE:=(128,132,136,141,154,150,154,158,163,167, 171,175,180,184,188,192,195,199,203,206, 210,213,216,220,223,226,228,231,234,236, 238,241,243,244,246,247,248,249,250,251, 252,253,254,255,255, 255,255,255,254,254, 253,252,251,249,246,244,243,241,238,236, 234,231,228,226,223,220,216,213,210,206, 203,199,195,192,188,184,180,175,171,167, 163,158,154,150,145,141,136,132,128, 123, 119, 114, 110, 105, 101, 97, 92,88,84,80, 75,71,67,64,60,56,52,49,45,42, 39,35,32,29,27,24,21,19,17,14, 12, 11, 9, 7,6,4,3,2,1,1, 0,0,0,0, 0, 0, 0,0,1,1, 2, 3,4,6,7,9,11,12,14,17, 19,21,24,27,29,32,35,39,42,45, 49, 52, 56, 60,64,67,71,75,80,84, 88,92,97,101,105,110,114,119,123,128); BEGIN PROCESS(CLK,RST) BEGIN IF(RST='1') THEN C1<=(OTHERS=>'0'); ELSIF(CLK'EVENT AND CLK='1') THEN C1<=C1+1; END IF; END PROCESS; PROCESS(C1(3)) 6 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 BEGIN IF(C1(3)'EVENT AND C1(3)='1')THEN dac_out<=CONV_STD_LOGIC_VECTOR(VALUE(I),8); I<=I+1; IF(I=179) THEN I<=0; END IF; END IF; END PROCESS; END BEHAVIORAL; UCF file(User constraint File) Square waveform Aim: To generate Square wave using DAC change the frequency and amplitude. Procedure: Make the connection between FRC5 of the FPGA board to the DAC connector of the VTU card2. Make the connection between FRC1 of the FPGA board to the Dip switch connector of the VTU card2. Connect the downloading cable and power supply to the FPGA board. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial mode and select the respective BIT file and click program. Make the reset switch on (active low) and analyze the data. 7 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 VHDL CODING LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY square IS PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; dac_out : OUT STD_LOGIC_VECTOR(0 to 7)); END square; ARCHITECTURE BEHAVIORAL OF square IS SIGNAL C1:STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL I :INTEGER RANGE 0 TO 179; TYPE square IS ARRAY (0 TO 179) OF INTEGER RANGE 0 TO 255; CONSTANT VALUE: square:=(255,255,255,255,255,255,255,255,255,255, 255,255,255,255,255,255,255,255,255,255, 255,255,255,255,255,255,255,255,255,255, 255,255,255,255,255,255,255,255,255,255, 255,255,255,255,255,255,255,255,255,255, 255,255,255,255,255,255,255,255,255,255, 255,255,255,255,255,255,255,255,255,255, 255,255,255,255,255,255,255,255,255,255, 255,255,255,255,255,255,255,255,255,255, 0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0,0,0); BEGIN PROCESS(CLK,RST) BEGIN IF(RST='1') THEN C1<=(OTHERS=>'0'); ELSIF(CLK'EVENT AND CLK='1') THEN C1<=C1+1; END IF; END PROCESS; PROCESS(C1(3)) BEGIN IF(C1(3)'EVENT AND C1(3)='1')THEN 8 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 dac_out<=CONV_STD_LOGIC_VECTOR(VALUE(I),8); I<=I+1; IF(I=179) THEN I<=0; END IF; END IF; END PROCESS; END BEHAVIORAL; UCF file(User constraint File) Triangular waveform Aim: To generate Triangular wave using DAC change the frequency and amplitude. Procedure: Make the connection between FRC5 of the FPGA board to the DAC connector of the VTU card2. Make the connection between FRC1 of the FPGA board to the Dip switch connector of the VTU card2. Connect the downloading cable and power supply to the FPGA board. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial mode and select the respective BIT file and click program. Make the reset switch on (active low) and analyze the data. 9 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 VHDL CODING LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY Triangular IS PORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; dac_out : OUT STD_LOGIC_VECTOR(0 to 7)); END Triangular; ARCHITECTURE BEHAVIORAL OF Triangular IS SIGNAL C1:STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL I :INTEGER RANGE 0 TO 179; TYPE Triangular IS ARRAY (0 TO 1) OF INTEGER RANGE 0 TO 255; CONSTANT VALUE: Triangular:=(255,0); BEGIN PROCESS(CLK,RST) BEGIN IF(RST='1') THEN C1<=(OTHERS=>'0'); ELSIF(CLK'EVENT AND CLK='1') THEN C1<=C1+1; END IF; END PROCESS; PROCESS(C1(3)) BEGIN IF(C1(3)'EVENT AND C1(3)='1')THEN dac_out<=CONV_STD_LOGIC_VECTOR(VALUE(I),8); I<=I+1; IF(I=179) THEN I<=0; END IF; END IF; END PROCESS; END BEHAVIORAL; UCF file(User constraint File) 10 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 4. LCD DISPLAY 8 data pins D7:D0 Bi-directional data/command pins. Alphanumeric characters are sent in ASCII format. RS: Register Select RS = 0 -> Command Register is selected RS = 1 -> Data Register is selected R/W: Read or Write 0 -> Write, 1 -> Read 11 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 E: Enable (Latch data) Used to latch the data present on the data pins. A high-to-low edge is needed to latch the data. -- THE NUMBERS constant ONE : std_logic_vector(7 downto 0) := "00110001";//31 constant TWO : std_logic_vector(7 downto 0) := "00110010";//32 constant THREE : std_logic_vector(7 downto 0) := "00110011";//33 constant FOUR : std_logic_vector(7 downto 0) := "00110100";//34 constant FIVE : std_logic_vector(7 downto 0) := "00110101";//35 constant SIX : std_logic_vector(7 downto 0) := "00110110";//36 constant SEVEN : std_logic_vector(7 downto 0) := "00110111";//37 constant EIGHT : std_logic_vector(7 downto 0) := "00111000";//38 constant NINE : std_logic_vector(7 downto 0) := "00111001";//39 constant ZERO : std_logic_vector(7 downto 0) := "00110000";//30 -- THE CHARACTERS constant A : std_logic_vector(7 downto 0) := "01000001"; //41 constant B : std_logic_vector(7 downto 0) := "01000010";//42 constant C : std_logic_vector(7 downto 0) := "01000011";//43 constant D : std_logic_vector(7 downto 0) := "01000100";//44 constant E : std_logic_vector(7 downto 0) := "01000101";//45 constant F : std_logic_vector(7 downto 0) := "01000110";//46 constant G : std_logic_vector(7 downto 0) := "01000111";//47 constant H : std_logic_vector(7 downto 0) := "01001000";//48 constant I : std_logic_vector(7 downto 0) := "01001001";//49 constant J : std_logic_vector(7 downto 0) := "01001010";//4A constant K : std_logic_vector(7 downto 0) := "01001011";//4B constant L : std_logic_vector(7 downto 0) := "01001100";//4C constant M : std_logic_vector(7 downto 0) := "01001101";//4D constant N : std_logic_vector(7 downto 0) := "01001110";//4E constant O : std_logic_vector(7 downto 0) := "01001111";//4F constant P : std_logic_vector(7 downto 0) := "01010000";//50 constant Q: std_logic_vector(7 downto 0) := "01010001";//51 constant R : std_logic_vector(7 downto 0) := "01010010";//52 constant S : std_logic_vector(7 downto 0) := "01010011";//53 constant T : std_logic_vector(7 downto 0) := "01010100";//54 constant U : std_logic_vector(7 downto 0) := "01010101";//55 constant V : std_logic_vector(7 downto 0) := "01010110";//56 constant W : std_logic_vector(7 downto 0) := "01010111";//57 constant X : std_logic_vector(7 downto 0) := "01011000";//58 constant Y : std_logic_vector(7 downto 0) := "01011001";//59 constant Z : std_logic_vector(7 downto 0) := "01011010";//5A constant SPACE: std_logic_vector(7 downto 0) := "00100000";// 20 constant SLASH: std_logic_vector(7 downto 0) := "00101111";//2F constant MINUS: std_logic_vector(7 downto 0) := "00101101";//2D constant EQUAL: std_logic_vector(7 downto 0) := "00111101";//3D 12 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 constant PLUS : std_logic_vector(7 downto 0) := "00101011";//2B constant STAR : std_logic_vector(7 downto 0) := "00101010";//2A constant DOT : std_logic_vector(7 downto 0) := "00101110";//2E LIST OF COMMANDS 5. Write VHDL code to display messages on the given LCD Aim: To Display the message on the LCD panel Procedure: Make the connection between FRC5 of the FPGA board to the LCD Display connector of the VTU card1. Connect the downloading cable and power supply to the FPGA board Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial mode and select the respective BIT file and click program. 13 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 1 LINE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; Uncomment the following library declaration if instantiating any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity lcd_disp is port ( clk : in std_logic; ----clock i/p lcd_rw : out std_logic; ---read&write control lcd_e : out std_logic; ----enable control lcd_rs : out std_logic; ----data or command control data : out std_logic_vector(7 downto 0)); ---data line end lcd_disp; architecture Behavioral of lcd_disp is constant N: integer :=21; type arr is array (1 to N) of std_logic_vector(7 downto 0); constant datas : arr := (X"38",X"0c",X"06",X"01",X"80", X"4A",X"41",X"49",X"4E",X"20",X"55",X"4E",X"49",X"56", X"45",X"52",X"53",X"49",X"54",X"59",X"20"); --command and data to display begin lcd_rw <= '0'; ----lcd write process(clk) variable i : integer := 0; variable j : integer := 1; begin if clk'event and clk = '1' then if i <= 0500000 then i := i + 1; lcd_e <= '1'; data <= datas(j)(7 downto 0); elsif i > 0500000 and i < 1000000 then i := i + 1; lcd_e <= '0'; elsif i = 1000000 then j := j + 1; i := 0; end if; if j <= 5 then lcd_rs <= '0'; ---command signal elsif j > 5 then lcd_rs <= '1'; ----data signal 14 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 end if; if j = 21 then ---repeated display of data j := 5; end if; end if; end process; end Behavioral; UCF file(User constraint file) NET "CLK" LOC = "P52" ; NET " data <0>" LOC = "P14" ; NET " data <1>" LOC = "P15" ; NET " data <2>" LOC = "P17" ; NET " data <3>" LOC = "P18" ; NET " data <4>" LOC = "P21" ; NET " data <5>" LOC = "P23" ; NET " data <6>" LOC = "P24" ; NET " data <7>" LOC = "P26" ; NET "lcd_e " LOC = "P13" ; NET " lcd_rw " LOC = "P12" ; NET " lcd_rs" LOC = "P1" ; 2 LINE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; Uncomment the following library declaration if instantiating any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity lcd_disp is port ( clk : in std_logic; ----clock i/p lcd_rw : out std_logic; ---read&write control lcd_e : out std_logic; ----enable control lcd_rs : out std_logic; ----data or command control data : out std_logic_vector(7 downto 0)); ---data line end lcd_disp; architecture Behavioral of lcd_disp is constant N: integer :=38; type arr is array (1 to N) of std_logic_vector(7 downto 0); constant datas : arr := (X"38",X"0c",X"06",X"01",X"80", X"4A",X"41",X"49",X"4E",X"20",X"55",X"4E",X"49",X"56", X"45",X"52",X"53",X"49",X"54",X"59",X"20", 15 ECE Dept. SET-JU  HDL LAB MANUAL 2017-18 X"C0", X"4A",X"41",X"49",X"4E",X"20",X"55",X"4E",X"49",X"56",X"45",X"52",X"53",X"49",X"54",X"59",X"20"); begin lcd_rw <= '0'; ----lcd write process(clk) variable i : integer := 0; variable j : integer := 1; begin if clk'event and clk = '1' then if i <= 0500000 then i := i + 1; lcd_e <= '1'; data <= datas(j)(7 downto 0); elsif i > 0500000 and i < 1000000 then i := i + 1; lcd_e <= '0'; elsif i = 1000000 then j := j + 1; i := 0; end if; if j <= 5 then lcd_rs <= '0'; ---command signal elsif j > 5 and j<= 21 then lcd_rs <= '1'; ----data signal elsif j = 22 then lcd_rs <= '0'; ---command signal elsif j > 22 lcd_rs <= '1'; ----data signal end if; if j = 38 then ---repeated display of data j := 5; end if; end if; end process; end Behavioral; 16 ECE Dept. SET-JU  VIVA QUESTIONS What type of language is VHDL? What is the basic building unit of a VHDL design? What do all VHDL designs begin with? Which block describes a design's interface? Which block describes a design's behavior? What is the difference between simulation and synthesis? Which data type defines a single logic signal? Which data type describes a bus? What two ways can a vector's range be described? What are the IEEE STD_LOGIC_1164 data types for single logic signals and buses? Why is it desirable to use IEEE STD_LOGIC_1164 data typing? What are the only two values for a Boolean type? What are the numerical data types? What is SUBTYPING used for? What type is use to create a user data type? What reserved word is used to declare a user data type? Create the use data type DAYS and assign it the values: MON, TUE, WED, THU, FRI, SAT and SUN. Which data type is used for a string of ASCII characters? Which data type includes time units as values? 20 Create the entity block for a three input XOR gate. Which symbol is used to end all VHDL statements? What part of a port declaration defines signals in or out direction? Which VHDL construct is used to define a literal constant in an entity block?  Create the integer constant included in an entity block called BUS_SIZE and assign it a value of 32. Which symbols are used as an assignment operator to assign a literal to an identifier name? What are the two primary ways to describe a logic circuits function within an architecture block? Create the architecture block for the 3-input XOR gate of question 21. Which symbols are used to assign an expression's result to an output interface signal? What are the rules used to define an identifier name? What symbols define a comment line? Write the statements that will allow a design to access all the contents of the IEEE ARITH Make the delay in question 33 transport rather than inertial. How does a transport delay differ from an inertial delay? What is the purpose of a SIGNAL declaration? Where are SIGNAL declarations placed in the design? Write an assignment statement that assigns the contents of s(5) to t(2). 37.What is the purpose of a process' sensitivity list? 38 Under what conditions is a process run? What is an EVENT? What is the difference between event and non-event driven process execution? Write a process block that keeps a running tally of each time an interrupt (INT) signal is asserted high. Which symbols are used to differentiate between logic 1 and an integer 1? What are the results of using CLK'event as a condition in the if statement of the DEF example? 44.In an if..then..else construct, which statements are executed if the condition is TRUE and which if it is FALSE? 45. What reserved word is used to nest if..then..else statements?  Write the process block that separately tallies positive and negative transitions of the signal TIME_OUT. What is the purpose of a for loop? What are the requirements for a for loop? Write a process block that uses a for loop to set a zero flag high if all the bits in a sixteen (16) bit word are low (zero). Write is the general rule for component declarations? What is meant by instantiating a component? How do signal declarations differ from port interface declarations? What is the prime use of signals? How many parameters can be passed into a function? How many results can be returned from a function? Write a function that returns the sum of two 8-bit words. How are functions called? How do procedures differ from functions? Which standard library does not require a library or use statement? What is a PACKAGE? When is a PACKAGE BODY used? What is the name of the library used by the current design to store compiled results? Which standard library is used to access the keyboard and monitor screen?  JAIN UNIVERSITY Declared as Deemed-to-be Univ ersity u/s 3 of the UGC Act 1956 School of Engineering and Technology DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING SIXTH SEMESTER -HDL Laboratory (ECL-68) Name:………………………………………………………………….. Batch:………………… USN Number:……………………………………………………….. Date:………………….. SI Title of experiment Sub Group O=10 C =10 R=10 NO CYCLE -1 EXPERIMENTS AND NAND OR NOR 1. Basic gates XOR XNOR ALL gates 2. Multiplexer 2:1 MUX 4:1 MUX 8:1 MUX 3. De Multiplexer 1:2 DEMUX 1:4 DEMUX 1:8 DEMUX 4. Encoder Without Priority 8:3 4:2 5. Encoder With Priority 8:3 4:2 6. Decoder 3:8 2:4 7. Binary to Gray conversion 4 bit 8. Gray to Binary conversion 4 bit 9. Comparator 1 bit 4 bit 10. ALU 8 Bit 32 Bit 11. Adder Half Adder Full Adder 12. Subtractor Half Subtractor Full Subtractor  CYCLE -2 EXPERIMENTS D Flip Flop 14. Flip Flop T Flip Flop SR Flip Flop JK Flip Flop BCD 15. U/Down Counter Counter Binary Up/Down Counter CYCLE -3 EXPERIMENTS --Hardware Interfacing Experiments Generation of different Sine Waveform 16. Square waveform waveforms using DAC Triangular Waveform 17. 16x2 LCD interface Stepper Motor speed and direction Control 18. Control external lights using relays 19. LAB TEST GRAND TOTAL AVERAGE LAB INTERNAL TOTAL Student signature Staff In charge