A WSe₂ vertical field emission transistor

A WSe2 vertical field emission transistor Antonio Di Bartolomeo1,2,3,*, Francesca Urban1,2,3, Maurizio Passacantando4, Niall McEvoy5, Lisanne Peters5, Laura Iemmo1,,2,3, Giuseppe Luongo1,2,3, Francesco Romeo1,3, and Filippo Giubileo3 1 Physics Department “E. R. Caianiello”, University of Salerno, via Giovanni Paolo II n. 132, Fisciano 84084, Italy 2 Interdepartmental Centre NanoMates, University of Salerno, via Giovanni Paolo II n. 132, Fisciano 84084, Italy 3 CNR-SPIN Salerno, via Giovanni Paolo II n. 132, Fisciano 84084, Italy 4 Department of Physical and Chemical Science, University of L’Aquila, and CNR-SPIN L’Aquila, via Vetoio, Coppito 67100, L’Aquila, Italy 5 AMBER & School of Chemistry, Trinity College Dublin, Dublin 2, Ireland *E-mail: adibartolomeo@unisa.it Keywords: 2D materials, field effect transistors, field emission, tungsten diselenide Abstract We report the first observation of gate-controlled field emission current from a tungsten diselenide (WSe2) monolayer, synthesized by chemical-vapour deposition on SiO2/Si substrate. Ni contacted WSe2 monolayer back-gated transistors, under high vacuum, exhibit n-type conduction and drain-bias dependent transfer characteristics, which are attributed to oxygen/water desorption and drain induced Schottky barrier lowering, respectively. The gate-tuned n-type conduction enables field emission, i.e. the extraction of electrons by quantum tunnelling, even from the flat part of the WSe2 monolayers. Electron emission occurs under an electric field ~100 V μm−1 and exhibit good time stability. Remarkably, the field emission current can be modulated by the back-gate voltage. The first field-emission vertical transistor based on WSe2 monolayer is thus demonstrated and can pave the way to further optimize new WSe2 based devices for use in vacuum electronics. Introduction In the past decade, transition metal dichalcogenides (TMDs) have attracted a lot of attention due to several promising properties for electronic and optoelectronic applications, including pristine interfaces without outof-plane dangling bonds, flexibility, tuneable bandgap in the range 0.7-2.2 eV, moderate mobility comparable to that of Si channels in modern devices, transparency, broadband light response, photoluminescence, thermal stability in air and high scalability in device fabrication 1–3 . Mechanical and liquid exfoliation 4, chemical vapour deposition (CVD) 5,6 , pulsed laser deposition 7 molecular beam epitaxy 8,9, etc. have been used for their production. Most of the TMDs, such as MoS2, MoSe2, WS2 , MoTe2, HfSe2, ZrSe2 , show natural n-type conduction, with p-type behaviour achieved only through suitable doping or coupling to other conducting or 1 dielectric materials 10,11. On the contrary, air exposed WSe2, that is an important member of the TMD family, shows predominantly p-type conduction or ambipolar behaviour 12–15. Similar to other TMDs, the WSe2 band structure evolves from a narrow (~1.2 𝑒𝑉) and indirect bandgap in the bulk form to a wider (~1.6 𝑒𝑉) and direct bandgap in the monolayer counterpart 16–18 . Besides the number of layers, a vertical electric field can enable further bandgap tuning 19. WSe2 has also emerged among other TMDs, and in particular over the widely studied MoS2, due to its lower electron and hole effective masses and thus higher mobility, demonstrated up to the record value of 500 𝑐𝑚2 𝑉𝑠 for holes at room temperature 13,20,21. The high bandgap and mobility make WSe2 a suitable two-dimensional (2D) channel material for high speed flexible electronics complementary inverters 25 𝑚𝑉 22–24 . WSe2 and field effect transistors (FETs) with the ideal subthreshold swing 𝑆𝑆 = 60 𝑑𝑒𝑐𝑎𝑑𝑒 26 have been demonstrated. Furthermore, the strong light interaction, with white light absorption of 5-10% in a monolayer 27, and the giant luminescence at room temperature 28 have been exploited in WSe2- based photodetectors 29,30 or light emitting diodes 31. As for any other semiconducting materials, the control of the doping type and level in WSe2 is an important parameter for its electronic and optoelectronic exploitation and, to date, chemical and substitutional doping are the two major applied doping strategies. The first approach consists of the adsorption of atoms or molecules on the surface of the material, which leads to the alteration of its electronic structure as a consequence of surface charge transfer 26,32 , while substitutional doping of the transition metal or of the chalcogen atoms is pursued in the second approach 33,34. Electric control of carrier concentration by a gate in field-effect transistor structures is another effective way to tune the doping level and type. Such strategy is viable, for instance, in field emission (FE) applications, where electrons are extracted from the material by quantum tunnelling through the surface potential barrier upon the application of a strong electric field. FE is of great relevance to a variety of applications, ranging from electron microscopy and lithography to display technology or vacuum electronics. Indeed, lateral field emission transistors have recently gained popularity due to their potential for many high-frequency and high-power applications 35,36 . In such devices, the traditional approach of placing a gate roughly in between the source (cathode) tip and the drain (anode), has been replaced by a gate behind the emitting tip, controlling its doping level and conductivity. In such a way, a narrower gate voltage can modulate the source-drain field-emission current by depleting or enhancing the carrier density available at the source for tunnelling 37. The gate control of doping and therefore of the FE current is particularly effective when the cathode is made of a low-dimensional material. Indeed, FE current tuning up to six orders of magnitude, by a modest gate voltage up to 20V, has been reported for graphene vertical emitters 38. Also, high emission current 𝑉 density over 0.1 A𝑐𝑚−2 , low turn-on field of few 𝜇𝑚 and sensitive gate modulation were obtained from micro- gated graphene nanomesh field emitter arrays fabricated on a SiO2/Si substrate, used as the back gate 39. The increasing positive gate was observed to lower the turn-on field and increase the field-enhancement factor. Moreover, electron FE in field-effect transistors with vacuum transport parallel to the back-gate substrate have been reported from planar graphene edge sources in which the field emitted electrons have been shown to have an energy spectrum very near the Fermi energy of the graphene source 2 40,41 . Despite the suitable combination of mechanical and electronic properties, to date, only few studies have considered TMDs in field emission devices. TMDs possess atomically sharp edges like graphene, as well as localized defects such as vacancies or substitutional atoms, which can enhance the surface electric field and lower the on-set voltage needed to enhance the tunnelling probability of electrons to vacuum. FE current from MoS2 flakes with low turn-on field and high field enhancement factor has been reported both from the edges 42 and the flat part 43,44 of few-layers MoS2 flakes. The natural n-doping of MoS2, possibly controlled by a back gate, has been pointed out as an important ingredient for future applications of MoS2 FE in vacuum nanoelectronic and flat panel displays. The recent observation of metallic edges in atomically thin WSe 2 monolayers grown by CVD 45 , the lower bandgap (~1.6 vs. ~1.8 eV), effective electron mass (0.33 vs. 0.57 𝑚0 , the rest mass of the electron) and electron affinity (~3.9 vs. ~4.2 eV) 46 would suggest that WSe2 is a far better field emitter than MoS2. Yet, no field emission has been reported from WSe2 layers to date. In this paper, we use CVD to fabricate monolayer and few-layer WSe2 flakes on SiO2/Si substrate and investigate their electrical properties, in high vacuum, using back-gated transistor structures. We show that the WSe2 flakes, contacted by Ni, exhibit n-type conduction, with conductivity highly controlled by the back-gate voltage. Taking advantage of the gate-controlled n-type doping, we locally probe the FE current from a monolayer WSe2 and we achieve a FE current in the range on the 𝜇𝐴 from the flat part of the flake. More importantly, we demonstrate that the FE current can be modulated by the back-gate voltage, thus realizing the first vertical FE transistor based on a WSe2 monolayer. We unveil the physics mechanisms underlying the operation of such a device and give indications for its optimization to enhance its driving current capability and to lower the applied voltage. This study can pave the way to the further exploitation of WSe2 in a new generation of devices for vacuum electronics. Experimental WSe2 flakes, consisting of mono and few layers, were synthesized by CVD on heavily doped p-Si substrates (Boron doped, resistivity < 0.005 𝛺 𝑐𝑚), covered by 300 nm dry thermal SiO2. The CVD growth was performed in a two-zone quartz tube furnace. The growth substrate was placed face down on a WOx seed layer, which was made by sputtering a 20 nm layer of W, using a GATAN 682 Precision Etching and Coating System (PECS), followed by an oxidation step on a hotplate for 1 h at 500 °C. The seed layer-substrate stack creates a microreactor, similar to previous reports on MoS2 growth 47. This microreactor was placed in the centre of the high-temperature zone of the furnace, heated to 850 °C. Se was placed upstream in the lowtemperature heating zone, which was independently heated to 250 °C. A 50 sccm flow of Ar:H2 (9:1) transported Se vapour from the low-temperature zone to the high-temperature zone where it reacted with the WOx in the microreactor. A reaction of 40 minutes and a growth pressure of 6.0±0.2 Torr were used to grow the WSe2 flakes, which, initially selected by optical microscopy, were characterized by Raman and photoluminescence (PL) spectroscopy. Some flakes, identified as monolayers, were used for the fabrication of FETs with Ni/Au (5/50 𝑛𝑚) contacts. The Ni/Au contacts were patterned by electron beam lithography in a 3 sequence of parallel leads for two or four probe measurements. The metals were deposited by sputtering using a Gatan precision etching and coating system. Figure 1 - (a) Layout of a back-gate transistor fabricated with WSe2 on a SiO2/Si substrate. (b) SEM top view of a CVD-grown WSe2 contacted with Ni/Au parallel leads. The device between leads 1 and 2 is used for the electrical measurements. (c) Raman spectrum of the flake under excitation wavelength of 532 nm showing 1 +𝐴 −1 and ~260 𝑐𝑚−1 , respectively. (d) 𝐸2𝑔 1𝑔 peak and 2LA(M) peak at frequencies of ~250 𝑐𝑚 Photoluminescence spectrum of the flake with maximum at ~778 nm and FWHM ~23 𝑐𝑚−1. Both Raman and PL spectra indicate that the flake is a monolayer. Fig. 1(a) shows the layout of a typical device, where the Si substrate, functioning as the back-gate, is connected to a voltage generator and the metal leads, constituting the source and the drain of the transistor, are connected to a source-measurement unit (SMU). Fig. 1(b) shows a scanning electron microscope (SEM) top view of a contacted WSe2 flake. The transistor formed between the leads 1 and 2 corresponds to a WSe 2 channel with length 𝐿 ≈ 2 𝜇𝑚 and average width 𝑊 ≈ 19 𝜇𝑚. The Raman spectrum of the flake with unpolarized incident laser, shown in Fig. 1(c), exhibits two peaks around ~250 𝑐𝑚−1 and ~260 𝑐𝑚−1 . The peak observed at 4 1 and 𝐴 ~250 𝑐𝑚−1 stems from a combination of the 𝐸2𝑔 1𝑔 vibrational modes which correspond to in-plane vibrations of W and Se atoms and out-of-plane vibration of Se atoms, respectively. The peak at ~260 cm-1 corresponds to the 2LA(M) phonons, a second order resonant Raman mode due to LA phonons at the M point in the Brillouin zone 48,49. These peaks, under the excitation wavelength of 532 nm, are typical of a WSe 2 mono and bilayers 50–52 . Finally, Fig. 1(d) reports the photoluminescence spectrum of the flake with an intense and narrow peak at ~778 𝑛𝑚, corresponding to ~1.59 𝑒𝑉 bandgap, a value closer to a monolayer than to a bilayer 50,53 . All electrical measurements were performed with the sample kept inside a Zeiss LEO 1530 SEM chamber in high vacuum (pressure <10-6 Torr) and at room temperature. Two W-tips, mounted on two piezoelectric-driven arms installed inside the SEM chamber, and the SEM sample holder were electrically connected to a semiconductor parameter analyser (Keithley 4200-SCS) working as source-measurement units (SMUs) for the three-terminal characterization of the device. The setup allowed voltage and current measurements with resolution of 10 µV and 10 −13 𝐴, respectively. Results and discussions Transistor characterization - The output characteristics (𝐼𝑑𝑠 - 𝑉𝑑𝑠 , drain-to-source current-voltage curves) of the WSe2 FET are shown in Fig. 2(a) for different gate voltages, 𝑉𝑔𝑠. These curves correspond to a maximum 𝑛𝐴 current lower than 30 𝜇𝑚 , a device resistance higher than several tens 𝑀Ω, and show asymmetry (rectification) between the positive and the negative 𝑉𝑑𝑠 sweeps as well as a modulation by the gate voltage. The rectification ratio, defined as the current ratio at ∓5 𝑉, depends on the gate voltage and is higher at positive 𝑉𝑔𝑠, as reported in Fig. 2(b). We have extensively discussed a similar behaviour in a previous work on MoS2 FETs demonstrating the relevance of the Schottky barriers (SBs) with slightly different heights, formed by the metal lead on the 2D layered channel 54. The local variation of the barrier height can be caused by defects, unreacted precursor (visible for instance under lead 1 in Fig. 1(b)) or other process residues which may cause spatial inhomogeneity of the Schottky barrier height. The gate modulation of the channel current at given drain biases, i.e. the 𝐼𝑑𝑠 − 𝑉𝑔𝑠 transfer characteristics, are shown in Fig. 2(c), both on linear and logarithmic scale. The transfer curves reveal high current at positive 𝑉𝑔𝑠 (“on” state) and current suppression at negative 𝑉𝑔𝑠 (“off” state), thus indicating an n-type conduction with on/off ratio over 103 . WSe2 transistors often show ambipolar conduction, with prevailing p-type behaviour, especially for pristine air-exposed WSe2 contacted by high (> 5.0 𝑒𝑉) work-function metals such as Ni 12,24,55. N-type transistors are fabricated using suitable, low work-function metal contacts, such as Ti, Ag, In, and Al to favour the alignment of the metal Fermi level to the WSe 2 conduction band and achieve small n-type Schottky barrier heights 22,46 . Moreover, on untreated WSe2 devices, the carrier type has been also observed to evolve from p-type to ambipolar, and n-type while increasing the WSe2 channel thickness, due to the change in the bandgap of WSe2 and in the carrier band offsets relative to the metal contacts 56,57 . Oxygen and water, which have low kinetic energy for adsorption, are easily deposited on the air exposed WSe2 surface and cause 5 a p-type doping, which further corroborates p-type behaviour in transistors with high work-function metal contacts 30,58. The desorption of such adsorbates in high vacuum can transform the WSe2 channel from p to ntype and originate the observed high-resistance Schottky Ni contacts. Furthermore, n-type doping of WSe2 can be favoured by positive charges trapped in the SiO2 gate dielectric or at the WSe2/SiO2 interface 59,60 or by interstitial/substitutional W defects resulting from the growth in a tungsten rich atmosphere, as the prevailing triangular shapes of the CVD flakes seem to indicate 61. Figure 2 - Electrical characterization of the WSe 2 FET. (a) Output characteristics at different gate voltages, showing slight rectifying behaviour. (b) Current rectification ratio at ∓5 𝑉 (𝐼𝑑𝑠 (−5𝑉)/𝐼𝑑𝑠 (+5𝑉)) as a function of the gate voltage. (c) Transfer characteristics at different drain biases in linear and logarithmic scale; the inset shows the mobility as a function of the gate voltage. (d) Hysteresis in the transfer characteristics during a 𝑉𝑔𝑠 loop consisting of a reverse and a forward sweep. The threshold voltage, 𝑉𝑡ℎ , which separates the exponentially increasing off-state current from the on-state current, where the dependence on 𝑉𝑔𝑠 becomes a linear or power law, can be estimated from the x-axis intersection of the straight lines fitting the transfer curves in the range 𝑉𝑔𝑠 > 20 𝑉, as shown in Fig. 2(c). Assuming an average 𝑉𝑡ℎ ~16 𝑉 and using the output characteristics, we can evaluate the effective channel 6 𝐿 1 1 𝜕𝐼𝑑𝑠 | , (𝑉 −𝑉 ) 𝜕𝑉 𝑜𝑥 𝑔𝑠 𝑡ℎ 𝑑𝑠 𝑉 =𝑐𝑜𝑠𝑡 𝑔𝑠 mobility 62 as 𝜇𝑒𝑓𝑓 = 𝑊 𝐶 obtaining a value of ~0.01 𝑐𝑚2 𝑉𝑠 at 𝑉𝑔𝑠 = 40 𝑉 (here, 𝐿 and 𝑊 are the channel length and width, 𝐶𝑆𝑖𝑂2 is the capacitance per unit area of the SiO2 gate dielectric: 𝐶𝑆𝑖𝑂2 = 𝜖0 ∙𝜖𝑆𝑖𝑂2 𝑡𝑆𝑖𝑂2 𝐹 = 1.15 ∙ 10−8 𝑐𝑚2 with 𝜖0 the vacuum permittivity, 𝜖𝑆𝑖𝑂2 = 3.9 and 𝑡𝑆𝑖𝑂2 = 300 nm the SiO2 thickness). For a more direct comparison to the literature, we can consider the commonly used field-effect channel mobility, 𝜇𝐹𝐸 , which uses the transconductance rather than the drain conductance, although its definition is rigorous only for 𝑉𝑔𝑠 > 𝑉𝑡ℎ : 𝜇𝐹𝐸 = 𝐿 1 1 𝜕𝐼𝑑𝑠 | 𝑊 𝐶𝑜𝑥 𝑉𝑑𝑠 𝜕𝑉𝑔𝑠 𝑉 𝑑𝑠 =𝑐𝑜𝑠𝑡 The inset of Fig. 2(c) shows 𝜇𝐹𝐸 growing linearly with 𝑉𝑔𝑠 and achieving the value 𝜇𝐹𝐸 ~0.01 with the estimation of 𝜇𝑒𝑓𝑓 . The obtained mobility lies on the low side of the range up to 50 reported for FETs with CVD-grown WSe2 on SiO2 dielectric 6,24,63,64 𝑐𝑚2 𝑉𝑠 consistent 𝑐𝑚2 , 𝑉𝑠 typically . The low value of mobility is likely affected by the high contact resistance due to the presence of Schottky barriers; besides, it points toward a defective device with an interfacial trap density, which can be estimated from the subthreshold slope of the transfer curves. Indeed, the sub-threshold swing 𝑆𝑆, that is the gate voltage change corresponding to one- decade increase of the transistor current, depends on the capacitance per unit area of the trap states, 𝐶𝑇 , and of the channel depletion layer 𝐶𝐷𝐿 : 𝑆𝑆 = 𝑑𝑉𝑔𝑠 𝑑 log 𝐼𝑑𝑠 ≈ ln(10) 𝑘𝑇 𝐶𝑇 + 𝐶𝐷𝐿 (1 + ) 𝑞 𝐶𝑆𝑖𝑂2 (here, 𝑘 is the Boltzmann constant, 𝑇 is the temperature, 𝑞 is the electron charge). The depletion layer capacitance 𝐶𝐷𝐿 can be considered null for atomically thin channels, since it can be assumed that the channel is fully depleted below threshold. From the 𝐼𝑑𝑠 − 𝑉𝑔𝑠 curves of Fig. 3(c), we obtain a relatively high 𝑆𝑆 ~ 15 𝑉 𝑑𝑒𝑐𝑎𝑑𝑒 corresponding to a density of trap states 𝐷𝑇 = with similar estimations reported in the literature 65 𝐶𝑇 𝑞2 ≈ 1.7 ∙ 1013 𝑐𝑚−2 𝑒𝑉 −1 , a value consistent . The presence of traps, which can be filled or emptied during the forward (F) and reverse (R) gate sweep, manifests as a hysteresis in the transfer characteristics as we have reported and extensively studied for MoS2 back-gated transistors 59 . The width of the hysteresis (𝑊~11.5 V at 10-8 A for the transfer obtained with 𝑉𝑑𝑠 = −15 𝑉, see Fig. 2(d)) can be used for a rough evaluation of the charge density trapped during a R-F 𝑉𝑔𝑠 cycle 59: 𝑛𝑡 = 𝑊 𝐶𝑜𝑥 = 8.3 ∙ 1011 𝑐𝑚−2 𝑞 indicating that less than 5% of the available trap states are filled/emptied during the sweep. Figs. 2(c) and 2(d) show that threshold voltage, subthreshold swing, mobility and hysteresis width are affected by the applied drain bias. The dependence of the transistor parameters on 𝑉𝑑𝑠 has been previously studied on similar WSe2 devices and attributed to short channel effects 65. The 𝑉𝑑𝑠 dependence, in the high bias regime, is further investigated in Figs. 3(a) and 3(b), which show the transfer curves, the threshold voltage and the off 7 current for increasing drain bias. As pictured in the inset of Fig. 3(b), for a given 𝑉𝑔𝑠, the increasing absolute value of 𝑉𝑑𝑠 results in a lowering of the Schottky barrier, 𝜙, and a consequent decrease/rise of the threshold voltage/device current. Such an effect, referred to as drain induced barrier lowering (DIBL), can be quantified Δ𝑉𝑡ℎ as | Δ𝑉𝑑𝑠 𝑉 | ≈ 1.1 . 𝑉 Despite the long sweep range, the device does not exhibit a clear transition to p-type conduction (ambipolar behaviour). Here, gate biases higher than 100 V were avoided to prevent device damage. Figure 3 - High-bias electrical characterization of the WSe 2 FET. (a) Transfer characteristics at different drain biases in linear and logarithmic scale. (b) Threshold voltage and off current at 𝑉𝑔𝑠 = −60 𝑉 versus drain bias; the inset shows the drain (1) to source (2) band diagram for increasing drain bias (the brown-dashed curves correspond to lower 𝑉𝑑𝑠 ). WSe2 vertical field emission transistor - The n-type gate-tuneable conduction, combined with the favourable geometrical shape and low electron affinity, suggested the investigation of the field emission properties of the WSe2 flakes. The piezoelectric control of the arms inside the SEM chamber, with W-tips movements at a resolution better than 5 𝑛𝑚, made it possible to establish the direct W-tip/WSe2 electrical contact. This feature allowed electrical measurements on flakes with useless or missing metal leads. More importantly, we exploited such an opportunity to measure the field emission current from the WSe2 to the W-tip positioned at given distance on the top of the flake. Furthermore, using the SEM sample holder electrically connected to the backgate of the sample, we were able to observe, for the first time, a gate-modulated FE current from WSe2 monolayer, thus demonstrating the first WSe2 vertical field emission transistor. The setup used for FE measurements and a SEM image of a measured flake are shown in Figs. 4(a) and 4(b). The flake, which has Raman and PL spectra similar to those reported in Fig. 1, lies partially under a Ni/Au pad, which is used as the source terminal, connected to one of the W-tips. The second W-tip functions as the drain electrode (anode) and can be moved on the flake and accurately positioned at controlled distances 𝑑 from it. The 𝐼𝑑𝑠 − 𝑉𝑑𝑠 curves of Fig. 4(c) are obtained with the drain W-tip in electrical contact with the flake. The 8 similarity with the output characteristics of Fig. 2(a) and the modulation by the gate are evident; moreover, the obvious asymmetry of the contacts enhances the rectifying behaviour and the limited contact area and quality reduces the current. The transfer characteristics of the Fig. 4(d) confirm the n-type behaviour of the WSe2 monolayer and the DIBL effect. Figure 4 - (a) Layout of a back-gate FE transistor with a WSe2 monolayer channel over a SiO2/Si substrate. The W-tip labelled as the drain, which collects field emitted electrons and monitors the current, is kept at a distance 𝑑 from the sample, while the voltage is ramped up. (b) SEM top view of a CVD-grown WSe2 monolayer contacted with a Ni/Au pad (forming the source or cathode) and probed with a W-tip used as the drain (or anode) for the FE current. Output (c) and transfer (d) characteristics of the WSe2 FET with contacts made of a Ni/Au pad and a W-Tip showing a n-type device, strongly affected by drain induced barrier lowering. The FE current was measured with the drain W-tip at distance 𝑑~400 𝑛𝑚 on the top of the flake (Fig. 4(b)). The current was monitored while the voltage was ramped up until 120 V (a constraint imposed to avoid damage of the device or of the measurement setup). The use of a tip-shaped anode is an effective technique to probe the FE of limited areas in alternative to the standard parallel-plate setup that averages the phenomenon over the entire sample 66–70. 9 Fig. 5(a) shows that, when the W-tip is positioned above the WSe2 flake and for a drain voltage up to ~60 𝑉, the current fluctuates around the noise floor < 10−13 𝐴, and there is no measurable charge flow. For 𝑉𝑑𝑠 > 60 𝑉 a steep exponential increase in the current is observed. Although quite noisy, the measured current reasonably follows the behaviour predicted by Fowler-Nordheim (FN) theory of quantum tunnelling through a triangular barrier, as shown in Fig 5(b). According to FN model 71: 𝐼𝑑𝑠 = 𝑆 𝑎 ES2 𝜙3/2 ) ∙ 𝑒𝑥𝑝 (−𝑏 𝜙 𝐸𝑆 where S is the emitting surface area, 𝑎 = 1.54 · 10 −6 𝐴 𝑉 −2 𝑒𝑉 and 𝑏 = 6.83 · 107 𝑉𝑐𝑚−1 𝑒𝑉 −3/2 are constants, 𝐸𝑆 (𝑉𝑐𝑚−1 ) is the electric field at the emitting surface and 𝜙 is the electron affinity of the emitting material, that is ~3.9 𝑒𝑉 for WSe2 . The electric field 𝐸𝑆 =  𝑉𝑑𝑠 /𝑑, with  the so-called field 16,72 enhancement factor, i.e. the ratio between the electric field at the sample surface and the applied field 𝑉𝑑𝑠 /𝑑. 2 The Fowler-Nordheim model is easily checked though the so-called FN plot of 𝑙𝑛(𝐼𝑑𝑠 /𝑉𝑑𝑠 ) vs. 1/𝑉𝑑𝑠, which is expected to exhibit a linear behaviour. Fig. 5(c) refers to the FE current extracted from a nearby region of the flake with the W-tip at the same distance 𝑑~400 𝑛𝑚. Despite the large fluctuations and the dramatic change in the first sweep, it demonstrates a very the important feature, that is the modulation of the FE current by the gate voltage. Indeed, the FE current is enhanced by the application of an increasing positive 𝑉𝑔𝑠. Fig. 5(d) indicates that the modulation of the FE 𝑑𝑉 𝑉 current by 𝑉𝑔𝑠 follows an exponential law, with a 𝑆𝑆 = 𝑑 log𝑔𝑠𝐼 ~33 𝑑𝑒𝑐𝑎𝑑𝑒 comparable to that achieved on the WSe2 FET discussed before. 𝑑𝑠 We remark that the FE curves typically show large instabilities, with peaks, valleys or permanent changes, due to desorption of adsorbates or atomic-level modification of the emitting surface caused by Joule heating. Hence, some electric conditioning is needed to stabilize the emitting surface before undertaking any systematic FE study. Accordingly, we repeated the FE test after a few trial sweeps and obtained the smoother curves of Fig. 6 (a). Such curves, together with the 𝐼𝑑𝑠 − 𝑉𝑔𝑠 transfer characteristic shown in the inset, confirm the exponential voltage-gate modulation of the FE current. Remarkably, the inset of Fig. 6(a) gives a 𝑆𝑆 = 𝑑𝑉𝑔𝑠 𝑑 log 𝐼𝑑𝑠 𝑉 ~30 𝑑𝑒𝑐𝑎𝑑𝑒 , thus consolidating the previous rough estimation through a direct measurement. We remark that the 𝑆𝑆 value could be improved by reducing the gate oxide thickness. Assuming a tip diameter of 𝑛𝐴 0.5 𝜇𝑚, the maximum current of the device attains a value a ~10 𝜇𝑚 , which can be increased by reducing the contact resistance at the source or substantially enhanced by optimizing the field emission extraction process. These observations demonstrate a new device, namely a WSe 2-based vertical field emission transistor. The FN plot of Fig. 6(b), which proves the FE origin of the observed current, can be used to evaluate the field enhancement factor 𝛽 = −𝑏 𝑑 𝜙3/2 /𝑚, where 𝑚 is the slope of the fitting straight lines. The field enhancement factor results ~55 and is independent of the gate voltage, as shown in Fig. 6(c). On the contrary, the turn-on field, defined as the field applied to extract a current of 1 pA, shown in the same figure, decreases linearly with 𝑉𝑔𝑠, with a slope 𝑑𝐸𝑡𝑢𝑟𝑛−𝑜𝑛 𝑑𝑉𝑔𝑠 𝑉 1 𝑉 = 0.7 𝜇𝑚 𝑉 and an average value of 110 𝜇𝑚 over the explored range. 10 Figure 5 - Field emission measurements with the W-tip at a distance 𝑑~400 𝑛𝑚 from the WSe2 flake. (a) FE current measured at floating back-gate and with 𝑉𝑑𝑠 steps of 0.5 V, and (b) corresponding Fowler-Nordheim plot. (c) FE measurements at given 𝑉𝑔𝑠 values and 𝑉𝑑𝑠 steps of 1 V. The corresponding FN plot is shown as inset. (d) Field emission current at 𝑉𝑑𝑠 = 100 𝑉 showing an exponential dependence on 𝑉𝑔𝑠 (the values at 𝑉𝑔𝑠 = −5 𝑉, shown for comparison, refer to floating gate). 𝑉 We notice that an electric field greater than 103 𝜇𝑚 is typically needed to extract electrons from a metal or a semiconductor. The relatively high field or, equivalently, low field enhancement factor (good emitters achieve 𝛽~1000 or more) here obtained are caused by the fact that we have extracted electrons from the flat part of the flake, without taking advantage from the 2D shape of the flake. The geometrical field enhancement would greatly increase the FE current if the extraction was performed from the sharp edge of the flake. The vertical electron emission from the surface of 2D materials might require a modification of the FN to account for the reduced dimensionality, the energy spectrum, the non-conserving in-plane electron momentum, the finite-temperature and the space-charge-limited effects. A better fit of the experimental data, as shown in 11 the inset of Fig. 6b, can be achieved considering the new high-field regime, 𝐼𝑑𝑠 ∼ exp(−𝑏Φ3/2 /𝐸𝑆 ), of saturated surface field emission proposed for 2D materials.73 Figure 6 - Field emission measurements after electrical conditioning, with the W-tip at a distance 𝑑~400 𝑛𝑚 from the WSe2 monolayer. (a) FE current measured at given back-gate voltages (𝑉𝑑𝑠 steps of 1 V), and (b) corresponding Fowler-Nordheim plot (the inset shows the modified F-N plot to consider the effects related to the 2D nature of the emitter). (c) Turn-on field and field enhancement factor versus 𝑉𝑔𝑠. (d) Field emission 12 current stability at 𝑉𝑑𝑠 = 60 𝑉 and 𝑉𝑑𝑠 = 80 𝑉 (the gate current is monitored as well). (e) Band diagram for (e) the unbiased device and for (f) the device under 𝑉𝑑𝑠 > 𝑉𝑔𝑠 > 0 𝑉 bias condition. Fig. 6 (d) shows that the field emission current has high stability, checked over a time of half an hour, to enable practical applications of the proposed FE transistor. Finally, Fig. 6 (e) and 6 (f) display the energy band diagram along the vertical direction for the unbiased and biased (𝑉𝑑𝑠 > 𝑉𝑔𝑠 > 0 𝑉 ) devices and clarify the proposed physical mechanism underlying the operation of the device. The application of a positive gate voltage induces n-doping in the WSe2 channel. The availability of electrons impinging on the field narrowed vacuum barrier, resulting from the 𝑉𝑑𝑠 voltage, favors the FE current, which is thereby gate-controlled. In a further development, electrons could be emitted from the edge of the flake which would substantially enhance the drive current capability of the device and lower the operational voltages. Also, a reduced source contact resistance and a thinner gate dielectric would enhance the channel conductance and the transconductance of the device. Obviously, this requires a more complex layout and is the matter for further dedicated work. Conclusions We have synthesized and characterized WSe 2 monolayers on a SiO2/Si substrate, which we have contacted by Ni to form back-gated field effect transistors. We have taken advantage of the gate-controlled n-type conduction of the WSe2 flakes to report, for the first time, their field emission properties. We have shown that electrons can be efficiently extracted from the flat part of a WSe2 monolayer upon the application of an electric 𝑉 field ~100 𝜇𝑚. We have proven that the field emission current can be modulated by the back gate and is stable. We have thereby demonstrated the first vertical field emission transistor suggesting a model for the underlying physics mechanisms. The device can be optimized by reducing the thickness of the gate dielectric to improve its transconductance and by reducing the source contact resistance to increase its current driving capability. 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