High-Level Synthesis Countermeasure Using Threshold Implementation with Mixed Number of Shares
Pages 18 - 26
Abstract
In recent years, there has been widespread adoption of the Internet of Things (IoT) devices, some of which involve the processing of sensitive information. In such devices, cipher-dedicated circuits are often used to encrypt sensitive information. However, the cipher circuits may be still vulnerable to side-channel attacks (SCA), such as differential power analysis (DPA) which exploits information by analyzing power consumption. To cope with DPA, threshold implementation (TI), a masking method which provides provable security, can be adopted in cipher circuits implementation. From the design-productivity perspective, integrating TI into the state-of-the-art high-level synthesis (HLS)-based design flow for cipher circuits implementation is ideal. In this approach, however, mitigating the hardware resource overhead is challenging as have been observed in previous work. In this paper, we propose a novel HLS-based countermeasure that mixes different numbers of shares to reduce the hardware overhead. Our countermeasure demonstrates secure against SCA while simultaneously reducing resource utilization along with a small latency overhead.
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Index Terms
- High-Level Synthesis Countermeasure Using Threshold Implementation with Mixed Number of Shares
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June 2024
147 pages
ISBN:9798400717277
DOI:10.1145/3665283
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Published: 19 June 2024
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HEART 2024
HEART 2024: 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
June 19 - 21, 2024
Porto, Portugal
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