Lateral NWFET optimization for beyond 7nm nodes
D Yakimets, D Jang, P Raghavan… - … Conference on IC …, 2015 - ieeexplore.ieee.org
2015 International Conference on IC Design & Technology (ICICDT), 2015•ieeexplore.ieee.org
In this study, different S/D contacting options for lateral NWFET devices are benchmarked at
7nm node dimensions and beyond. Comparison is done at both DC and ring oscillator
levels. It is demonstrated that implementing a direct contact to a fin made of Si/SiGe super-
lattice results in 13% performance improvement. Also, we conclude that the integration of
internal spacers between the NWs is a must for lateral NWFETs in order to reduce device
parasitic capacitance.
7nm node dimensions and beyond. Comparison is done at both DC and ring oscillator
levels. It is demonstrated that implementing a direct contact to a fin made of Si/SiGe super-
lattice results in 13% performance improvement. Also, we conclude that the integration of
internal spacers between the NWs is a must for lateral NWFETs in order to reduce device
parasitic capacitance.
In this study, different S/D contacting options for lateral NWFET devices are benchmarked at 7nm node dimensions and beyond. Comparison is done at both DC and ring oscillator levels. It is demonstrated that implementing a direct contact to a fin made of Si/SiGe super-lattice results in 13% performance improvement. Also, we conclude that the integration of internal spacers between the NWs is a must for lateral NWFETs in order to reduce device parasitic capacitance.
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