A 14nm logic technology using 2 nd -generation FinFET transistors with a novel subfin
doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-…

We propose a compact model for nanosheet FETs that take the effects of quantum confinement
into account. The model captures the nanosheet width and thickness dependence of the …

In this letter, an analytical surface potential based compact model for thermal noise in high
electron mobility transistors (HEMTs) is presented. The model is based on the recently …

This work presents new compact models that capture advanced physical effects presented in
industry FinFETs. The presented models are introduced into the industry standard compact …

We present compact models that capture published cryogenic temperature effects on silicon
carrier mobility and velocity saturation, as well as fully depleted silicon on insulator (FDSOI) …

In this paper, a surface-potential-based compact model is proposed for the capacitance of an
AlGaN/GaN high-electron mobility transistor (HEMT) dual field-plate (FP) structure, ie, with …

A deep learning (DL) technique to extract the set of Berkeley short-channel IGFET model-common
multigate (BSIM-CMG) compact model parameters directly from experimental …

We present a surface potential-based compact model for nanowire FETs, which considers 1-D
electrostatics along with the effect of multiple energy subbands. The model is valid for any …

We model the effects of cross-sectional radius scaling on ${C}$ – ${V}$ and ${I}$ – ${V}$
characteristics of gate-all-around FETs (GAAFETs), capturing the continuous transition from a 3-…

Nanosheet gate-all-around transistors are analyzed for RF applications using calibrated
TCAD simulations. The effects of stack spacing and number of stacks on device performance …