A customizable multiprocessor for globally asynchronous locally synchronous execution
Proceedings of the 7th International Workshop on Java Technologies for Real …, 2009•dl.acm.org
This paper presents a novel execution architecture for Globally Asynchronous Locally
Synchronous (GALS) systems, in our case particularly targeting system level programming
language SystemJ. SystemJ extends Java with both synchronous and asynchronous
concurrency and reactivity to control program execution. The proposed architecture is based
on separating the control-driven and data-driven operations onto two types of processors,
respectively control and data processors, and it is aimed at complex embedded applications …
Synchronous (GALS) systems, in our case particularly targeting system level programming
language SystemJ. SystemJ extends Java with both synchronous and asynchronous
concurrency and reactivity to control program execution. The proposed architecture is based
on separating the control-driven and data-driven operations onto two types of processors,
respectively control and data processors, and it is aimed at complex embedded applications …
This paper presents a novel execution architecture for Globally Asynchronous Locally Synchronous (GALS) systems, in our case particularly targeting system level programming language SystemJ. SystemJ extends Java with both synchronous and asynchronous concurrency and reactivity to control program execution. The proposed architecture is based on separating the control-driven and data-driven operations onto two types of processors, respectively control and data processors, and it is aimed at complex embedded applications designed as GALS. The control processor is introduced to execute efficiently the control constructs, which implement concurrency, reactivity, and control flow in SystemJ. The data processor executes the Java data-driven transformational operations and can be any traditional processor. Control and data processors form hybrid multiprocessors, called GALS multiprocessors, which can then be easily customized for specific application and are implemented as a system on programmable chip (SoPC). Benchmarks show significant improvement in code size and execution speed of the resulting architecture over traditional processors.
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