Erdin et al., 2017 - Google Patents
Analysis of decoupling capacitors inside via arrays with mutual interactionErdin et al., 2017
- Document ID
- 11442333882761968337
- Author
- Erdin I
- Achar R
- Publication year
- Publication venue
- 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)
External Links
Snippet
A new method is developed to assess the effectiveness of local decoupling capacitors on parallel-plate power and ground conductors. The proposed method calculates the loop- inductance of multiple capacitors including their mutual interactions and the effect of power …
- 239000003990 capacitor 0 title abstract description 45
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K9/00—Screening of apparatus or components against electric or magnetic fields
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Fan et al. | Quantifying SMT decoupling capacitor placement in DC power-bus design for multilayer PCBs | |
Archambeault et al. | Analysis of power/ground-plane EMI decoupling performance using the partial-element equivalent circuit technique | |
US7149666B2 (en) | Methods for modeling interactions between massively coupled multiple vias in multilayered electronic packaging structures | |
US5566083A (en) | Method for analyzing voltage fluctuations in multilayered electronic packaging structures | |
Ye et al. | EMI mitigation with multilayer power-bus stacks and via stitching of reference planes | |
Erdin et al. | Multipin optimization method for placement of decoupling capacitors using a genetic algorithm | |
Kim et al. | Inductance calculations for plane-pair area fills with vias in a power distribution network using a cavity model and partial inductances | |
Erdin et al. | Efficient decoupling capacitor placement based on driving point impedance | |
Wang et al. | Variability analysis of crosstalk among differential vias using polynomial-chaos and response surface methods | |
Sun et al. | A pattern-based analytical method for impedance calculation of the power distribution network in mobile platforms | |
Fan et al. | Lumped-circuit model extraction for vias in multilayer substrates | |
Lee et al. | Analysis and suppression of SSN noise coupling between power/ground plane cavities through cutouts in multilayer packages and PCBs | |
Riener et al. | 3D modeling of inductive and capacitive coupling between surface‐mounted multilayer‐capacitors | |
Erdin et al. | Analysis of decoupling capacitors inside via arrays with mutual interaction | |
Yuan et al. | A systematic coupled approach for electromagnetic susceptibility analysis of a shielded device with multilayer circuitry | |
Park et al. | Fast and accurate calculation of system-level ESD noise coupling to a signal trace by PEEC model decomposition | |
Roy et al. | Macromodeling of multilayered power distribution networks based on multiconductor transmission line approach | |
Deutsch et al. | Application of the short-pulse propagation technique for broadband characterization of PCB and other interconnect technologies | |
Xu | System level power integrity transient analysis using a physics-based approach | |
Umekawa | Simple modeling method of EMI simulation for PCB | |
Chen | PCB microstrip line far-end crosstalk mitigation by surface mount capacitors | |
Berbel et al. | Modeling technique of the conducted emission of integrated circuit under different temperatures | |
Fizeşan et al. | Power integrity design tips to minimize the effects of mounting inductance of decoupling capacitors | |
Barnes et al. | Benchmarking and Reproducibility in Computational and Experimental Characterization of Electronic Packages for Signal/Power Integrity: Four benchmarks serve as standardized cases | |
Phyu et al. | Analysis of electromagnetic susceptibility on high speed circuits located in a shielded enclosure |