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WO2024244774A1 - 一种超声换能器装置及显示装置 - Google Patents

一种超声换能器装置及显示装置 Download PDF

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Publication number
WO2024244774A1
WO2024244774A1 PCT/CN2024/088347 CN2024088347W WO2024244774A1 WO 2024244774 A1 WO2024244774 A1 WO 2024244774A1 CN 2024088347 W CN2024088347 W CN 2024088347W WO 2024244774 A1 WO2024244774 A1 WO 2024244774A1
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WO
WIPO (PCT)
Prior art keywords
ultrasonic
transistor
electrode
ultrasonic transducer
electrically connected
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Application number
PCT/CN2024/088347
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English (en)
French (fr)
Inventor
秦云科
佟月
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Publication of WO2024244774A1 publication Critical patent/WO2024244774A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
    • B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
    • B06B1/06—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
    • B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
    • B06B3/00—Methods or apparatus specially adapted for transmitting mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays

Definitions

  • the present disclosure relates to the field of ultrasonic transducer technology, and in particular to an ultrasonic transducer device and a display device.
  • Fingerprints are unique and invariable features of the human body that can be distinguished from others. They are composed of a series of ridges and valleys on the surface of the fingertips. The composition details of these ridges and valleys determine the uniqueness of the fingerprint pattern. Display panels with fingerprint recognition functions have been developed for personal identity authentication, increasing the information security of display devices. At present, there are many developed fingerprint recognition technologies, and ultrasonic fingerprint recognition is one of them.
  • Existing fingerprint recognition technologies can be mainly divided into optical fingerprint recognition, capacitive fingerprint recognition and ultrasonic fingerprint recognition according to their working principles.
  • optical fingerprint recognition is strongly affected by external light, and the speed and accuracy of fingerprint recognition will decrease under strong external light; capacitive fingerprint recognition cannot accurately determine the dielectric constant of oil and water when there are oil stains and stains on the user's fingers, resulting in reduced speed and accuracy of fingerprint recognition.
  • ultrasonic fingerprint recognition technology relies on the advantages of good penetration, short wavelength and high energy of ultrasonic waves, and can achieve higher recognition speed and recognition accuracy in various usage scenarios (including strong light scenarios, scenarios with oil stains or stains on fingers).
  • the embodiments of the present disclosure provide an ultrasonic transducer device and a display device, and the specific scheme is as follows:
  • An ultrasonic transducer device provided in an embodiment of the present disclosure includes a substrate, wherein the substrate includes a plurality of ultrasonic units distributed in an array, and each of the ultrasonic units includes:
  • a thin film transistor circuit is arranged on the substrate;
  • At least one first ultrasonic transducer is arranged on the side of the thin film transistor circuit away from the base substrate, the first ultrasonic transducer includes a first electrode, a first vibration membrane layer and a second electrode stacked and arranged on the side of the thin film transistor circuit away from the base substrate, a cavity is provided between the first electrode and the first vibration membrane layer, the first electrode is electrically connected to the thin film transistor circuit, and the second electrode is electrically connected to the driving voltage line.
  • the ultrasonic transducer device provided in the embodiment of the present disclosure further includes a plurality of drive signal lines for loading drive signals to the thin film transistor circuit, and at least two adjacent rows of ultrasonic units share the same drive signal line, or at least two adjacent columns of ultrasonic units share the same drive signal line.
  • the thin film transistor circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, and a storage capacitor;
  • the drive signal line includes: a first gate line, a second gate line, a third gate line, a first voltage line, a second voltage line, the drive voltage line and a signal reading line;
  • the gate of the first transistor is electrically connected to the first gate line, the first electrode of the first transistor is electrically connected to the first voltage line, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor;
  • the gate of the second transistor is electrically connected to the second gate line, and the second electrode of the second transistor is electrically connected to the gate of the third transistor;
  • a first electrode of the third transistor is electrically connected to the second voltage line, and a second electrode of the third transistor is electrically connected to a first electrode of the fourth transistor;
  • the gate of the fourth transistor is electrically connected to the third gate line, and the second The electrode is electrically connected to the signal reading line;
  • a first end of the storage capacitor is electrically connected to the second voltage line, and a second end of the storage capacitor is electrically connected to the gate of the third transistor;
  • the first electrode of the first ultrasonic transducer is electrically connected to the first electrode of the second transistor.
  • every two adjacent columns of the ultrasonic units constitute a first group
  • a driving voltage line is provided at the first gap between the two columns of the ultrasonic units in the first group
  • the second electrodes of the first ultrasonic transducers in the two columns of the ultrasonic units of the same first group are electrically connected to the driving voltage line at the first gap.
  • the first gate line spaced apart from the driving voltage line is also provided at the first gap, and the gates of the first transistors in the two columns of the ultrasonic units of the same first group are electrically connected to the first gate line at the first gap.
  • a second voltage line is arranged at the second gap between each two adjacent first groups of ultrasonic units, and the second voltage line is electrically connected to the first electrodes of all the third transistors in the two columns of ultrasonic units on both sides thereof.
  • two adjacent columns of ultrasonic units in the same first group are symmetrically arranged about the first gap, and two adjacent first groups of ultrasonic units are symmetrically arranged about the second gap.
  • every two adjacent rows of the ultrasonic units form a second group
  • a first voltage line is arranged at the third gap between the two rows of the ultrasonic units in the second group, and the first electrodes of all the first transistors in the two rows of the ultrasonic units of the same second group are electrically connected to the first voltage line at the third gap.
  • a first gap is provided at the fourth gap between each adjacent two ultrasonic units of the second group.
  • a second gate line wherein the second gate line is electrically connected to the gates of all the second transistors in the two rows of the ultrasonic units on both sides thereof.
  • two adjacent columns of ultrasonic units in the same second group are symmetrically arranged about the third gap, and two adjacent columns of ultrasonic units in the second group are symmetrically arranged about the fourth gap.
  • the number of the first ultrasonic transducers in each of the ultrasonic units is 1 or 2, and the orthographic projection of each of the first ultrasonic transducers on the substrate does not overlap with the orthographic projection of the thin film transistor circuit and each signal line on the substrate.
  • the number of the first ultrasonic transducers in each of the ultrasonic units is 3, and the orthographic projection of each of the first ultrasonic transducers on the substrate overlaps with the orthographic projection of the thin film transistor circuit and other signal lines on the substrate.
  • the first electrodes of each of the first ultrasonic transducers in the same ultrasonic unit are an integral structure
  • the second electrodes of each of the first ultrasonic transducers in the same ultrasonic unit are an integral structure
  • the cavities of each of the first ultrasonic transducers in the same ultrasonic unit are separated from each other by the first vibration membrane layer.
  • the width-to-length ratio of the third transistor is greater than or equal to the width-to-length ratio of the fourth transistor.
  • At least one of the first transistor, the second transistor, the third transistor and the fourth transistor is a dual-gate transistor.
  • the active layer of the third transistor and the active layer of the fourth transistor are an integrated structure
  • the second electrode of the third transistor and the first electrode of the fourth transistor are an integrated structure
  • the second electrode of the third transistor is electrically connected to the active layer of the third transistor.
  • the substrate further includes a virtual ultrasonic unit located outside the plurality of ultrasonic units distributed in the array, the virtual ultrasonic unit includes the thin film transistor circuit and a second ultrasonic transducer, the second ultrasonic transducer includes a third electrode, a second vibration membrane layer and a fourth electrode stacked on a side of the thin film transistor circuit away from the substrate, a sacrificial layer is provided between the third electrode and the second vibration membrane layer, the third electrode is electrically connected to the thin film transistor circuit, and the fourth electrode is electrically connected to the driving voltage line.
  • an embodiment of the present disclosure further provides a display device, including a display panel and the above-mentioned ultrasonic transducer device provided by an embodiment of the present disclosure.
  • the display panel is a liquid crystal display panel
  • each of the ultrasonic units in the ultrasonic transducer device is arranged in a non-luminous area within the liquid crystal display panel.
  • the display panel is an organic light-emitting display panel
  • the ultrasonic transducer device is disposed on the back side of the organic light-emitting display panel.
  • FIG1 is a schematic diagram of a planar structure of an ultrasonic transducer device provided in an embodiment of the present disclosure
  • FIG2 is a schematic cross-sectional view of an ultrasonic unit in FIG1 ;
  • FIG3 is a schematic diagram of a specific circuit of a thin film transistor circuit
  • FIG4 is a schematic diagram of the working timing of the thin film transistor circuit shown in FIG3 ;
  • FIG5 is a schematic diagram of a layout corresponding to several ultrasonic units in FIG1 ;
  • FIG6 is a schematic diagram of another layout corresponding to several ultrasonic units in FIG1 ;
  • FIG7 is a schematic diagram of another layout corresponding to several ultrasonic units in FIG1 ;
  • FIG8 is a schematic diagram of another layout corresponding to several ultrasonic units in FIG1;
  • FIG9 is a schematic diagram of another layout corresponding to several ultrasonic units in FIG1 ;
  • FIG10 is a schematic diagram of another layout corresponding to several ultrasonic units in FIG1 ;
  • FIG11 is a schematic diagram of another layout corresponding to several ultrasonic units in FIG1 ;
  • FIG12 is a schematic diagram of another layout corresponding to several ultrasonic units in FIG1 ;
  • FIG13 is a schematic diagram of another layout corresponding to several ultrasonic units in FIG1 ;
  • FIG14 is a schematic diagram of another layout corresponding to several ultrasonic units in FIG1 ;
  • FIG15 is a schematic diagram of another layout corresponding to several ultrasonic units in FIG1 ;
  • FIG16 is a schematic diagram of another planar structure of the ultrasonic transducer device provided in an embodiment of the present disclosure.
  • FIG17 is a schematic diagram of another layout corresponding to several ultrasonic units in FIG1 ;
  • FIG18 is a schematic diagram of the structure of a display device provided by an embodiment of the present disclosure.
  • FIG. 19 is a schematic diagram of the structure of another display device provided in an embodiment of the present disclosure.
  • the ultrasonic fingerprint recognition is PVDF ultrasonic fingerprint recognition, which is not affected by external light and does not require a display screen to provide a light source. It can realize 3D fingerprint and deep skin information detection and has strong anti-counterfeiting capabilities.
  • the technology is monopolized by Qualcomm and requires special PVDF materials and special polarization equipment, which is relatively expensive.
  • an embodiment of the present disclosure provides an ultrasonic transducer device, as shown in FIG1 , including a substrate substrate 1, the substrate substrate 1 including a plurality of ultrasonic units P distributed in an array; as shown in FIG2 , FIG2 is a cross-sectional schematic diagram of an ultrasonic unit P in FIG1 , each ultrasonic unit P including:
  • a thin film transistor circuit 2 is arranged on the base substrate 1;
  • At least one first ultrasonic transducer 3 is arranged on the side of the thin film transistor circuit 2 away from the substrate substrate 1.
  • the first ultrasonic transducer 3 includes a first electrode 31, a first vibration membrane layer 32 and a second electrode 33 stacked on the side of the thin film transistor circuit 2 away from the substrate substrate 1.
  • a cavity 34 is provided between the first electrode 31 and the first vibration membrane layer 32.
  • the first electrode 31 is electrically connected to the thin film transistor circuit 2, and the second electrode 33 is electrically connected to the driving voltage line.
  • the ultrasonic transducer (CMUT) device provided in the embodiment of the present disclosure combines a thin-film transistor circuit with an ultrasonic transducer to form a large-area, arrayed ultrasonic fingerprint recognition structure, which is capable of fingerprint recognition and has a simple structure and high recognition accuracy.
  • CMUT ultrasonic transducer
  • the main functions of CMUT are: in the transmitting stage, the transducer converts the input electrical energy into mechanical energy and transmits it under the action of the excitation signal to realize the transmission of ultrasonic waves; in the receiving stage, the transducer converts the sound waves into electrical signals to realize the reception of ultrasonic waves. Therefore, the ultrasonic unit in the ultrasonic transducer (CMUT) device provided in the embodiment of the present disclosure can be combined with the display panel.
  • the ultrasonic wave is transmitted to the person's finger. Since the ridges and valleys on the surface of the finger have different reflection intensities for the ultrasonic signal, the ultrasonic energy reflected by the ridges and valleys of the finger is different. By converting this energy difference into a difference in electrical signals, the ridges and valleys of the fingerprint can be imaged, and then fingerprint recognition can be performed.
  • the material of the first vibration membrane layer may be PI or PET, etc.
  • the substrate may be a rigid substrate, such as a glass substrate; or a flexible substrate.
  • Substrate such as PI.
  • the ultrasonic transducer provided in the embodiment of the present disclosure is made of a glass-based or flexible PI-based material, can have a larger area, and can flexibly fit the surface of the human body and objects, which has advantages far exceeding those of silicon-based CMUT devices.
  • the thin film transistor circuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a storage capacitor CB ; wherein,
  • the gate of the first transistor T1 is electrically connected to the first gate line G1, the first electrode of the first transistor T1 is electrically connected to the first voltage line Vbias, and the second electrode of the first transistor T1 is electrically connected to the first electrode of the second transistor T2;
  • the gate of the second transistor T2 is electrically connected to the second gate line G2, and the second electrode of the second transistor T2 is electrically connected to the gate of the third transistor T3;
  • a first electrode of the third transistor T3 is electrically connected to the second voltage line Vdd, and a second electrode of the third transistor T3 is electrically connected to a first electrode of the fourth transistor T4;
  • a gate of the fourth transistor T4 is electrically connected to the third gate line G3, and a second electrode of the fourth transistor T4 is electrically connected to the signal reading line Vread;
  • a first end of the storage capacitor CB is electrically connected to the second voltage line Vdd, and a second end of the storage capacitor CB is electrically connected to the gate of the third transistor T3;
  • the first electrode of the first ultrasonic transducer 3 is electrically connected to the first electrode of the second transistor T2 , and the second electrode 33 of the first ultrasonic transducer 3 is electrically connected to the driving voltage line Vda; wherein Vda is used to input a DC voltage Vdc and an AC voltage Vda to the second electrode 33 .
  • the thin film transistor circuit shown in FIG3 is only one of the circuit structures listed in the embodiments of the present disclosure.
  • the thin film transistor circuit in the embodiments of the present disclosure is not limited to the structure shown in FIG3.
  • Other circuits that can be combined with the first ultrasonic transducer to realize ultrasonic fingerprint recognition all fall within the scope of protection of the embodiments of the present disclosure.
  • the first transistor T1 includes a first active layer 11, a first gate 12, a first source 13 and a first drain 14 which are sequentially stacked between the substrate 1 and the first ultrasonic transducer 3
  • the second transistor T2 includes a first active layer 11, a first gate 12, a first source 13 and a first drain 14 which are sequentially stacked between the substrate 1 and the first ultrasonic transducer 3.
  • the first ultrasonic transducer 3 includes a second active layer 21, a second gate 22, a second source 23 and a second drain 24, the third transistor T3 includes a third active layer 41, a third gate 42, a third source 43 and a third drain 44 which are sequentially stacked between the substrate 1 and the first ultrasonic transducer 3, and the fourth transistor T4 includes a third active layer 41, a fourth gate 51, a third source 43 and a third drain 44 which are sequentially stacked between the substrate 1 and the first ultrasonic transducer 3, that is, the fourth transistor T4 can share the active layer, source and drain with the third transistor T4.
  • the first active layer 11, the second active layer 21 and the third active layer 41 are located in the same film layer (active layer)
  • the first gate 12, the second gate 22, the third gate 42 and the fourth gate 51 are located in the same film layer (Gate1 layer)
  • the first electrode C1 of the storage capacitor CB is located in the Gate1 layer
  • the second electrode C2 of the storage capacitor CB is located in the Gate2 layer
  • the first source 13, the first drain 14, the second source 23, the second drain 24, the third source 43 and the third drain 44 are located in the same film layer (SD layer).
  • the first electrode of each transistor in FIG. 3 may be a source electrode, and the second electrode may be a drain electrode; of course, the first electrode may be a drain electrode, and the second electrode may be a source electrode.
  • a light shielding layer LS is further provided between the substrate 1 and the active layer.
  • the light shielding layer LS can be used to shield the active layer, and can also be used to replace the Gate1 layer and the Gate2 layer to form a storage capacitor C B (This is illustrated in the present disclosure);
  • a first buffer layer 6 is further arranged between the light-shielding layer LS and the active layer
  • a first gate insulating layer 7 is further arranged between the active layer and the Gate1 layer
  • a second gate insulating layer 8 is further arranged between the Gate1 layer and the Gate2 layer
  • an interlayer insulating layer 9 is further arranged between the Gate2 layer and the SD layer
  • a flat layer 10 is further arranged between the SD layer and the first ultrasonic transducer 3
  • a first passivation layer 20 is further arranged between the flat layer 10 and the first ultrasonic transducer 3
  • a first electrode 31 of the first ultrasonic transducer 3 is electrically connected to the first electrode (second drain 24)
  • the cavity 34 can be made by using a sacrificial layer, and the sacrificial layer is etched with a hole 35 .
  • the manufacturing method of the sacrificial layer is the same as that of the prior art, and will not be described in detail herein.
  • stage t1 (ultrasonic emission stage) both DC voltage Vdc and AC voltage Vac are applied to the second electrode of CMUT, the first transistor T1 and the second transistor T2 are turned on, the first voltage line Vbias is at a constant potential, and the first vibration membrane layer of CMUT vibrates at a high frequency to emit sound waves.
  • the t2 stage (collection stage) only the DC voltage Vdc needs to be added to the left end of the CMUT, and no AC voltage Vac is needed.
  • the first transistor T1 is turned off, and the second transistor T2 is turned on.
  • the external sound wave signal is reflected by the finger and reaches the CMUT, pressing the first vibration membrane layer to vibrate and generate AC current (charge).
  • the AC amplitude within the half cycle is collected and the charge is stored in the storage capacitor CB .
  • the third transistor T3 and the fourth transistor T4 are turned on, and the charge stored in the storage capacitor CB is converted into current through the third transistor T3, and finally output through the fourth transistor T4.
  • the output current is read through the signal reading line Vread to realize fingerprint recognition.
  • the reading in the t3 stage may not be performed directly, that is, there may be a buffer stage t3' between the t2 stage and the t3 stage, and the t3 stage may be performed when reading is needed.
  • the voltage on the first voltage line Vbias may be lowered to reduce power consumption.
  • FIG. 5-FIG. 8 are respectively schematic layout diagrams corresponding to several ultrasonic units P in FIG. 1, and the ultrasonic transducer device includes a plurality of drive signal lines for loading drive signals to the thin film transistor circuit, and the drive signal lines include a first gate line G1, a second gate line G2, a third gate line, a first voltage line Vbias, a second voltage line Vdd, a drive voltage line Vda, and a signal reading line Vread, and at least two adjacent rows of ultrasonic units P share the same drive signal line (for example, Vbias is shared), or at least two adjacent columns of ultrasonic units P share the same drive signal line (for example, Vbias is shared).
  • Vbias is shared
  • Vbias is shared
  • the first gate line G1, the second voltage line Vdd and the signal read line Vread can be located in the SD layer
  • the second gate line G2 and the third gate line G3 can be located in the Gate1 layer
  • the first voltage line Vbias can be located in the Gate2 layer
  • the driving voltage line Vda and the second electrode 33 are located in the same layer.
  • every two adjacent columns of ultrasonic units P form a first group A1, and a driving voltage line Vda is provided at the first gap B1 between the two columns of ultrasonic units P in the first group A1, and the second electrodes 33 of the first ultrasonic transducers 3 in the two columns of ultrasonic units P of the same first group A1 are electrically connected to the driving voltage line Vda at the first gap B1.
  • two adjacent columns of ultrasonic units P share a driving voltage line Vda, which can save space, simplify the design, and is conducive to high-resolution design.
  • a first gate line G1 spaced apart from the driving voltage line Vda is further provided at the first gap B1, and the gates of the first transistors T1 in the two columns of ultrasonic units P of the same first group A1 are electrically connected to the first gate line G1 at the first gap B1.
  • two adjacent columns of ultrasonic units P share a first gate line G1, which can further save space, further simplify the design, and facilitate further high-resolution design.
  • a second voltage line Vdd is provided at the second gap B2 between each two adjacent first groups (A1) of ultrasonic units P, and the second voltage line Vdd is electrically connected to the first electrodes of all third transistors T3 in the two columns of ultrasonic units P on both sides thereof.
  • two adjacent columns of ultrasonic units P share a second voltage line Vdd, which can further save space, further simplify the design, and facilitate further high-resolution design.
  • the ultrasonic transducer device provided in the embodiment of the present disclosure, as shown in Fig. 5 and Fig. 6, two adjacent columns of ultrasonic units P in the same first group A1 are symmetrically arranged about the first gap B1, and two adjacent first groups (A1) of ultrasonic units P are symmetrically arranged about the second gap B2.
  • the adjacent left and right ultrasonic units P are mirror-symmetrical structures, and the size of each ultrasonic unit P can be 75 microns*75 microns, but is certainly not limited thereto.
  • every two adjacent rows of ultrasonic units P form a second group A2, and a first voltage line Vbias is provided at the third gap B3 between two rows of ultrasonic units P in the second group A2, and the first electrodes of all first transistors T1 in the two rows of ultrasonic units P of the same second group A2 are electrically connected to the first voltage line Vbias at the third gap B3.
  • two adjacent rows of ultrasonic units P share a first voltage line Vbias, which can further save space, further simplify the design, and facilitate further high-resolution design.
  • a second gate line G2 is provided at the fourth gap B4 between each two adjacent second groups (A2) of ultrasonic units P, and the second gate line G2 is electrically connected to the gates of all second transistors T2 in the two rows of ultrasonic units P on both sides thereof.
  • two adjacent rows of ultrasonic units P share a second gate line G2, which can further save space, further simplify the design, and facilitate further high-resolution design.
  • the ultrasonic transducer device provided in the embodiment of the present disclosure, as shown in Fig. 7 and Fig. 8, two adjacent columns of ultrasonic units P in the same second group A2 are symmetrically arranged about the third gap B3, and two adjacent second groups (A2) of ultrasonic units P are symmetrically arranged about the fourth gap B4.
  • four adjacent ultrasonic units P in the upper, lower, left and right directions are mirror-symmetrical structures, and the size of each ultrasonic unit P can be 75 microns*75 microns, but is certainly not limited thereto.
  • Figure 5 takes two adjacent columns of ultrasonic units P sharing a driving voltage line Vda and two adjacent columns of ultrasonic units P sharing a second voltage line Vdd as an example
  • Figure 6 takes two adjacent columns of ultrasonic units P sharing a first gate line G1 as an example based on Figure 5
  • Figure 7 takes two adjacent rows of ultrasonic units P sharing a first voltage line Vbias as an example based on Figure 5
  • Figure 8 takes two adjacent rows of ultrasonic units P sharing a first voltage line Vbias and two adjacent rows of ultrasonic units P sharing a second gate line G2 as an example based on Figure 5.
  • the above-mentioned ultrasonic transducer device provided in the embodiment of the present disclosure can simultaneously adopt Vda sharing, Vdd sharing, G1 sharing, Vbias sharing, and G2 sharing, and of course, it can also choose to adopt one or more signal line sharing methods.
  • the above-mentioned common signal lines may not be shared. As shown in FIG. 9 , the gap between the ultrasonic units contains all the complete signal lines.
  • the number of the first ultrasonic transducer 3 in each ultrasonic unit P is 1, and the orthographic projection of each first ultrasonic transducer 3 on the substrate 1 does not overlap with the orthographic projection of the thin film transistor circuit 2 and each signal line (such as Vda, Vdd, G1, Vbias, G2) on the substrate 1.
  • the overlapping capacitance parasite capacitance
  • the number of first ultrasonic transducers 3 in each ultrasonic unit P is 2, and the orthographic projection of each first ultrasonic transducer 3 on the substrate 1 does not overlap with the orthographic projection of the thin film transistor circuit 2 and each signal line (such as Vda, Vdd, G1, Vbias, G2) on the substrate 1.
  • the overlapping capacitance parasite capacitance
  • the conversion performance between mechanical energy and electrical energy of the first ultrasonic transducer 3 can be improved; on the other hand, the two first ultrasonic transducers 3 are conducive to improving the transmission sound pressure and signal receiving sensitivity.
  • the number of first ultrasonic transducers 3 in each ultrasonic unit P is 3, and the orthographic projection of each first ultrasonic transducer 3 on the substrate 1 overlaps with the orthographic projection of the thin film transistor circuit 2 and other signal lines (such as G3, etc.) on the substrate 1.
  • the overlapping capacitance can be ensured to be within an acceptable range, and the provision of three first ultrasonic transducers 3 is conducive to further improving the emission sound pressure and signal receiving sensitivity, so one, two or three first ultrasonic transducers 3 can be designed as needed.
  • the structures shown in FIG. 10 and FIG. 11 can simultaneously adopt the above-mentioned solution of sharing the signal lines.
  • the ultrasonic transducer device provided in the embodiment of the present disclosure, as shown in FIG. 10 and FIG. 11, when the number of the first ultrasonic transducers 3 in the ultrasonic unit P is greater than or equal to 2, the first electrodes 31 of each first ultrasonic transducer 3 in the same ultrasonic unit P are an integrated structure, the second electrodes 33 of each first ultrasonic transducer 3 in the same ultrasonic unit P are an integrated structure, and the cavities 34 of each first ultrasonic transducer 3 in the same ultrasonic unit P are separated from each other by the first vibration membrane layer 32.
  • the first electrode 31 formed in one piece can be manufactured first, the second passivation layer 30 can be formed on the first electrode 31, the sacrificial layer can be formed on the second passivation layer 30, the sacrificial layer can be patterned so that the sacrificial layer corresponds to two or three cavity patterns to be formed, the first vibration membrane layer 32 can be formed on the sacrificial layer, the sacrificial layer etching hole 35 can be made at the connection between the three cavity structures corresponding to the first vibration membrane layer 32, and the sacrificial layer can be removed from the sacrificial layer etching hole 35.
  • the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are The transistor T4 can adopt different TFT structures and sizes according to actual needs; for example, using LTPO process, the second transistor T2 can adopt oxide TFT to reduce the leakage current I off and reduce the loss of charge stored in the storage capacitor CB to stabilize the gate potential of the third transistor T3.
  • the width-to-length ratio of the third transistor T3 is equal to the width-to-length ratio of the fourth transistor T4.
  • the width-to-length ratio of the third transistor T3 may be greater than the width-to-length ratio of the fourth transistor T4, which can improve the efficiency of converting voltage into current.
  • At least one of the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 is a dual-gate transistor.
  • Fig. 13 takes the third transistor T3 as an example of a dual-gate transistor, which can reduce leakage current on the one hand, and improve the uniformity of the film layer between the transistors on the other hand to reduce the difference between the transistors.
  • the active layer of the third transistor T3 and the active layer of the fourth transistor T4 are an integrated structure (both are 41), the second electrode of the third transistor T3 and the first electrode of the fourth transistor T4 are an integrated structure (referred to as the fourth drain 52), and the second electrode 52 of the third transistor T3 is electrically connected to the active layer of the third transistor T3.
  • the third transistor T3 includes a third active layer 41, a third gate 42, a third source 43 and a fourth drain 52
  • the fourth transistor T4 includes a third active layer 41, a fourth gate 51, a third drain 44 (at this time, serving as the source of the fourth transistor) and a fourth drain 52.
  • the storage capacitor CB in the thin film transistor circuit 2 can also be omitted, and the storage capacitor CB can be replaced by a capacitor formed by Vdd and the gate of the third transistor T3, which can simplify the thin film transistor circuit.
  • FIG. 15 is another plan view of the ultrasonic transducer device, the substrate 1 further includes a virtual ultrasonic unit P' located outside the plurality of ultrasonic units P distributed in the array; as shown in FIG. 16, FIG. 16 is a diagram of an ultrasonic unit P and a virtual ultrasonic unit P' in FIG.
  • Schematic diagram of layout of acoustic unit P', virtual ultrasonic unit P' includes the above-mentioned thin film transistor circuit 2 and second ultrasonic transducer 3', the second ultrasonic transducer 3' includes a third electrode 31', a second vibration membrane layer 32' and a fourth electrode 33' stacked and arranged on the side of the thin film transistor circuit 2 away from the substrate 1, a sacrificial layer 36 is provided between the third electrode 31' and the second vibration membrane layer 32', the third electrode 31' is electrically connected to the thin film transistor circuit 2, and the fourth electrode 33' is electrically connected to the driving voltage line Vda.
  • the virtual ultrasonic unit P' since the virtual ultrasonic unit P' retains the sacrificial layer 36, that is, there is no sacrificial layer etching hole 35, it can neither transmit nor receive acoustic wave signals, which is equivalent to a dymmy unit.
  • the arrangement of dummy units can be in various ways, generally requiring multiple units, which can be arranged in multiple rows, multiple columns, or dispersedly, etc.
  • FIG. 16 takes the left and right sides of the ultrasonic unit P distributed in the array as an example.
  • the virtual ultrasonic unit P' only outputs the basic signal (including noise) generated by factors such as transistors and signal lines.
  • the basic signal of the dummy unit is subtracted from the signal received by the normal ultrasonic unit P, and the pure sound wave signal is obtained. Therefore, the noise can be greatly reduced and the fingerprint recognition accuracy can be improved.
  • the signal lines mentioned in the above embodiments are shared, two or three first ultrasonic transducers are designed for one ultrasonic unit, T3 and T4 with different width-to-length ratios are designed, dual-gate structure transistors are designed, and source-drain solutions of T3 and T4 are added, which can be flexibly combined as needed.
  • the ultrasonic unit P in the upper left corner is a structure with different width-to-length ratios of T3 and T4
  • the ultrasonic unit P in the upper right corner is a structure including two first ultrasonic transducers 3
  • the ultrasonic unit P in the lower left corner is a third transistor T3 with a dual-gate structure
  • the ultrasonic unit P in the lower right corner is a structure including three first ultrasonic transducers 3.
  • the number of the first ultrasonic transducers 3 can make the emission intensity and the receiving sensitivity different; the different sizes of the first ultrasonic transducers 3 can make the frequency of the transmitted sound wave and the frequency of the received signal differentiated, which may meet certain specific requirements; when the first ultrasonic transducers 3 are designed the same, different transistors are designed, and the signal receiving sensitivity can be differentiated.
  • different ultrasonic units P in the same ultrasonic transducer device are designed with different structures, and each ultrasonic unit P can read different signals and realize different functions. Therefore, technical personnel in this field can design the structures of different ultrasonic units P in the same ultrasonic transducer device according to actual needs.
  • the shape of the cavity 35 may be, but is not limited to, a circle, and may also be, for example, a square.
  • the materials of each film layer in the first ultrasonic transducer, the materials of each film layer in the thin film transistor circuit, and the materials of some other insulating layers are the same as those in the prior art and are not described in detail here.
  • the embodiment of the present disclosure also provides a display device, as shown in FIG18 and FIG19, including a display panel and the ultrasonic transducer device provided in the embodiment of the present disclosure. Since the principle of solving the problem of the display device is similar to that of the aforementioned ultrasonic transducer device, the implementation of the display device can refer to the implementation of the aforementioned ultrasonic transducer device, and the repeated parts will not be repeated.
  • the display panel may be a liquid crystal display panel 100, and each ultrasonic unit P in the ultrasonic transducer device is arranged in a non-luminous area BB in the liquid crystal display panel 100.
  • the plurality of ultrasonic units P distributed in an array may be evenly dispersed and arranged in the non-luminous area BB of the liquid crystal display panel 100, and a fingerprint recognition function over a large area may be realized.
  • the principle of fingerprint recognition may refer to the description in the aforementioned ultrasonic transducer device.
  • the liquid crystal display panel 100 includes an array substrate and a color filter substrate that are relatively arranged and a liquid crystal layer 101 arranged therebetween; wherein the array substrate includes: a substrate 102, a pixel circuit 103 arranged on the substrate 102, a pixel electrode 104 electrically connected to the pixel circuit 103, a common electrode 105 insulated from the pixel electrode 104, and a first orientation layer 106 located between the common electrode 105 and the negative liquid crystal layer 101; the color filter substrate includes: a cover plate 107, a color filter layer 108 and a black matrix layer 109 arranged on a side of the cover plate 107 facing the array substrate, a planar layer 110 arranged on a side of the color filter layer 108 and the black matrix layer 109 facing the array substrate, and a second orientation layer 111 arranged on a side of the planar layer 110 facing the array substrate, etc.
  • the array substrate includes: a substrate 102, a pixel circuit 103 arranged on the substrate 102, a pixel electrode
  • the liquid crystal display panel 100 also includes other necessary structures well known to those skilled in the art, which will not be described in detail here.
  • the display panel may be an organic light-emitting display panel 200, and the ultrasonic transducer device 300 is disposed on the back of the organic light-emitting display panel 200.
  • the array-distributed multiple ultrasonic units P can be evenly dispersed and disposed on the back of the organic light-emitting display panel 200, and a large-area fingerprint recognition function can be realized.
  • the principle can refer to the description of the aforementioned ultrasonic transducer device.
  • a transmission layer 400 that is beneficial to the transmission of sound waves can be arranged between the organic light-emitting display panel 200 and the ultrasonic transducer device 300, and the transmission layer 400 can be an epoxy adhesive material or other materials that can achieve efficient transmission of sound waves.
  • the above-mentioned display device provided in the embodiment of the present disclosure can also be an acoustic wave pen, which can emit sound waves (one frequency or multiple frequencies).
  • a corresponding transistor + CMUT structure is set in the screen of the display device to receive sound waves.
  • the acoustic wave pen can be used for writing, drawing, etc.
  • the display device provided in the embodiment of the present disclosure may also be a flat speaker or microphone, used as a sound-emitting product or sound collection (voice recognition) and so on.
  • the display device manufactured with the ultrasonic transducer provided in the embodiment of the present disclosure can also be used in the field of ultrasonic imaging, such as B-ultrasound in the field of medical imaging.
  • the embodiments of the present disclosure provide an ultrasonic transducer device and a display device, which form a large-area, arrayed ultrasonic fingerprint recognition structure by combining a thin-film transistor circuit and an ultrasonic transducer.
  • the structure is simple and the recognition accuracy is high, and fingerprint recognition can be performed.

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Abstract

一种超声换能器装置，包括衬底基板（1），衬底基板（1）包括阵列分布的多个超声单元（P），每一超声单元（P）包括：薄膜晶体管电路（2），设置在衬底基板（1）上；至少一个第一超声换能器（3），设置在薄膜晶体管电路（2）背离衬底基板（1）的一侧，第一超声换能器（3）包括层叠设置在薄膜晶体管电路（2）背离衬底基板（1）一侧的第一电极（31）、第一振动膜层（32）和第二电极（33），第一电极（31）和第一振动膜层（32）之间具有空腔（34），第一电极（31）与薄膜晶体管电路（2）电连接，第二电极（33）与驱动电压线电连接。

Description

一种超声换能器装置及显示装置
相关申请的交叉引用
本申请要求在2023年5月26日提交中华人民共和国国家知识产权局、申请号为202310609058.5、发明名称为“一种超声换能器装置及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及超声换能技术领域，特别涉及一种超声换能器装置及显示装置。
背景技术
指纹是人体与生俱来的独一无二的并可与他人相区别的不变特征，它由指端皮肤表面上的一系列脊和谷组成，这些脊和谷的组成细节决定了指纹图案的唯一性。由此发展起来的带有指纹识别功能的显示面板已被用于个人身份验证，增加了显示装置的信息安全性。目前，已发展起来的指纹识别技术有多种，超声波指纹识别是其中的一种。
现有的指纹识别技术依照工作原理，主要可以分为光学指纹识别、电容式指纹识别和超声波指纹识别。其中，光学指纹识别受外界光的影响极强，在外界光的强烈照射下指纹识别的速度和准确度均会下降；电容式指纹识别则在用户的手指上具有油渍和污渍的情况下，不能准确判断出油和水的介电常数而导致指纹识别的速度和准确度降低。与光学指纹识别和电容式指纹识别相比，超声波指纹识别技术依靠超声波的穿透性好、波长短、能量高的特长点，在各种使用情境下(包括强光情境、手指具有油渍或污渍情境)均可以获得较高的识别速度以及识别准确率。
发明内容
本公开实施例提供了一种超声换能器装置及显示装置，具体方案如下：
本公开实施例提供的一种超声换能器装置，包括衬底基板，所述衬底基板包括阵列分布的多个超声单元，每一所述超声单元包括：
薄膜晶体管电路，设置在所述衬底基板上；
至少一个第一超声换能器，设置在所述薄膜晶体管电路背离所述衬底基板的一侧，所述第一超声换能器包括层叠设置在所述薄膜晶体管电路背离所述衬底基板一侧的第一电极、第一振动膜层和第二电极，所述第一电极和所述第一振动膜层之间具有空腔，所述第一电极与所述薄膜晶体管电路电连接，所述第二电极与驱动电压线电连接。
在一种可能的实现方式中，在本公开实施例提供的上述超声换能器装置中，还包括用于向所述薄膜晶体管电路加载驱动信号的多条驱动信号线，至少存在相邻两行所述超声单元之间共用同一所述驱动信号线，或，至少存在相邻两列所述超声单元之间共用同一所述驱动信号线。
在一种可能的实现方式中，在本公开实施例提供的上述超声换能器装置中，所述薄膜晶体管电路包括：第一晶体管，第二晶体管，第三晶体管，第四晶体管，以及存储电容；所述驱动信号线包括：第一栅线、第二栅线、第三栅线、第一电压线、第二电压线、所述驱动电压线和信号读取线；其中，
所述第一晶体管的栅极与所述第一栅线电连接，所述第一晶体管的第一极与所述第一电压线电连接，所述第一晶体管的第二极与所述第二晶体管的第一极电连接；
所述第二晶体管的栅极与所述第二栅线电连接，所述第二晶体管的第二极与所述第三晶体管的栅极电连接；
所述第三晶体管的第一极与所述第二电压线电连接，所述第三晶体管的第二极与所述第四晶体管的第一极电连接；
所述第四晶体管的栅极与所述第三栅线电连接，所述第四晶体管的第二 极与所述信号读取线电连接；
所述存储电容的第一端与所述第二电压线电连接，所述存储电容的第二端与所述第三晶体管的栅极电连接；
所述第一超声换能器的第一电极与所述第二晶体管的第一极电连接。
在一种可能的实现方式中，在本公开实施例提供的上述超声换能器装置中，每相邻两列所述超声单元为第一组，所述第一组中的两列所述超声单元之间第一间隙处设置有一条所述驱动电压线，同一所述第一组的两列所述超声单元内所述第一超声换能器的第二电极均与所述第一间隙处的所述驱动电压线电连接。
在一种可能的实现方式中，在本公开实施例提供的上述超声换能器装置中，所述第一间隙处还设置有与所述驱动电压线间隔设置的所述第一栅线，同一所述第一组的两列所述超声单元内所述第一晶体管的栅极均与所述第一间隙处的所述第一栅线电连接。
在一种可能的实现方式中，在本公开实施例提供的上述超声换能器装置中，每相邻两个所述第一组所述超声单元之间第二间隙处设置有一条所述第二电压线，所述第二电压线与其两侧的两列所述超声单元内所有所述第三晶体管的第一极均电连接。
在一种可能的实现方式中，在本公开实施例提供的上述超声换能器装置中，同一所述第一组内相邻两列所述超声单元关于所述第一间隙对称设置，相邻两个所述第一组所述超声单元关于所述第二间隙对称设置。
在一种可能的实现方式中，在本公开实施例提供的上述超声换能器装置中，每相邻两行所述超声单元为第二组，所述第二组中的两行所述超声单元之间第三间隙处设置有一条所述第一电压线，同一所述第二组的两行所述超声单元内所有所述第一晶体管的第一极均与所述第三间隙处的所述第一电压线电连接。
在一种可能的实现方式中，在本公开实施例提供的上述超声换能器装置中，每相邻两个所述第二组所述超声单元之间第四间隙处设置有一条所述第 二栅线，所述第二栅线与其两侧的两行所述超声单元内所有所述第二晶体管的栅极均电连接。
在一种可能的实现方式中，在本公开实施例提供的上述超声换能器装置中，同一所述第二组内相邻两列所述超声单元关于所述第三间隙对称设置，相邻两个所述第二组所述超声单元关于所述第四间隙对称设置。
在一种可能的实现方式中，在本公开实施例提供的上述超声换能器装置中，每一所述超声单元内的所述第一超声换能器的数量为1个或2个，各所述第一超声换能器在所述衬底基板上的正投影与所述薄膜晶体管电路以及各信号线在所述衬底基板上的正投影均不交叠。
在一种可能的实现方式中，在本公开实施例提供的上述超声换能器装置中，每一所述超声单元内的所述第一超声换能器的数量为3个，各所述第一超声换能器在所述衬底基板上的正投影与所述薄膜晶体管电路以及其他信号线在所述衬底基板上的正投影存在交叠。
在一种可能的实现方式中，在本公开实施例提供的上述超声换能器装置中，当所述超声单元内的所述第一超声换能器的数量大于或等于2个时，同一所述超声单元内各所述第一超声换能器的第一电极为一体结构，同一所述超声单元内各所述第一超声换能器的第二电极为一体结构，同一所述超声单元内各所述第一超声换能器的空腔通过所述第一振动膜层相互隔开。
在一种可能的实现方式中，在本公开实施例提供的上述超声换能器装置中，所述第三晶体管的宽长比大于或等于所述第四晶体管的宽长比。
在一种可能的实现方式中，在本公开实施例提供的上述超声换能器装置中，所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第四晶体管其中至少之一为双栅晶体管。
在一种可能的实现方式中，在本公开实施例提供的上述超声换能器装置中，所述第三晶体管的有源层和所述第四晶体管的有源层为一体结构，所述第三晶体管的第二极和所述第四晶体管的第一极为一体结构，所述第三晶体管的第二极与所述第三晶体管的有源层电连接。
在一种可能的实现方式中，在本公开实施例提供的上述超声换能器装置中，所述衬底基板还包括位于所述阵列分布的多个超声单元外侧的虚拟超声单元，所述虚拟超声单元包括所述薄膜晶体管电路和第二超声换能器，所述第二超声换能器包括层叠设置在所述薄膜晶体管电路背离所述衬底基板一侧的第三电极、第二振动膜层和第四电极，所述第三电极和所述第二振动膜层之间具有牺牲层，所述第三电极与所述薄膜晶体管电路电连接，所述第四电极与所述驱动电压线电连接。
相应地，本公开实施例还提供了一种显示装置，包括显示面板以及本公开实施例提供的上述超声换能器装置。
在一种可能的实现方式中，在本公开实施例提供的上述显示装置中，所述显示面板为液晶显示面板，所述超声换能器装置中的各所述超声单元设置在所述液晶显示面板内的非发光区。
在一种可能的实现方式中，在本公开实施例提供的上述显示装置中，所述显示面板为有机发光显示面板，所述超声换能器装置设置在所述有机发光显示面板的背面。
附图说明
图1为本公开实施例提供的超声换能器装置的一种平面结构示意图；
图2为图1中一个超声单元的截面示意图；
图3为薄膜晶体管电路的具体电路示意图；
图4为图3所示的薄膜晶体管电路的工作时序示意图；
图5为图1中若干超声单元对应的一种layout示意图；
图6为图1中若干超声单元对应的又一种layout示意图；
图7为图1中若干超声单元对应的又一种layout示意图；
图8为图1中若干超声单元对应的又一种layout示意图；
图9为图1中若干超声单元对应的又一种layout示意图；
图10为图1中若干超声单元对应的又一种layout示意图；
图11为图1中若干超声单元对应的又一种layout示意图；
图12为图1中若干超声单元对应的又一种layout示意图；
图13为图1中若干超声单元对应的又一种layout示意图；
图14为图1中若干超声单元对应的又一种layout示意图；
图15为图1中若干超声单元对应的又一种layout示意图；
图16为本公开实施例提供的超声换能器装置的又一种平面结构示意图；
图17为图1中若干超声单元对应的又一种layout示意图；
图18为本公开实施例提供的一种显示装置的结构示意图；
图19为本公开实施例提供的又一种显示装置的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元 件或具有相同或类似功能的元件。
相关技术中，最常用的超声波指纹识别为PVDF超声波指纹识别，其不受外界光干扰，不需要显示屏提供光源，可实现3D指纹和皮肤深层信息探测，防假能力强，但技术被高通垄断，并且需要PVDF特殊材料和特殊的极化设备，成本较高。
有鉴于此，本公开实施例提供了一种超声换能器装置，如图1所示，包括衬底基板1，衬底基板1包括阵列分布的多个超声单元P；如图2所示，图2为图1中一个超声单元P的截面示意图，每一超声单元P包括：
薄膜晶体管电路2，设置在衬底基板1上；
至少一个第一超声换能器3，设置在薄膜晶体管电路2背离衬底基板1的一侧，第一超声换能器3包括层叠设置在薄膜晶体管电路2背离衬底基板1一侧的第一电极31、第一振动膜层32和第二电极33，第一电极31和第一振动膜层32之间具有空腔34，第一电极31与薄膜晶体管电路2电连接，第二电极33与驱动电压线电连接。
本公开实施例提供的上述超声换能器(CMUT)装置，通过将薄膜晶体管电路和超声换能器结合，形成了大面积、阵列化的超声波指纹识别结构，能够进行指纹识别，结构简单且识别精度高。
具体地，CMUT的主要功能有：在发射阶段，换能器在激励信号作用下将输入的电能转换为机械能传递出去，实现超声波的发射；在接收阶段，换能器将声波转换为电信号，实现超声波的接收。因此，可以将本公开实施例提供的超声换能器(CMUT)装置中的超声单元与显示面板结合，在用户触摸显示面板时，超声波传递到人的手指，由于手指表面的脊和谷对超声波信号的反射强度不同，导致经过手指的脊和谷反射的超声波能量不同，将这种能量的差异转换成电信号的差异，即可进行对指纹的脊和谷的成像，进而进行指纹识别。
可选地，第一振动膜层的材料可以为PI或PET等。
可选地，衬底基板可以采用刚性基板，例如玻璃基板；也可以采用柔性 基板，例如PI。
本公开实施例提供的超声换能器制作采用玻璃基或柔性PI基制作，面积可以更大，还能柔性贴合人体和物体表面，优势远超硅基CMUT器件。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，如图2和图3所示，薄膜晶体管电路包括：第一晶体管T1，第二晶体管T2，第三晶体管T3，第四晶体管T4，以及存储电容CB；其中，
第一晶体管T1的栅极与第一栅线G1电连接，第一晶体管T1的第一极与第一电压线Vbias电连接，第一晶体管T1的第二极与第二晶体管T2的第一极电连接；
第二晶体管T2的栅极与第二栅线G2电连接，第二晶体管T2的第二极与第三晶体管T3的栅极电连接；
第三晶体管T3的第一极与第二电压线Vdd电连接，第三晶体管T3的第二极与第四晶体管T4的第一极电连接；
第四晶体管T4的栅极与第三栅线G3电连接，第四晶体管T4的第二极与信号读取线Vread电连接；
存储电容CB的第一端与第二电压线Vdd电连接，存储电容CB的第二端与第三晶体管T3的栅极电连接；
第一超声换能器3的第一电极与第二晶体管T2的第一极电连接，第一超声换能器3的第二电极33与驱动电压线Vda电连接；其中Vda用于向第二电极33输入直流电压Vdc以及交流电压Vda。
需要说明的是，图3所示的薄膜晶体管电路只是本公开实施例列举的其中一种电路结构，本公开实施例中的薄膜晶体管电路不限于图3所示的结构，其它能够与第一超声换能器结合实现超声指纹识别的电路均属于本公开实施例保护的范围。
如图2所示，第一晶体管T1包括依次层叠设置在衬底基板1和第一超声换能器3之间的第一有源层11、第一栅极12、第一源极13和第一漏极14，第二晶体管T2包括依次层叠设置在衬底基板1和第一超声换能器3之间的第 二有源层21、第二栅极22、第二源极23和第二漏极24，第三晶体管T3包括依次层叠设置在衬底基板1和第一超声换能器3之间的第三有源层41、第三栅极42、第三源极43和第三漏极44，第四晶体管T4包括依次层叠设置在衬底基板1和第一超声换能器3之间的第三有源层41、第四栅极51、第三源极43和第三漏极44，即第四晶体管T4可以和第三晶体管T4共用有源层、源极和漏极。其中，第一有源层11、第二有源层21和第三有源层41位于同一膜层(有源层)，第一栅极12、第二栅极22、第三栅极42和第四栅极51位于同一膜层(Gate1层)，存储电容CB的第一极板C1位于Gate1层，存储电容CB的第二极板C2位于Gate2层，第一源极13、第一漏极14、第二源极23、第二漏极24、第三源极43和第三漏极44位于同一膜层(SD层)。
具体地，图3中各晶体管的第一极可以为源极，第二极可以为漏极；当然，也可以是第一极为漏极，第二极为源极。
如图2所示，在衬底基板1和有源层之间还设置遮光层LS，遮光层LS可以用于遮光有源层，也可以用于取代Gate1层与Gate2层形成存储电容CB(本公开以此示意)；在遮光层LS和有源层之间还设置第一缓冲层6，在有源层和Gate1层之间还设置第一栅绝缘层7，在Gate1层和Gate2层之间还设置第二栅绝缘层8，在Gate2层和SD层之间还设置层间绝缘层9，在SD层和第一超声换能器3之间还设置平坦层10，在平坦层10和第一超声换能器3之间还设置第一钝化层20，第一超声换能器3的第一电极31通过贯穿第一钝化层20和平坦层10的过孔与第二晶体管T2的第一极(第二漏极24)电连接，在第一电极31和空腔34之间还设置第二钝化层30，在第二电极33上方还设置第二缓冲层40，在第二缓冲层40上方还设置第三缓冲层50。
当然，对于该超声换能器装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不予赘述。
具体地，如图2所示，空腔34可以采用牺牲层的方式制作，牺牲层刻蚀孔为35，牺牲层的制作方式与现有技术相同，在此不做详述。
下面结合图3所示的薄膜晶体管电路和图4所示的时序对本公开实施例 提供的上述超声换能器装置实现指纹识别的原理进行说明，如下：
在t1阶段(超声波发射阶段)，CMUT的第二电极既要加直流电压Vdc，也要加交流电压Vac，第一晶体管T1和第二晶体管T2打开，第一电压线Vbias上为恒定电位，CMUT的第一振动膜层高频振动，发射声波。
在t2阶段(采集阶段)，CMUT左端只需加直流电压Vdc，不需要加交流电压Vac，第一晶体管T1关闭，第二晶体管T2打开，外界声波信号经手指反射到达CMUT，压迫第一振动膜层产生振动，产生交流电流(电荷)，采集半周期内的交流幅值，将电荷储存在存储电容CB中。
在t3阶段(读取阶段)，第三晶体管T3和第四晶体管T4打开，存储电容CB中存储的电荷经过第三晶体管T3的转换成电流，最终经第四晶体管T4输出，通过信号读取线Vread读取输出的电流，实现指纹识别。
在具体实施时，在t2阶段采集完电荷后，可以不直接进行t3阶段的读取，即在t2阶段和t3阶段还可以有缓冲阶段t3’，在需要读取的时候再进行t3阶段，t3’阶段可以将第一电压线Vbias上的电压拉低，以降低功耗。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，如图3、图5-图8所示，图5-图8分别为图1中若干超声单元P对应的layout(版图)示意图，该超声换能器装置包括用于向薄膜晶体管电路加载驱动信号的多条驱动信号线，驱动信号线包括第一栅线G1、第二栅线G2、第三栅线各、第一电压线Vbias、第二电压线Vdd、驱动电压线Vda和信号读取线Vread，至少存在相邻两行超声单元P之间共用同一驱动信号线(例如Vbias共用)，或，至少存在相邻两列超声单元P之间共用同一驱动信号线(例如Vbias共用)。这样可以节约空间，简化设计，有利于高分辨率的设计。
具体地，如图2和图3所示，第一栅线G1、第二电压线Vdd和信号读取线Vread可以位于SD层，第二栅线G2和第三栅线G3可以位于Gate1层，第一电压线Vbias可以位于Gate2层，驱动电压线Vda和第二电极33位于同一层。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，如图5 所示，每相邻两列超声单元P为第一组A1，第一组A1中的两列超声单元P之间第一间隙B1处设置有一条驱动电压线Vda，同一第一组A1的两列超声单元P内第一超声换能器3的第二电极33均与第一间隙B1处的驱动电压线Vda电连接。这样相邻两列超声单元P共用一条驱动电压线Vda，可以节约空间，简化设计，有利于高分辨率的设计。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，如图6所示，第一间隙B1处还设置有与驱动电压线Vda间隔设置的第一栅线G1，同一第一组A1的两列超声单元P内第一晶体管T1的栅极均与第一间隙B1处的第一栅线G1电连接。这样相邻两列超声单元P共用一条第一栅线G1，可以进一步节约空间，进一步简化设计，有利于进一步高分辨率的设计。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，如图5所示，每相邻两个第一组(A1)超声单元P之间第二间隙B2处设置有一条第二电压线Vdd，第二电压线Vdd与其两侧的两列超声单元P内所有第三晶体管T3的第一极均电连接。这样相邻两列超声单元P共用一条第二电压线Vdd，可以进一步节约空间，进一步简化设计，有利于进一步高分辨率的设计。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，如图5和图6所示，同一第一组A1内相邻两列超声单元P关于第一间隙B1对称设置，相邻两个第一组(A1)超声单元P关于第二间隙B2对称设置。这样相邻左右两个超声单元P为镜像对称结构，每一超声单元P的尺寸可以为75微米*75微米，当然不限于此。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，如图7所示，每相邻两行超声单元P为第二组A2，第二组A2中的两行超声单元P之间第三间隙B3处设置有一条第一电压线Vbias，同一第二组A2的两行超声单元P内所有第一晶体管T1的第一极均与第三间隙B3处的第一电压线Vbias电连接。这样相邻两行超声单元P共用一条第一电压线Vbias，可以进一步节约空间，进一步简化设计，有利于进一步高分辨率的设计。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，如图8 所示，每相邻两个第二组(A2)超声单元P之间第四间隙B4处设置有一条第二栅线G2，第二栅线G2与其两侧的两行超声单元P内所有第二晶体管T2的栅极均电连接。这样相邻两行超声单元P共用一条第二栅线G2，可以进一步节约空间，进一步简化设计，有利于进一步高分辨率的设计。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，如图7和图8所示，同一第二组A2内相邻两列超声单元P关于第三间隙B3对称设置，相邻两个第二组(A2)超声单元P关于第四间隙B4对称设置。这样相邻上下左右四个超声单元P为镜像对称结构，每一超声单元P的尺寸可以为75微米*75微米，当然不限于此。
具体地，如图5-图8所示，图5是以相邻两列超声单元P共用一条驱动电压线Vda以及相邻两列超声单元P共用一条第二电压线Vdd为例，图6是在图5的基础上以相邻两列超声单元P共用一条第一栅线G1为例，图7是在图5的基础上以相邻两行超声单元P共用一条第一电压线Vbias为例，图8是在图5的基础上以相邻两行超声单元P共用一条第一电压线Vbias以及相邻两行超声单元P共用一条第二栅线G2为例。在具体实施时，本公开实施例提供的上述超声换能器装置可以同时采用Vda共用、Vdd共用、G1共用、Vbias共用、G2共用，当然也可以选择采用其中一种或几种信号线共用的方式。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，对于布线空间充足的情况下，上述提到的各共用信号线也可以不共用，如图9所示，超声单元间隙处包含完整的所有信号线。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，如图2、图5-图8所示，每一超声单元P内的第一超声换能器3的数量为1个，各第一超声换能器3在衬底基板1上的正投影与薄膜晶体管电路2以及各信号线(例如Vda、Vdd、G1、Vbias、G2)在衬底基板1上的正投影均不交叠。这样可以降低交叠电容(寄生电容)，从而提高第一超声换能器3的机械能-电能之间的转换性能。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，如图10所示，每一超声单元P内的第一超声换能器3的数量为2个，各第一超声换能器3在衬底基板1上的正投影与薄膜晶体管电路2以及各信号线(例如Vda、Vdd、G1、Vbias、G2)在衬底基板1上的正投影均不交叠。这样一方面可以降低交叠电容(寄生电容)，提高第一超声换能器3的机械能-电能之间的转换性能；另一方面两个第一超声换能器3有利于提高发射声压和信号接收灵敏度。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，如图11所示，每一超声单元P内的第一超声换能器3的数量为3个，各第一超声换能器3在衬底基板1上的正投影与薄膜晶体管电路2以及其他信号线(例如G3等)在衬底基板1上的正投影存在交叠。这样可以保证交叠电容在可接受的范围内，设置三个第一超声换能器3有利于进一步提高发射声压和信号接收灵敏度，因此可以根据需要设计一个、两个或三个第一超声换能器3。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，图10和图11所示的结构可以同时采用上述各信号线共用的方案。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，如图10和图11所示，当超声单元P内的第一超声换能器3的数量大于或等于2个时，同一超声单元P内各第一超声换能器3的第一电极31为一体结构，同一超声单元P内各第一超声换能器3的第二电极33为一体结构，同一超声单元P内各第一超声换能器3的空腔34通过第一振动膜层32相互隔开。这样在制作时，可以先制作一体成型的第一电极31，在第一电极31上形成第二钝化层30，在第二钝化层30上形成牺牲层，对牺牲层进构图，使得牺牲层对应两个或三个待形成的空腔图形，在牺牲层上形成第一振动膜层32，在第一振动膜层32对应三个空腔结构连接处制作牺牲层刻蚀孔35，从牺牲层刻蚀孔35处将牺牲层去除。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，如图2、图5-图11所示，第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体 管T4均可以根据实际需求，采用不同TFT结构和尺寸；例如采用LTPO工艺，其中第二晶体管T2可以采用Oxide TFT以降低漏电流Ioff，降低存储电容CB存储的电荷的损失，以稳定第三晶体管T3的栅极电位。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，如图12所示，第三晶体管T3的宽长比等于第四晶体管T4的宽长比。当然，也可以是第三晶体管T3的宽长比大于第四晶体管T4的宽长比，这样可以提高电压转换为电流的效率。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，如图13所示，第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4其中至少之一为双栅晶体管。图13是以第三晶体管T3为双栅晶体管为例，这样一方面可以降低漏电流，另一方面可以提高各晶体管之间膜层的均一性以减少各晶体管之间的差异。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，如图14所示，第三晶体管T3的有源层和第四晶体管T4的有源层为一体结构(均为41)，第三晶体管T3的第二极和第四晶体管T4的第一极为一体结构(称为第四漏极52)，第三晶体管T3的第二极52与第三晶体管T3的有源层电连接。这样第三晶体管T3包括第三有源层41、第三栅极42、第三源极43和第四漏极52，第四晶体管T4包括第三有源层41、第四栅极51、第三漏极44(此时作为第四晶体管的源极)和第四漏极52，通过增加与第三有源层41通过过孔连接的第四漏极52，可以降低晶体管的电阻，提高信号传输性能。
在具体实施时，薄膜晶体管电路2里的存储电容CB也可以省掉，利用Vdd和第三晶体管T3的栅极形成的电容代替存储电容CB，可以简化薄膜晶体管电路。
在具体实施时，为了降低超声波指纹识别时的噪声，在本公开实施例提供的上述超声换能器装置中，如图15所示，图15为超声换能器装置的又一种平面示意图，衬底基板1还包括位于阵列分布的多个超声单元P外侧的虚拟超声单元P’；如图16所示，图16为图15中一个超声单元P和一个虚拟超 声单元P’的layout示意图，虚拟超声单元P’包括上述薄膜晶体管电路2和第二超声换能器3’，第二超声换能器3’包括层叠设置在薄膜晶体管电路2背离衬底基板1一侧的第三电极31’、第二振动膜层32’和第四电极33’，第三电极31’和第二振动膜层32’之间具有牺牲层36，第三电极31’与薄膜晶体管电路2电连接，第四电极33’与驱动电压线Vda电连接。具体地，虚拟超声单元P’由于保留牺牲层36，即没有牺牲层刻蚀孔35，因此其既不能发射声波信号，也不能接收声波信号，相当于dymmy单元，dummy单元的布置可以有多种方式，一般需要多个，可以多行，多列，或是分散设置等，图16是以在阵列分布的超声单元P左右两侧为例。通过设置虚拟超声单元P’，虚拟超声单元P’只输出晶体管和信号线等因素所产生的基础信号(含噪声)，用正常超声单元P接收到的信号减去dummy单元的基础信号，得到的即是纯粹的声波信号，因此可大大降低噪声，提高指纹识别精度。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，以上实施例中提到的各信号线共用、一个超声单元设计两个或三个第一超声换能器、设计不同宽长比的T3和T4、设计双栅结构晶体管以及增设T3和T4的源漏极方案，可以根据需要进行灵活组合。例如，如图17所示，示意出四个超声单元P，左上角的超声单元P为T3和T4的宽长比不同的结构，右上角的超声单元P为包括两个第一超声换能器3的结构，左下角的超声单元P为第三晶体管T3具有双栅结构，右下角的超声单元P为包括三个第一超声换能器3的结构。其中，第一超声换能器3个数的多少，可使得发射强度和接收灵敏度有所差异；第一超声换能器3不同的尺寸，可以使得发射声波的频率和接收信号的频率差异化，有可能满足某些特定需求；当第一超声换能器3设计相同，设计不同的晶体管，可以对信号接收灵敏度进行差异化。这样，同一超声换能器装置中不同超声单元P设计成不同的结构，各超声单元P可以读取不同的信号，实现不同的功能，因此本领域技术人员可以根据实际需要设计同一超声换能器装置中不同超声单元P的结构。
在具体实施时，在本公开实施例提供的上述超声换能器装置中，如图5- 图15和图17所示，空腔35的形状可以为但不限于圆形，例如还可以为方形等。
在具体实施时，第一超声换能器中各膜层的材料、薄膜晶体管电路中各膜层的材料以及其它一些绝缘层的材料均与现有技术中相同，在此不做详述。
基于同一发明构思，本公开实施例还提供了一种显示装置，如图18和图19所示，包括显示面板以及本公开实施例提供的上述超声换能器装置。由于该显示装置解决问题的原理与前述一种超声换能器装置相似，因此该显示装置的实施可以参见前述超声换能器装置的实施，重复之处不再赘述。
在具体实施时，在本公开实施例提供的上述显示装置中，如图18所示，显示面板可以为液晶显示面板100，超声换能器装置中的各超声单元P设置在液晶显示面板100内的非发光区BB。这样可以将阵列分布的多个超声单元P均匀分散设置在液晶显示面板100的非发光区BB，可以实现大面积的指纹识别功能。指纹识别原理可以参见前述一种超声换能器装置中的描述。
具体地，如图18所示，液晶显示面板100包括相对设置的阵列基板和彩膜基板以及设置在二者之间的液晶层101；其中，阵列基板包括：衬底102，设置在衬底102上的像素电路103，与像素电路103电连接的像素电极104，与像素电极104绝缘设置的公共电极105，位于公共电极105和阴液晶层101之间的第一取向层106；彩膜基板包括：盖板107，设置在盖板107面向阵列基板一侧的彩膜层108和黑矩阵层109，设置在彩膜层108和黑矩阵层109面向阵列基板一侧的平坦层110，以及设置在平坦层110面向阵列基板一侧的第二取向层111等。
具体地，液晶显示面板100还包括本领域技术人员熟知的其它必不可少的结构，在此不做详述。
在具体实施时，在本公开实施例提供的上述显示装置中，如图19所示，显示面板可以为有机发光显示面板200，超声换能器装置300设置在有机发光显示面板200的背面。这样可以将阵列分布的多个超声单元P均匀分散设置在有机发光显示面板200的背面，可以实现大面积的指纹识别功能。指纹识别原 理可以参见前述一种超声换能器装置中的描述。
在具体实施时，在本公开实施例提供的上述显示装置中，如图19所示，有机发光显示面板200和超声换能器装置300之间可以设置有利于声波传输的传输层400，传输层400可以是环氧胶类材料或其它能起到声波高效传输的材料。
需要说明的是，有机发光显面板的结构与现有技术中的相同，在此不做详述。
在具体实施时，本公开实施例提供的上述显示装置还可以是声波笔，该声波笔可发射声波(一种频率或多种频率)，显示装置的屏幕中设置相应的晶体管+CMUT结构用于接收声波，该声波笔可用于写字，画画等。
在具体实施时，本公开实施例提供的上述显示装置还可以是平板扬声器或者麦克风，用作发声产品或者收声(语音识别)等方面。
在具体实施时，本公开实施例提供的上述具有超声换能器制作的显示装置还可以用于超声成像领域，例如医疗影像领域的B超等。
本公开实施例提供了一种超声换能器装置及显示装置，通过将薄膜晶体管电路和超声换能器结合，形成了大面积、阵列化的超声波指纹识别结构，能够进行指纹识别，结构简单且识别精度高。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (20)

  1. 一种超声换能器装置，其中，包括衬底基板，所述衬底基板包括阵列分布的多个超声单元，每一所述超声单元包括：
    薄膜晶体管电路，设置在所述衬底基板上；
    至少一个第一超声换能器，设置在所述薄膜晶体管电路背离所述衬底基板的一侧，所述第一超声换能器包括层叠设置在所述薄膜晶体管电路背离所述衬底基板一侧的第一电极、第一振动膜层和第二电极，所述第一电极和所述第一振动膜层之间具有空腔，所述第一电极与所述薄膜晶体管电路电连接，所述第二电极与驱动电压线电连接。
  2. 如权利要求1所述的超声换能器装置，其中，还包括用于向所述薄膜晶体管电路加载驱动信号的多条驱动信号线，至少存在相邻两行所述超声单元之间共用同一所述驱动信号线，或，至少存在相邻两列所述超声单元之间共用同一所述驱动信号线。
  3. 如权利要求2所述的超声换能器装置，其中，所述薄膜晶体管电路包括：第一晶体管，第二晶体管，第三晶体管，第四晶体管，以及存储电容；所述驱动信号线包括：第一栅线、第二栅线、第三栅线、第一电压线、第二电压线、所述驱动电压线和信号读取线；其中，
    所述第一晶体管的栅极与所述第一栅线电连接，所述第一晶体管的第一极与所述第一电压线电连接，所述第一晶体管的第二极与所述第二晶体管的第一极电连接；
    所述第二晶体管的栅极与所述第二栅线电连接，所述第二晶体管的第二极与所述第三晶体管的栅极电连接；
    所述第三晶体管的第一极与所述第二电压线电连接，所述第三晶体管的第二极与所述第四晶体管的第一极电连接；
    所述第四晶体管的栅极与所述第三栅线电连接，所述第四晶体管的第二极与所述信号读取线电连接；
    所述存储电容的第一端与所述第二电压线电连接，所述存储电容的第二端与所述第三晶体管的栅极电连接；
    所述第一超声换能器的第一电极与所述第二晶体管的第一极电连接。
  4. 如权利要求3所述的超声换能器装置，其中，每相邻两列所述超声单元为第一组，所述第一组中的两列所述超声单元之间第一间隙处设置有一条所述驱动电压线，同一所述第一组的两列所述超声单元内所述第一超声换能器的第二电极均与所述第一间隙处的所述驱动电压线电连接。
  5. 如权利要求4所述的超声换能器装置，其中，所述第一间隙处还设置有与所述驱动电压线间隔设置的所述第一栅线，同一所述第一组的两列所述超声单元内所述第一晶体管的栅极均与所述第一间隙处的所述第一栅线电连接。
  6. 如权利要求4或5所述的超声换能器装置，其中，每相邻两个所述第一组所述超声单元之间第二间隙处设置有一条所述第二电压线，所述第二电压线与其两侧的两列所述超声单元内所有所述第三晶体管的第一极均电连接。
  7. 如权利要求6所述的超声换能器装置，其中，同一所述第一组内相邻两列所述超声单元关于所述第一间隙对称设置，相邻两个所述第一组所述超声单元关于所述第二间隙对称设置。
  8. 如权利要求3-7任一项所述的超声换能器装置，其中，每相邻两行所述超声单元为第二组，所述第二组中的两行所述超声单元之间第三间隙处设置有一条所述第一电压线，同一所述第二组的两行所述超声单元内所有所述第一晶体管的第一极均与所述第三间隙处的所述第一电压线电连接。
  9. 如权利要求8所述的超声换能器装置，其中，每相邻两个所述第二组所述超声单元之间第四间隙处设置有一条所述第二栅线，所述第二栅线与其两侧的两行所述超声单元内所有所述第二晶体管的栅极均电连接。
  10. 如权利要求9所述的超声换能器装置，其中，同一所述第二组内相邻两列所述超声单元关于所述第三间隙对称设置，相邻两个所述第二组所述超声单元关于所述第四间隙对称设置。
  11. 如权利要求1-10任一项所述的超声换能器装置，其中，每一所述超声单元内的所述第一超声换能器的数量为1个或2个，各所述第一超声换能器在所述衬底基板上的正投影与所述薄膜晶体管电路以及各信号线在所述衬底基板上的正投影均不交叠。
  12. 如权利要求1-10任一项所述的超声换能器装置，其中，每一所述超声单元内的所述第一超声换能器的数量为3个，各所述第一超声换能器在所述衬底基板上的正投影与所述薄膜晶体管电路以及其他信号线在所述衬底基板上的正投影存在交叠。
  13. 如权利要求11或12所述的超声换能器装置，其中，当所述超声单元内的所述第一超声换能器的数量大于或等于2个时，同一所述超声单元内各所述第一超声换能器的第一电极为一体结构，同一所述超声单元内各所述第一超声换能器的第二电极为一体结构，同一所述超声单元内各所述第一超声换能器的空腔通过所述第一振动膜层相互隔开。
  14. 如权利要求3-13任一项所述的超声换能器装置，其中，所述第三晶体管的宽长比大于或等于所述第四晶体管的宽长比。
  15. 如权利要求3-14任一项所述的超声换能器装置，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管和所述第四晶体管其中至少之一为双栅晶体管。
  16. 如权利要求3-15任一项所述的超声换能器装置，其中，所述第三晶体管的有源层和所述第四晶体管的有源层为一体结构，所述第三晶体管的第二极和所述第四晶体管的第一极为一体结构，所述第三晶体管的第二极与所述第三晶体管的有源层电连接。
  17. 如权利要求1-16任一项所述的超声换能器装置，其中，所述衬底基板还包括位于所述阵列分布的多个超声单元外侧的虚拟超声单元，所述虚拟超声单元包括所述薄膜晶体管电路和第二超声换能器，所述第二超声换能器包括层叠设置在所述薄膜晶体管电路背离所述衬底基板一侧的第三电极、第二振动膜层和第四电极，所述第三电极和所述第二振动膜层之间具有牺牲层， 所述第三电极与所述薄膜晶体管电路电连接，所述第四电极与所述驱动电压线电连接。
  18. 一种显示装置，其中，包括显示面板以及如权利要求1-17任一项所述的超声换能器装置。
  19. 如权利要求18所述的显示装置，其中，所述显示面板为液晶显示面板，所述超声换能器装置中的各所述超声单元设置在所述液晶显示面板内的非发光区。
  20. 如权利要求18所述的显示装置，其中，所述显示面板为有机发光显示面板，所述超声换能器装置设置在所述有机发光显示面板的背面。
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