WO2024141756A1

WO2024141756A1 - Method of manufacturing three-dimensional microstructures

Info

Publication number: WO2024141756A1
Application number: PCT/GB2023/053377
Authority: WO
Inventors: Christiaan Johannes BEKKER; Cristian BONATO
Original assignee: Heriot-Watt University
Priority date: 2022-12-28
Filing date: 2023-12-27
Publication date: 2024-07-04
Also published as: GB2625818A; GB202219798D0

Abstract

A method of etching a three-dimensional microstructure in a substrate comprising: providing a substrate (100); depositing an inorganic mask layer (110) on the surface of the substrate, wherein the inorganic mask layer has a different composition from the substrate; providing a polymer-based photoresist layer (120) on the inorganic mask layer (110); forming a first three-dimensional lithographic mask (122) in the polymer-based photoresist layer (120) comprising exposing the polymer-based photoresist layer with patterned illumination (L) and developing the polymer-based photoresist layer; etching the photoresist mask (122) and the inorganic mask layer (110) with a first reactive ion etching process (R1) to produce a second three-dimensional lithographic mask (112) in the inorganic mask layer (110); and etching the second three-dimensional lithographic mask (112) and the substrate (100) with a second reactive ion etching process (R2) to produce a three-dimensional microstructure (102) in the substrate.

Description

METHOD OF MANUFACTURING THREE-DIMENSIONAL MICROSTRUCTURES

TECHNICAL FIELD

The present application relates to the manufacturing of three-dimensional microstructures, and more particularly, but not exclusively, to microlens arrays.

BACKGROUND

Three-dimensional microstructures are manufactured for applications including optical components, such as microlens arrays. Within the field of lithographic etching, where etching is largely uniaxially applied from above the substrate, such structures may also be referred to as being “2.5-dimensional”. For example, arrays of microlenses are used to collimate the output of arrays of vertical-cavity surface-emitting lasers (VCSELs) and to focus light onto image sensors. Microlenses are also used to enhance optical coupling in optical interconnects for optical transceiver chips.

The term “microstructure” has been used within this application to refer to structures having at least one dimension that is (e.g. at least two dimensions that are) up to 250pm in size, including “nanostructures”, e.g. structures having at least one dimension that is (e.g. at least two dimensions that are) 1 nm to 250pm in size.

In an existing manufacturing method, three-dimensional microstructures are formed by focussed ion beam (FIB) milling with a nanometre-scale beam of ions (e.g. gallium ions), that ablates a substrate to form high-resolution microstructures. However, FIB milling is very slow and expensive, which limits its commercial application.

In an alternative manufacturing method, three-dimensional microstructures are formed by reactive ion etching (RIE) through a three-dimensional polymer-based photoresist mask. However, limitations upon the shape control, reproducibility and aspect ratio (height relative to inplane size) of the features of the photoresist mask, and the sensitivity of the etch rate of suitable photoresists to the etch conditions during RIE etching of the underlying substrate limits manufacturing performance of the microstructures, and in the case that the microstructures are used as optical components that limits their optical performance. SUMMARY OF THE DISCLOSURE

According to a first aspect, there is provided a method of etching a three-dimensional microstructure in a substrate comprising: providing a substrate (100); depositing an inorganic mask layer (110) on the surface of the substrate, wherein the inorganic mask layer has a different composition from the substrate; providing a polymer-based photoresist layer (120) on the inorganic mask layer (110); forming a first three-dimensional lithographic mask (122) in the polymer-based photoresist layer (120) comprising exposing the polymer-based photoresist layer with patterned illumination (L) and developing the polymer-based photoresist layer; etching the photoresist mask (122) and the inorganic mask layer (110) with a first reactive ion etching process (R1) to produce a second three-dimensional lithographic mask (112) in the inorganic mask layer (110); and etching the second three-dimensional lithographic mask (112) and the substrate (100) with a second reactive ion etching process (R2) to produce a three-dimensional microstructure (102) in the substrate.

According to a second aspect, there is provided a three-dimensional microstructure (102) formed in a substrate by the method of the first aspect.

The inorganic mask layer (110) may be one of amorphous dielectric, amorphous semiconductor, polycrystalline dielectric, and polycrystalline semiconductor.

The inorganic mask layer (110) may be a layer of silicon oxide, silicon nitride, silicon oxynitride, aluminium oxide, silicon, a group lll-V semiconductor, or a group ll-VI semiconductor.

The substrate (100) may be a semiconductor substrate.

The semiconductor substrate may be a silicon carbide substrate.

The material of the inorganic mask layer (110) may etch at 0.8 times to 1.5 times the rate at which the material of the photoresist mask (122) etches during the first reactive ion etching process (R1).

During the first reactive ion etching process (R1) a plasma may be formed from a gas comprising trifluoromethane. During the first reactive ion etching process (R1) a plasma may be formed from a gas comprising argon and oxygen.

The material of the substrate (100) may etch at 0.5 times to 6 times the rate at which the material of the inorganic mask (120) etches during the second reactive ion etching process (R2).

During the second reactive ion etching process (R2) a plasma may be formed from a gas comprising sulphur hexafluoride, and one or both of argon and oxygen.

The second reactive ion etching process may use a plasma formed from a gas with a greater proportion of oxygen than the first reactive ion etch process.

The photoresist layer (120) may be thermally cured by a baking step during which the temperature of the substrate is raised by up to 10°C per minute.

The photoresist layer (120) may be thermally cured by a baking step during which the temperature of the substrate is raised by up to a maximum temperature of 95 to 100°C

The patterned illumination (P) may comprise a plurality of illumination stages (P1 , P2, P3) focused within the photoresist layer (120) to focal planes with different depths (D1 , D2, D3) beneath the upper surface of the photoresist layer (120).

The plurality of illumination stages (P1 , P2, P3) focussed to different depths (D1 , D2, D3) may have spatially different patterns of exposure in their respective focal planes.

The different depths (D1 , D2, D3) may be spaced apart by 2pm to 5pm.

An etch wall (106) may be provided proximate the microstructure (102) and coated with an optically reflective coating (108).

The 3D microstructure (102) may be a micro-lens array.

The microstructure (102) may be aligned with a light emitter (140) within the substrate (100).

The 3D microstructure (102) may be a micro-lens shaped to refract light emitted from the light emitter (140) into a substantially parallel beam (E’, E1’) or a convergently focussed beam. An etch wall (106) may be provided proximate the microstructure (102) to receive light (E) emitted by the light emitter (140) and coated with an optically reflective coating (108), and the etch wall may be shaped to reflect the received light (E) into a substantially parallel beam (E2’).

The microstructure (102) may have at least one of a height or width that is 1nm to 250pm in size.

The various embodiments described above represent individual features of the invention which can be applied generally to the system of the invention. These features may be taken individually as preferred features or more than one of these preferred features may be combined with one another in any combination.

DESCRIPTION OF THE DRAWINGS

Examples are further described hereinafter with reference to the accompanying drawings, in which:

• Figures 1A to 1 D illustrates steps in the manufacture of microlenses etched into a substrate;

• Figure 1 E shows a schematic cross-sectional view of a microlens of Figure 1 D in use;

• Figure 1 F shows a scanning electron microscope (SEM) image of a small portion of a wafer on which a two-dimensional array of hemispherical microlenses has been manufactured, and Figure 1G shows an enlarged view of one of the microlenses of Figure 1 F;

• Figure 2A shows an SEM of a further microlens array, in which each microlens is formed within a trench, and Figure 2B shows an enlarged view of one of the microlenses of Figure 2A;

• Figure 2C shows a cross-sectional measurement of the height of the microlens of Figure 2B;

• Figure 3 shows a schematic cross-sectional view of a second microlens in use; and

• Figure 4 shows a schematic cross-sectional view of a third microlens in use.

DETAILED DESCRIPTION

Like reference numerals refer to like elements throughout. In the described examples, like features have been identified with like numerals, albeit in some cases having one or more of: increments of suffix letters; and typographical marks (e.g. asterisks). For example, in different figures, 102 and 102’ have been used to indicate a microstructure etched into a substrate. Figures 1A to 1 D illustrate steps in the manufacture of microstructures (e.g. microlenses), and Figure 1 E shows a microlens in use.

As shown in Figure 1A, the substrate 100 in which microstructures are to be formed is provided with an inorganic mask layer 110, and a cured polymer-based photoresist layer 120 (e.g. thermally cured) is provided on the inorganic mask layer.

The substrate 100 may be a semiconductor substrate (e.g. a group IV semiconductor substrate {e.g. diamond, silicon, germanium, silicon carbide, and silicon-germanium}, a lll-V semiconductor substrate, or a group ll-VI semiconductor substrate). The substrate may be a substrate of silicon nitride, sapphire (AI2O3), ITO (indium tin oxide), GaAs, GaN, AIN, or Ga2Os, or a transition metal dichalcogenide semiconductor. In the case that light emitting diode microstructures are being formed, light emitters may be formed in the semiconductor substrate. For example, the substrate may be a silicon carbide (SiC) substrate in which emitters have been formed, e.g. by atomic-scale defects or individual dopants in the silicon carbide. For example, the silicon carbide substrate may be approximately 500pm thick, with a 15pm thick epilayer.

The inorganic mask layer 110 is much less sensitive to etching by oxygen (e.g. relatively insensitive to etching by oxygen) within a reactive ion etching plasma than photoresist, which is an organic polymer based material. The inorganic mask layer 110 is a chemical vapour-deposited (e.g. plasma-enhanced deposited) or physical vapour-deposited dielectric or semiconductor mask layer. The material of the inorganic mask layer 110 is substantially uniform (e.g. having uniform density, hardness, and concentrations of species), and not crystalline, to avoid anisotropic etch rates, e.g. the inorganic mask layer may be a layer of one of amorphous dielectric, amorphous semiconductor, polycrystalline dielectric, and polycrystalline semiconductor. The crystal structure of the inorganic mask layer 110 is substantially isotropic (e.g. polycrystalline or amorphous) to facilitate a uniform transfer of the photoresist pattern to the photoresist layer 120. The inorganic mask layer 110 may be a layer of silicon dioxide (silica, SiO2), silicon nitride (SisN^, or silicon oxynitride (SiO_xN_y), aluminium oxide (AI2O3), which may be an amorphous layer. The inorganic mask layer 110 may be polycrystalline silicon (Si). The material from which the inorganic mask layer 110 is formed may be chosen to provide suitable etch selectivity against the substrate in which the microstructure is being formed. The material structure of the inorganic mask layer 110 makes it substantially impervious to the primary chemical etchant used for etching the substrate in the second reactive ion etching process (R2). The inorganic mask layer 110 may have a thickness of 500nm to 60pm, e.g. 1 pm to 60pm, or 2pm to 10pm. The illustrated inorganic mask layer 110 is a 5pm thick layer of silicon dioxide deposited by plasma-enhanced chemical vapour deposition (PECVD).

The photoresist layer 120 is a polymer-based resin material. The photoresist is supplied as a liquid, which may be spread across the surface of the inorganic mask layer 110 by spinning the substrate at high speed (e.g. 3000rpm) to produce a coating layer of uncured photoresist. The cured photoresist layer 120 may have a thickness of 500nm to 60pm, e.g. 1 pm to 60pm, e.g. 2 to 10 pm, e.g. 8pm thick). The illustrated cured photoresist layer 120 has a thickness of 5pm.

The inorganic mask layer 110 may be 0.8 times to 1.5 times the thickness of the cured photoresist 120 (e.g. in inverse correspondence with their respective etch rates during the first reactive ion etching process R1 , discussed further below).

Where smaller chips are processed, to minimize the formation of an edge bead at the edge of the substrate, when spinning the photoresist, the substrate may be abutted by other bodies with face that is flush with the face of the inorganic mask layer (e.g. dummy substrate sections). Alternatively, for wafer-scale processing, conventional edge-bead removal techniques can be applied.

The photoresist layer is then cured to produce the structure shown in Figure 1A. The photoresist layer is thermally cured. Thermally curing the photoresist with a gradually increasing temperature enables solvent to evaporate from within a relatively thick photoresist layer without causing bubbling or distortion of the corresponding photoresist mask during subsequent development or other processes.

For example:

• After spin coating, solvent may evaporate from the photoresist at room temperature for 5 to 10 minutes.

• The substrate may be heated (e.g. within an oven, or on a hotplate) to 60°C, and maintained at that temperature for 10 to 20 minutes in an initial heating stage.

• The temperature of the substrate may be raised by up to 10°C per minute, up to a maximum temperature of 95 to 100°C (e.g. being raised from room temperature, or raised from 60°C where the initial heating stage is used).

• The substrate may be maintained at the maximum temperature for 20 to 30 minutes.

• The substrate is gradually cooled to room temperature, e.g. being cooled over 5 to 10 minutes. The cured photoresist layer 120 is then exposed to a pattern of light P, generally indicated in Figure 1 B(i), that produces a corresponding exposure pattern in the photoresist layer, having regions 120A that are not sufficiently exposed to be washed away during a development stage, and regions 120B that are sufficiently exposed to be washed away during a development stage.

As is illustrated in Figures 1 B(ii), 1 B(iii) and 1 B(iv), the pattern of illumination P may comprise a plurality of illumination stages P1 , P2, P3 (sub-steps) in which the exposure beam (e.g. laser writing beam, or electron beam) is focused at a plurality of different depths D1 , D2, D3 within the photoresist layer 120 (i.e. depth beneath upper surface of the photoresist layer 120). Exposures of illumination stages P1 , P2, P3 focused at different depths D1 , D2, D3, registered in-plane (i.e. parallel to the upper surface of the substrate, and perpendicular to the depth), provide a cumulative exposure pattern, which is taken into account in designing the exposure patterns of each illumination stage.

The illustrated photoresist layer 120 is formed from a positive photoresist (e.g. ma-P1275G from Micro Resist technology, or PMMA), in which exposure to light degrades the photoresist. Where the photoresist has been sufficiently exposed it is then dissolved by washing with a developer solvent. (Alternatively, a negative photoresist may be used, e.g. Sll-8.)

Positive photoresist that has been exposed sufficiently that it may be washed away (or conversely retained, in the case of negative photoresist) in a subsequent development stage may be referred to as being “exposed”.

The unexposed photoresist 120A may be relatively opaque to radiation in the exposure sensitivity range (e.g. 350nm to 450nm) of the photoresist, for example absorbing at least 75% (e.g. at least 90%) of the radiation in 200pm depth. However, the exposed photoresist 120B may be relatively transparent to radiation in the exposure sensitivity range, for example transmitting at least 75% (e.g. at least 90%) of the radiation in a 200pm depth.

As illustrated, the depth to which each layer 120Bi , 120Bii, 120Biii is exposed (the development front) may be varied in correspondence with the pattern of intensity (modulated dose) of the respective illumination stage P1 , P2, P3. Accordingly, the depth to which photoresist may be exposed (the development front) may be patterned even with only a single illumination stage P1 . The depth to which each layer 120Bi, 120BH, 120Biii is exposed is additionally subject to cumulative exposure arising from any other illumination stages, and from any scattering of radiation within the photoresist 120. Although Figures 1 B(ii) to 1 B(iv) illustrate illumination stages at only three different depths D1 , D2, D3, the cumulative profile to which the photoresist is exposed (development front) may be built-up from one, two or a much larger number of illumination stages, e.g. up to 20 illumination stages at different depths. There may be 1 to 20 illumination stages focussed at different depths. Where a plurality of illumination stages P1-P3 are used, the illumination stages may be focussed at depths D1-D3 that are spaced apart by 2pm to 5pm, e.g. 3pm to 4pm. The use of multiple illumination stages focussed at different depths enhances resolution and reduces the risk of overexposure.

Figure 1 Bv illustrates the structure of Figure 1 Biv, after the exposed photoresist 120Bi, 120BH, 120Biii has been washed away during the subsequent development stage, leaving a residue of the unexposed photoresist 120A, with the outline of the original cured photoresist layer 120 indicated by a dashed line. The residue 120A of the polymer-based photoresist layer 120 forms a photoresist mask 122, which is a first three-dimensional lithographic mask. The photoresist mask 122 is then baked in a drying process to reduce retained solvent, e.g. 10min at 60°C.

Alternatively, the pattern of the photoresist mask 122 may be written by electron-beam lithography (EBL). As with optical lithography described above, the EBL may comprise a plurality of illumination stages (e.g. 1 to 20 illumination stages) focussed at different depths D1 , D2, D3 within the photoresist layer 120, with spatially different patterns P1, P2, P3 of exposure at different depths (focal planes). PMMA photoresist may be particularly suitable for use with EBL.

A first reactive ion etching process R1 uses first etch conditions. The etch gas and plasma conditions may be chosen to provide an etch selectivity of the material of the inorganic mask layer 110 relative to the photoresist mask 122 that is close to unity (e.g. the inorganic mask material etches at 0.8 times to 1.5 times the rate at which the photoresist mask etches).

For example, where the substrate 100 is silicon carbide, the plasma in the first reactive ion etching process R1 may be formed from trifluoromethane (CHF3) gas, argon (Ar) and oxygen (O2) (oxygen has a much lower etch rate of silicon carbide than for the inorganic mask layer 110, e.g. silicon dioxide). The trifluoromethane preferentially etches the inorganic mask layer 110, and the oxygen preferentially etches the photoresist mask 122. The relative proportions of argon and oxygen are controlled to control the selectivity of the first reactive ion etching process R1 , with a greater proportion of argon increasing selectivity (e.g. up to about 4), and a greater proportion of oxygen reducing selectivity (e.g. well below unity). For example, the etch selectivity may be tuned by varying the relative proportions of argon and oxygen, whilst maintaining the sum of their flow rates. The argon provides thermal cooling of the chip, in addition to a small amount of physical etching of both the photoresist mask 122 and the inorganic mask layer 110.

For example: By volume (i.e. in standard cubic centimetres per minute, seem), a gas mixture of 25 parts trifluoromethane, 7 parts argon, and 3 parts oxygen may be used. With 105W plasma RF power (e.g. 90 to 110W), 20 mTorr (2.67 Pa) etch pressure, and 12 mTorr (1.60 Pa) helium pressure to the back side of the carrier wafer for cooling, this gas mixture provided approximately unity selectivity during the first reactive ion etching process R1. Temperature control may be provided by alternating between periods of etching and periods substantially without etching, during which heat is dissipated from the wafer and its carrier (e.g. off periods of 20% to 100% of the on periods). Temperature control may prevent the temperature of the photoresist mask 122 rising to a level sufficient to soften and reflow the photoresist mask (e.g. avoiding exceeding above 60°C).

The first reactive ion etching process R1 is used to anisotropically etch both the photoresist mask 122 and the inorganic mask layer 110, to produce an inorganic mask 112, which is a second three-dimensional lithographic mask. The first reactive ion etching process R1 proceeds until the maximally etched regions of the inorganic mask layer 110 have been etched through. The inorganic mask 112 is produced by the first reactive ion etching process R1 causing the transfer to the inorganic mask layer 110 of a three-dimensional pattern corresponding to that of the photoresist mask 122. Differences in shape between the photoresist mask 122 and the inorganic mask 112 arise, including from differences in the etch rates of the material of the photoresist mask and the material of the inorganic mask, as well as from the first reactive ion etching process R1 not being purely unidirectional.

The use of near unity selectivity (0.8 to 1.5) in the first reactive ion etching process R1 enables good resolution of the inorganic mask 112 formed from the inorganic mask layer 110.

A second reactive ion etching process R2 is used under second etch conditions. The etch gas and plasma conditions may be chosen to provide selectivity of 0.5 to 6, or 1 to 2 (i.e. to etch the material of substrate 100 at a rate that is 0.5 times to 6 times faster, or 1 times to 2 times faster, than the rate at which it etches the material of the inorganic mask 112).

The etch selectivity of 0.5 to 6, when the silicon dioxide inorganic mask is used on silicon carbide enables accurate production of high features in the microstructure with high resolution and control, and selectivity of 1 to 2 may provide further enhanced fidelity in the transfer of the pattern of the inorganic mask 112 to the substrate 100. In contrast, hard masks commonly used for binary, two-dimensional etching result in a much higher selectivity when used on a silicon carbide substrate with a sulphur hexafluoride-based etch with similar silicon carbide etching performance, e.g. selectivity of approximately 20 to 90 for a nickel hard mask, and over 150 for copper hard mask.

An inorganic mask 112 formed from aluminium oxide may alternatively be used, and may be preferred where selectivity in the upper part of the range 0.5 to 6 is required.

Where the substrate 100 is silicon carbide, the plasma in the second reactive ion etching process R2 may be formed from a mixture of sulphur hexafluoride (SFe), argon (Ar) and oxygen (O2). The oxygen acts to densify the plasma and enhance the etch rate of the silicon carbide substrate through chemical etching of the carbon atoms. The sulphur hexafluoride (primary chemical etchant in the in the illustrated second reactive ion etching process R2) preferentially etches the silicon carbide over silicon dioxide with a selectivity of approximately 5. The selectivity may be reduced by the introduction of a low proportion of trifluoromethane into the RIE plasma, which etches the silicon dioxide, but substantially does not etch silicon carbide. Again, the argon provide thermal cooling of the substrate, including a small amount of physical etching.

The gas mixture was between 0 and 10 seem of each of the argon and oxygen, with the volume of sulphur hexafluoride remaining at least twice the sum of the volumes of argon and oxygen. For example: By volume (i.e. in standard cubic centimetres per minute, seem), a gas mixture of 20 parts sulphur hexafluoride, 5 parts oxygen, and 2 parts argon may be used.

With a 160W plasma RF power (e.g. 120W to 200W), 10 mTorr (1.33 Pa) etch pressure, and 12 mTorr (1.60 Pa) helium pressure to the back side of the carrier wafer for cooling, this gas mixture provided approximately 1.2 etch selectivity during the second reactive ion etching process R2. Temperature control may be provided by alternating between periods of etching and periods substantially without etching, during which heat is dissipated from the wafer and its carrier (e.g. off periods of 20% to 100% of the on periods). Temperature control may prevent an enhanced etching rate of the substrate that may increase roughness of the etched surfaces, and may reduce the presence of temperature gradients that may lead to uneven etching, so enhancing the controllability and reproducibility of the microstructure formation.

The second reactive ion etching process R2 is used to anisotropically etch both the inorganic mask 112 and the substrate 100, to produce a microstructure(s) 102 etched into the substrate. The microstructure 102 in the substrate is produced by the second reactive ion etching process R2 causing transfer to the substrate 100 of a three-dimensional pattern corresponding to that of the inorganic mask 112. Differences in shape between the inorganic mask 112 and the microstructure 102 arise, including from differences in the etch rates of the material of the inorganic mask and the material of the substrate (etch selectivity), as well as from the second reactive ion etching process R2 not being purely unidirectional. In particular, by the selection of a greater or lesser etch selectivity, the vertical aspect ratio of the microstructures 102 can be selected.

In both the first and second reactive ion etching processes R1 , R2, the etch mechanism for the mask material may be dominated by chemical etching, producing volatile products, as opposed to physical etching by bombarding the surface and sputtering target material. Rates of physical etching are primarily dependent upon the hardness of the material being etched. Rates of chemical etching are dependent upon the chemical reactions of the plasma ions and the material being etched. Accordingly, the combination of the gas in the plasma, the respective mask and the underlying layer, for each reactive ion etching process R1 , R2 is chosen to enable the required etch selectivity. Excess physical etching would be damaging to the surface of the photoresist mask 122, leading to roughness in the shape transferred to the inorganic mask 112.

The intermediary inorganic mask takes a three-dimensional shape that corresponds to the initial photoresist mask, and the microstructure etched into the substrate then takes a shape that corresponds to the three-dimensional shape of the inorganic mask. By using the intermediary inorganic mask, two separate reactive ion etching processes R1 , R2 can be used with different etch gases and plasma properties, enabling the manufacture of the microstructure to be decoupled, to a great extent, from the selectivity of the substrate over the photoresist mask, as arises in a single reactive ion etching process in the absence of the inorganic mask. By tuning the two independent reactive ion etch processes R1 , R2, this decoupling enables three- dimensional microstructures to be accurately, reproducibly and rapidly formed, with a substantial, controllable etch depth. The use of an inorganic mask that is more durable than a conventional photoresist mask enables the microstructure to be etched with a greater etch depth, when required, than would be possible with only a photoresist mask (i.e. without the inorganic mask). For example the etch depth of the microstructures may be between 2 and 30 pm.

By the use of two largely decoupled reactive ion etching processes R1 , R2, the disclosed method enables microstructures of substantial height to be formed, without the prior art problem of poor resolution from the use of a particularly thick photoresist layer, or the prior art problem of baked- on photoresist residues from the use of hard-baked photoresist. Additionally, by the choice of one or both of the first reactive ion etching process R1 and the second reactive ion etching process R2 (e.g. choice of gas chemistries in forming their respective plasmas), microstructures of different heights can be formed with the identical photoresist masks 122. Similarly, by the choice of second reactive ion etching process R2, microstructures of different heights can be formed with the same first reactive ion etching process R1. For example, this may enable the use of a standardised process for formation of the photoresist mask 122 and may enable the use of a standardised first reactive ion etching process R1 , one or both of which may simplify manufacturing and further enhance manufacturing reliability and yield.

Figure 1 E schematically illustrates a manufactured microstructure 102, which is a microlens (e.g. a substantially hemispherical solid immersion lens).

Figure 1 F shows a scanning electron microscope image of a small portion of a silicon carbide wafer substrate 100 on which a two-dimensional array of hemispherical microlenses 102 was formed by the disclosed method. The disclosed method enables the production of thousands of microlenses to be accurately formed in just a few hours. Figure 1G shows an enlarged view of one of the microlenses 102 of Figure 1 F, which has a height of approximately 5pm, and is generally hemispherical.

Figures 1A to 1C have illustrated the use of a silicon dioxide inorganic mask layer 110 and inorganic mask 112. Alternatively, the inorganic mask layer 110 may be formed from silicon nitride, silicon oxynitride, or aluminium oxide. The material of the inorganic mask layer 110 is chosen to provide the selectivities discussed above.

The substrate may comprise a light emitter 140, and the microlens 102 (or other microstructure) may be formed over the light emitter. In the case of a silicon carbide substrate, quantum emitters may be formed by atomic-scale defects or individual dopants in the silicon carbide.

The microstructure may be an optical component, for example a microlens, and the light emitter may be on an optical axis of the microstructure. As shown in Figure 1 E, in the case that the microlens 102 is a hemispherical microlens, the light emitter 140 may be provided at the centre of curvature of the microlens, enabling emitted light E to be incident perpendicular to the surface of the microlens, maximising the proportion of the emitted light that is transmitted out of the substrate, and so addressing the limitation by total internal reflection of photon emission from high refractive index materials. Manufacture by the disclosed method can enable the brightness of the light emitter to be substantially and reliably increased over other geometries. The emitted light E has a wide angular spread and may be captured by optics with a large aperture. Figure 2A shows a scanning electron microscope (SEM) image of a further array of microlenses 102 manufactured by the disclosed method, and Figure 2B shows an enlarged view of one of the microlenses. The solid line of Figure 2C shows a cross-sectional height measurement of the microlens 102 of Figure 2B, and a perfect hemispherical shape is indicated by the dotted line, for reference.

The microstructure may have other shapes apart from being hemispherical. For example, in the case that the microstructure is a microlens, the microlens may be shaped to refract emitted light E’ into a substantially parallel (or focussed) beam, enabling the emitted light to be captured with a smaller optical aperture. For example, by suitable shaping of the microlens, light may be coupled to an optical fibre.

For example, by the use of a second reactive ion etching process R2 that has a selectivity greater than unity, a greater aspect ratio microlens 102’ may be formed, e.g. a prolate hemispheroid (e.g. having a cross-sectional shape of half an ellipse with a long axis perpendicular to the surface of the substrate), which refracts the emitted light E’ towards the optical axis (vertical axis as shown) of the microlens, as shown in Figure 3.

The microstructure (e.g. microlens 102, 102’) may be formed within a trench 104, which spaces apart a surrounding etch wall 106 from the microlens, as shown in Figure 2B. The provision of a trench 104 may increase the solid angle over through which light E’ transmitted by the microlens 102 may be captured (or for light in the opposite direction, received), by the etch wall reflecting light away from the substrate. The surround etch wall 106 may be angled at approximately 45° to the plane of the substrate, e.g. being angled at 30° to 60°.

A surrounding etch wall 106 may be provided with a coating 108 (shown in Figure 4) that is optically reflective at the operating wavelength(s) of the emitted light E, E’ (or conversely, received light), which may enhance the optical coupling of the microstructure with other optical elements. For example, the coating may be a metallization layer, e.g. gold (Au), aluminium (Al), nickel (Ni) or chromium (Cr).

As shown in Figure 4 the microstructure 102’ may be surrounded by an etch wall 106 that is shaped to reflect emitted light from the microstructure (or conversely received light) into a parallel or focussed beam. The etch wall 106 may be provided with a reflective coating 108. Where the light reflected by the etch wall 106 is emitted from the microlens 102’ approximately radially, the etch wall 106 may be shaped approximately parabolically, and vertically aligned with the respect to an emitter 140 in the substrate 100 to produce a parallel beam of light E2’.

The microstructures illustrated in the above figures have been microlenses, e.g. solid immersion microlenses. Microlenses may have use including in semiconductor photonics, biophotonics and electronic circuit investigations (e.g. used as magnifiers to image microcircuits, improving spatial resolution). The disclosed method may also be used in the manufacture of other optical elements for optics industry, e.g. Fresnel lenses, blazed gratings, optical channels, optical interconnects for integrated photonic circuits and telecommunications transmitters/receivers/transceivers, and light collectors for single photon devices in quantum sensing and quantum networking and quantum computing devices. Further, the present method may be used in the formation of other microstructures, for example in the formation of microstructures for power electronics, in which the shape of the structure provides a channel for electrons.

The features of specific examples above may be used in combination or interchangeably depending on the context. For a surrounding etch wall, which may or may not be provided with a reflective coating, may be provided with microstructures other than those that comprise a light emitter.

Throughout the description and claims of this specification, the words “comprise” and “contain” and variations of them mean “including but not limited to”, and they are not intended to (and do not) exclude other moieties, additives, components, integers or steps. Throughout the description and claims of this specification, the singular encompasses the plural unless the context otherwise requires. In particular, where the indefinite article is used, the specification is to be understood as contemplating plurality as well as singularity, unless the context requires otherwise.

Features, integers, characteristics, compounds, chemical moieties or groups described in conjunction with a particular aspect, embodiment or example of the invention are to be understood to be applicable to any other aspect, embodiment or example described herein unless incompatible therewith. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive. The invention is not restricted to the details of any foregoing embodiments. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed. The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

Claims

1 . A method of etching a three-dimensional microstructure in a substrate comprising: providing a substrate (100); depositing an inorganic mask layer (110) on the surface of the substrate, wherein the inorganic mask layer has a different composition from the substrate; providing a polymer-based photoresist layer (120) on the inorganic mask layer (110); forming a first three-dimensional lithographic mask (122) in the polymer-based photoresist layer (120) comprising exposing the polymer-based photoresist layer with patterned illumination (L) and developing the polymer-based photoresist layer; etching the photoresist mask (122) and the inorganic mask layer (110) with a first reactive ion etching process (R1) to produce a second three-dimensional lithographic mask (112) in the inorganic mask layer (110); and etching the second three-dimensional lithographic mask (112) and the substrate (100) with a second reactive ion etching process (R2) to produce a three-dimensional microstructure (102) in the substrate.

2. The method according to claim 1 , wherein the inorganic mask layer (110) is one of amorphous dielectric, amorphous semiconductor, polycrystalline dielectric, and polycrystalline semiconductor.

3. The method according to claim 1 or claim 2, wherein the inorganic mask layer (110) is a layer of silicon oxide, silicon nitride, silicon oxynitride, aluminium oxide, silicon, a group lll-V semiconductor, or a group ll-VI semiconductor.

4. The method according to any one of claims 1 to 3, wherein the substrate (100) is a semiconductor substrate.

5. The method according to claim 4, wherein the semiconductor substrate is a silicon carbide substrate.

6. The method according to any preceding claim, wherein the material of the inorganic mask layer (110) etches at 0.8 times to 1.5 times the rate at which the material of the photoresist mask (122) etches during the first reactive ion etching process (R1).

7. The method according to any preceding claim, wherein during the first reactive ion etching process (R1) a plasma is formed from a gas comprising trifluoromethane.

8. The method according to claim 7, wherein during the first reactive ion etching process (R1) a plasma is formed from a gas comprising argon and oxygen.

9. The method according to any preceding claim, wherein the material of the substrate (100) etches at 0.5 times to 6 times the rate at which the material of the inorganic mask (120) etches during the second reactive ion etching process (R2).

10. The method according to any preceding claim, wherein during the second reactive ion etching process (R2) a plasma is formed from a gas comprising sulphur hexafluoride, and one or both of argon and oxygen.

11. The method according to any preceding claim, wherein the second reactive ion etching process uses a plasma formed from a gas with a greater proportion of oxygen than the first reactive ion etch process.

12. The method according to any preceding claim, wherein the photoresist layer (120) is thermally cured by a baking step during which the temperature of the substrate is raised by up to 10°C per minute, up to a maximum temperature of 95 to 100°C.

13. The method according to any preceding claim, wherein the patterned illumination (P) comprises a plurality of illumination stages (P1 , P2, P3) focused within the photoresist layer (120) to focal planes with different depths (D1 , D2, D3) beneath the upper surface of the photoresist layer.

14. The method according to claim 13, wherein the plurality of illumination stages (P1 , P2, P3) focussed to different depths (D1 , D2, D3) have spatially different patterns of exposure in their respective focal planes.

15. The method according to claim 13 or claim 14, wherein the different depths (D1 , D2, D3) are spaced apart by 2pm to 5pm.

16. The method according to any preceding claim, wherein an etch wall (106) is provided proximate the microstructure (102) and coated with an optically reflective coating (108).

17. The method three-dimensional microstructure according to any preceding claim, wherein the 3D microstructure (102) is a micro-lens array.

18. The method according to any preceding claim, wherein the microstructure (102) is aligned with a light emitter (140) within the substrate (100).

19. The method according to claim 18, wherein the 3D microstructure (102) is a micro-lens shaped to refract light (E) emitted from the light emitter (140) into a substantially parallel beam (E, E1’) or a convergently focussed beam.

20. The method according to claim 18 or claim 19, wherein an etch wall (106) is provided proximate the microstructure (102) to receive light (E) emitted by the light emitter (140) and coated with an optically reflective coating (108), and the etch wall is shaped to reflect the received light into a substantially parallel beam (E2’).

21. The method according to any preceding claim, wherein the microstructure (102) has at least one of a height or width that is 1 nm to 250pm in size.

22. A three-dimensional microstructure (102) formed in a substrate by the method of any preceding claim.