WO2024099038A1 - Gain control apparatus and method - Google Patents

Abstract

The present invention relates to a gain control apparatus and control method. According to an embodiment, the gain control apparatus may comprise: a voltage measurement circuit, configured to receive a measured voltage of an amplifier, compare the measured voltage with a plurality of threshold voltages in a preset order, and output a control signal on the basis of comparison results; a change-over switch, separately coupling the plurality of threshold voltages to the voltage measurement circuit in the preset order so as to compare same with the measured voltage; and a gain control circuit, configured to output a gain signal to the amplifier on the basis of the control signal output by the voltage measurement circuit.

Description

Gain control device and method Technical Field

The present application relates to the field of power amplifier gain control, and in particular to a gain control circuit of an amplifier and an electronic device having the circuit.

Background technique

Typically, in audio devices such as speakers, the audio output is generated by multiplying the input signal by the gain of the corresponding circuit, and its maximum output amplitude is generally determined by the supply voltage. In order to make the speaker work in an appropriate voltage range, a protection mechanism needs to be added to the circuit, such as providing an automatic gain control (AGC) circuit in the front stage of the power amplifier. Specifically, a protection threshold can be set and the speaker output can be compared with it. If the signal amplitude is higher than the set threshold voltage, the AGC circuit can reduce the amplifier gain to avoid truncation distortion and protect the speaker; conversely, if the signal amplitude is lower than the set release threshold voltage, the AGC circuit will increase the amplifier gain to achieve the effect of increasing the volume and ensuring the sound quality.

In the AGC control circuit of the prior art, in order to improve the gain control accuracy, it is generally necessary to set multiple AGC control circuits to compare the output signal with multiple preset thresholds to obtain a gain signal. Since each control circuit includes discrete electronic devices such as a comparator, this will increase the occupied area of the entire AGC control circuit and the power consumption of the circuit.

Summary of the invention

In order to solve the above technical problems, the present application provides an automatic gain control device and method, which can reduce circuit area and circuit power consumption while ensuring sound quality.

One aspect of the present invention provides a gain control device, which includes: a voltage detection circuit, configured to receive a detection voltage of an amplifier and compare the detection voltage with multiple threshold voltages in a preset order, and output a control signal based on the comparison result; a switching switch, coupling the multiple threshold voltages to the voltage detection circuit in the preset order to compare with the detection voltage; and a gain control circuit, configured to output a gain signal to the amplifier based on the control signal output by the voltage detection circuit.

In some embodiments, the device further includes: a mode signal generating circuit configured to generate a mode signal based on a magnitude relationship between the multiple threshold voltages, the mode signal being associated with the preset order of comparing the multiple threshold voltages with the detection voltage respectively.

In some embodiments, the multiple threshold voltages include a first threshold voltage and at least one fixed threshold voltage, the first threshold voltage is associated with the supply voltage of the amplifier, and the mode signal is determined based on a comparison result of the first threshold voltage and the at least one fixed threshold voltage.

In some embodiments, the voltage detection circuit includes: a plurality of comparators, one input terminal of each comparator is coupled to the detection voltage of the amplifier, and another input terminal of each comparator is coupled to one of the plurality of threshold voltages.

In some embodiments, the control signal includes a gain increase control signal, a gain decrease control signal, and a zero-crossing signal.

In some embodiments, the plurality of comparators include a first comparator having a positive input terminal coupled to a detection voltage of the amplifier and a negative input terminal coupled to a common mode level, and the zero-crossing signal is determined based on an output of the first comparator.

In some embodiments, the multiple comparators include a second comparator, whose positive input and reverse input are respectively coupled to one of the multiple threshold voltages and the detection voltage of the amplifier via the switching switch, and the increased gain control signal is determined at least based on the output of the second comparator.

In some embodiments, the multiple comparators include a third comparator and a fourth comparator, the inverting input terminal of the third comparator is coupled to the detection voltage of the amplifier, and the other end is coupled to one of the multiple threshold voltages via the switching switch, the positive input terminal of the fourth comparator is coupled to the detection voltage of the amplifier, and the other end is coupled to one of the multiple threshold voltages via the switching switch, and the gain reduction control signal is determined based on at least the outputs of the third comparator and the fourth comparator.

In some embodiments, the voltage detection circuit further includes: a first reduced gain control signal generating circuit, which includes N triggers connected in series, and the C terminal of each trigger is coupled to the output terminal of the third comparator and the fourth comparator, N≥2.

In some embodiments, the zero-crossing signal is further configured to clear the outputs of the N flip-flops.

In some embodiments, the voltage detection circuit further comprises: a second gain reduction control signal generating The circuit comprises an AND gate operation unit, a first input end of the AND gate operation unit is coupled to the first reduced gain control signal generating circuit, and a second input end of the AND gate operation unit is coupled to the outputs of the third comparator and the fourth comparator.

In some embodiments, the gain control device further includes: a switching signal generating circuit configured to generate a switch switching signal of the switch based on a result of comparing the detection voltage of the amplifier with the plurality of threshold voltages.

In some embodiments, the mode signal generating circuit includes: a fifth comparator, whose positive input terminal and reverse input terminal are respectively coupled to the first threshold voltage and the fixed at least one level threshold voltage via a mode switching switch; a second trigger, whose C terminal is coupled to the output terminal of the fifth comparator; a third trigger, whose C terminal is coupled to the output terminal of the fifth comparator via an inverter, and whose D terminal is connected to the Q terminal of the second trigger; wherein the mode signal is determined based on the Q terminal outputs of the second trigger and the third trigger.

In some embodiments, the voltage detection circuit is configured to output the control signal according to the comparison result and the mode signal.

One aspect of the present invention provides a gain control method, which includes: determining multiple threshold voltages, the multiple threshold voltages include a first threshold voltage and at least one fixed threshold voltage, wherein the first threshold voltage is associated with the supply voltage of the amplifier; comparing the first threshold voltage with the at least one fixed threshold voltage, and determining a mode signal for gain control according to the comparison result; comparing the detection voltage of the amplifier with the multiple threshold voltages in a preset order, and outputting a control signal according to the comparison result, wherein the mode signal is associated with the preset order in which the multiple threshold voltages are compared with the detection voltage; wherein a first gain reduction control signal is output when the detection voltage of the amplifier is greater than the first threshold voltage; and when there is at least one threshold voltage less than the first threshold voltage and the detection voltage of the amplifier is greater than the at least one fixed threshold voltage, another corresponding gain reduction control signal is output, and the first gain reduction control signal is configured to have a higher priority than the other gain reduction control signal.

In some embodiments, the fixed at least one level threshold voltage includes at least a second threshold voltage and a third threshold voltage, and comparing the first threshold voltage with the fixed at least one level threshold voltage, and determining the mode signal of the gain control according to the comparison result includes: when the first threshold voltage is greater than the second threshold voltage and the third threshold voltage, determining the mode signal as the first mode signal; when the first threshold voltage is between the second threshold voltage and the third threshold voltage, The mode signal is determined to be a second mode signal; when the first threshold voltage is less than the second threshold voltage and the third threshold voltage, the mode signal is determined to be a third mode signal.

In some embodiments, the comparing the detection voltage of the amplifier with the multiple threshold voltages in a preset order and outputting a control signal according to the comparison result includes: under a first mode signal, outputting a third gain reduction control signal when the detection voltage of the amplifier is greater than the third threshold voltage, outputting a second gain reduction control signal when the detection voltage of the amplifier is greater than the second threshold voltage, and outputting the first gain reduction control signal when the detection voltage of the amplifier is greater than the first threshold voltage; under a second mode signal, outputting the third gain reduction control signal when the detection voltage of the amplifier is greater than the third threshold voltage, outputting the first gain reduction control signal when the detection voltage of the amplifier is greater than the first threshold voltage, and under a third mode signal, outputting the first gain reduction control signal when the detection voltage of the amplifier is greater than the first threshold voltage, wherein the first gain reduction control signal, the second gain reduction control signal, and the third gain reduction control signal are associated with different gain reduction start times.

In some embodiments, the method further includes comparing a detection voltage of the amplifier with a fixed fourth threshold voltage, and outputting an increase gain control signal in response to when the detection voltage of the amplifier is less than the fourth threshold voltage, wherein the first decrease gain control signal is configured to have a higher priority than the increase gain control signal.

Another aspect of the present invention provides an audio device, comprising the gain control device described above, and a speaker coupled to the gain control device.

By using the exemplary gain control device provided by the present invention, by setting a switching switch to switch between multiple threshold voltages in a preset order, the reuse of circuit elements can be achieved, thereby simplifying the analog circuit structure. Under the premise of ensuring the increase of volume and the reduction of output truncation noise, the occupied area of the gain control circuit can be reduced and the power consumption of the circuit can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

By describing the embodiments of the present application in more detail in conjunction with the accompanying drawings, the above and other purposes, features and advantages of the present application will become more apparent. The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

FIG1 is a schematic structural block diagram of a gain control device according to an embodiment of the present invention;

FIG2 is a schematic structural block diagram of a gain control device according to an embodiment of the present invention;

3 is a schematic circuit diagram of a voltage detection circuit in a gain control device according to an embodiment of the present invention;

4 is a schematic circuit diagram of a mode signal generating circuit in a gain control device according to an embodiment of the present invention;

FIG5 is a flow chart of a gain control method according to an embodiment of the present invention;

6 is a flow chart of a method for performing gain control according to a gain control mode according to an embodiment of the present invention;

FIG7 is a gain control signal effect diagram in a control mode according to an embodiment of the present invention;

FIG8 is a gain control signal effect diagram in another control mode according to an embodiment of the present invention;

FIG. 9 is a diagram showing the effect of a gain control signal in another control mode according to an embodiment of the present invention.

Detailed ways

Some example embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments, rather than all the embodiments. It should be understood that the present invention should not be limited to the specific details of these example embodiments. Instead, embodiments of the present invention can be implemented without these specific details or in other alternatives without departing from the ideas and principles of the present invention defined in the claims.

Referring to FIG1 , it shows a schematic structural block diagram of a gain control device according to an embodiment of the present invention, and the gain control device may include a voltage detection circuit 110, a switch 120, and a gain control circuit 130. The gain control device may provide a gain signal for the audio amplifier. Schematically, as shown in FIG1 , the voltage detection circuit 110 in the gain control device may receive a detection voltage and other signals of the amplifier 100. The detection voltage may be, for example, the output voltage signal V _OUT of the amplifier 100 shown in FIG1 , that is, the voltage detection circuit 110 is coupled to the output end of the amplifier 100. The present invention is not limited thereto, and the voltage detection circuit 110 may also be coupled to the input end of the amplifier, and the detection voltage may be the input voltage signal V _IN of the amplifier 100 accordingly. The corresponding amplifier output voltage value may be obtained by gain conversion. In some embodiments, in order to facilitate the circuit implementation of voltage comparison, the detection voltage of the amplifier 100 may also be a voltage signal after the output voltage signal V _OUT or the input voltage signal V _IN is reduced in voltage.

After receiving the detection voltage of the amplifier 100, the voltage detection circuit 110 can compare the detection voltage with a plurality of threshold voltages in a preset order, and output a control signal as a basis for determining the gain control according to the comparison result. The threshold voltages can be stored in a predetermined register, for example, and the number of the threshold voltages can be It is determined according to the gain control accuracy. For example, more than 3 (for example, 4, 5, 6, etc.) threshold voltages may be set. In one embodiment, the control signal may include a gain increase control signal, a gain decrease control signal and a zero-crossing signal. For example, when the detection voltage crosses the zero point or is in the adjacent interval of the zero-crossing point, the voltage detection circuit 110 may generate a zero-crossing signal; when the detection voltage is less than a set threshold voltage (for example, a release threshold), the voltage detection circuit 110 may generate a gain increase control signal; and when the detection voltage is greater than another set threshold voltage (for example, a start threshold), the voltage detection circuit 110 may generate a gain decrease control signal, and the generated control signal may be output to the gain control circuit. In one embodiment, multiple levels of start threshold voltages may be set, and the number of the start threshold voltages may be determined according to the gain control accuracy. For example, more than 2 (for example, 3, 4, etc.) start threshold voltages may be set. Different start threshold voltages may correspond to different gain decrease control signals, that is, when the detection voltage is greater than one of the start threshold voltages, the voltage detection circuit 110 may generate a corresponding level of gain decrease control signal. Different levels of gain reduction control signals may be associated with different gain reduction start-up times. For example, the gain reduction start-up time corresponding to a larger start-up threshold voltage may be smaller than the gain reduction start-up time corresponding to a smaller start-up threshold voltage, so that when it is detected that the output voltage of the amplifier 100 is large (for example, close to the truncation voltage), the gain control device can respond quickly to reduce the gain of the amplifier to avoid truncation noise, and when the output voltage of the amplifier 100 is small, the amplifier can be controlled to smoothly reduce the gain to ensure a stable volume.

In one embodiment, among the set multi-level startup threshold voltages, one of the threshold voltages (hereinafter referred to as the first threshold voltage) can be configured to be related to the supply voltage of the amplifier 100, while the other threshold voltages can be configured to be pre-set fixed values. For example, the magnitude of the first threshold voltage can be configured to be associated with the magnitude of the supply voltage of the amplifier 100, for example, the two are positively correlated, that is, the value of the first threshold voltage decreases as the supply voltage decreases. Configuring the first threshold voltage to be specifically set according to the actual supply voltage of the amplifier can reduce the power consumption of the audio power amplification system at low power, for example, while preventing truncation distortion. In a specific implementation, the first threshold voltage in the multi-level threshold voltage can also be compared with the remaining fixed threshold voltages, and the gain control mode can be determined based on the comparison result. Under different control modes, the detection voltage of the amplifier can be compared with each threshold voltage in different comparison orders, and different gain control signals may be generated, which will be described in detail later.

One end of the switch 120 is coupled to a plurality of threshold voltages, and one or more of the threshold voltages may be coupled to the voltage detection circuit 110 in a predetermined order to be compared with the detection voltage. In one example, the switch 120 may have a multi-pole multi-throw configuration, or may be configured by The switch is composed of several single-pole multi-throw or double-pole multi-throw switches. The switches' poles can be connected to circuit elements such as comparators inside the voltage detection circuit 110, and the throws can be connected to different threshold voltages. Each switch can be implemented in a variety of ways, including but not limited to field effect transistors, bipolar transistors, diodes and/or other types of switches.

The present invention sets a switching switch 120, which can, for example, couple different threshold voltages to the same comparator in the voltage detection circuit 110 in a preset order under the control of a switch switching signal, thereby achieving the effect of multiplexing the comparator in the voltage detection circuit 110. In this way, the number of analog circuit modules in the voltage detection circuit can be reduced, thereby reducing the circuit's occupied area and reducing the circuit's power consumption.

The input end of the gain control circuit 130 is coupled to the voltage detection circuit 110, and the gain control circuit 130 can receive the control signal output by the voltage detection circuit 110 and generate a gain signal based on the control signal, and then output the gain signal to the amplifier 100. For example, after receiving the increase gain control signal, the gain control circuit 130 can generate a gain increase signal to control the amplifier 100 to increase the gain, and when receiving the decrease gain control signal, it can generate a gain decrease signal to control the amplifier 100 to decrease the gain, so as to maintain the output voltage of the amplifier within a preset range.

FIG2 is a schematic structural block diagram of a gain control device according to an embodiment of the present invention, which includes a voltage detection circuit 110, a switching switch 120, and a gain control circuit 130. The arrangement and functions of these devices or circuits are the same as those of the circuit shown in FIG1 and are not described in detail here.

As shown in FIG2 , the gain control device further includes a switching signal generating circuit 140, which can be configured to generate a switch switching signal to control the switch 120 to couple multiple threshold voltages to the voltage detection circuit 110. In one embodiment, the switch switching signal can be generated based on the result of comparing the detection voltage of the amplifier 100 with multiple threshold voltages. After receiving the switch switching signal, the switch 120 can couple multiple threshold voltages connected to different throws to the voltage detection circuit 110 in a preset order. As shown in FIG2 , the switch 120 is connected to four threshold voltages through its multiple throws S1, S2, S3, and S4. Although only four throws are shown connected to four threshold voltages in the figure, it can be understood that it is only an example and not a limitation. Fewer (for example, 3) or more (for example, 5, 6, etc.) threshold voltages can be set according to actual applications. The switch 120 can also connect the multiple threshold voltages to the voltage detection circuit 110 through its multiple blades (not shown). In the example of FIG. 2 , the throw S4 is connected to the release threshold voltage RLS_Vref, while the throws S1 , S2 , S3 are connected to the multi-level start threshold voltages AGC1_Vref, AGC2_Vref, and AGC3_Vref, respectively.

In one embodiment, the switching signal generating circuit 140 can be configured to detect the voltage of the amplifier 100 and multiple The threshold voltages are compared in a preset order (e.g., ascending order) to generate corresponding switch switching signals, so that the output voltage of the amplifier 100 can be smoothly increased. For example, for the example of FIG. 2 , assuming that AGC1_Vref>AGC2_Vref>AGC3_Vref>RLS_Vref, the switch signal generation circuit 140 can first output a default switch switching signal to close the throw S4 so as to couple RLS_Vref to the voltage detection circuit 110. After the detection voltage is greater than RLS_Vref, the switch signal generation circuit 140 can generate a new switch signal to close the throw S3 so as to couple AGC3_Vref to the voltage detection circuit 110. After that, after the detection voltage is greater than AGC3_Vref, the switch signal generation circuit 140 can generate a new switch signal to close the throw S2 so as to couple AGC2_Vref to the voltage detection circuit 110. After that, after the detection voltage is greater than AGC2_Vref, the switch signal generation circuit 140 can generate a new switch signal to close the throw S1 so as to couple AGC1_Vref to the voltage detection circuit 110. It can be seen that under the control of the switching signal generating circuit 140, the switching switch 120 can couple the illustrated multiple threshold voltages to the voltage detection circuit 110 in the order of RLS_Vref→AGC3_Vref→AGC2_Vref→AGC1_Vref. When the threshold voltage is set to more than 4 (for example, 5, 6, etc.), the switching signal can be deduced accordingly.

In this embodiment, the switching signal generating circuit 140 can be implemented by a conventional comparator circuit. In one example, as described below, since the gain control signal can be determined based on the comparison results of the detection voltage of the amplifier and each threshold voltage, the switching signal generating circuit 140 can be implemented by multiplexing the comparator circuit in the voltage detection circuit 110.

The control principle of the gain control device of an example of the present invention is further described in detail below with reference to FIG. 2 and in combination with specific threshold voltages, control signal examples, etc. As mentioned above, the release threshold voltage RLS_Vref can be associated with the gain control signal. If the voltage detection circuit 110 detects that the detection voltage of the amplifier is less than the threshold voltage, it will generate the gain control signal RLS_FLAG. The start threshold voltages AGC3_Vref, AGC2_Vref, and AGC1_Vref can be associated with the gain control signal. That is, if the detection voltage of the amplifier exceeds the above threshold voltage, the voltage detection circuit 110 can generate corresponding gain control signals AGC3_FLAG, AGC2_FLAG, and AGC1_FLAG and output the corresponding control signal to the gain control circuit 130. In addition, when it is detected that the detection voltage of the amplifier exceeds the zero crossing point or is in the zero crossing interval, the voltage detection circuit 110 can also generate a zero crossing signal ZeroCross_FLAG.

After receiving one or more of the control signals RLS_FLAG, ZeroCross_FLAG, AGC3_FLAG, AGC2_FLAG, and AGC1_FLAG, the gain control circuit 130 may generate a gain signal according to a preset gain change logic and transmit the gain signal to the amplifier 100. To control the reduction or recovery of the gain of the amplifier. For example, after receiving RLS_FLAG and maintaining a high level for a predetermined time, the gain control circuit 130 can generate a gain signal for increasing the gain to control the amplifier 100 to increase the gain, and when receiving AGC3_FLAG, AGC2_FLAG or AGC1_FLAG, a gain signal for reducing the gain can be generated according to different levels of the corresponding gain reduction control signal to control the amplifier 100 to reduce the gain, thereby maintaining the output voltage of the amplifier within a preset range.

In one example, the gain reduction control signals AGC1_FLAG, AGC2_FLAG, and AGC3_FLAG can be configured to be associated with different gain reduction start times, for example, the gain reduction start times of AGC1_FLAG, AGC2_FLAG, and AGC3_FLAG are successively increased. For example, after receiving the control signal AGC3_FLAG or AGC2_FLAG, the gain control circuit 130 can trigger timing when the signal is triggered, and generate a gain signal to reduce the gain of the amplifier after determining that the signal is maintained or reaches a certain time, and after receiving the control signal AGC1_FLAG, the gain signal can be immediately generated to reduce the gain of the amplifier. In this way, when, for example, it is monitored that the detection voltage of the amplifier is greater than AGC1_Vref, the gain of the amplifier can be quickly reduced to avoid truncation distortion.

In one example, AGC1_FLAG, AGC2_FLAG, AGC3_FLAG, and RLS_FLAG can be configured to have different priorities, for example, the priorities of AGC1_FLAG, AGC2_FLAG, and AGC3_FLAG decrease in sequence, that is, AGC1_FLAG has the highest priority among all control signals, and once it is triggered, all other control signals being timed are invalid, and the corresponding timing is reset. This can prevent logical conflicts between different gain reduction control signals, so that when, for example, the detection voltage of the amplifier is detected to be greater than AGC1_Vref, the gain of the amplifier is quickly reduced to avoid truncation distortion.

In one example, one of the multi-level startup threshold voltages AGC1_Vref, AGC2_Vref, and AGC3_Vref associated with the gain reduction control signal can vary with the supply voltage of the amplifier, for example, the magnitude of the threshold voltage AGC1_Vref associated with the control signal AGC1_FLAG with the highest priority varies according to the actual supply voltage of the amplifier 100. In this way, when the supply voltage of the amplifier fluctuates (for example, lower than the rated voltage), the threshold voltage AGC1_Vref for monitoring truncation distortion can be reduced accordingly, thereby improving the applicability of the gain control device.

When AGC1_Vref changes with the actual supply voltage of the amplifier, its actual value may be greater than AGC2_Vref and AGC3_Vref, or between AGC2_Vref and AGC3_Vref, or less than AGC2_Vref and AGC3_Vref. AGC2_Vref and AGC1_Vref are coupled to the voltage detection circuit 110 under the control of the switch switching signal generated by the switch signal generating circuit 140. Therefore, when the magnitude relationship among the threshold voltages AGC1_Vref, AGC2_Vref and AGC3_Vref changes, it is necessary to adjust the generation order of the switch switching signals accordingly, so that the threshold voltages of each level can still be compared with the detection voltage in a preset order (for example, ascending order) to generate the switch switching signal, thereby achieving a smooth increase in the output voltage of the amplifier, and being able to reduce the gain in time when the detection voltage is greater than AGC1_Vref to prevent truncation distortion.

To this end, as shown in FIG2 , in one embodiment, the gain control device further includes a mode signal generating circuit 150, which may be configured to generate a mode signal (MODE_FLAG) based on the magnitude relationship between the multiple threshold voltages AGC1_Vref, AGC2_Vref, and AGC3_Vref, and the mode signal may be associated with a preset sequence of comparing the multiple threshold voltages with the detection voltages, that is, the mode signal is associated with the switching sequence of the switch 120. For example, the mode signal generating circuit 150 may output the mode signal MODE_FLAG to the switching signal generating circuit 140, which determines the comparison sequence between the detection voltage of the amplifier and the multiple threshold voltages accordingly after receiving the MODE_FLAG, and generates a corresponding switch switching signal to control the switch 120 to couple the corresponding threshold voltages to the voltage detection circuit 110 in the aforementioned preset sequence.

2 , when the amplifier is powered on and gain control is started, the mode signal generating circuit 150 can determine the corresponding mode signal based on the comparison relationship between the threshold voltages AGC1_Vref, AGC2_Vref, and AGC3_Vref related to reducing the gain control signal. Since only the threshold voltage AGC1_Vref is variable according to the actual supply voltage of the amplifier, the AGC1_Vref can be compared with AGC2_Vref and AGC3_Vref and the mode signal can be determined based on the comparison result. Moreover, the number of mode signals is the same as the number of the set start threshold voltages. For example, when AGC1_Vref is greater than AGC2_Vref and AGC3_Vref, the mode signal generating circuit 150 generates a default mode signal MODE1_FLAG; when AGC1_Vref is between AGC2_Vref and AGC3_Vref, the mode signal generating circuit 150 generates a second mode signal MODE2_FLAG; and when AGC1_Vref is less than AGC2_Vref and AGC3_Vref, the mode signal generating circuit 150 generates a third mode signal MODE3_FLAG.

Different mode signals determine the order in which the detection voltage of the amplifier is compared with the threshold voltages of each level, and accordingly, they determine the switching order of the switches S1-S4, so that, for example, the detection voltage of the amplifier can be compared with the threshold voltages of each level in a preset order (for example, ascending order). For example, assuming that after the amplifier is powered on, the switch 120 is initially switched to S4 and RLS_Vref is coupled to the voltage detection circuit 110, therefore, under MODE1_FLAG, the switching order of the switch is The switching sequence can be S4→S3→S2→S1. Under MODE2_FLAG, the switching sequence of the switch can be S4→S3→S1 (because the gain will be immediately reduced when the detection voltage is greater than AGC1_Vref, the switch generally does not need to be switched to S2). Under MODE3_FLAG, the switching sequence of the switch can be S4→S1. The switching control of the switch under different mode signals will be described in detail later in conjunction with Figures 6-8.

In this embodiment, since different control signals correspond to different gain change logics and have different priorities, the voltage detection circuit 110 can generate control signals with different timings under different mode signals. Accordingly, the gain control circuit 130 will generate different gain signals to achieve gain control of the amplifier, which can improve the applicability of the gain control device. For example, even when the supply voltage of the amplifier is at a low potential, the output voltage of the amplifier can still be smoothly increased, and truncation distortion can be prevented, while reducing system power consumption.

In some embodiments, as shown in FIG. 2 , the mode signal MODE_FLAG may also be output to the voltage detection circuit 110 for determining the generation of a portion of the gain control signal, which will be described in detail below in conjunction with FIG. 3 .

FIG3 is a schematic circuit diagram of a voltage detection circuit in a gain control device according to an embodiment of the present invention, which is implemented as an analog circuit. As shown in FIG3, in one embodiment, the voltage detection circuit may include a plurality of comparators 202-208, one input end of each comparator is directly or through a switching switch (the switch blade and the throw and the threshold voltage connected to each throw are shown in FIG3) coupled to the detection voltage AGC_IN of the amplifier 100, and the other input end is directly coupled to the voltage (common mode level) for judging whether the detection voltage is zero-crossing or coupled to one of the plurality of threshold voltages through the switching switch. By using the switching switch, the present embodiment only needs to set 4 comparators to realize the multi-stage gain control of the amplifier, while the prior art method will require at least 9 comparators, therefore, the present embodiment can simplify the analog circuit structure, reduce the circuit occupation area and reduce the circuit power consumption.

The positive input terminal of the first comparator 202 is coupled to the detection voltage AGC_IN of the amplifier, and the reverse input terminal is coupled to the common mode level VCM. By comparing the detection voltage received by it with the preset common mode level, when the first comparator 202 determines that the detection voltage is equal to the common mode level VCM, it can be determined that the voltage signal passes through the zero point and outputs the zero-crossing signal ZeroCross_FLAG. As described below, the zero-crossing signal can be used together with the gain reduction control signal (AGC1_FLAG, AGC2_FLAG, AGC3_FLAG) and/or the gain increase control signal (RLS_FLAG) to determine the gain signal to control the gain of the amplifier. As shown in the figure, the XOR gate 212 compares the delayed comparison signal obtained after the zero-crossing signal ZeroCross_FLAG passes through the delay circuit 210 (composed of an inverter and a delay unit in series) with the zero-crossing signal After ZeroCross_FLAG is processed accordingly, a clear signal CLR_FLAG is output. The clear signal CLR_FLAG flips to a high level when a zero-crossing signal is output. The clear signal CLR_FLAG can be used to clear the outputs of the triggers 220 and 222, which will also be described in detail later.

The positive input terminal and the reverse input terminal of the second comparator 204 are respectively coupled to a release threshold voltage RLS_Vref associated with the gain control and the detection voltage AGC_IN of the amplifier among the multiple threshold voltages via a switching switch, wherein RLS_Vref includes a pair of threshold voltages RLS_VH and RLS_VL whose absolute values of the difference with the common mode voltage VCM are equal but are positive and negative to each other, so as to judge whether the gain needs to be increased when the detection voltage AGC_IN is positive and negative respectively. In one example, the switching of the threshold voltage can be performed based on the switch switching signal. Specifically, when the detection voltage signal AGC_IN is in a high level phase, such as AGC_IN>VCM (for example, for a sinusoidal signal, the phase is 0-π/2), the switch switching signal can control the positive input terminal of the comparator 204 to be connected to the threshold voltage RLS_VH, and the reverse input terminal to be connected to the detection voltage AGC_IN, and when the detection voltage signal AGC_IN is in a low level phase, such as AGC_IN<VCM (for example, for a sinusoidal signal, the phase is π-3/2π), the switch switching signal will control the positive input terminal of the comparator 204 to be connected to the detection voltage AGC_IN, and the reverse input terminal to be connected to the threshold voltage RLS_VL. Through this signal control, when the detection voltage AGC_IN is between RLS_VH and RLS_VL, the comparator 204 will output the gain control signal RLS_FLAG. In an example, as shown in FIG. 3 , in order to ensure the priority of the gain control signals AGC1_FLAG, AGC2_FLAG, and AGC3_FLAG being reduced, the gain control signal RLS_FLAG can be output through an AND gate operation unit 216, a first input end of the AND gate operation unit 216 receiving the output signal of the comparator 204, and a second input end receiving the output of the NOR gate 214, the NOR gate 214 being provided with three input ends, which respectively receive the gain control signals AGC1_FLAG, AGC2_FLAG, and AGC3_FLAG being reduced.

The third comparator 206 and the fourth comparator 208 are used to determine at least one gain reduction control signal. The inverting input terminal of the third comparator 206 is coupled to the detection voltage AGC_IN of the amplifier, and the other end is coupled to one of the threshold voltages (AGC1_VL, AGC2_VL, AGC3_VL) via a switching switch. The positive input terminal of the fourth comparator 208 is coupled to the detection voltage AGC_IN of the amplifier, and the other end is coupled to one of the threshold voltages (AGC1_VH, AGC2_VH, AGC3_VH) via a switching switch. Wherein the threshold voltages AGC1_VL, AGC2_VL, AGC3_VL are respectively associated with the threshold voltages AGC1_VH, AGC2_VH, AGC3_VH, for example, the absolute values of the differences between AGC1_VL, AGC1_VH and the common mode voltage VCM are equal, but the positive and negative values are opposite, and the same is true for AGC2_Vref and AGC3_Vref. That is, the voltage pair (AGC1_VH, AGC1_VL), (AGC2_VH, AGC2_VL), (AGC3_VH, AGC3_VL) correspond to AGC1_Vref, AGC2_Vref, AGC3_Vref shown in FIG2 , respectively. The switch control signal can simultaneously control the positive input terminal of the third comparator 206 and the negative input terminal of the fourth comparator 208 to be coupled to a pair of threshold voltage pairs, respectively. Although the figure only shows that the comparators 206 and 208 are respectively connected to three threshold voltages, it can be understood that fewer (e.g., 2) or more (e.g., 4) threshold voltages can be set based on actual needs.

Multiple threshold voltages AGC1_VH, AGC2_VH, and AGC3_VH can be set according to actual needs. As an example, the relationship is AGC1_VH>AGC2_VH>AGC3_VH. In another example, as described above, the value of the first threshold voltage (for example, the voltage pair of AGC1_VH and AGC1_VL) among the three threshold voltages can be positively correlated with the supply voltage of the amplifier 100, and the other two threshold voltages AGC2_VH/AGC2_VL and AGC3_VH/AGC3_VL are configured to have fixed values, so when the supply voltage of the amplifier is small, the actual AGC1_VH may be between AGC2_VH and AGC3_VH, or less than AGC2_VH and AGC3_VH. As described above, under different mode signals, the threshold voltages AGC1_VH, AGC2_VH, and AGC3_VH will be coupled to the inverting input terminal of the comparator 208 in a corresponding preset order. Accordingly, the threshold voltages AGC1_VL, AGC2_VL, AGC3_VL will also be coupled to the positive input terminal of the comparator 206 in a predetermined order.

As shown in Fig. 3, the outputs of the third comparator 206 and the fourth comparator 208 are outputted after being ORed by the OR gate 218, which can be used to determine at least one gain reduction control signal. For example, when AGC_IN exceeds AGC3_VH or is lower than AGC3_VL, the output of the OR gate 218 can be used to determine AGC3_FLAG, when AGC_IN exceeds AGC2_VH or is lower than AGC2_VL, the output of the OR gate 218 can be used to determine AGC2_FLAG, and when AGC_IN exceeds AGC1_VH or is lower than AGC1_VL, the output of the OR gate 218 can be used to determine AGC1_FLAG.

In order to be able to track each gain reduction control signal (e.g., AGC1_FLAG, AGC2_FLAG, AGC3_FLAG) for the gain control circuit 130 to determine the gain signal of the amplifier, a separate gain control signal generation circuit is required to generate each gain reduction control signal separately. In one embodiment, each gain reduction control signal can be separated by a trigger. As shown in FIG3, the gain control signal generation circuit may include N triggers connected in series, N ≥ 2, which may correspond to the number of gain reduction control signals, or may be less than the number of gain reduction control signals (e.g., N = the number of gain reduction control signals - 1), and the trigger may be selected as a D trigger. The C terminal of each trigger 220, 222 is coupled to the output terminal of the third comparator 206 and the fourth comparator 208 through the OR gate 218. The D terminal of the trigger 220 is coupled to the pull-up level. Since the detection voltage AGC_IN of the amplifier exceeds the ratio When AGC3_VH connected to comparator 208 is lower than AGC3_VL connected to comparator 206, OR gate 218 will output a rising edge signal. The output pulse signal can trigger trigger 220 to output a high level at the Q end. Therefore, the gain control signal AGC3_FLAG can be reduced based on the Q end output of trigger 220.

The Q terminal of the trigger 220 is connected to the D terminal of the trigger 222. For example, when the detection voltage AGC_IN of the amplifier exceeds AGC3_VH, the switch can connect the threshold voltages AGC2_VH and AGC2_VL to the comparator 208 and the comparator 206 respectively under the control of the switching signal. At this time, if AGC_IN exceeds AGC2_VH connected to the comparator 208 or is lower than AGC2_VL connected to the comparator 206, the OR gate 218 will output a high level again, and the output pulse signal can trigger the trigger 222 to output a high level at the Q terminal, so the gain control signal AGC2_FLAG can be determined based on the Q terminal output of the trigger 222. In an example, the clear terminal CLR of the triggers 220 and 222 is coupled to the clear signal CLR_FLAG output by the XOR gate 212, which is used to clear the Q terminal output of the trigger when the detection voltage AGC_IN passes through zero.

By analogy, in one example, a third flip-flop (not shown) connected in series with the flip-flop 222 may be set to determine the reduced gain control signal AGC1_FLAG.

In another example, the gain reduction control signal generating circuit of AGC1_FLAG can be implemented by other circuit modules to adapt to the situation that the threshold voltage AGC1_VH/AGC1_VL varies with the supply voltage of the amplifier. FIG3 shows a specific embodiment. As shown in the figure, an AND gate operation unit 224 can be set to determine the gain reduction control signal AGC1_FLAG. The first input terminal of the AND gate 224 is coupled to the gain reduction control signal AGC2_FLAG output by the trigger 222 through the OR gate 226. The second input terminal of the AND gate 224 is coupled to the outputs of the third comparator 206 and the fourth comparator 208 through the OR gate 218. The first input terminal of the OR gate 226 is coupled to the output signal of the last trigger of the plurality of serially connected triggers 220 and 222, and the input of the second input terminal of the OR gate 226 is coupled to the mode signal through a gate circuit. For example, the second input terminal receives the output of the OR gate 228, and the first input terminal of the OR gate 228 is coupled to the mode signal MODE3_FLAG. The second input terminal of the OR gate 230 receives the output of the AND gate 230, and the first input terminal of the AND gate 230 is coupled to the mode signal MODE2_FLAG, and the second input terminal of the AND gate 230 is coupled to the output signal AGC3_FLAG of the trigger 220. With this exemplary circuit configuration, the voltage detection circuit determines AGC1_FLAG according to the voltage comparison result and the mode signal, so as to adapt to different gain control modes. For example, in mode MODE2 (AGC2_VH>AGC1_VH>AGC3_VH), the gain control signal AGC1_FLAG can be triggered before AGC2_FLAG, and in mode MODE3 (AGC2_VH>AGC3_VH> In the case of AGC1_VH, the gain control signal AGC1_FLAG may be triggered before AGC2_FLAG and AGC3_FLAG. The amplifier gain control in different control modes will be described in detail below.

FIG4 is a schematic circuit diagram of a mode signal generating circuit in a gain control device according to an embodiment of the present invention, which can be applied to the case where three start-up threshold voltages (AGC1_Vref, AGC2_Vref, AGC3_Vref) are provided as shown in FIG2-3. As shown in FIG4, the mode signal generating circuit may include a comparator 302 and two triggers 304 and 306. The positive input terminal and the reverse input terminal of the comparator 302 are respectively coupled to the first threshold voltage (e.g., AGC1_VL) and the fixed threshold voltage (e.g., AGC2_VL, AGC3_VL) via a switching switch 308. The switching switch 308 can be controlled by the mode signal MODE2_FLAG. Specifically, when MODE2_FLAG is 0 (e.g., when the system works in the default MODE1), its inverted signal is 1, and at this time, the positive input terminal of the comparator 302 is coupled to AGC1_VL, and the reverse input terminal is coupled to AGC2_VL. When MODE2_FLAG is 1, the positive input of the comparator 302 is coupled to AGC3_VL, and the negative input is coupled to AGC1_VL. The D terminal of the trigger 304 is coupled to the pull-up level, and its C terminal is coupled to the output terminal of the comparator 302, and its Q terminal output can be used to determine the mode signal MODE2_FLAG. The C terminal of the trigger 306 is coupled to the output terminal of the comparator 302 via the inverter 310, and the D terminal is connected to the Q terminal of the trigger 304. The mode signal MODE3_FLAG can be determined based on the Q terminal output of the trigger 306.

The working principle of the mode signal generating circuit shown in Figure 4 is as follows: in the initial state, the positive input terminal of the comparator 302 is coupled to AGC1_VL, and the reverse input terminal is coupled to AGC2_VL. If the system is in the default MODE1 (ie, AGC1_VL<AGC2_VL), the comparator 302 outputs a low level, and the outputs of the triggers 304 and 306 are also low levels, that is, MODE2_FLAG and MODE3_FLAG are both 0, and the output at the inverter 312 is 1, so the switching switch 308 does not switch.

If AGC1_VL changes and the working mode is no longer MODE1, for example, AGC1_VL>AGC2_VL, the output of comparator 302 changes from low to high, and the output pulse signal can trigger trigger 304 to output a high level at the Q end, that is, MODE2_FLAG is 1. At this time, the switch 308 switches, that is, the positive input end of comparator 302 will be coupled to AGC3_VL, and the reverse input end will be coupled to AGC1_VL. If AGC1_VL<AGC3_VL, then comparator 302 still outputs a high level, and the mode signal MODE2_FLAG is still 1. If AGC1_VL>AGC3_VL, then the output of comparator 302 changes from high to low again, and a pulse signal is formed through inverter 310 to trigger trigger 306 to output a high level at the Q end, that is, MODE3_FLAG is 1, so that it can be determined that the system is in working state. Mode MODE3.

It is understandable that although FIG. 4 illustrates a specific circuit structure, the present application is not limited thereto. For example, when fewer or more threshold voltages are set, a person skilled in the art may design a corresponding circuit through a comparator or a trigger to determine the mode signal.

FIG5 shows a flow chart of a gain control method according to an embodiment of the present invention. As shown in FIG5 , the control method may include the following steps:

Step 410 : determining a plurality of threshold voltages, where the plurality of threshold voltages may include a first threshold voltage and at least one fixed threshold voltage, wherein the first threshold voltage is associated with a supply voltage of the amplifier.

In one embodiment, in combination with FIG. 2-3, a multi-level startup threshold voltage AGC1_Vref, AGC2_Vref, AGC3_Vref and a release threshold voltage RLS_Vref can be determined according to actual needs, wherein each level of startup threshold voltage includes a pair of positive and negative threshold voltages, for example, AGC1_Vref includes a positive value AGC1_VH and a corresponding negative value AGC1_VL, and AGC2_Vref, AGC3_Vref and so on. Among them, the multi-level threshold voltage may include a first threshold voltage (for example, threshold voltage AGC1_Vref) associated with the supply voltage of the amplifier, and the remaining at least one level of threshold voltage AGC2_Vref, AGC3_Vref can be configured to have a fixed preset value (hereinafter referred to as the second threshold voltage and the third threshold voltage, respectively). Through this configuration, the present invention can adjust the gain control mode according to the actual supply voltage of the amplifier, thereby improving the applicability of the gain control and reducing the power consumption of the circuit. It can be understood that fewer (for example, 2 levels) or more (for example, 4 levels) startup threshold voltages can be determined according to actual needs, that is, the gain control method of this embodiment is not limited to application to the gain control device shown in FIG. 2-3.

Step 420: compare the first threshold voltage with the fixed at least one level threshold voltage, and determine a gain control mode signal according to the comparison result.

For example, since the first threshold voltage AGC1_Vref is related to the supply voltage of the amplifier, its actual value may be greater than the threshold voltages AGC2_Vref and AGC3_Vref, or may be less than the threshold voltages AGC2_Vref and AGC3_Vref. In one embodiment, the first threshold voltage AGC1_Vref may be compared with the fixed second threshold voltage AGC2_Vref and the third threshold voltage AGC3_Vref, and the mode signal of the gain control may be determined according to the comparison result. For example, when AGC1_Vref is greater than AGC2_Vref and AGC3_Vref, it may be determined as the first mode MODE1 (default mode), for example, the mode signal generating circuit generates the first mode signal MODE1_FLAG, and when AGC1_Vref is between AGC2_Vref and AGC3_Vref, it may be determined as the second mode MODE2 and generate the second mode signal MODE1_FLAG. The third mode signal MODE2_FLAG can be generated. When AGC1_Vref is less than AGC2_Vref and AGC3_Vref, the third mode MODE3 can be determined and the third mode signal MODE3_FLAG can be generated.

In one example, the determined mode signal may be associated with a preset order of comparing the multiple threshold voltages with the detection voltage respectively. According to the mode signal, the comparison order between the detection voltage of the amplifier and the respective threshold voltages may be determined, and on this basis, the gain control method may proceed to the next step.

Step 430 , comparing the detection voltage of the amplifier with the plurality of threshold voltages in a preset order, and outputting a control signal according to the comparison result.

In one embodiment, the input audio signal is processed by the amplifier and output as a detection voltage signal AGC_IN. In conjunction with Figures 2-3, the determined mode signal also determines the switching order of the switch, so that a switch switching signal can be generated according to the size of the detection voltage AGC_IN to control the switch to connect the threshold voltages of each level to the voltage detection circuit in a preset order, thereby comparing the detection voltage with the threshold voltages of each level AGC3_Vref, AGC2_Vref, and AGC1_Vref, and outputting corresponding control signals AGC3_FLAG, AGC2_FLAG, and AGC1_FLAG according to the comparison results, so that the generation timing of the gain control signal is adapted to different control modes, thereby achieving the effect of controlling the gain of the amplifier.

For example, when the detection voltage is greater than the adjustable threshold voltage AGC1_Vref, the voltage detection circuit can output the gain reduction control signal AGC1_FLAG, and when the detection voltage is greater than the fixed threshold voltages AGC2_Vref and AGC3_Vref, the corresponding gain reduction control signals AGC2_FLAG and AGC3_FLAG are output respectively. Among them, AGC1_FLAG, AGC2_FLAG, and AGC3_FLAG can be configured to have different priorities, for example, the priority of AGC1_FLAG is higher than the priority of AGC2_FLAG and AGC3_FLAG, that is, AGC1_FLAG has the highest priority among all control signals. Once it is triggered, AGC2_FLAG and AGC3_FLAG are invalid, and the corresponding timing is cleared, so that logical conflicts between different gain reduction control signals can be prevented.

In one embodiment, AGC1_FLAG and AGC2_FLAG/AGC3_FLAG may be associated with different gain reduction start times, respectively, and AGC2_FLAG and AGC3_FLAG may also be associated with different gain reduction start times, respectively. For example, the gain reduction start time associated with AGC1_FLAG may be less than the gain reduction start time associated with AGC2_FLAG and AGC3_FLAG, so that the gain can be quickly reduced when the detection voltage is large to prevent the amplifier from truncated distortion, and the gain reduction speed can be slowed down when the detection voltage is small to steadily increase the output volume.

In one embodiment, the detection voltage AGC_IN of the amplifier is compared with other threshold voltages. By comparison, other gain control signals can be determined. For example, the detection voltage AGC_IN can be compared with a fixed release threshold voltage RLS_Vref, and in response to the detection voltage of the amplifier being less than the threshold voltage RLS_Vref, the gain control signal RLS_FLAG is output to increase. For example, the detection voltage AGC_IN can be compared with a preset common mode level, and the zero-crossing signal ZeroCross_FLAG is output when the detection voltage is equal to the common mode level. Referring to FIG. 3 , the zero-crossing signal ZeroCross_FLAG can be used to generate a clearing signal CLR_FLAG, which can be used to clear part of the gain reduction control signal (AGC2_FLAG, AGC3_FLAG). In one embodiment, the zero-crossing signal ZeroCross_FLAG and the gain reduction control signals AGC2_FLAG and AGC3_FLAG can be used to determine the gain signal to more smoothly control the gain of the amplifier. In addition, the zero-crossing signal ZeroCross_FLAG can also be used to determine the gain signal with the gain control signal RLS_FLAG to increase the gain to control the gain of the amplifier.

In one embodiment, each control signal AGC1_FLAG, AGC2_FLAG, AGC3_FLAG, and RLS_FLAG can be configured to have different priorities. For example, AGC1_FLAG has the highest priority among all control signals. Once it is triggered, all other control signals being timed are invalid, and the corresponding start time timing is reset. In this way, when, for example, the output voltage of the amplifier is detected to be greater than AGC1_Vref, the gain of the amplifier can be quickly reduced to avoid truncation distortion.

Although not shown, the gain control method of this embodiment may further include a step of determining a gain signal, wherein the gain signal is determined according to the control signal to control the gain of the amplifier.

In one embodiment, referring to FIG. 2 , after receiving one or more of the control signals AGC1_FLAG, AGC2_FLAG, AGC3_FLAG, RLS_FLAG, and ZeroCross_FLAG, the gain control circuit 130 may determine a gain signal according to a preset gain change logic to control the gain of the amplifier.

For example, after receiving the gain increase control signal RLS_FLAG, if the gain control circuit 130 determines that the signal continues to be at a high level within a predetermined time (e.g., 10ms), it can determine to increase the gain, for example, increase the gain by 0.5dB, and increase the gain after waiting for the next zero crossing signal ZeroCross_FLAG or a predetermined time (e.g., 20ms).

Different gain change logics may also be set for different gain reduction control signals. For example, after receiving the gain reduction control signal AGC3_FLAG, if the gain control circuit 130 determines that the signal is triggered, it will time the first start time (e.g., 10ms), and when the zero crossing signal is triggered, it determines to reduce the gain by 0.5dB. After receiving the gain reduction control signal AGC2_FLAG, if the gain control circuit 130 determines that the signal is triggered, it will time the second start time, and the second start time (e.g., 1ms) may be is less than the first start-up time associated with AGC3_FLAG, and determines to reduce the gain by 0.5dB after the zero-crossing signal is triggered. After receiving the gain reduction control signal AGC1_FLAG, if the gain control circuit 130 determines that the third start-up time is timed after the signal is triggered, the third start-up time may be less than the second start-up time or even 0, that is, the gain is directly reduced after the signal is triggered. In one example, as described above, the priority of AGC1_FLAG can be configured to be the highest. If it is triggered, the gain control circuit 130 can determine that all other control signals RLS_FLAG, AGC3_FLAG, and AGC2_FLAG being timed are invalid, and reset these control signals to zero and re-time.

As described above, the automatic gain control method of the present application can first determine the mode signal of the gain control, and then perform gain control on the amplifier according to different control modes. FIG6 is a flow chart of a method for performing gain control according to a gain control mode according to an embodiment of the present invention. As shown in FIG6, the gain control method may include the following steps:

In step 510, a detection voltage signal of an amplifier is received.

1-2, the input audio signal is processed by the amplifier and output as a detection voltage signal AGC_IN, and the output signal can be connected to the voltage detection circuit 110 and the switching signal generation circuit 140. The switching signal generation circuit 140 can generate a switch switching signal according to the change value of AGC_IN to control the switch 120 to couple the corresponding threshold voltage to the voltage detection circuit 110, and the voltage detection circuit 110 can generate a control signal according to the comparison between AGC_IN and each threshold voltage.

In step 520, a threshold voltage associated with the increased gain control signal is coupled to a voltage detection circuit.

2-3 , the initial state of the switch 120 can be configured as S4 closed and the rest open, thereby coupling the threshold voltage RLS_Vref to the voltage detection circuit 110. Alternatively, after detecting the zero-crossing signal, the switch signal generation circuit can control the switch 120 to couple the threshold voltage RLS_Vref to the voltage detection circuit 120.

In steps 530 and 540, the threshold voltages are compared, and a mode signal for gain control is determined according to the comparison result.

As described above, the first threshold voltage AGC1_Vref may be associated with the supply voltage of the amplifier, and its actual value may be greater than the fixed second threshold voltage AGC2_Vref and the third threshold voltage AGC3_Vref, or may be less than the threshold voltages AGC2_Vref and AGC3_Vref. In an example, assuming that AGC2_Vref is greater than AGC3_Vref, referring to FIG. 4, the mode signal generating circuit may first compare the actually determined AGC1_Vref with AGC2_Vref (step 530). If AGC1_Vref is greater than AGC2_Vref, the control mode MODE1 (default control mode) may be determined, and the corresponding output Mode signal MODE1_FLAG, if AGC1_Vref is less than AGC2_Vref, then AGC1_Vref is compared with AGC3_Vref (step 540), if AGC1_Vref is greater than AGC3_Vref, control mode MODE2 can be determined and MODE2_FLAG can be output, otherwise control mode MODE3 can be determined and MODE3_FLAG can be output.

After determining the gain control mode, the gain control device can adjust the gain control method accordingly to perform gain control on the amplifier, for example, determining the switching order of the switch so that each threshold voltage can be compared with the detection voltage in a preset order (for example, ascending order), so that the amplifier can be flexibly controlled according to its supply voltage to achieve a smooth increase in the output voltage of the amplifier and effectively prevent truncation distortion, while also reducing power consumption. The following further describes the working principle of the gain control device under each control mode in conjunction with FIGS. 7-9.

Fig. 7 shows a gain control signal effect diagram under control mode MODE1. As shown in the figure, assuming that the detection voltage AGC_IN of the amplifier is a sine wave, when AGC_IN is equal to the common mode voltage VCM, the voltage detection circuit can output a zero-crossing signal ZeroCross_FLAG (not shown), and when AGC_IN is between RLS_VH and RLS_VL (non-common mode voltage), the voltage detection circuit can output a high-level RLS_FLAG signal. After receiving the control signal, the gain control circuit 130 can determine the gain signal according to the preset gain change logic and output it to the amplifier. For example, if it is determined that the RLS_FLAG signal is continuously at a high level within a predetermined time (e.g., 10ms), a gain signal with increased gain (e.g., 0.5dB) can be output and output to the amplifier.

2-3 , when AGC_IN exceeds RLS_VH or is lower than RLS_VL, RLS_FLAG will turn to a low level, and at the same time, the switching signal generating circuit 140 can control the switching switch 120 to couple the threshold voltage AGC3_Vref (including a pair of AGC3_VH and AGC3_VL) to the voltage detecting circuit 110 .

The voltage detection circuit 110 can compare AGC_IN with AGC3_VH and AGC3_VL. If it is less than AGC3_VH or greater than AGC3_VL, all control signals are low level, and the gain control circuit 130 can output a gain signal with increased gain after ZeroCross_FLAG is triggered and output it to the amplifier. If AGC_IN exceeds AGC3_VH or is lower than AGC3_VL, the trigger 220 receives a positive pulse and outputs a high-level AGC3_FLAG signal. At the same time, the switching signal generation circuit 140 can control the switching switch 120 to couple the threshold voltage AGC2_Vref (including a pair of AGC2_VH and AGC2_VL) to the voltage detection circuit 110. In one embodiment, the gain control circuit 130 performs timing after receiving the AGC3_FLAG signal. If the signal timing reaches a predetermined time (e.g., 10ms), a gain signal with reduced gain (e.g., 0.5dB) can be output and output to the amplifier when the zero-crossing signal is triggered.

After the switch 120 is switched, the voltage detection circuit 110 can compare AGC_IN with AGC2_VH and AGC2_VL. If it is less than AGC2_VH or greater than AGC2_VL, only AGC3_FLAG is at a high level. If AGC_IN exceeds AGC2_VH or is lower than AGC2_VL, the trigger 220 and the trigger 222 receive a positive pulse again, thereby outputting a high-level AGC2_FLAG. At the same time, the switching signal generation circuit 140 can control the switch 120 to couple the threshold voltage AGC1_Vref (including a pair of AGC1_VH and AGC1_VL) to the voltage detection circuit 110. In one embodiment, the gain control circuit 130 can clear the timing of AGC1_FLAG after receiving the AGC2_FLAG signal, and time the AGC2_FLAG signal. If the signal timing reaches a predetermined time (e.g., 500μs), a gain signal with a gain reduction of 0.5dB can be output when the zero-crossing signal is triggered and output to the amplifier.

After the switch 120 is switched, the voltage detection circuit 110 can compare AGC_IN with AGC1_VH and AGC1_VL. If it is less than AGC1_VH or greater than AGC1_VL, only AGC2_FLAG and AGC3_FLAG are high level. If AGC_IN exceeds AGC1_VH or is lower than AGC1_VL, both input terminals of the AND gate 224 receive high level signals, thereby outputting high level AGC1_FLAG. In one embodiment, in response to receiving the AGC1_FLAG signal, the gain control circuit 130 can immediately generate a gain signal that reduces the gain by 0.5dB to directly control the amplifier to reduce the gain to prevent truncation distortion. At the same time, since AGC1_FLAG has the highest priority, the remaining control signals AGC2_FLAG and AGC3_FLAG are invalid, and their corresponding timings are cleared. In addition, in response to receiving the AGC1_FLAG signal for the second time, the gain control circuit 130 may perform timing. If the signal timing reaches a predetermined time (eg, 50 μs), a gain signal with a gain reduced by 0.5 dB may be output to the amplifier to improve the stability of the amplifier output voltage.

In one embodiment, the switch 120 can keep coupling the threshold voltage AGC1_Vref to the voltage detection circuit 110. When the detection voltage AGC_IN is lower than AGC1_VH or higher than AGC1_VL, AGC1_FLAG will turn to a low level, and AGC2_FLAG and AGC3_FLAG will also jump to a low level when AGC_IN crosses zero.

FIG8 shows a gain control signal effect diagram under control mode MODE2. As shown in FIG8, in this mode, AGC1_Vref is between AGC2_Vref and AGC3_Vref. Similar to FIG7, when AGC_IN is between RLS_VH and RLS_VL, the voltage detection circuit can output a high-level RLS_FLAG signal. When the gain control circuit 130 determines that the RLS_FLAG signal is continuously at a high level within a predetermined time (e.g., 10ms), it outputs a gain signal with a gain increase of 0.5dB and outputs it to the amplifier.

When AGC_IN exceeds RLS_VH or is lower than RLS_VL, RLS_FLAG will turn to a low level. Meanwhile, the switching signal generating circuit 140 can control the switching switch 120 to couple the threshold voltage AGC3_Vref to the voltage detecting circuit 110 .

The voltage detection circuit 110 can compare AGC_IN with AGC3_VH and AGC3_VL. If it is less than AGC3_VH or greater than AGC3_VL, all control signals are low level, and the gain control circuit 130 can output a gain signal with increased gain after ZeroCross_FLAG is triggered and output it to the amplifier. If AGC_IN exceeds AGC3_VH or is lower than AGC3_VL, the trigger 220 receives a positive pulse and outputs a high-level AGC3_FLAG signal. At the same time, the switching signal generation circuit 140 can control the switching switch 120 to couple the threshold voltage AGC1_Vref to the voltage detection circuit 110. In one embodiment, the gain control circuit 130 performs timing after receiving the AGC3_FLAG signal. If the signal timing reaches a predetermined time (e.g., 10ms), a gain signal with reduced gain (e.g., 0.5dB) can be output and output to the amplifier when the zero-crossing signal is triggered.

After the switch 120 is switched, the voltage detection circuit 110 can compare AGC_IN with AGC1_VH and AGC1_VL. If it is less than AGC1_VH or greater than AGC1_VL, only AGC3_FLAG is at a high level. If AGC_IN exceeds AGC1_VH or is lower than AGC1_VL, the trigger 222 is triggered again, and both input terminals of the AND gate 224 receive high-level signals, and the control signal AGC1_FLAG is also turned to a high level. In one embodiment, in response to receiving the AGC1_FLAG signal, the gain control circuit 130 can immediately generate a gain signal that reduces the gain by 0.5dB to directly control the amplifier to reduce the gain to prevent truncation distortion. At the same time, since AGC1_FLAG has the highest priority, the remaining control signals AGC2_FLAG and AGC3_FLAG are invalid, and their corresponding timings are cleared. In addition, in response to receiving the AGC1_FLAG signal for the second time, the gain control circuit 130 may perform timing. If the signal timing reaches a predetermined time (eg, 50 μs), a gain signal with a gain reduced by 0.5 dB may be output to the amplifier to improve the stability of the amplifier output voltage.

It can be seen that, generally speaking, under the control mode MODE2, the voltage detection circuit 110 only needs to compare the detection voltage AGC_IN with AGC3_Vref and AGC1_Vref to generate a control signal, thereby ensuring that the amplifier can still smoothly increase the output voltage of the amplifier under a low supply voltage, and effectively prevent the occurrence of truncation distortion, while also reducing circuit power consumption.

Figure 9 shows the gain control signal effect diagram under control mode MODE3. As shown in Figure 9, in this mode, AGC1_Vref is less than AGC2_Vref and AGC3_Vref. Similar to Figure 7-8, when AGC_IN is between RLS_VH and RLS_VL, the voltage detection circuit can output a high level. When the gain control circuit 130 determines that the RLS_FLAG signal is continuously at a high level for a predetermined time (eg, 10 ms), it outputs a gain signal with a gain increase of 0.5 dB to the amplifier.

When AGC_IN exceeds RLS_VH or is lower than RLS_VL, RLS_FLAG will turn to a low level. Meanwhile, the switching signal generating circuit 140 can control the switching switch 120 to couple the threshold voltage AGC1_Vref to the voltage detecting circuit 110 .

After the switch 120 is switched, the voltage detection circuit 110 can compare AGC_IN with AGC1_VH and AGC1_VL. If it is less than AGC1_VH or greater than AGC1_VL, all control signals are low level, and the gain control circuit 130 can output a gain signal with increased gain after ZeroCross_FLAG is triggered and output it to the amplifier. If AGC_IN exceeds AGC1_VH or is lower than AGC1_VL, the trigger 220 receives a positive pulse and outputs a high level AGC3_FLAG signal. At the same time, both input ends of the AND gate 224 receive high level signals, and the control signal AGC1_FLAG is also converted to a high level. In one embodiment, as described above, in response to receiving the AGC1_FLAG signal, the gain control circuit 130 can immediately generate a gain signal to directly control the amplifier to reduce the gain to prevent truncation distortion. At the same time, since AGC1_FLAG has the highest priority, the control signal AGC3_FLAG is invalid and does not start the corresponding timing. In addition, in response to receiving the AGC1_FLAG signal for the second time, the gain control circuit 130 may perform timing. If the signal timing reaches a predetermined time (eg, 50 μs), a gain signal with a gain reduced by 0.5 dB may be output to the amplifier to improve the stability of the amplifier output voltage.

It can be seen that, generally speaking, under the control mode MODE3, the voltage detection circuit 110 only needs to compare the detection voltage AGC_IN with AGC1_Vref, thereby ensuring that the amplifier can still smoothly increase the output voltage of the amplifier under a low supply voltage, effectively preventing the occurrence of truncation distortion, and reducing circuit power consumption.

The present invention also provides an audio device, which electronic device can be a playback device including a power amplifier, such as a speaker, which includes the gain control device described above, and the gain control device can be coupled to the speaker so that the gain of the amplifier can be controlled according to the gain control method described above.

The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations. It cannot be considered that these advantages, strengths, effects, etc. must be possessed by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limiting. The above details are not limiting. The above specific details are necessary to implement this application.

The block diagrams of the devices, devices, equipment, and systems involved in this application are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagram. As will be appreciated by those skilled in the art, these devices, devices, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open words, referring to "including but not limited to", and can be used interchangeably with them. As commonly used herein, the word "coupled" refers to two or more elements that can be directly connected or connected through one or more intermediate elements. Similarly, as commonly used herein, the word "connected" refers to two or more elements that can be directly connected or connected through one or more intermediate elements. The words "or" and "and" used here refer to the words "and/or", and can be used interchangeably with them, unless the context clearly indicates otherwise. The words "such as" used here refer to the phrase "such as but not limited to", and can be used interchangeably with them.

It should also be noted that in the apparatus, device and method of the present application, each component or each step can be decomposed and/or recombined. Such decomposition and/or recombination should be regarded as equivalent solutions of the present application.

The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims (20)

A gain control device, comprising: A voltage detection circuit is configured to receive a detection voltage of the amplifier and compare the detection voltage with a plurality of threshold voltages in a preset order, and output a control signal according to the comparison result; A switching switch is used to couple the plurality of threshold voltages to the voltage detection circuit in the preset order to compare with the detection voltage; and The gain control circuit is configured to output a gain signal to the amplifier based on a control signal output by the voltage detection circuit. The gain control device according to claim 1 further includes: a mode signal generating circuit, which is configured to generate a mode signal based on the magnitude relationship between the multiple threshold voltages, and the mode signal is associated with the preset order of comparing the multiple threshold voltages with the detection voltage respectively. The gain control device according to claim 2, wherein the multiple threshold voltages include a first threshold voltage and at least one fixed threshold voltage, the first threshold voltage is associated with the supply voltage of the amplifier, and the mode signal is determined based on a comparison result of the first threshold voltage and the at least one fixed threshold voltage. The gain control device according to claim 1, wherein the voltage detection circuit comprises: A plurality of comparators are provided, wherein one input terminal of each comparator is coupled to the detection voltage of the amplifier, and the other input terminal of each comparator is coupled to one of the plurality of threshold voltages. The gain control device according to claim 4, wherein the control signal comprises a gain increase control signal, a gain decrease control signal and a zero-crossing signal. The gain control device according to claim 5, wherein the plurality of comparators include a first comparator, a positive input terminal of the first comparator is coupled to the detection voltage of the amplifier, a negative input terminal of the first comparator is coupled to a common mode level, and the zero-crossing signal is determined based on an output of the first comparator. The gain control device according to claim 5, wherein the plurality of comparators include a second comparator, a positive input terminal and a negative input terminal of the second comparator are respectively coupled to one of the plurality of threshold voltages and a detection voltage of the amplifier via the switching switch, and the increased gain control signal is determined based on at least an output of the second comparator. The gain control device according to claim 5, wherein the plurality of comparators include a third comparator and a fourth comparator, the inverting input terminal of the third comparator is coupled to the detection voltage of the amplifier, and the other terminal is coupled to one of the plurality of threshold voltages via the switching switch, the positive input terminal of the fourth comparator is coupled to the detection voltage of the amplifier, and the other terminal is coupled to one of the plurality of threshold voltages via the switching switch, and the gain reduction control signal is determined based on at least the outputs of the third comparator and the fourth comparator. The gain control device according to claim 8, wherein the voltage detection circuit further comprises: The first gain reduction control signal generating circuit comprises N flip-flops connected in series, wherein the C terminal of each flip-flop is coupled to the output terminals of the third comparator and the fourth comparator, and N≥2. The gain control device according to claim 9, wherein the zero-crossing signal is further configured to clear the outputs of the N flip-flops. The gain control device according to claim 9, wherein the voltage detection circuit further comprises: The second gain reduction control signal generating circuit comprises an AND gate operation unit, wherein a first input end of the AND gate operation unit is coupled to the first gain reduction control signal generating circuit, and a second input end of the AND gate operation unit is coupled to the outputs of the third comparator and the fourth comparator. The gain control device according to claim 1, further comprising: a switching signal generating circuit configured to generate a switch switching signal of the switching switch based on a result of comparing the detection voltage of the amplifier with the plurality of threshold voltages. The gain control device according to claim 3, wherein the mode signal generating circuit comprises: a fifth comparator, wherein a positive input terminal and a negative input terminal of the fifth comparator are respectively coupled to the first threshold voltage and the fixed at least one level threshold voltage via a mode switching switch; A second trigger, a C terminal of which is coupled to the output terminal of the fifth comparator; A third flip-flop, a C terminal of which is coupled to the output terminal of the fifth comparator via an inverter, and a D terminal of which is connected to the Q terminal of the second flip-flop; The mode signal is determined based on the Q-end outputs of the second flip-flop and the third flip-flop. A gain control method, comprising: Determine a plurality of threshold voltages, the plurality of threshold voltages comprising a first threshold voltage and at least one fixed threshold voltage, wherein the first threshold voltage is associated with a supply voltage of the amplifier; Comparing the first threshold voltage with the fixed at least one level threshold voltage, and determining a mode signal of gain control according to the comparison result; Comparing the detection voltage of the amplifier with the plurality of threshold voltages in a preset order, and outputting a control signal according to the comparison result, wherein the mode signal is associated with the preset order in which the plurality of threshold voltages are compared with the detection voltage; Wherein, a first gain reduction control signal is output when the detection voltage of the amplifier is greater than the first threshold voltage; another gain reduction control signal is output when there is at least one threshold voltage less than the first threshold voltage and the detection voltage of the amplifier is greater than the fixed at least one threshold voltage, and the first gain reduction control signal is configured to have a higher priority than the other gain reduction control signal. The gain control method according to claim 14, wherein the fixed at least one threshold voltage includes at least a second threshold voltage and a third threshold voltage, and comparing the first threshold voltage with the fixed at least one threshold voltage, and determining the mode signal of the gain control according to the comparison result comprises: When the first threshold voltage is greater than the second threshold voltage and the third threshold voltage, it is determined that The mode signal is a first mode signal; When the first threshold voltage is between the second threshold voltage and the third threshold voltage, determining that the mode signal is a second mode signal; When the first threshold voltage is less than the second threshold voltage and the third threshold voltage, the mode signal is determined to be a third mode signal. The gain control method according to claim 15, wherein the step of comparing the detection voltage of the amplifier with the plurality of threshold voltages in a preset order and outputting a control signal according to the comparison result comprises: In the first mode signal, when the detection voltage of the amplifier is greater than the third threshold voltage, a third gain reduction control signal is output; when the detection voltage of the amplifier is greater than the second threshold voltage, a second gain reduction control signal is output; when the detection voltage of the amplifier is greater than the first threshold voltage, the first gain reduction control signal is output; In the second mode signal, when the detection voltage of the amplifier is greater than the third threshold voltage, the third gain reduction control signal is output, and when the detection voltage of the amplifier is greater than the first threshold voltage, the first gain reduction control signal is output, In the third mode signal, when the detection voltage of the amplifier is greater than the first threshold voltage, the first gain reduction control signal is output, The first gain reduction control signal, the second gain reduction control signal, and the third gain reduction control signal are associated with different gain reduction start times. The gain control method according to claim 14, further comprising: The detection voltage of the amplifier is compared with a fixed fourth threshold voltage, and an increase gain control signal is output in response when the detection voltage of the amplifier is less than the fourth threshold voltage, wherein the first decrease gain control signal is configured to have a higher priority than the increase gain control signal. An audio device comprises a gain control device and a speaker coupled to the gain control device, wherein the gain control device comprises: A voltage detection circuit is configured to receive a detection voltage of the amplifier and compare the detection voltage with a plurality of threshold voltages in a preset order, and output a control signal according to the comparison result; A switching switch is used to couple the plurality of threshold voltages to the voltage detection circuit in the preset order to compare with the detection voltage; and The gain control circuit is configured to output a gain signal to the amplifier based on a control signal output by the voltage detection circuit. The audio device according to claim 18, wherein the gain control device further comprises: a mode signal generating circuit, which is configured to generate a mode signal based on the magnitude relationship between the multiple threshold voltages, and the mode signal is associated with the preset order of comparing the multiple threshold voltages with the detection voltage respectively. The audio device according to claim 18, wherein the gain control device further comprises: a switching signal generating circuit configured to generate a switch switching signal of the switching switch based on a result of comparing the detection voltage of the amplifier with the plurality of threshold voltages.