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WO2024020860A1 - 一种音频格式转换装置 - Google Patents

一种音频格式转换装置 Download PDF

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Publication number
WO2024020860A1
WO2024020860A1 PCT/CN2022/108274 CN2022108274W WO2024020860A1 WO 2024020860 A1 WO2024020860 A1 WO 2024020860A1 CN 2022108274 W CN2022108274 W CN 2022108274W WO 2024020860 A1 WO2024020860 A1 WO 2024020860A1
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Prior art keywords
audio
data
format
clock signal
module
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PCT/CN2022/108274
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English (en)
French (fr)
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任衍坤
姜南
欧阳旭阳
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苏州长风航空电子有限公司
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Publication of WO2024020860A1 publication Critical patent/WO2024020860A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/16—Sound input; Sound output
    • G06F3/162—Interface to dedicated audio devices, e.g. audio drivers, interface to CODECs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus

Definitions

  • the present invention relates to audio format conversion technology, and in particular, to an audio format conversion device based on a field programmable logic gate array (FPGA).
  • FPGA field programmable logic gate array
  • HD Audio High Definition Audio
  • Intel and Dolby has large data transmission bandwidth, high audio playback accuracy, supports multi-channel array microphone audio input, lower CPU usage and low-level driver
  • the program can be used universally and other features. Since its launch, HD Audio has obvious advantages and huge development potential.
  • the HD Audio audio specification is widely used in many CPUs.
  • the HD Audio audio decoder is currently only in the hands of REALTEK, and there is a risk of shortage in the domestic market.
  • I2S integrated circuit built-in audio bus
  • Philips for audio data transmission between digital audio devices. It is also a widely used audio standard.
  • the existing I2S decoder technology on the market is mature and there are many manufacturers.
  • the present invention provides an audio format conversion device based on a field programmable gate array, and its purpose is to provide an audio format conversion device that can be used in any model of A device that converts HD Audio format audio data into I2S format audio data on a field programmable gate array to ensure the normal use of HD Audio format audio.
  • an audio format conversion device based on a field programmable gate array.
  • the device includes a clock management module, and the clock management module is used to provide one or more clocks. signal; the device converts audio data in HD Audio format into audio data in I2S format according to the clock signal; the device includes: a data processing module, and a serial-to-parallel conversion module electrically connected to the data processing module, Storage unit operation module, parallel-to-serial conversion module; wherein, the data processing module collects the audio data in the HD Audio format, and the parallel-to-serial conversion module outputs the audio data in the I2S format converted by the device.
  • the data processing module and the clock management module receive the audio clock signal of the HD Audio format audio data; the clock management module generates the clock signal according to the audio clock signal.
  • the clock signal includes at least a second clock signal, and the frequency of the second clock signal is twice that of the audio clock signal;
  • the data processing module collects audio data in the HD Audio format It includes: the data processing module collects audio data in HD Audio format at the rising edge and falling edge of the audio clock signal or at the rising edge of the second clock signal.
  • the device converts audio data in HD Audio format into audio data in I2S format according to the clock signal, including: the serial-to-parallel conversion module receives the audio data in HD Audio format, performs serial-to-parallel Convert, and return the converted parallel audio data to the data processing module; the data processing module identifies the left channel data and right channel data in the parallel audio data, and sets the channel mark bit; The device stores the left channel data and/or the right channel data, and outputs the audio data in the I2S format.
  • the device storing the left channel data and/or the right channel data includes: the storage unit operation module receives the left channel data and/or the right channel data through the serial-to-parallel conversion module. or the right channel data, and store the left channel data and/or the right channel data respectively according to the channel mark bit and the audio clock signal or the second clock signal.
  • the clock signal includes an output audio clock and a channel switching clock; the outputting the audio data in the I2S format includes: the storage unit operation module reads the audio data according to the channel switching clock.
  • the left channel data and/or the right channel data are transmitted to the parallel-to-serial conversion module; the parallel-to-serial conversion module converts the left channel data and/or the Right channel data, output the audio data in the I2S format.
  • the storage unit operation module is electrically connected to at least one memory, which may be a storage unit inside the device, or any device with a storage function that can be externally connected to the device.
  • the memory includes at least two FIFO memories, and the two FIFO memories store the left channel data and the right channel data respectively.
  • the data processing module also receives a frame synchronization clock signal, which is used to identify and synchronize instructions and audio data; performing serial-to-parallel conversion includes: in each of the synchronization clock signals The falling edge of , performs serial-to-parallel conversion.
  • the advantages of the present invention are: (1) breaking the restriction that audio output in HD Audio format can only be realized by REALTEK decoders; (2) realizing audio data based on any type of field programmable gate array Conversion, the implementation of technical solutions is flexible and does not rely on hardware equipment, that is, the chip has more selectivity and is cheaper; (3) The audio in HD Audio format is processed separately for the left channel and right channel data to ensure The integrity of the audio data is ensured; (4) The audio output method is flexible and can be output in two channels or in mono; (5) The audio data in I2S format is output, which can reduce the sampling bandwidth. coming timing error.
  • Figure 1 Schematic diagram of the overall structure of an audio format conversion device based on a field programmable gate array provided by an embodiment of the present invention.
  • Figure 2 A schematic diagram of the overall structure of an audio format conversion device based on a field programmable gate array provided by another embodiment of the present invention.
  • "at least one kind” means one kind, two kinds, three kinds, four kinds, five kinds, six kinds, seven kinds. One species, eight species, or more species.
  • multiple kinds means two kinds (numbers), three kinds (numbers), four kinds (numbers), five kinds (numbers), six kinds (numbers), seven kinds (numbers), eight kinds (numbers) (person) or more (person).
  • field programmable gate array or other similar terms include any form of programmable logic device. It should be understood that with the development of computer technology and electronic technology, any chip used for logic function design and digital circuit design, regardless of how its model, size, structure, component units, materials, performance, etc. change or update, should Included in the field programmable gate array range.
  • the terms “comprising”, “comprising”, “containing” and “having” are open-ended and do not exclude additional unrecited elements, steps or ingredients.
  • the term “consisting essentially of” means a scope limitation to the specified element, step or ingredient plus the optional presence of other elements, steps or ingredients that do not materially affect the basic and novel characteristics of the claimed subject matter. It should be understood that the term “comprises” encompasses the terms “consisting essentially of” and “consisting of”.
  • the invention provides an audio format conversion device based on a field programmable gate array, including a clock management module for providing one or more clock signals; the device converts audio data in HD Audio format into audio data in I2S format according to the clock signal. ;
  • the device includes: a data processing module, and a serial-to-parallel conversion module, a storage unit operation module, and a parallel-to-serial conversion module that are circuit-connected to the data processing module; among them, the data processing module collects audio data in HD Audio format, and the parallel-to-serial conversion module outputs Audio data in I2S format converted by the device.
  • the audio format conversion device can use any type of field programmable gate array (FPGA) on the hardware circuit.
  • the audio format conversion device may include one or more general input or output pins or other interfaces for communication, which may be electrically connected to the HD Audio format audio data interface while ensuring that the level standard is consistent.
  • the audio data in HD Audio format can be output by any model of processor (CPU) or any other electronic device with this function.
  • the audio data in the I2S format involved in the following embodiments can be any number of data (hereinafter referred to as "sampling number of bits"), such as commonly used 16 bits, 32 bits, etc.
  • the sampling frequency of audio data in I2S format can be set to 8K to 48K Hz or other non-standard frequencies (hereinafter referred to as "sampling frequency"), but usually, the sampling frequency The higher the value, the better the output audio quality; and for audio data in I2S format, the maximum sampling frequency that the decoder can support is 48K Hz. Therefore, for audio data in I2S format, using a sampling frequency of 48K Hz can achieve the best output audio quality.
  • the audio data obtained by the audio format conversion device according to the present invention can be applied to audio data in the I2S format with a sampling frequency of 48K Hz.
  • the audio format conversion device can be electrically connected to any device capable of generating audio data in HD Audio format to receive audio data in HD Audio format and convert it into audio data in I2S format for output.
  • any device capable of generating audio data in HD Audio format to receive audio data in HD Audio format and convert it into audio data in I2S format for output.
  • the following embodiments take a processor (CPU) as a device for generating audio data in HD Audio format as an example for description.
  • FIG. 1 An audio format conversion device based on a field programmable gate array provided by one embodiment of the present invention is shown in Figure 1.
  • the audio format conversion device based on a field programmable gate array includes a clock management module, which is used to provide one or more clock signals.
  • the audio format conversion device converts audio data in HD Audio format into audio data in I2S format based on the clock signal.
  • the audio format conversion device includes a data processing module, a serial-to-parallel conversion module, a storage unit operation module, and a parallel-to-serial conversion module that are electrically connected to the data processing module.
  • the data processing module collects audio data in HD Audio format
  • the parallel-to-serial conversion module outputs the converted audio data in I2S format.
  • the processor (CPU) can generate audio data in HD Audio format.
  • the audio data in HD Audio format includes an audio clock signal (BCLK).
  • the frequency of the audio clock signal (BCLK) is 24MHz.
  • the audio format conversion device can be electrically connected to the processor (CPU) through pins/interfaces to receive audio data and audio clock signals (BCLK) in HD Audio format, thereby completing format conversion.
  • the audio data in the original HD Audio format is serial audio data
  • the processor (CPU) can transmit the audio data to the audio format conversion device through the serial data interface (SDO).
  • the audio format conversion device receives or samples HD Audio format audio data through the data processing module, and receives an audio clock signal (BCLK).
  • the data processing module can sample HD Audio format audio data on the rising and falling edges of the audio clock signal (BCLK), as shown in Figure 1; in order to implement the timing constraints of the field programmable gate array , or sampling can be performed on the rising edge of the second clock signal (CLK2), as shown in Figure 2.
  • BCLK audio clock signal
  • CLK2 second clock signal
  • the data processing module also receives a synchronous clock signal (SYNC) of the processor (CPU), and the synchronous clock signal (SYNC) is used for data transmission and processing integrity.
  • SYNC synchronous clock signal
  • the data processing module can receive the parallel audio data returned by the serial-to-parallel conversion module, and process and judge it. Specifically, the data processing module performs the first conversion on the falling edge of each synchronous clock signal (SYNC). Judgment is made based on parallel data, taking 32-bit data as an example. If the first parallel data is "00H, 07H, 06H, 00", then the subsequent data is marked as the audio data of the left channel; if the first parallel data is is "00H, 07H, 06H, 01", then the subsequent data is marked as the audio data of the right channel.
  • SYNC synchronous clock signal
  • the data processing module can set the flag bit (LR) separately, so that the serial-to-parallel conversion module and the storage unit operation module can identify the left channel data and the right channel data, for example, if the current left channel channel data, set the flag bit (LR) to 1; if it is right channel data, set the flag bit (LR) to 0.
  • the clock management module receives the audio clock signal (BCLK) of audio data in HD Audio format to generate one or more clock signals.
  • the field programmable gate array itself can also generate a system clock (CLK) for the operation of the audio format conversion device; further, the clock management module can generate any required clock signal based on the system clock (CLK), such as for I2S
  • CLK system clock
  • the clock signal outputted by the audio data format; the system clock (CLK) can be a clock generated by a crystal oscillator circuit, and any commonly used frequency thereof can be applied in the present invention.
  • the audio format conversion device can perform conversion operations according to the clock signal, including but not limited to sampling, receiving, sending, storing, reading audio data, and serial-to-parallel or parallel-to-serial conversion of the audio data.
  • the clock management module may generate multiple clock signals, including at least the second clock signal (CLK2).
  • the second clock signal (CLK2) may be generated from the audio clock signal (BCLK), and its frequency is twice as high as the audio clock signal (BCLK).
  • the audio format conversion device ensures data alignment through a synchronous clock signal (SYNC).
  • the synchronous clock signal (SYNC) is sent by the processor (CPU) and is used as a frame synchronization signal for identifying and Synchronize command words, data streams, etc.
  • the data processing module samples the audio data in the HD Audio format at the falling edge of the synchronous clock signal (SYNC); since the audio data in the HD Audio format is serial data, the use of the synchronous clock signal (SYNC) can ensure the integrity of the audio data sampling .
  • the clock management module also generates an output audio clock (BCLK_I2S) and a channel switching clock (LRCLK_I2S), wherein, according to the I2S decoder (that is, the decoding used to decode the audio data in the I2S format
  • the sampling frequency that the device (the same below) can support, the output audio clock (BCLK_I2S) is 2 times the sampling frequency multiplied by the number of sampling bits (the sampling frequency is usually but not limited to 48K Hz, the number of sampling bits is usually but not limited to 16 or 32 bit), the frequency of the channel switching clock (LRCLK_I2S) is the same as the sampling frequency.
  • the clock management module also generates a master clock (MCLK_I2S) for the I2S decoder to decode and output the I2S format audio data generated by the audio format conversion device.
  • MCLK_I2S master clock
  • the frequency of the main clock (MCLK_I2S) is 256 times the sampling frequency.
  • the serial-to-parallel conversion module receives the HD Audio format audio data collected by the data processing module, and converts the serial HD Audio format audio data into parallel audio data, so that the data processing module can process and judge the parallel audio data.
  • the storage unit operation module receives the parallel audio data identified and processed by the data processing module through the serial-to-parallel conversion module, and stores and reads it.
  • the storage unit operation module controls and manages the storage space to perform read and write operations on parallel audio data.
  • the storage space uses a FIFO memory for storage.
  • the storage unit operation module stores left channel data and right channel data respectively according to the mark bit (LR) and the clock signal, where the clock signal can be the basis for the data processing module to receive or sample audio data in HD Audio format.
  • the clock signal is the audio clock signal (BCLK) or the second clock signal (CLK2).
  • the storage space includes at least two FIFO memories, respectively used to store left channel data and right channel data.
  • the storage unit operation module when the value of the flag bit (LR) (for example, the value is 1) is expressed as left channel data, the storage unit operation module writes the audio data into the FIFO memory that stores the left channel data; when the value of the flag bit (LR) When the value (for example, the value is 0) is represented as right channel data, the storage unit operation module writes the audio data into the FIFO memory that stores the right channel data.
  • the storage space may be an internal storage space of the audio format conversion device and/or an external memory external to the audio format conversion device, and the storage unit operation module is used to control reading and writing of the storage space.
  • the storage unit operation module performs read operations based on the channel switching clock (LRCLK_I2S) and the output audio clock (BCLK_I2S). Specifically, when the channel switching clock (LRCLK_I2S) is the left channel data signal (for example, the signal is high), the storage unit operation module reads the memory storing the left channel data based on the output audio clock (BCLK_I2S) and transmits to the parallel-to-serial conversion module; when the channel switching clock (LRCLK_I2S) is the right channel data signal (for example, the signal is low), the storage unit operation module reads the memory storing the right channel data based on the output audio clock (BCLK_I2S) , and transmitted to the parallel-to-serial conversion module.
  • the channel switching clock (LRCLK_I2S) is the left channel data signal (for example, the signal is high)
  • the storage unit operation module reads the memory storing the left channel data based on the output audio clock (BCLK_I2S) and transmit
  • the memory unit operation module can determine whether to perform a read operation based on the current state of the memory. For example, when the memory state is non-empty, the memory unit operation module determines that a read operation can be performed.
  • the parallel-to-serial conversion module is electrically connected to the storage unit operation module, and can receive parallel audio data read and transmitted by the storage unit operation module. Specifically, the parallel-to-serial conversion module can receive parallel audio data according to the output audio clock (BCLK_I2S) and channel switching clock (LRCLK_I2S), and convert it into audio data in I2S format.
  • BCLK_I2S output audio clock
  • LRCLK_I2S channel switching clock
  • the parallel-to-serial conversion module receives the left channel data and/or the right channel data according to the channel switching clock (LRCLK_I2S), and converts the left channel data and the right channel data into Audio data that is serial and can be recognized by the I2S decoder, that is, audio data in I2S format.
  • LCLK_I2S channel switching clock
  • the parallel-to-serial conversion module can output the audio data in I2S format to the I2S decoder.
  • the I2S decoder switches the clock according to the main clock (MCLK_I2S), the output audio clock (BCLK_I2S) and the channel switching clock. (LRCLK_I2S) for decoding output.
  • the parallel-to-serial conversion module can select left channel data and/or right channel data for output according to actual needs.
  • each module/device can choose any one implementation and When combined with other modules/devices, a complete audio format conversion device can be formed to achieve the technical effects of the present invention.
  • the audio format conversion device based on a field programmable gate array provided by the present invention has been introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The above implementation description is only for assistance. Understand the core idea of the present invention; at the same time, for those of ordinary skill in the art, there will be changes in the specific implementation and application scope based on the idea of the present invention, and changes and improvements to the present invention will be possible, and It will not exceed the concept and scope defined by the appended claims. In summary, the content of this description should not be construed as limiting the present invention.

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Abstract

一种基于现场可编程门阵列的音频格式转换装置，所述装置包括时钟管理模块，所述时钟管理模块用于提供一个或多个时钟信号；所述装置包括：数据处理模块，以及与所述数据处理模块电气连接的串并转换模块、存储单元操作模块、并串转换模块。该装置可以实现将HD Audio格式的音频数据转换为I2S格式的音频数据。

Description

一种音频格式转换装置 技术领域
本发明涉及音频格式转换技术，尤其涉及一种基于现场可编程逻辑门阵列(FPGA)的音频格式转化装置。
背景技术
HD Audio(High Definition Audio)是Intel与杜比公司合力推出的新一代音频规范，具有数据传输带宽大、音频回放精度高、支持多声道阵列麦克风音频输入、CPU的占用率更低和底层驱动程序可以通用等特点。HD Audio自推出以来，优势十分明显，发展潜力巨大。HD Audio音频规范在众多CPU中应用广泛，然而HD Audio音频解码器目前仅仅掌握在REALTEK公司手中，在国内市场存在断货风险。
集成电路内置音频总线(I2S，Inter—IC Sound)是飞利浦公司为数字音频设备之间的音频数据传输而制定的一种总线标准，也是目前广泛使用的音频标准。同时，市场已有的I2S解码器技术成熟，生产厂家众多。
但是，目前市场尚不存在将HD Audio格式的音频数据转换为I2S格式的音频数据的装置或方法。因此，本领域技术人员亟待开发出一种HD Audio格式的音频数据转换为I2S格式的音频数据的技术，从而能够解决REALTEK解码器断货风险，保证HD Audio格式的音频正常使用。
发明内容
为解决上述无法将HD Audio格式的音频数据转换为I2S格式的音频数 据的缺陷，本发明提供了一种基于现场可编程门阵列的音频格式转换装置，其目的在于提供一种可以在任何型号的现场可编程门阵列上实现将HD Audio格式的音频数据转换为I2S格式的音频数据的装置，保证HD Audio格式的音频正常使用。
为了实现上述目的，本发明采用的一种技术方案是：一种基于现场可编程门阵列的音频格式转换装置，所述装置包括时钟管理模块，所述时钟管理模块用于提供一个或多个时钟信号；所述装置根据所述时钟信号实现将HD Audio格式的音频数据转换为I2S格式的音频数据；所述装置包括：数据处理模块，以及与所述数据处理模块电气连接的串并转换模块、存储单元操作模块、并串转换模块；其中，所述数据处理模块采集所述HD Audio格式的音频数据，所述并串转换模块输出经所述装置转换得到的所述I2S格式的音频数据。
在一个优选实施例中，所述数据处理模块和所述时钟管理模块接收所述HD Audio格式的音频数据的音频时钟信号；所述时钟管理模块根据所述音频时钟信号产生所述时钟信号。
在一个优选实施例中，所述时钟信号至少包括第二时钟信号，所述第二时钟信号的频率是所述音频时钟信号的2倍；所述数据处理模块采集所述HD Audio格式的音频数据包括：所述数据处理模块在所述音频时钟信号的上升沿和下降沿或在所述第二时钟信号的上升沿采集HD Audio格式的音频数据。
在一个优选实施例中，所述装置根据所述时钟信号实现HD Audio格式的音频数据转换为I2S格式的音频数据包括：所述串并转换模块接收所述 HD Audio格式的音频数据，执行串并转换，并将转换得到的并行音频数据返回至所述数据处理模块；所述数据处理模块识别所述并行音频数据中的左声道数据和右声道数据，并设置声道标记位；所述装置存储所述左声道数据和/或所述右声道数据，并输出所述I2S格式的音频数据。
在一个优选实施例中，所述装置存储所述左声道数据和/或所述右声道数据包括：所述存储单元操作模块通过所述串并转换模块接收所述左声道数据和/或所述右声道数据，并根据所述声道标记位，以及所述音频时钟信号或所述第二时钟信号，分别存储所述左声道数据和/或所述右声道数据。
在一个优选实施例中，所述时钟信号包括输出音频时钟和声道切换时钟；所述输出所述I2S格式的音频数据包括：所述存储单元操作模块根据所述声道切换时钟读取所述左声道数据和/或所述右声道数据，并传输至所述并串转换模块；所述并串转换模块根据所述输出音频时钟并串转换所述左声道数据和/或所述右声道数据，输出所述I2S格式的音频数据。
在一个优选实施例中，所述存储单元操作模块电气连接至少一个存储器，所述存储器可以是所述装置内部的存储单元，或是可外接于所述装置的任何具有存储功能的器件。
在一个优选实施例中，所述存储器至少包括2个FIFO存储器，所述2个FIFO存储器分别存储所述左声道数据和所述右声道数据。
在一个优选实施例中，所述数据处理模块还接收帧同步时钟信号，所述帧同步信号用于识别和同步指令和音频数据；所述执行串并转换包括：在每个所述同步时钟信号的下降沿执行串并转换。
与现有技术相比，本发明的优点在于：(1)打破了只能由REALTEK解码器实现HD Audio格式的音频的输出限制；(2)基于任意型号的现场可编程门阵列实现音频数据的转换，技术方案的实现灵活，且不依赖硬件设备，即芯片的选择性较多，并且价格较低；(3)对HD Audio格式的音频进行左声道和右声道数据的分别处理，保证了音频数据的完整性；(4)音频输出方式灵活，既可以以双声道进行输出，也可以以单声道进行输出；(5)以I2S格式的音频数据进行输出，可以减小采样带来的时序误差。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1：本发明一个实施例提供的基于现场可编程门阵列的音频格式转换装置的整体结构示意图。
图2：本发明另一个实施例提供的基于现场可编程门阵列的音频格式转换装置的整体结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而 不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明的保护的范围。
在本文中，“上”、“下”、“左”、“右”等指示方向的用词仅为表述方便，而非是限制性的。
在本文中，“第一”、“第二”对于本文所使用的处于相同关系的构件名称所划分的术语，本发明不受限于本文描述的顺序。
在本文中，“至少一种(个)”表示一种(个)、两种(个)、三种(个)、四种(个)、五种(个)、六种(个)、七种(个)、八种(个)或更多种(个)。
在本文中，“多种(个)”表示两种(个)、三种(个)、四种(个)、五种(个)、六种(个)、七种(个)、八种(个)或更多种(个)。
在本文中，“现场可编程门阵列”或其它类似术语包括任何形式的可编程逻辑器件。应当理解的是，随着计算机技术和电子技术的发展，任何用于逻辑功能设计、数字电路设计的芯片，无论其型号、大小、结构、组件单元、材料、性能等如何变化或更新，都应当包含于现场可编程门阵列的范围。
在本文中，“包括”、“包含”、“含有”和“具有”等用语是开放性的，不排除额外的未列举的元素、步骤或成分。表述“由…组成”排除未指明的任何元素、步骤或成分。“基本上由…组成”用语指范围限制在指定的元素、步骤或成分，加上任选存在的不会实质上影响所要求保护的主题的基本和新的特征的元素、步骤或成分。应当理解，“包括”用语涵盖“基本上由…组成”和“由…组成”用语。
本发明提供一种基于现场可编程门阵列的音频格式转换装置，包括时钟 管理模块，用于提供一个或多个时钟信号；装置根据时钟信号实现HD Audio格式的音频数据转换为I2S格式的音频数据；装置包括：数据处理模块，以及与数据处理模块电路连接的串并转换模块、存储单元操作模块、并串转换模块；其中，数据处理模块采集HD Audio格式的音频数据，并串转换模块输出经装置转换得到的I2S格式的音频数据。
本发明提供的音频格式转换装置在硬件电路上可以使用任意型号的现场可编程门阵列(FPGA)。具体地，音频格式转换装置可以包括一个或多个通用的输入或输出管脚或其他用于通信的接口，其可以与HD Audio格式的音频数据接口在保证电平标准一致的情况下实现电气连接，该HD Audio格式的音频数据可以由任意型号的处理器(CPU)或其他任何具有该功能的电子设备输出。
应当理解的是，不作为对本发明限制地，以下实施例中涉及的I2S格式的音频数据可以为任意位数的数据(以下简称“采样位数”)，例如常用的16位、32位等。
应当理解的是，不作为对本发明限制地，对于I2S格式的音频数据的采样频率可以设定为8K至48K Hz或其他非标准频率(以下简称“采样频率”)，但通常情况下，采样频率越高，输出的音频质量越好；而对于I2S格式的音频数据，其解码器能够支持的最大采样频率为48K Hz。因此，对于I2S格式的音频数据，使用48K Hz的采样频率能够达到其最好的输出音频质量。而根据本发明音频格式转换装置得到的音频数据，可以适用以48K Hz的采样频率I2S格式的音频数据。
应当理解的是，本发明提供的音频格式转换装置可以与任何能够产生 HD Audio格式的音频数据的装置电气连接，以接收HD Audio格式的音频数据，并将其转换为I2S格式的音频数据进行输出。为方便说明，不作为对本发明限制地，以下实施例中均以处理器(CPU)作为HD Audio格式的音频数据的发生装置为例进行说明。
本发明的一个实施例提供的基于现场可编程门阵列的音频格式转换装置如图1所示。
如图1所示，基于现场可编程门阵列的音频格式转换装置包括时钟管理模块，该时钟管理模块用于提供一个或多个时钟信号。音频格式转换装置根据时钟信号实现HD Audio格式的音频数据转换为I2S格式的音频数据。
具体地，音频格式转换装置包括数据处理模块，以及与数据处理模块电气连接的串并转换模块、存储单元操作模块、并串转换模块。其中，数据处理模块采集HD Audio格式的音频数据，并串转换模块输出经转换得到的I2S格式的音频数据。
数据处理模块
处理器(CPU)可以产生HD Audio格式的音频数据，该HD Audio格式的音频数据包括音频时钟信号(BCLK)，本实施例中音频时钟信号(BCLK)的频率为24M Hz。可选地，音频格式转换装置可以通过管脚/接口与处理器(CPU)电气连接，以接收HD Audio格式的音频数据和音频时钟信号(BCLK)，从而完成格式转换。原始的HD Audio格式的音频数据为串行音频数据，处理器(CPU)可以通过串行数据接口(SDO)向音频格式转换装置传输音频数据。可选地，音频格式转换装置通过数据处理模块接收或采样HD Audio格式的音频数据，以及接收音频时钟信号(BCLK)。
在可选实施例中，数据处理模块可以在音频时钟信号(BCLK)的上升沿和下降沿对HD Audio格式的音频数据进行采样，如图1所示；为实现现场可编程门阵列的时序约束，也可以在第二时钟信号(CLK2)的上升沿进行采样，如图2所示。
进一步地，在其他可选实施例中，数据处理模块还接收处理器(CPU)的同步时钟信号(SYNC)，该同步时钟信号(SYNC)用于数据传输和处理的完整性。
更进一步地，数据处理模块可以接收串并转换模块返回的并行音频数据，并对其进行处理和判断，具体地，数据处理模块对在每个同步时钟信号(SYNC)的下降沿转换的第一个并行数据进行判断，以32位数据为例，若该第一个并行数据为“00H、07H、06H、00”，则后续数据标记为左声道的音频数据；若该第一个并行数据为“00H、07H、06H、01”，则后续数据标记为右声道的音频数据。在其他可选实施例中，数据处理模块可以单独设置标记位(LR)，以使得串并转换模块和存储单元操作模块可以识别左声道数据和右声道数据，例如，如当前为左声道数据，则将标记位(LR)设置为1；如当前为右声道数据，则将标记位(LR)设置为0。
时钟管理模块
时钟管理模块接收HD Audio格式的音频数据的音频时钟信号(BCLK)，以产生一个或多个时钟信号。其中，现场可编程门阵列本身还可以产生系统时钟(CLK)，用于音频格式转换装置的运行；进一步地，时钟管理模块可以根据系统时钟(CLK)产生任何需要的时钟信号，例如用于I2S格式的音频数据输出的时钟信号；系统时钟(CLK)可以是晶振电路产生的时钟，其 任何常用的频率都可以应用于本发明中。音频格式转换装置可以根据该时钟信号执行转换操作，包括但不限于采样、接收、发送、存储、读取音频数据，以及对音频数据进行串并或并串转换。
在本实施例中，时钟管理模块可以产生多个时钟信号，至少包括第二时钟信号(CLK2)。该第二时钟信号(CLK2)可以由音频时钟信号(BCLK)产生，其频率为音频时钟信号(BCLK)的2倍。
进一步地，在其他可选实施例中，音频格式转换装置通过同步时钟信号(SYNC)保证数据的对齐，同步时钟信号(SYNC)由处理器(CPU)发出，其作为帧同步信号用于识别和同步命令字、数据流等。数据处理模块在同步时钟信号(SYNC)的下降沿对HD Audio格式的音频数据进行采样；由于HD Audio格式的音频数据为串行数据，使用同步时钟信号(SYNC)可以保证音频数据采样的完整性。
更进一步地，在其他可选实施例中，时钟管理模块还产生输出音频时钟(BCLK_I2S)和声道切换时钟(LRCLK_I2S)，其中，根据I2S解码器(即用于解码I2S格式的音频数据的解码器，下同)能够支持的采样频率，输出音频时钟(BCLK_I2S)为2倍的采样频率乘以采样位数(采样频率通常但不限制为48K Hz，采样位数通常但不限制为16或32位)，声道切换时钟(LRCLK_I2S)的频率与采样频率相同。
再进一步地，在其他可选实施例中，时钟管理模块还产生主时钟(MCLK_I2S)，用于I2S解码器对音频格式转换装置生成的I2S格式的音频数据进行解码输出。在本实施例中，主时钟(MCLK_I2S)的频率为采样频率的256倍。
串并转换模块
串并转换模块接收数据处理模块采集的HD Audio格式的音频数据，并将串行的HD Audio格式的音频数据转换为并行的音频数据，以便于数据处理模块对并行的音频数据进行处理和判断。
存储单元操作模块
存储单元操作模块通过串并转换模块接收经数据处理模块识别和处理的并行音频数据，并对其进行存储和读取。存储单元操作模块控制和管理存储空间，以对并行音频数据进行读写操作。
在本实施例中，如图1或2所示，存储空间使用FIFO存储器进行存储。具体地，存储单元操作模块根据标记位(LR)和时钟信号分别存储左声道数据和右声道数据，其中，时钟信号可以为数据处理模块接收或采样HD Audio格式的音频数据时所根据的时钟信号，即音频时钟信号(BCLK)或第二时钟信号(CLK2)。在本实施例中，存储空间包括至少2个FIFO存储器，分别用于存储左声道数据和右声道数据。进一步地，当标记位(LR)的值(例如值为1)表示为左声道数据时，存储单元操作模块将音频数据写入存储左声道数据的FIFO存储器；当标记位(LR)的值(例如值为0)表示为右声道数据时，存储单元操作模块将音频数据写入存储右声道数据的FIFO存储器。
进一步地，在其他可选实施例中，存储空间可以是音频格式转换装置的内部存储空间和/或外接于音频格式转换装置的外部存储器，存储单元操作模块用于控制存储空间的读和写。
在本实施例中，存储单元操作模块根据声道切换时钟(LRCLK_I2S)和 输出音频时钟(BCLK_I2S)进行读操作。具体地，当声道切换时钟(LRCLK_I2S)为左声道数据信号(例如信号为高)时，存储单元操作模块基于输出音频时钟(BCLK_I2S)对存储左声道数据的存储器进行读取，并传输至并串转换模块；当声道切换时钟(LRCLK_I2S)为右声道数据信号(例如信号为低)时，存储单元操作模块基于输出音频时钟(BCLK_I2S)对存储右声道数据的存储器进行读取，并传输至并串转换模块。
进一步地，在其他可选实施例中，存储单元操作模块可以根据存储器的当前状态判断是否进行读操作，例如，当存储器状态为非空时，存储单元操作模块判断为可以进行读操作。
并串转换模块
并串转换模块与存储单元操作模块电气连接，其可以接收存储单元操作模块读取并传输的并行音频数据。具体地，并串转换模块可以根据该输出音频时钟(BCLK_I2S)和声道切换时钟(LRCLK_I2S)接收并行的音频数据，并转换为I2S格式的音频数。
进一步地，并串转换模块根据声道切换时钟(LRCLK_I2S)接收左声道数据和/或所述右声道数据，并根据输出音频时钟(BCLK_I2S)将左声道数据和右声道数据转换为串行的并且可以被I2S解码器识别的音频数据，即I2S格式的音频数据。
更进一步地，在其他可选实施例中，并串转换模块可以将I2S格式的音频数据输出至I2S解码器，I2S解码器根据主时钟(MCLK_I2S)、输出音频时钟(BCLK_I2S)和声道切换时钟(LRCLK_I2S)进行解码输出。
再进一步地，在其他可选实施例中，并串转换模块可以根据实际需要选 择左声道数据和/或右声道数据进行输出。
以上对音频格式转换装置中的主要模块/器件进行了说明，其中每个模块/器件中存在多种可选的实施方式，应当理解的是，每个模块/器件可以任选一种实施方式并与其他模块/器件进行组合，均能够形成完整的音频格式转换装置，达到本发明的技术效果。
以上对本发明所提供的一种基于现场可编程门阵列的音频格式转换装置进行了详尽介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施的说明只是用于帮助理解本发明的核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，对本发明的变更和改进将是可能的，而不会超出附加权利要求所规定的构思和范围，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (9)

  1. 一种基于现场可编程门阵列的音频格式转换装置，其特征在于，所述装置包括时钟管理模块，所述时钟管理模块用于提供一个或多个时钟信号；所述装置根据所述时钟信号实现将HD Audio格式的音频数据转换为I2S格式的音频数据；所述装置包括：
    数据处理模块，以及与所述数据处理模块电气连接的串并转换模块、存储单元操作模块、并串转换模块；
    其中，所述数据处理模块采集所述HD Audio格式的音频数据，所述并串转换模块输出经所述装置转换得到的所述I2S格式的音频数据。
  2. 根据权利要求1所述的装置，其特征在于，所述数据处理模块和所述时钟管理模块接收所述HD Audio格式的音频数据的音频时钟信号；所述时钟管理模块根据所述音频时钟信号产生所述时钟信号。
  3. 根据权利要求2所述的装置，其特征在于，所述时钟信号至少包括第二时钟信号，所述第二时钟信号的频率是所述音频时钟信号的2倍；所述数据处理模块采集所述HD Audio格式的音频数据包括：
    所述数据处理模块在所述音频时钟信号的上升沿和下降沿或在所述第二时钟信号的上升沿采集HD Audio格式的音频数据。
  4. 根据权利要求3所述的装置，其特征在于，所述装置根据所述时钟信号实现HD Audio格式的音频数据转换为I2S格式的音频数据包括：
    所述串并转换模块接收所述HD Audio格式的音频数据，执行串并转换，并将转换得到的并行音频数据返回至所述数据处理模块；
    所述数据处理模块识别所述并行音频数据中的左声道数据和右声道数据，并设置声道标记位；
    所述装置存储所述左声道数据和/或所述右声道数据，并输出所述I2S格式的音频数据。
  5. 根据权利要求4所述的装置，其特征在于，所述装置存储所述左声道数据和/或所述右声道数据包括：
    所述存储单元操作模块通过所述串并转换模块接收所述左声道数据和/或所述右声道数据，并根据所述声道标记位，以及所述音频时钟信号或所述第二时钟信号，分别存储所述左声道数据和/或所述右声道数据。
  6. 根据权利要求4所述的装置，其特征在于，所述时钟信号包括输出音频时钟和声道切换时钟；所述输出所述I2S格式的音频数据包括：
    所述存储单元操作模块根据所述声道切换时钟读取所述左声道数据和/或所述右声道数据，并传输至所述并串转换模块；
    所述并串转换模块根据所述输出音频时钟并串转换所述左声道数据和/或所述右声道数据，输出所述I2S格式的音频数据。
  7. 根据权利要求5所述的装置，其特征在于，所述存储单元操作模块电气连接至少一个存储器，所述存储器可以是所述装置内部的存储单元，或是可外接于所述装置的任何具有存储功能的器件。
  8. 根据权利要求7所述的装置，其特征在于，所述存储器至少包括2个FIFO存储器，所述2个FIFO存储器分别存储所述左声道数据和所述右声道数据。
  9. 根据权利要求4-8所述的装置，其特征在于，所述数据处理模块还接收帧同步时钟信号，所述帧同步信号用于识别和同步指令和音频数据；所述执行串并转换包括：在每个所述同步时钟信号的下降沿执行串并转换。
PCT/CN2022/108274 2022-07-26 2022-07-27 一种音频格式转换装置 WO2024020860A1 (zh)

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