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WO2022111240A1 - 一种智能低边功率开关的控制电路及芯片 - Google Patents

一种智能低边功率开关的控制电路及芯片 Download PDF

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Publication number
WO2022111240A1
WO2022111240A1 PCT/CN2021/128277 CN2021128277W WO2022111240A1 WO 2022111240 A1 WO2022111240 A1 WO 2022111240A1 CN 2021128277 W CN2021128277 W CN 2021128277W WO 2022111240 A1 WO2022111240 A1 WO 2022111240A1
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WIPO (PCT)
Prior art keywords
nmos transistor
drain
source
transistor
node
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PCT/CN2021/128277
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English (en)
French (fr)
Inventor
闫兆文
汪西虎
姚和平
唐威
苏海伟
Original Assignee
上海维安半导体有限公司
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Publication of WO2022111240A1 publication Critical patent/WO2022111240A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/08104—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
    • H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K2017/0806—Modifications for protecting switching circuit against overcurrent or overvoltage against excessive temperature

Definitions

  • the invention relates to the technical field of circuits, in particular to a control circuit and a chip of an intelligent low-side power switch.
  • intelligent power switch integrated circuit aims to integrate all high-voltage power devices and low-voltage circuits on the same chip, which can not only improve the overall performance of the chip, but also reduce production costs.
  • the present invention provides a control circuit for an intelligent low-side power switch, which includes:
  • a second NMOS transistor the source of the second NMOS transistor is connected to a first resistor and then grounded in parallel with the source of the first NMOS transistor, the drain of the second NMOS transistor and the first NMOS transistor connected in parallel to a first node and then connected to a load external terminal, the gate of the control terminal is connected to a sixth resistor and a seventh resistor and finally connected to a second node in parallel and then connected to a voltage input terminal through a second resistor;
  • a protection module connected in parallel between the voltage input terminal and the ground, for electrostatic protection
  • an over-temperature protection module connected in parallel between the second node and the ground, for turning off the working current of the control terminal of the first NMOS transistor when the working temperature reaches a preset temperature
  • a current limiting module is connected in parallel between the second node and the ground, and is provided with a sixth NMOS transistor and the second NMOS transistor, the gate of the sixth NMOS transistor and the source of the second NMOS transistor
  • the drain of the sixth NMOS transistor is connected to the gate of the first NMOS transistor, so that when the current collected by the current sampling second NMOS transistor exceeds a preset electrical current, the sixth NMOS transistor is connected
  • the NMOS is turned on to discharge the gate of the first NMOS tube, thereby limiting the output current of the first NMOS tube;
  • An overvoltage protection module is connected in parallel between the first node and the ground, and a fourth zener diode is arranged for pulling down when the drain voltage of the first NMOS transistor exceeds a preset voltage The gate voltage of the first NMOS transistor turns off the first NMOS transistor;
  • a clamping module connected in parallel between the first node and the ground, for when the voltage applied between the drain of the first NMOS transistor and the ground is higher than a preset voltage of the clamping module , the clamping module is turned on, and the voltage applied to both ends of the drain and source of the first NMOS transistor is clamped at a preset voltage value, so that the drain-source breakdown of the first NMOS transistor is avoided.
  • the protection module includes:
  • a first PNP tube the emitter of the first PNP tube is connected to the voltage input terminal, the base of the first PNP tube is short-circuited to the emitter of the first PNP tube, the first PNP tube The collector of the tube is grounded.
  • the over-temperature protection module includes:
  • a current mirror unit connected in parallel between the second node and the ground, and providing a bias current output terminal
  • a start-up unit connected in parallel between the bias current output terminal and the ground, and provides a start-up current output terminal
  • a PATA current source is connected in parallel between the bias current output terminal and ground, and a start-up terminal is connected to the start-up current output terminal for generating a voltage proportional to the operating temperature according to the bias current PATA current;
  • An over-temperature control unit is connected in parallel between the bias current output terminal and the ground, and is used to control the current input to the control terminal of the first NMOS transistor when the operating temperature increases.
  • the current mirror unit includes:
  • the source is connected to the second node, and the control terminal is short-circuited with the drain;
  • a second PMOS transistor the source is connected to the second node, the drain is grounded through a first Zener diode, the control terminal is connected to the control terminal of the first PMOS transistor, and is connected to the ground through a second Zener diode the second node;
  • a third NMOS transistor the source is grounded, the drain is connected to the drain of the first PMOS transistor, and the control terminal is short-circuited with the source;
  • the drain of the second PMOS transistor forms the bias current output terminal.
  • the starting unit includes:
  • the source is connected to the bias current output terminal, the drain is grounded through a capacitor, and the control terminal and the drain are short-circuited;
  • a fourth PMOS transistor the source is connected to the bias current output terminal, the drain is grounded, and the control terminal is connected to the control terminal of the third PMOS transistor;
  • the drain of the fourth PMOS transistor forms the start-up current output terminal.
  • the PTAT current source includes:
  • the source is connected to the bias current output terminal, and the drain is connected to the startup current output terminal;
  • the source is connected to the bias current output terminal, the control terminal is short-circuited with the drain, and is connected to the control terminal of the fifth PMOS tube;
  • the collector is connected to the drain of the fifth PMOS tube, the emitter is grounded, and the base and the collector are short-circuited;
  • a second NPN transistor the collector is connected to the drain of the sixth PMOS transistor, the emitter is grounded through a third resistor, and the base is connected to the base of the first NPN transistor.
  • the over-temperature control unit includes:
  • a seventh PMOS transistor the source is connected to the bias current output terminal, and the drain is grounded through a first series resistance voltage divider circuit;
  • an eighth PMOS transistor the source is connected to the bias current output terminal, and the control terminal is connected to the control terminal of the seventh PMOS transistor and the control terminal of the sixth PMOS transistor;
  • a third NPN transistor the collector is connected to the drain of the eighth PMOS transistor, the base is connected to the drain of the seventh PMOS transistor, and the emitter is grounded;
  • a fourth NMOS transistor the source is grounded, and the drain is connected to the control terminal of the second NMOS transistor;
  • first inverter In series with each other, a first inverter, a second inverter and a third inverter, the input end of the first inverter is connected to the drain of the eighth PMOS transistor, the first inverter The output end of the three-inverter is connected to the control end of the fourth NMOS transistor;
  • a fifth NMOS transistor the source is grounded, the drain is connected to the voltage dividing node of the first series resistance voltage divider circuit, and the control terminal is connected between the second inverter and the third inverter.
  • the current limiting module includes:
  • a sixth NMOS transistor the drain is connected to the control terminal of the second NMOS transistor, the source is grounded, and the control terminal is connected to the source of the second NMOS transistor;
  • a second series resistance voltage divider circuit connected in series between the second node and the control terminal of the second NMOS transistor
  • a seventh NMOS transistor the drain is connected to the second node, the source is connected to the voltage dividing node of the second series resistance voltage divider circuit, and the control terminal is shorted to the source;
  • a third Zener diode is connected between the control terminal of the second NMOS transistor and the control terminal of the sixth NMOS transistor.
  • the overvoltage protection module includes:
  • an eighth NMOS transistor the drain of which is connected to the control terminal of the first NMOS transistor
  • a ninth NMOS transistor the drain is connected to the source of the eighth NMOS transistor, the source is grounded, and the control terminal is short-circuited with the source;
  • the drain is connected to the control terminal of the eighth NMOS transistor, the source is grounded, and the control terminal is short-circuited with the source;
  • the anode is connected to the control terminal of the eighth NMOS transistor, and the cathode is connected to the first node;
  • the positive electrode is connected to the source electrode of the eighth NMOS transistor, and the negative electrode is connected to the control terminal of the eighth NMOS transistor;
  • a sixth Zener diode the anode is connected to the source of the eighth NMOS transistor, and the cathode is grounded.
  • the clamping module includes:
  • a second PNP tube, the emitter of the second PNP tube is connected to the first node, the collector of the second PNP tube is grounded, and the base of the second PNP tube and the emitter are short-circuited.
  • control circuit is formed in a chip.
  • the present invention also provides a chip, which includes the control circuit as described above.
  • the above technical solution has the following advantages or beneficial effects: by embedding a protection module, an over-temperature protection module, a current limiting module, an over-voltage protection module and a clamping voltage module, the energy generated by the first NMOS tube due to high inductive load at the moment of turning off can be solved.
  • the problem of single-pulse avalanche energy breakdown and damage occurs to protect the first NMOS transistor and has high reliability.
  • FIG. 1 is a schematic diagram of a circuit structure of an embodiment of the present invention.
  • the present invention provides a control circuit for an intelligent low-side power switch, which includes:
  • a second NMOS transistor the source of the second NMOS transistor is connected to a first resistor and then grounded in parallel with the source of the first NMOS transistor, the drain of the second NMOS transistor and the first NMOS transistor It is connected in parallel to a first node and then connected to a load external terminal LOAD.
  • the gate of the control terminal is connected to a sixth resistor R6 and a seventh resistor R7 and finally connected to a second node 2 in parallel and then connected to a voltage through a second resistor R2 input terminal VIN;
  • a protection module 3 connected in parallel between the voltage input terminal VIN and the ground GND, for electrostatic protection
  • an over-temperature protection module connected in parallel between the second node 2 and the ground GND, for cutting off the working current of the control terminal of the first NMOS transistor Q1 when the working temperature reaches a preset temperature
  • a current limiting module 5 is connected in parallel between the second node 2 and the ground GND, and is provided with a sixth NMOS transistor Q13 and the above-mentioned second NMOS transistor Q2, the gate of the sixth NMOS transistor Q13 and the source of the second NMOS transistor Q2 connected, the drain of the sixth NMS transistor Q13 is connected to the gate of the first NMOS transistor Q1, for when the current collected by the current sampling second NMOS transistor Q2 exceeds a preset current The gate of an NMOS transistor Q1 is discharged, thereby limiting the output current of the first NMOS transistor Q1;
  • An overvoltage protection module 6 is connected in parallel between the first node 1 and the ground GND, and a fourth qi diode D4 is arranged to pull down the first NMOS transistor when the drain voltage of the first NMOS transistor Q1 exceeds a preset voltage The gate voltage of Q1 turns off the first NMOS transistor Q1;
  • a clamping module 7 is connected in parallel between the first node 1 and the ground GND, for when the voltage applied between the drain of the first NMOS transistor Q1 and the ground GND is higher than the preset voltage of the clamping module 7,
  • the clamping module 7 is turned on to clamp the voltage applied across the drain and source of the first NMOS transistor Q1 to a preset voltage value, and the first NMOS transistor Q1 avoids drain-source breakdown.
  • the protection module 3 is connected in parallel with the first NMOS transistor Q1 between the voltage input terminal VIN and the ground GND, so as to protect the first NMOS transistor from static electricity.
  • an over-temperature protection module is connected between the second node 2 and the ground GND.
  • the over-temperature protection module can pull down the first NMOS transistor Q1. control the terminal voltage, so that the first NMOS transistor Q1 is turned off. Further, if the operating temperature decreases, the over-temperature protection module generates a temperature hysteresis. When the operating temperature drops below a certain temperature, the first NMOS transistor Q1 is in an on state.
  • the current limiting module 5 is connected between the second node 2 and the ground GND.
  • the voltages of the control terminals of the first NMOS transistor Q1 and the second NMOS transistor Q2 are equal.
  • the second NMOS transistor Q2 and the first resistor R1 can monitor the current of the first NMOS transistor Q1 in real time; when the voltage provided by the voltage input terminal VIN is high, the current of the first NMOS transistor Q1 increases, and the first resistor R1
  • the voltage at both ends increases, so that the control terminal voltage of the first NMOS transistor Q1 decreases, and the current flowing through the first NMOS transistor Q1 decreases accordingly, so as to protect the first NMOS transistor Q1.
  • an overvoltage protection module 6 is connected between the first node 1 and the second node 2.
  • the overvoltage protection module 6 is used to make the first NMOS transistor Q1 larger.
  • the voltage of the control terminal of the transistor Q1 is reduced, so that the first NMOS transistor Q1 is turned off.
  • a clamping module 7 is connected in parallel between the first node 1 and the ground GND.
  • the first NMOS transistor Q1 When the first NMOS transistor Q1 is turned off, the energy of the breakdown voltage generated by the high inductive load is released, and the first NMOS transistor Q1 is turned off.
  • the drain voltage of Q1 When the drain voltage of Q1 is clamped to a predetermined value lower than its breakdown voltage, the first NMOS transistor Q1 is effectively prevented from being broken down, so as to protect the first NMOS transistor Q1.
  • over-temperature protection module Through the built-in protection module 3, over-temperature protection module, current limiting module 5, over-voltage protection module 6 and voltage clamping module 7, the single-pulse avalanche energy generated by the energy generated by the high inductive load at the moment of turn-off of the first NMOS transistor Q1 is solved.
  • the problem of breakdown and damage is to protect the first NMOS transistor Q1, which has high reliability.
  • the protection module 3 includes:
  • a first PNP transistor VT1 the emitter of the first PNP transistor VT1 is connected to the voltage input terminal VIN, the base of the first PNP transistor VT1 is short-circuited to the emitter of the first PNP transistor VT1, and the collector of the first PNP transistor VT1 Ground GND.
  • the protection module 3 in the above technical solution is the first PNP tube VT1, and the first PNP tube VT1 plays the role of electrostatic protection.
  • the over-temperature protection module includes:
  • a current mirror unit 40 connected in parallel between the second node 2 and the ground GND, and providing a bias current output terminal;
  • a start-up unit 41 is connected in parallel between the bias current output terminal and the ground GND, and provides a start-up current output terminal;
  • a PATA current source 42 is connected in parallel between the bias current output terminal and the ground GND, and a start-up terminal is connected to the start-up current output terminal for generating a PATA current proportional to the operating temperature according to the bias current;
  • An over-temperature control unit 43 is connected in parallel between the bias current output terminal and the ground GND to control the current input to the control terminal of the first NMOS transistor Q1 when the operating temperature increases.
  • the over-temperature protection module in the above technical solution includes a current mirror unit 40 , a start-up unit 41 , a PATA current source 42 and an over-temperature control unit 43 .
  • the bias current output terminal is provided through the current mirror unit 40 and the bias current is output.
  • the working state of each module is 0. After the voltage input terminal VIN provides a voltage, the starting unit 41 is turned on to start the working state of other modules.
  • the PATA current that is proportional to the operating temperature can be generated according to the bias current provided by the current mirror unit 40 .
  • the over-temperature control unit 43 can pull down the first NMOS transistor Q1.
  • the control terminal voltage of the NMOS transistor Q1 turns off the first NMOS transistor Q1.
  • the over-temperature control unit 43 generates a temperature hysteresis.
  • the first NMOS transistor Q1 turns off. is on.
  • the current mirror unit 40 includes:
  • a first PMOS transistor Q3, the source is connected to the second node 2, and the control terminal is short-circuited with the drain;
  • a second PMOS transistor Q4 the source is connected to the second node 2, the drain is grounded to GND through a first Zener diode D1, the control terminal is connected to the control terminal of the first PMOS transistor Q3, and is connected through a second Zener diode D2 connected to the second node 2;
  • a third NMOS transistor Q5 the source is grounded to GND, the drain is connected to the drain of the first PMOS transistor Q3, and the control terminal is shorted to the source;
  • the drain of the second PMOS transistor Q4 forms a bias current output terminal.
  • the above-mentioned current mirror unit 40 includes a first PMOS transistor Q3, a second PMOS transistor Q4, a third NMOS transistor Q5, and a first Zener diode D1 and a second Zener diode D2 for providing bias current, wherein , the second PMOS transistor Q4 mirrors the current of the first PMOS transistor Q3, the drain of the second PMOS transistor Q4 is connected to the cathode of the first Zener diode D1, and provides a bias current for the PATA current source 42 that generates the above-mentioned PATA current, And the first Zener diode D1 serves as a voltage regulator of the PATA current source 42 that generates the PATA current.
  • the third NMOS transistor Q5 is used as a constant current source.
  • the anode of the second Zener diode D2 is connected to the control terminal of the second PMOS transistor Q4, and the cathode is connected to the source of the second PMOS transistor Q4 to protect the control terminal of the second PMOS transistor Q4 from being broken down.
  • the starting unit 41 includes:
  • a third PMOS transistor Q5 the source is connected to the bias current output terminal, the drain is grounded through a capacitor C, and the control terminal is short-circuited with the drain;
  • a fourth PMOS transistor Q6 the source is connected to the bias current output terminal, the drain is grounded to GND, and the control terminal is connected to the control terminal of the third PMOS transistor Q5;
  • the drain of the fourth PMOS transistor Q6 forms a start-up current output terminal.
  • the start-up unit 41 in the above technical solution includes a third PMOS transistor Q5, a fourth PMOS transistor Q6 and a capacitor C.
  • the third PMOS transistor Q5 and the fourth PMOS transistor Q6 are turned on, and then the third PMOS transistor Q5 charges both ends of the capacitor C, and the fourth PMOS transistor Q6 is input to the PATA current source 42
  • the voltage across the capacitor C is equal to the source voltages of the third PMOS transistor Q5 and the fourth PMOS transistor Q6
  • the third PMOS transistor Q5 and the fourth PMOS transistor Q6 are turned off, and the startup unit 41 is completed.
  • the PTAT current source 42 includes:
  • a fifth PMOS transistor Q7 the source is connected to the bias current output terminal, and the drain is connected to the startup current output terminal;
  • a sixth PMOS transistor Q8, the source is connected to the bias current output terminal, the control terminal is short-circuited with the drain, and is connected to the control terminal of the fifth PMOS transistor Q7;
  • a first NPN transistor VT2 the collector is connected to the drain of the fifth PMOS transistor Q7, the emitter is grounded to GND, and the base and the collector are short-circuited;
  • a second NPN transistor VT3 the collector is connected to the drain of the sixth PMOS transistor Q8, the emitter is grounded to GND through a third resistor R3, and the base is connected to the base of the first NPN transistor VT2.
  • the above-mentioned PTAT current source 42 is formed by connecting the fifth PMOS transistor Q7 , the sixth PMOS transistor Q8 , the first NPN transistor VT2 , the second NPN transistor VT3 and the third resistor R3 .
  • the number ratio of the first NPN transistor VT2 and the second NPN transistor VT3 is set to be 1:4, and a plurality of second NPN transistors VT3 are connected in parallel with each other.
  • the over-temperature control unit 43 includes:
  • a seventh PMOS transistor Q9 the source is connected to the bias current output terminal, and the drain is grounded to GND through a first series resistance voltage divider circuit 8;
  • an eighth PMOS transistor Q10 the source is connected to the bias current output terminal, and the control terminal is connected to the control terminal of the seventh PMOS transistor Q9 and the control terminal of the sixth PMOS transistor Q8;
  • a third NPN transistor VT4 the collector is connected to the drain of the eighth PMOS transistor Q10, the base is connected to the drain of the seventh PMOS transistor Q9, and the emitter is grounded to GND;
  • a fourth NMOS transistor Q11 the source is grounded to GND, and the drain is connected to the control terminal of the second NMOS transistor Q2;
  • first inverter INV1 In series with each other, a first inverter INV1, a second inverter INV2 and a third inverter INV3, the input end of the first inverter INV1 is connected to the drain of the eighth PMOS transistor Q10, the third inverter INV1 The output end of the inverter INV3 is connected to the control end of the fourth NMOS transistor Q11;
  • a fifth NMOS transistor Q12 the source is grounded GND, the drain is connected to the voltage dividing node of the first series resistance voltage dividing circuit 8, and the control terminal is connected between the second inverter INV2 and the third inverter INV3.
  • the third NPN transistor VT4 when the operating temperature of the circuit is at a normal temperature, the third NPN transistor VT4 is turned off, and the potential of its collector is relatively high, passing through the first inverter INV1 and the second inverter INV2 connected in series. And the third inverter INV3 outputs a low potential, and inputs the low potential to the control terminal of the fourth NMOS transistor Q11, so that the fourth NMOS transistor Q11 is turned off and the first NMOS transistor Q1 works normally.
  • the first series resistance voltage divider circuit 8 includes a fourth resistor R4 and a fifth resistor R5, and the control terminal of the fifth NMOS transistor Q12 is connected between the second inverter INV2 and the third inverter INV3 , the second inverter INV2 outputs a high potential, so that the fifth NMOS transistor Q12 is turned on, and the fourth resistor R4 is short-circuited.
  • the third NPN transistor VT4 When the operating temperature reaches the preset temperature for over-temperature protection, the third NPN transistor VT4 is turned on, its collector outputs a low potential, and then passes through the first inverter INV1, the second inverter INV2 and the third inverter INV3 A high potential is output, thereby pulling down the voltage of the control terminal of the first NMOS transistor Q1, so that the first NMOS transistor Q1 is turned off.
  • the second NMOS transistor Q2 is turned off.
  • the fourth resistor R4 in the first series resistor divider circuit 8 is turned on, so that the third NPN transistor VT4 is turned on.
  • the potential of the base electrode is raised to generate a temperature hysteresis amount.
  • the third NPN transistor VT4 is turned off again, so that the first NMOS transistor Q1 is turned on.
  • the current limiting module 5 includes:
  • a sixth NMOS transistor Q13 the drain is connected to the control terminal of the second NMOS transistor Q2, the source is grounded to GND, and the control terminal is connected to the source of the second NMOS transistor Q2;
  • a second series resistance voltage divider circuit 9 is connected in series between the second node 2 and the control terminal of the second NMOS transistor Q2;
  • a seventh NMOS transistor Q14 the drain is connected to the second node 2, the source is connected to the voltage dividing node of the second series resistance voltage dividing circuit 9, and the control terminal is short-circuited with the source;
  • a third Zener diode D3 is connected between the control terminal of the second NMOS transistor Q2 and the control terminal of the sixth NMOS transistor Q13.
  • the second series resistance voltage divider circuit 9 includes a sixth resistor R6 and a seventh resistor R7, both of which are current-limiting resistors, the first resistor R1 is used as a sampling resistor, and the second NMOS transistor Q2 is used for current sampling
  • the sixth NMOS transistor Q13 is a pull-down transistor.
  • the magnitude of the current limiting value can be determined by adjusting the number ratio of the second NMOS transistors Q2 and the first NMOS transistors Q1 or adjusting the resistance value of the first resistor R1.
  • the overvoltage protection module 6 includes:
  • an eighth NMOS transistor Q15 the drain of which is connected to the control terminal of the first NMOS transistor Q1;
  • a ninth NMOS transistor Q16 the drain is connected to the source of the eighth NMOS transistor Q15, the source is grounded to GND, and the control terminal is short-circuited with the source;
  • a tenth NMOS transistor Q17 the drain is connected to the control terminal of the eighth NMOS transistor Q15, the source is grounded to GND, and the control terminal is short-circuited with the source;
  • a fourth Zener diode D4 the anode is connected to the control terminal of the eighth NMOS transistor Q15, and the cathode is connected to the first node 1;
  • a sixth Zener diode D6 the anode is connected to the source of the eighth NMOS transistor Q15, and the cathode is grounded to GND.
  • the eighth NMOS transistor Q15 is a pull-down transistor.
  • the eighth NMOS transistor Q15 is turned on to turn on the first NMOS transistor Q15.
  • the voltage of the control terminal of the NMOS transistor Q1 is pulled down, so that the first NMOS transistor Q1 is turned off.
  • the clamping module 7 includes:
  • a second PNP transistor VT5 the emitter of the second PNP transistor VT5 is connected to the first node 1, the collector of the second PNP transistor VT5 is grounded to GND, and the base and the emitter of the second PNP transistor VT5 are short-circuited.
  • the clamping module 7 includes a second PNP transistor VT5.
  • the fifth Schottky diode D5 is used to protect the control terminal of the eighth NMOS transistor Q15
  • the sixth Zener diode D6 generates overvoltage protection.
  • the energy of the breakdown voltage generated by the high inductive load is released, and when the drain voltage of the first NMOS transistor Q1 is clamped to a preset value lower than its breakdown voltage, At the same time, the energy of the breakdown voltage is discharged to the ground, thereby effectively preventing the first NMOS transistor Q1 from being broken down, so as to protect the first NMOS transistor Q1.
  • control circuit is formed in a chip.
  • the present invention provides a chip, which includes the above-mentioned control circuit.

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Abstract

本发明涉及电路技术领域，尤其涉及一种智能低边功率开关的控制电路及芯片，其中，包括：第一NMOS管；第二NMOS管，其源极连接第一电阻后与第一NMOS管的源极并联接地，其与第一NMOS管的漏极并联至第一节点后连接负载，控制端并联至第二节点后通过第二电阻连接电压输入端；防护模块，并联于电压输入端与地之间；过温保护模块，并联于第二节点与地之间；限流模块，并联于第二节点与地之间，并设置检测端连接第二NMOS管的源极；过压保护模块，并联于第一节点与第二节点之间；钳压模块，并联于第一节点与地之间。有益效果：解决第一NMOS管在关断瞬间因高电感负荷产生的能量发生单脉冲雪崩能量击穿而损坏的问题，具有高可靠性。

Description

一种智能低边功率开关的控制电路及芯片 技术领域
本发明涉及电路技术领域，尤其涉及一种智能低边功率开关的控制电路及芯片。
背景技术
智能功率开关集成电路作为新一代的电力电子技术，旨在将所有的高压功率器件与低压电路集成在同一芯片上，不仅能提高芯片的整体性能，而且能够降低生产成本。
目前，市场上的智能功率开关大多是集过流保护、过压保护、过温保护为一体的功率开关，其广泛应用于家用电器、汽车电子和工业控制电子领域。然而，这些智能功率开关的保护功能还不足以满足汽车电子和工业控制电子的需要，并且其整体体积较大，生产成本也较高。尤其是汽车电子经常应用于电压瞬变、高能以及高电感负荷以及众多外部链接和人类干扰等苛刻条件下，这对智能功率开关高耐压、高性能以及高可靠性提出了新的需求。例如，随着人们对汽车电子响应速度的要求增加，当智能功率开关应用在高电感负荷上，过快的开关相应速度会产生高脉冲电压，使得功率器件发生雪崩击穿，短时间内功率器件区域电流集中，容易导致区域温度迅速上升而烧毁器件的问题。因此，针对上述问题，成文本领域技术人员亟待解决的难题。
发明内容
针对现有技术中存在的上述问题，现提供一种智能低边功率开关的控制电路及芯片。
具体技术方案如下：
本发明提供一种智能低边功率开关的控制电路，其中，包括：
一第一NMOS管；
一第二NMOS管，所述第二NMOS管的源极连接一第一电阻后与所述第一NMOS管的源极并联接地，所述第二NMOS管及所述第一NMOS管的漏极并联至一第一节点后连接至一负载外接端，控制端的栅极连接一第六电阻以及一第七电阻并最终并联至一第二节点后通过一第二电阻连接一电压输入端；
一防护模块，并联于所述电压输入端与地之间，用以进行静电防护；
一过温保护模块，并联于所述第二节点与地之间，用以当工作温度达到一预设温度时，关断所述第一NMOS管的控制端的工作电流；
一限流模块，并联于所述第二节点与地之间，并设置一第六NMOS管和所述第二NMOS管，所述第六NMOS管的栅极与所述第二NMOS管的源极连接，所述第六NMOS管的漏极与所述第一NMOS管的栅极连接，用以当所述电流采样第二NMOS管采集到的电流超过一预设电电流时所述第六NMOS开启，给所述第一NMOS管栅极放电，从而限制所述第一NMOS管的的输出电流；
一过压保护模块，并联于所述所述第一节点与所述地之间，设置一第四齐纳二极管，用以当所述第一NMOS管漏极电压超过预设电压时，拉低所述第一NMOS管栅极电压，关断所述第一NMOS管；
一钳压模块，并联于所述第一节点与地之间，用以当所述当加在所述第一NMOS管的漏极与地之间的电压高于钳压模块预设的电压时，钳压模块被开启，将加在所述第一NMOS管漏源两端的电压钳位在预设电压值，第一 NMOS管避免发生漏源击穿。
优选的，所述防护模块包括：
一第一PNP管，所述第一PNP管的发射极连接至所述电压输入端，所述第一PNP管的基极短接至所述第一PNP管的发射极，所述第一PNP管的集电极接地。
优选的，所述过温保护模块包括：
一电流镜单元，并联于所述第二节点与地之间，并提供一偏置电流输出端；
一启动单元，并联于所述偏置电流输出端与地之间，并提供一启动电流输出端；
一PATA电流源，并联于所述偏置电流输出端与地之间，并设置一启动端连接所述启动电流输出端，用于根据所述偏置电流产生一与所述工作温度成正比的PATA电流；
一过温控制单元，并联于所述偏置电流输出端与地之间，用以当所述工作温度升高时，控制输入所述第一NMOS管的控制端的电流。
优选的，所述电流镜单元包括：
一第一PMOS管，源极连接所述第二节点，控制端与漏极短接；
一第二PMOS管，源极连接所述第二节点，漏极通过一第一齐纳二极管接地接地，控制端连接所述第一PMOS管的控制端，并通过一第二齐纳二极管连接至所述第二节点；
一第三NMOS管，源极接地，漏极连接所述第一PMOS管的漏极，控制端与源极短接；
所述第二PMOS管的漏极形成所述偏置电流输出端。
优选的，所述启动单元包括：
一第三PMOS管，源极连接所述偏置电流输出端，漏极通过一电容接地，控制端与漏极短接；
一第四PMOS管，源极连接所述偏置电流输出端，漏极接地，控制端连接所述第三PMOS管的控制端；
所述第四PMOS管的漏极形成所述启动电流输出端。
优选的，所述PTAT电流源包括：
一第五PMOS管，源极连接所述偏置电流输出端，漏极连接所述启动电流输出端；
一第六PMOS管，源极连接所述偏置电流输出端，控制端与漏极短接，并连接所述第五PMOS管的控制端；
一第一NPN管，集电极连接所述第五PMOS管的漏极，发射极接地，基极与集电极短接；
一第二NPN管，集电极连接所述第六PMOS管的漏极，发射极通过一第三电阻接地，基极连接所述第一NPN管的基极。
优选的，所述过温控制单元包括：
一第七PMOS管，源极连接所述偏置电流输出端，漏极通过一第一串联电阻分压电路接地；
一第八PMOS管，源极连接所述偏置电流输出端，控制端连接所述第七PMOS管的控制端及所述第六PMOS管的控制端；
一第三NPN管，集电极连接所述第八PMOS管的漏极，基极连接所述第七PMOS管的漏极，发射极接地；
一第四NMOS管，源极接地，漏极连接所述第二NMOS管的控制端；
依次相互串联的，一第一反相器，一第二反相器以及一第三反相器，所述第一反相器的输入端连接所述第八PMOS管的漏极，所述第三反相器的输出端连接所述第四NMOS管的控制端；
一第五NMOS管，源极接地，漏极连接所述第一串联电阻分压电路的分压节点，控制端连接于所述第二反相器于所述第三反相器之间。
优选的，所述限流模块包括：
一第六NMOS管，漏极连接所述第二NMOS管的控制端，源极接地，控制端连接所述第二NMOS管的源极；
一第二串联电阻分压电路，串联于所述第二节点与所述第二NMOS管的控制端之间；
一第七NMOS管，漏极连接所述第二节点，源极连接所述第二串联电阻分压电路的分压节点，控制端与源极短接；
一第三齐纳二极管连接于所述第二NMOS管的控制端与所述第六NMOS管的控制端之间。
优选的，所述过压保护模块包括：
一第八NMOS管，漏极连接所述第一NMOS管的控制端；
一第九NMOS管，漏极连接所述第八NMOS管的源极，源极接地，控制端与源极短接；
一第十NMOS管，漏极连接所述第八NMOS管的控制端，源极接地，控制端与源极短接；
一第四齐纳二极管，正极连接所述第八NMOS管的控制端，负极连接所述第一节点；
一第五肖特基二极管，正极连接所述第八NMOS管的源极，负极连接所述第八NMOS管的控制端；
一第六齐纳二极管，正极连接所述第八NMOS管的源极，负极接地。
优选的，所述钳压模块包括：
一第二PNP管，所述第二PNP管的发射极连接所述第一节点，所述第二PNP管的集电极接地，所述第二PNP管的基极与发射极短接。
优选的，所述控制电路形成于一芯片中。
本发明还提供一种芯片，其中，包括如上述所述的控制电路。
上述技术方案具有如下优点或有益效果：通过内嵌防护模块、过温保护 模块、限流模块、过压保护模块以及钳压模块，解决第一NMOS管在关断瞬间因高电感负荷产生的能量发生单脉冲雪崩能量击穿而损坏的问题，以防护第一NMOS管，具有高可靠性。
附图说明
参考所附附图，以更加充分的描述本发明的实施例。然而，所附附图仅用于说明和阐述，并不构成对本发明范围的限制。
图1为本发明的实施例的电路结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
需要说明的是，在不冲突的情况下，本发明中的实施例及实施例中的特征可以相互组合。
下面结合附图和具体实施例对本发明作进一步说明，但不作为本发明的限定。
本发明提供一种智能低边功率开关的控制电路，其中，包括：
一第一NMOS管Q1；
一第二NMOS管，所述第二NMOS管的源极连接一第一电阻后与所述第一NMOS管的源极并联接地，所述第二NMOS管及所述第一NMOS管的漏极并联至一第一节点后连接至一负载外接端LOAD，控制端的栅极连接一 第六电阻R6以及一第七电阻R7并最终并联至一第二节点2后通过一第二电阻R2连接一电压输入端VIN；
一防护模块3，并联于电压输入端VIN与地GND之间，用以进行静电防护；
一过温保护模块，并联于第二节点2与地GND之间，用以当工作温度达到一预设温度时，截止第一NMOS管Q1的控制端的工作电流；
一限流模块5，并联于第二节点2与地GND之间，并设置一第六NMOS管Q13和上述第二NMOS管Q2，第六NMOS管Q13的栅极与第二NMOS管Q2源极连接，第六NMS管Q13漏极与第一NMOS管Q1的栅极连接，用以当电流采样第二NMOS管Q2采集到的电流超过一预设电电流时第六NMOS管Q13开启，给第一NMOS管Q1栅极放电，从而限制第一NMOS管Q1的输出电流；
一过压保护模块6，并联于第一节点1与地GND之间，设置一第四齐二极管D4，用以当第一NMOS管Q1漏极电压超过预设电压时，拉低第一NMOS管Q1栅极电压，关断第一NMOS管Q1；
一钳压模块7，并联于第一节点1与地GND之间，用以当加在第一NMOS管Q1的漏极与地GND之间的电压高于钳压模块7预设的电压时，钳压模块7被开启，将加在第一NMOS管Q1漏源两端的电压钳位在预设电压值，第一NMOS管Q1避免发生漏源击穿。
具体地，本实施例中，在电压输入端VIN和地GND之间连接防护模块3与第一NMOS管Q1并联，从而对第一NMOS管起到静电防护作用。
本实施例中，在第二节点2和地GND之间连接有过温保护模块，当工作温度达到过温保护的预设温度时，可通过该过温保护模块拉低第一NMOS管 Q1的控制端电压，从而使得第一NMOS管Q1关断，进一步，若工作温度降低时，过温保护模块产生温度迟滞量，当工作温度降低于一定温度时，第一NMOS管Q1处于开启状态。
本实施例中，在第二节点2与地GND之间连接限流模块5，当电压输入端VIN所提供的电压较低时，第一NMOS管Q1和第二NMOS管Q2的控制端电压相等，且第二NMOS管Q2与第一电阻R1可实时监测第一NMOS管Q1的电流；当电压输入端VIN所提供的电压较高时，第一NMOS管Q1的电流增大，第一电阻R1两端电压增大，进而使得第一NMOS管Q1的控制端电压减小，随之流经第一NMOS管Q1的电流减小，以起到保护第一NMOS管Q1的作用。
本实施例中，于第一节点1与第二节点2之间连接过压保护模块6，当第一NMOS管Q1的漏极电压较大时，通过该过压保护模块6，使得第一NMOS管Q1的控制端电压降低，从而第一NMOS管Q1关断。
本实例中，在第一节点1与地GND之间还并联有钳压模块7，当第一NMOS管Q1关断瞬间，因高电感负荷产生的击穿电压的能量被释放，第一NMOS管Q1的漏极电压被钳位到低于其击穿电压的一预设值时，从而有效防止第一NMOS管Q1被击穿，以起到保护第一NMOS管Q1的作用。
通过内嵌防护模块3、过温保护模块、限流模块5、过压保护模块6以及钳压模块7，解决第一NMOS管Q1在关断瞬间因高电感负荷产生的能量发生单脉冲雪崩能量击穿而损坏的问题，以防护第一NMOS管Q1，具有高可靠性。
在一种较优的实施例中，防护模块3包括：
一第一PNP管VT1，第一PNP管VT1的发射极连接至电压输入端VIN，第一PNP管VT1的基极短接至第一PNP管VT1的发射极，第一PNP管VT1 的集电极接地GND。
具体地，上述技术方案中的防护模块3为第一PNP管VT1，通过该第一PNP管VT1起到静电防护作用。
在一种较优的实施例中，过温保护模块包括：
一电流镜单元40，并联于第二节点2与地GND之间，并提供一偏置电流输出端；
一启动单元41，并联于偏置电流输出端与地GND之间，并提供一启动电流输出端；
一PATA电流源42，并联于偏置电流输出端与地GND之间，并设置一启动端连接启动电流输出端，用于根据偏置电流产生一与工作温度成正比的PATA电流；
一过温控制单元43，并联于偏置电流输出端与地GND之间，用以当工作温度升高时，控制输入第一NMOS管Q1的控制端的电流。
具体地，上述技术方案中的过温保护模块包括电流镜单元40、启动单元41、PATA电流源42以及过温控制单元43。
本实施例中，通过电流镜单元40提供偏置电流输出端并输出偏置电流。
本实施例中，在整个电路系统中未上电之前，每个模块的工作状态都为0，当电压输入端VIN提供电压后，启动单元41导通，用以启动其它模块的工作状态。
本实施例中，当上述启动单元41启动完成后，从而可根据电流镜单元40提供的偏置电流产生与工作温度成正比的PATA电流。
本实施例中，当电路的工作温度处于正常温度时，第一NMOS管Q1也正常工作，但是当工作温度达到过温保护的预设温度时，可通过该过温控制单元43拉低第一NMOS管Q1的控制端电压，从而使得第一NMOS管Q1关断，进一步，若工作温度降低时，过温控制单元43产生温度迟滞量，当工作温度降 低于一定温度时，第一NMOS管Q1处于开启状态。
在一种较优的实施例中，电流镜单元40包括：
一第一PMOS管Q3，源极连接第二节点2，控制端与漏极短接；
一第二PMOS管Q4，源极连接第二节点2，漏极通过一第一齐纳二极管D1接地接地GND，控制端连接第一PMOS管Q3的控制端，并通过一第二齐纳二极管D2连接至第二节点2；
一第三NMOS管Q5，源极接地GND，漏极连接第一PMOS管Q3的漏极，控制端与源极短接；
第二PMOS管Q4的漏极形成偏置电流输出端。
具体地，上述的电流镜单元40包括第一PMOS管Q3、第二PMOS管Q4、第三NMOS管Q5以及第一齐纳二极管D1、第二齐纳二极管D2，用以提供偏置电流，其中，第二PMOS管Q4镜像第一PMOS管Q3的电流，该第二PMOS管Q4的漏极连接第一齐纳二极管D1的阴极，为产生上述的PATA电流的PATA电流源42提供偏置电流，且第一齐纳二极管D1作为产生PATA电流的PATA电流源42的稳压管。
本实施例中，第三NMOS管Q5作为恒流源。第二齐纳二极管D2的阳极连接第二PMOS管Q4的控制端，阴极连接第二PMOS管Q4的源极，用于保护第二PMOS管Q4的控制端，防止其被击穿。
在一种较优的实施例中，启动单元41包括：
一第三PMOS管Q5，源极连接偏置电流输出端，漏极通过一电容C接地，控制端与漏极短接；
一第四PMOS管Q6，源极连接偏置电流输出端，漏极接地GND，控制端连接第三PMOS管Q5的控制端；
第四PMOS管Q6的漏极形成启动电流输出端。
具体地，上述技术方案中的启动单元41包括第三PMOS管Q5、第四 PMOS管Q6以及电容C。当上述电压输入端VIN提供电压后，第三PMOS管Q5和第四PMOS管Q6导通，进而第三PMOS管Q5给电容C的两端充电，第四PMOS管Q6向上述PATA电流源42输入电流，进一步当电容C的两端电压与第三PMOS管Q5以及第四PMOS管Q6的源极电压相等时，第三PMOS管Q5和第四PMOS管Q6截止，则启动单元41启动完成。
在一种较优的实施例中，PTAT电流源42包括：
一第五PMOS管Q7，源极连接偏置电流输出端，漏极连接启动电流输出端；
一第六PMOS管Q8，源极连接偏置电流输出端，控制端与漏极短接，并连接第五PMOS管Q7的控制端；
一第一NPN管VT2，集电极连接第五PMOS管Q7的漏极，发射极接地GND，基极与集电极短接；
一第二NPN管VT3，集电极连接第六PMOS管Q8的漏极，发射极通过一第三电阻R3接地GND，基极连接第一NPN管VT2的基极。
具体地，上述PTAT电流源42通过第五PMOS管Q7、第六PMOS管Q8、第一NPN管VT2、第二NPN管VT3以及第三电阻R3连接组成。本实施例里中，设置第一NPN管VT2和第二NPN管VT3的个数比为1:4，多个第二NPN管VT3相互并联。
在一种较优的实施例中，过温控制单元43包括：
一第七PMOS管Q9，源极连接偏置电流输出端，漏极通过一第一串联电阻分压电路8接地GND；
一第八PMOS管Q10，源极连接偏置电流输出端，控制端连接第七PMOS管Q9的控制端及第六PMOS管Q8的控制端；
一第三NPN管VT4，集电极连接第八PMOS管Q10的漏极，基极连接第七PMOS管Q9的漏极，发射极接地GND；
一第四NMOS管Q11，源极接地GND，漏极连接第二NMOS管Q2的控制端；
依次相互串联的，一第一反相器INV1，一第二反相器INV2以及一第三反相器INV3，第一反相器INV1的输入端连接第八PMOS管Q10的漏极，第三反相器INV3的输出端连接第四NMOS管Q11的控制端；
一第五NMOS管Q12，源极接地GND，漏极连接第一串联电阻分压电路8的分压节点，控制端连接于第二反相器INV2于第三反相器INV3之间。
具体地，本实施例中，当电路的工作温度处于正常温度时，第三NPN管VT4截止，其集电极的电位较高，经过相互串联的第一反相器INV1，第二反相器INV2以及第三反相器INV3输出低电位，并将该低电位输入至第四NMOS管Q11的控制端，使得第四NMOS管Q11截止，第一NMOS管Q1正常工作。
本实施例中，上述第一串联电阻分压电路8包括第四电阻R4和第五电阻R5，第五NMOS管Q12的控制端连接于第二反相器INV2于第三反相器INV3之间，第二反相器INV2输出高电位，使得第五NMOS管Q12导通，将第四电阻R4短路。当工作温度达到过温保护的预设温度时，第三NPN管VT4导通，其集电极输出低电位，再经过第一反相器INV1，第二反相器INV2以及第三反相器INV3输出高电位，从而拉低上述第一NMOS管Q1的控制端电压，使得第一NMOS管Q1关断。
进一步地，此时第二NMOS管Q2截至，当上述工作温度降低时，由于第二NMOS管Q2截至，第一串联电阻分压电路8中的第四电阻R4接通，从而第三NPN管VT4的基极的电位被抬高产生温度迟滞量，当工作温度降低于一定温度时，第三NPN管VT4再次截止，从而使得第一NMOS管Q1处 于开启状态。
在一种较优的实施例中，限流模块5包括：
一第六NMOS管Q13，漏极连接第二NMOS管Q2的控制端，源极接地GND，控制端连接第二NMOS管Q2的源极；
一第二串联电阻分压电路9，串联于第二节点2与第二NMOS管Q2的控制端之间；
一第七NMOS管Q14，漏极连接第二节点2，源极连接第二串联电阻分压电路9的分压节点，控制端与源极短接；
一第三齐纳二极管D3连接于第二NMOS管Q2的控制端与第六NMOS管Q13的控制端之间。
具体地，本实施例中，第二串联电阻分压电路9包括第六电阻R6和第七电阻R7，均为限流电阻，上述第一电阻R1作为采样电阻，第二NMOS管Q2为电流采样管，第六NMOS管Q13为下拉管，当上述电压输入端VIN提供的电压较低时，第二NMOS管Q2和上述第一NMOS管Q1的控制端的电压相等，第二NMOS管Q2和第一电阻R1实时监测流过第一NMOS管Q1的电流。
本实施例中，当上述电压输入端VIN提供的电压较高时，流经第一NMOS管Q1的电流升高，第一电阻R1两端的电压升高，使得第六NMOS管Q13的控制端的电压大于其阈值电压而导通，并开始放电，第一NMOS管Q1的控制端的电压减小，从而流经第一NMOS管Q1的电流减小，进而起到限流作用，以保护第一NMOS管Q1。
另外，需要说明的是，本实施例中可通过调整第二NMOS管Q2和第一NMOS管Q1的个数比或者调整第一电阻R1的阻值来确定限流值的大小。
在一种较优的实施例中，过压保护模块6包括：
一第八NMOS管Q15，漏极连接第一NMOS管Q1的控制端；
一第九NMOS管Q16，漏极连接第八NMOS管Q15的源极，源极接地GND，控制端与源极短接；
一第十NMOS管Q17，漏极连接第八NMOS管Q15的控制端，源极接地GND，控制端与源极短接；
一第四齐纳二极管D4，正极连接第八NMOS管Q15的控制端，负极连接第一节点1；
一第五肖特基二极管D5，正极连接第八NMOS管Q15的源极，负极连接第八NMOS管Q15的控制端；
一第六齐纳二极管D6，正极连接第八NMOS管Q15的源极，负极接地GND。
具体地，本实施例中第八NMOS管Q15为下拉管，当第一NMOS管Q1的漏极的电压大于第四齐纳二极管D4的击穿电压时，第八NMOS管Q15导通将第一NMOS管Q1的控制端电压拉低，使得第一NMOS管Q1关断。
在一种较优的实施例中，钳压模块7包括：
一第二PNP管VT5，第二PNP管VT5的发射极连接第一节点1，第二PNP管VT5的集电极接地GND，第二PNP管VT5的基极与发射极短接。
具体地，本实施例中，钳压模块7包括第二PNP管VT5，当上述第五肖特基二极管D5用以保护第八NMOS管Q15的控制端，第六齐纳二极管D6发生过压保护时，第一NMOS管Q1关断瞬间，因高电感负荷产生的击穿电压的能量被释放，第一NMOS管Q1的漏极电压被钳位到低于其击穿电压的预设值时，同时将击穿电压的能量泄放至地，从而有效防止第一NMOS管Q1被击穿，以起到保护第一NMOS管Q1的作用。
在一种较优的实施例中，控制电路形成于一芯片中。
本发明该提供一种芯片，其中，包括如上述所述的控制电路。
以上所述仅为本发明较佳的实施例，并非因此限制本发明的实施方式及保护范围，对于本领域技术人员而言，应当能够意识到凡运用本发明说明书及图示内容所作出的等同替换和显而易见的变化所得到的方案，均应当包含在本发明的保护范围内。

Claims (12)

  1. 一种智能低边功率开关的控制电路，其特征在于，包括：
    一第一NMOS管；
    一第二NMOS管，所述第二NMOS管的源极连接一第一电阻后与所述第一NMOS管的源极并联接地，所述第二NMOS管及所述第一NMOS管的漏极并联至一第一节点后连接至一负载外接端，控制端的栅极连接一第六电阻以及一第七电阻并最终并联至一第二节点后通过一第二电阻连接一电压输入端；
    一防护模块，并联于所述电压输入端与地之间，用以进行静电防护；
    一过温保护模块，并联于所述第二节点与地之间，用以当工作温度达到一预设温度时，截止所述第一NMOS管的控制端的工作电流；
    一限流模块，并联于所述第二节点与地之间，并设置一第六NMOS管和所述第二NMOS管，所述第六NMOS管的栅极与所述第二NMOS管的源极连接，所述第六NMOS管的漏极与所述第一NMOS管的栅极连接，用以当所述电流采样第二NMOS管采集到的电流超过一预设电电流时所述第六NMOS开启，给所述第一NMOS管栅极放电，从而限制所述第一NMOS管的的输出电流；
    一过压保护模块，并联于所述所述第一节点与所述地之间，设置一第四齐纳二极管，用以当所述第一NMOS管漏极电压超过预设电压时，拉低所述第一NMOS管栅极电压，关断所述第一NMOS管；
    一钳压模块，并联于所述第一节点与地之间，用以当所述当加在所述第一NMOS管的漏极与地之间的电压高于钳压模块预设的电压时，钳压模块被开启，将加在所述第一NMOS管漏源两端的电压钳位在预设电压值，第一NMOS管避免发生漏源击穿。
  2. 如权利要求1所述的控制电路，其特征在于，所述防护模块包括：
    一第一PNP管，所述第一PNP管的发射极连接至所述电压输入端，所述第一PNP管的基极短接至所述第一PNP管的发射极，所述第一PNP管的集电极接地。
  3. 如权利要求1所述的控制电路，其特征在于，所述过温保护模块包括：
    一电流镜单元，并联于所述第二节点与地之间，并提供一偏置电流输出端；
    一启动单元，并联于所述偏置电流输出端与地之间，并提供一启动电流输出端；
    一PATA电流源，并联于所述偏置电流输出端与地之间，并设置一启动端连接所述启动电流输出端，用于根据所述偏置电流产生一与所述工作温度成正比的PATA电流；
    一过温控制单元，并联于所述偏置电流输出端与地之间，用以当所述工作温度升高时，控制输入所述第一NMOS管的控制端的电流。
  4. 如权利要求3所述的控制电路，其特征在于，所述电流镜单元包括：
    一第一PMOS管，源极连接所述第二节点，控制端与漏极短接；
    一第二PMOS管，源极连接所述第二节点，漏极通过一第一齐纳二极管接地接地，控制端连接所述第一PMOS管的控制端，并通过一第二齐纳二极管连接至所述第二节点；
    一第三NMOS管，源极接地，漏极连接所述第一PMOS管的漏极，控制端与源极短接；
    所述第二PMOS管的漏极形成所述偏置电流输出端。
  5. 如权利要求3所述的控制电路，其特征在于，所述启动单元包括：
    一第三PMOS管，源极连接所述偏置电流输出端，漏极通过一电容接地，控制端与漏极短接；
    一第四PMOS管，源极连接所述偏置电流输出端，漏极接地，控制端连接所述第三PMOS管的控制端；
    所述第四PMOS管的漏极形成所述启动电流输出端。
  6. 如权利要求3所述的控制电路，其特征在于，所述PTAT电流源包括：
    一第五PMOS管，源极连接所述偏置电流输出端，漏极连接所述启动电流输出端；
    一第六PMOS管，源极连接所述偏置电流输出端，控制端与漏极短接，并连接所述第五PMOS管的控制端；
    一第一NPN管，集电极连接所述第五PMOS管的漏极，发射极接地，基极与集电极短接；
    一第二NPN管，集电极连接所述第六PMOS管的漏极，发射极通过一第三电阻接地，基极连接所述第一NPN管的基极。
  7. 如权利要求6所述的控制电路，其特征在于，所述过温控制单元包括：
    一第七PMOS管，源极连接所述偏置电流输出端，漏极通过一第一串联电阻分压电路接地；
    一第八PMOS管，源极连接所述偏置电流输出端，控制端连接所述第七PMOS管的控制端及所述第六PMOS管的控制端；
    一第三NPN管，集电极连接所述第八PMOS管的漏极，基极连接所述第七PMOS管的漏极，发射极接地；
    一第四NMOS管，源极接地，漏极连接所述第二NMOS管的控制端；
    依次相互串联的，一第一反相器，一第二反相器以及一第三反相器，所述第一反相器的输入端连接所述第八PMOS管的漏极，所述第三反相器的输出端连接所述第四NMOS管的控制端；
    一第五NMOS管，源极接地，漏极连接所述第一串联电阻分压电路的分压节点，控制端连接于所述第二反相器于所述第三反相器之间。
  8. 如权利要求3所述的控制电路，其特征在于，所述限流模块包括：
    一第二串联电阻分压电路，串联于所述第二节点与所述第二NMOS管的控制端之间；
    一第七NMOS管，漏极连接所述第二节点，源极连接所述第二串联电阻分压电路的分压节点，控制端与源极短接；
    一第三齐纳二极管连接于所述第二NMOS管的控制端与所述第六NMOS管的控制端之间。
  9. 如权利要求3所述的控制电路，其特征在于，所述过压保护模块包括：
    一第八NMOS管，漏极连接所述第一NMOS管的控制端；
    一第九NMOS管，漏极连接所述第八NMOS管的源极，源极接地，控制端与源极短接；
    一第十NMOS管，漏极连接所述第八NMOS管的控制端，源极接地，控制端与源极短接；
    一第四齐纳二极管，正极连接所述第八NMOS管的控制端，负极连接所述第一节点；
    一第五肖特基二极管，正极连接所述第八NMOS管的源极，负极连接所述第八NMOS管的控制端；
    一第六齐纳二极管，正极连接所述第八NMOS管的源极，负极接地。
  10. 如权利要求3所述的控制电路，其特征在于，所述钳压模块包括：
    一第二PNP管，所述第二PNP管的发射极连接所述第一节点，所述第二PNP管的集电极接地，所述第二PNP管的基极与发射极短接。
  11. 如权利要求1-10中任一所述的控制电路，其特征在于，所述控制电路形成于一芯片中。
  12. 一种芯片，其特征在于，包括如权利要求1-10中任一所述的控制电路。
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CN112383293A (zh) * 2020-11-30 2021-02-19 上海维安半导体有限公司 一种智能低边功率开关的控制电路及芯片
CN214707671U (zh) * 2020-11-30 2021-11-12 上海维安半导体有限公司 一种智能低边功率开关的控制电路及芯片

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