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WO2022021945A1 - 半导体电感结构 - Google Patents

半导体电感结构 Download PDF

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Publication number
WO2022021945A1
WO2022021945A1 PCT/CN2021/087341 CN2021087341W WO2022021945A1 WO 2022021945 A1 WO2022021945 A1 WO 2022021945A1 CN 2021087341 W CN2021087341 W CN 2021087341W WO 2022021945 A1 WO2022021945 A1 WO 2022021945A1
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coil
metal
layer
layers
semiconductor
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PCT/CN2021/087341
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English (en)
French (fr)
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何乃龙
张森
赵景川
许杰
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无锡华润上华科技有限公司
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Publication of WO2022021945A1 publication Critical patent/WO2022021945A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/34—Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

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  • the present application relates to the field of semiconductors, in particular to semiconductor inductor structures.
  • the size of the chip is getting smaller and smaller. Because the magnetic flux of the coil of the chip itself is relatively small, the collected signal is greatly affected by the environment. At the same time, the chip itself will also generate parasitic inductance. The inductance of the mutual inductance coil is equivalent, the interference of the collected signal will be very large.
  • the usual way to increase the magnetic flux of the coil is to increase the number of turns of the coil, and increasing the number of turns will inevitably lead to an increase in the chip area. Increase.
  • a semiconductor inductor structure is provided.
  • a semiconductor inductor structure comprising:
  • a mutual inductance coil including a top coil and a bottom coil, the top coil and the bottom coil are located on different planes, and mutual inductance is formed between the two;
  • an intermediate structure the intermediate structure is located between the top layer coil and the bottom layer coil, including: an interlayer conductive layer and a communication structure, the communication structure is used to electrically connect the interlayer conductive layer and the top layer coil, the interlayer conductive layer and the bottom coil.
  • a semiconductor inductor structure comprising:
  • the inductance coil includes a plurality of coil layers, the plurality of the coil layers are arranged in a row, and each of the coil layers is located on a different plane, and adjacent coil layers are continuous coils;
  • the intermediate structure includes a plurality of communicating structures, and the communicating structures are used to electrically connect the adjacent coil layers.
  • FIG. 1 is a schematic structural diagram of a semiconductor inductor structure in an embodiment of the present application
  • FIG. 2 is a schematic cross-sectional structural diagram of a semiconductor inductor structure in an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a semiconductor inductor structure in another embodiment of the present application.
  • FIG. 4 is a schematic cross-sectional structure diagram of a semiconductor inductor structure in another embodiment of the present application.
  • Reference numerals 10, mutual inductance coil; 101, top layer coil; 102, bottom layer coil; 11, middle structure; 111, interlayer conductive layer; 112, connected structure; 20, inductor coil; 201, coil layer; 21, middle structure ; 211. Connected structure.
  • the size of the chip is getting smaller and smaller. Because the magnetic flux of the coil of the chip itself is relatively small, the collected signal is greatly affected by the environment. At the same time, the chip itself will also generate parasitic inductance. The inductance of the mutual inductance coil is equivalent, the interference of the collected signal will be very large.
  • the usual way to increase the magnetic flux of the coil is to increase the number of turns of the coil, and increasing the number of turns will inevitably lead to an increase in the chip area. Increase.
  • the present application provides a semiconductor inductor structure, including: a mutual inductance coil 10, including a top coil 101 and a bottom coil 102, the top coil 101 and the bottom coil 102 are located on different planes , and mutual inductance is formed between the two; the intermediate structure 11, which is located between the top coil 101 and the bottom coil 102, includes an interlayer conductive layer 111 and a connection structure 112, and the connection structure 112 is used to electrically connect the interlayer conductive layers. 111 and the top coil 101 , the interlayer conductive layer 111 and the bottom coil 102 .
  • the intermediate structure 11 connects the top coil 101 and the bottom coil 102, and the intermediate structure 11 includes an interlayer conductive layer 111 and a connection structure 112.
  • the interlayer conductive layer 111 and the connection structure 112 are both conductive structures. Therefore, the magnetic resistance of the magnetic circuit is greatly reduced, so that the magnetic flux between the top coil 101 and the bottom coil 102 increases, and the inductive reactance of the bottom coil 102 and the top coil 101 becomes larger.
  • the bottom coil 102 and the bottom coil 102 After the inductance of the mutual inductance coil 10 formed by the coil 102 becomes larger, the influence of the parasitic inductance generated by the chip itself on the mutual inductance coil 10 becomes smaller, so the interference to the collected signal also becomes smaller.
  • the intermediate structure 11 includes more than two interlayer conductive layers 111 , and the connection structure 112 is used to electrically connect the interlayer conductive layer 111 to the top coil 101 , and the interlayer conductive layer 111 to adjacent layers.
  • the intermediate structure 11 may include two interlayer conductive layers 111 and three connection structures 112. The number of interlayer conductive layers 111 and the number of connection structures 112 included in the intermediate structure 11 should be determined according to the specific structure of the semiconductor structure in the actual production process. Certainly.
  • the semiconductor inductor structure is located in the semiconductor structure formed by fab process packaging, and the top layer coil 101 is a back-end metal layer on the device wafer.
  • the bottom layer coil 102 can be a package metal coil .
  • the bottom layer coil 102 is a back-end metal layer on the device wafer, and the top layer coil 101 is a package metal coil.
  • the back-stage metal layer may be made of one or more of metal copper, metal aluminum, metal nickel, metal titanium or metal tungsten; the encapsulated metal coil may be an encapsulated copper coil.
  • the bottom coil 102 and the top coil 101 are arranged in a row, the plane where the bottom coil 102 is located and the plane where the top coil 101 is located are parallel to each other, and the vertical projection of the top coil 101 completely falls on the bottom coil 102 .
  • the interlayer conductive layer 111 is a metal layer, and the metal layer can be made of one or more of metal copper, metal aluminum, metal nickel, metal titanium or metal tungsten; the connection structure 112 is Metal through hole, the specific shape of the metal through hole depends on the actual production situation.
  • the communication structure 112 may be made of one or more of metal copper, metal aluminum, metal nickel, metal titanium or metal tungsten.
  • the present application further provides a semiconductor inductor structure, comprising: an inductor coil 20, the inductor coil 20 includes a plurality of coil layers 201, and the plurality of the coil layers 201 are arranged in a row, And each coil layer 201 is located on a different plane, and there are continuous coils between adjacent coil layers 201 .
  • the intermediate structure 21 , the intermediate structure 21 includes a plurality of communicating structures 211 , and the communicating structures 211 are used to electrically connect the adjacent coil layers 201 .
  • the semiconductor inductor structure is formed in a semiconductor structure formed by fan-out panel level packaging (FOPLP) technology, the inductor coil 20 is formed by copper wires, and the through holes in the semiconductor structure form the connection structure 211 .
  • FOPLP fan-out panel level packaging
  • the face of the coil layer 201 faces the face of the adjacent coil layers 201 , and there is a gap between two adjacent coil layers 201 , and the communication structure 211 connects the two adjacent coil layers 201 .
  • the coil layer 201 includes the metal coil layer 201 inside the semiconductor structure, which can be made of one or more of metal copper, metal aluminum, metal nickel, metal titanium or metal tungsten.
  • the communication structure 211 is a metal via, which may be a copper via, an aluminum via, a nickel via, a titanium via, or a tungsten via, or the like.
  • the communication structure 211 is electrically connected to the adjacent coil layers 201, the communication structure 211 is a conductive structure, and its magnetic permeability is greater than that of air, so the magnetic resistance of the magnetic circuit is greatly reduced, so that the magnetic resistance between adjacent coil layers 201 is greatly reduced.
  • the inductive reactance of the inductive coil 20 increases.
  • the influence of the parasitic inductance generated by the chip itself on the inductive coil 20 becomes smaller. Therefore, The interference of the collected signal is also reduced.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Coils Or Transformers For Communication (AREA)

Abstract

一种半导体电感结构，包括：互感线圈(10)，包括顶层线圈(101)和底层线圈(102)，顶层线圈(101)与底层线圈(102)位于不同的平面，且两者之间形成互感；中间结构(11)，中间结构(11)位于顶层线圈(101)与底层线圈(102)之间，包括，层间导电层(111)和连通结构(112)，连通结构(112)用于电连接层间导电层(111)与顶层线圈(101)、层间导电层(111)与底层线圈(102)。中间结构(11)连接顶层线圈(101)和底层线圈(102)，中间结构(11)包括层间导电层(111)和连通结构(112)，层间导电层(111)与连通结构(112)均为导电结构，两者的磁导率大于空气。

Description

半导体电感结构
相关申请的交叉引用
本申请要求于2020年7月30日提交中国专利局、申请号为2020107517495、发明名称为“半导体电感结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体领域，特别是涉及半导体电感结构。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成示例性技术。
随着技术的发展，芯片的尺寸也越来越小，由于芯片本身线圈的磁通量比较小，采集信号受环境影响较大，同时，芯片自身也会产生寄生电感，若这些寄生电感与我们采集信号的互感线圈电感相当，则采集信号受到的干扰会非常大。然而在现有技术中，通常增加线圈磁通量的方式就是增加线圈的圈数，而增加圈数的必然会导致芯片面积的增加，一方面与芯片小型化的趋势相悖，另一方面会导致成本的增加。
发明内容
根据本申请的各种实施例，提供一种半导体电感结构。
一种半导体电感结构，包括：
互感线圈，包括顶层线圈和底层线圈，所述顶层线圈与所述底层线圈位于不同的平面，且两者之间形成互感；
中间结构，所述中间结构位于所述顶层线圈与所述底层线圈之间，包括， 层间导电层和连通结构，所述连通结构用于电连接所述层间导电层与所述顶层线圈、所述层间导电层与所述底层线圈。
一种半导体电感结构，包括：
电感线圈，所述电感线圈包括若干个线圈层，若干所述线圈层之间呈一列排布，且各个所述线圈层位于不同的平面，相邻所述线圈层之间为连续的线圈；
中间结构，所述中间结构包括若干连通结构，所述连通结构用于电连接相邻所述线圈层。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或示例性技术中的技术方案，下面将对实施例或示例性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为本申请一个实施例中半导体电感结构的结构示意图；
图2为本申请一个实施例中半导体电感结构的截面结构示意图；
图3为本申请另一个实施例中半导体电感结构的结构示意图；
图4为本申请另一个实施例中半导体电感结构的截面结构示意图。
附图标记：10、互感线圈；101、顶层线圈；102、底层线圈；11、中间结构；111、层间导电层；112、连通结构；20、电感线圈；201、线圈层；21、中间结构；211、连通结构。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。 附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在本申请的描述中，需要理解的是，术语“上”、“下”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方法或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
随着技术的发展，芯片的尺寸也越来越小，由于芯片本身线圈的磁通量比较小，采集信号受环境影响较大，同时，芯片自身也会产生寄生电感，若这些寄生电感与我们采集信号的互感线圈电感相当，则采集信号受到的干扰会非常大。然而在现有技术中，通常增加线圈磁通量的方式就是增加线圈的圈数，而增加圈数的必然会导致芯片面积的增加，一方面与芯片小型化的趋势相悖，另一方面会导致成本的增加。
为了解决上述问题，如图1和图2所示，本申请提供了一种半导体电感结构，包括：互感线圈10，包括顶层线圈101和底层线圈102，顶层线圈101与底层线圈102位于不同的平面，且两者之间形成互感；中间结构11，中间结构11位于顶层线圈101与底层线圈102之间，包括，层间导电层111和连通结构112，连通结构112用于电连接层间导电层111与顶层线圈101、层间导电层111与底层线圈102。
通过上述技术方案，中间结构11连接顶层线圈101和底层线圈102，中间结构11包括层间导电层111和连通结构112，层间导电层111与连通结构 112均为导电结构，两者的磁导率大于空气，因此磁路的磁阻大大减小，使得顶层线圈101和底层线圈102之间的磁通量增大，则底层线圈102和顶层线圈101的感抗变大了，当底层线圈102和底层线圈102所组成的互感线圈10感抗变大后，芯片自身所产生的寄生电感对互感线圈10的影响变小，因此采集信号受到的干扰也变小了。
在一个可选的实施例中，中间结构11包括两个以上的层间导电层111，连通结构112用于电连接层间导电层111与顶层线圈101、层间导电层111与相邻层间导电层111、层间导电层111与底层线圈102。中间结构11可以包括两个层间导电层111和三个连通结构112，中间结构11所包含的层间导电层111数量及连通结构112的数量均需根据实际生产过程中半导体结构的具体结构而定。
在一个可选的实施例中，半导体电感结构位于fab工艺封装形成的半导体结构内，顶层线圈101为器件晶圆上的后段金属层，在此实施例中，底层线圈102可以为封装金属线圈。在其可选的实施例中，底层线圈102器件晶圆上的后段金属层，顶层线圈101则为封装金属线圈。后段金属层可以由金属铜、金属铝、金属镍、金属钛或金属钨中的一种或几种制成；封装金属线圈可以为封装铜线圈。
在一个可选的实施例中，底层线圈102与顶层线圈101呈一列排布，底层线圈102所在平面与顶层线圈101所在平面相互平行，顶层线圈101的垂直投影完全落在底层线圈102上。
在一个可选的实施例中，层间导电层111为金属层，金属层可以由金属铜、金属铝、金属镍、金属钛或金属钨中的一种或几种制成；连通结构112为金属通孔，金属通孔的具体形状根据实际生产情况而定。连通结构112可以由金属铜、金属铝、金属镍、金属钛或金属钨中的一种或几种制成。
如图3和图4所示，本申请还提供一种半导体电感结构，包括：电感线圈20，所述电感线圈20包括若干个线圈层201，若干所述线圈层201之间呈一列排布，且各个线圈层201位于不同的平面，相邻线圈层201之间为连续 的线圈。中间结构21，中间结构21包括若干连通结构211，连通结构211用于电连接相邻线圈层201。
在一个可选的实施例中，半导体电感结构形成于扇出型面板级封装(FOPLP)技术所形成的半导体结构内，通过铜线形成电感线圈20，半导体结构内的通孔形成连通结构211。
在一个可选的实施例中，所述线圈层201所在面朝向相邻所述线圈层201所在面，且相邻两个所述线圈层201之间存在间距，连通结构211连接相邻两个线圈层201的中心位置，线圈层201包括半导体结构内部的金属线圈层201，可以由金属铜、金属铝、金属镍、金属钛或金属钨中的一种或几种制成。在一个可选的实施例中，连通结构211为金属通孔，可以为铜通孔、铝通孔、镍通孔、钛通孔或钨通孔等。
通过上述技术方案，连通结构211电连接相邻的线圈层201，连通结构211为导电结构，其磁导率大于空气，因此磁路的磁阻大大减小，使得相邻线圈层201之间的磁通量增大，则电感线圈20的感抗变大了，当若干线圈层201所组成的电感线圈20的感抗变大后，芯片自身所产生的寄生电感对电感线圈20的影响变小，因此采集信号受到的干扰也变小了。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种半导体电感结构，包括：
    互感线圈，包括顶层线圈和底层线圈，所述顶层线圈与所述底层线圈位于不同的平面，且两者之间形成互感；
    中间结构，所述中间结构位于所述顶层线圈与所述底层线圈之间，包括，层间导电层和连通结构，所述连通结构用于电连接所述层间导电层与所述顶层线圈、所述层间导电层与所述底层线圈。
  2. 根据权利要求1所述的半导体电感结构，其中所述中间结构包括两个以上的层间导电层，所述连通结构用于电连接所述层间导电层与所述顶层线圈、所述层间导电层与相邻所述层间导电层、所述层间导电层与所述底层线圈。
  3. 根据权利要求1所述的半导体电感结构，其中所述顶层线圈和所述底层线圈为器件晶圆上的后段金属层。
  4. 根据权利要求1所述的半导体电感结构，其中所述顶层线圈或所述底层线圈为器件晶圆上的后段金属层。
  5. 根据权利要求4所述的半导体电感结构，其中所述后段金属层由金属铜、金属铝、金属镍、金属钛或金属钨中的一种或几种制成。
  6. 根据权利要求1所述的半导体电感结构，其中所述底层线圈和所述顶层线圈为封装金属线圈。
  7. 根据权利要求1所述的半导体电感结构，其中所述底层线圈或所述顶层线圈为封装金属线圈。
  8. 根据权利要求1所述的半导体电感结构，其中所述底层线圈与所述顶层线圈呈一列排布。
  9. 根据权利要求8所述的半导体电感结构，其中所述底层线圈所在平面与所述顶层线圈所在平面相互平行，所述顶层线圈的垂直投影落在所述底层线圈上。
  10. 根据权利要求1中所述的半导体电感结构，其中所述层间导电层为金 属层。
  11. 根据权利要求10所述的半导体电感结构，其中所述金属层由金属铜、金属铝、金属镍、金属钛或金属钨中的一种或几种制成。
  12. 根据权利要求1所述的半导体电感结构，其中所述连通结构为金属通孔。
  13. 一种半导体电感结构，包括：
    电感线圈，所述电感线圈包括若干个线圈层，若干所述线圈层之间呈一列排布，且各个所述线圈层位于不同的平面，相邻所述线圈层之间为连续的线圈；
    中间结构，所述中间结构包括若干连通结构，所述连通结构用于电连接相邻所述线圈层。
  14. 根据权利要求13所述的半导体电感结构，其中所述线圈层的所在面朝向相邻所述线圈层的所在面，且相邻两个所述线圈层之间存在间距，所述连通结构连接相邻两个所述线圈层的中心位置。
  15. 根据权利要求13所述的半导体电感结构，其中所述线圈层包括半导体结构内部的金属线圈层。
PCT/CN2021/087341 2020-07-30 2021-04-15 半导体电感结构 WO2022021945A1 (zh)

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