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WO2016029569A1 - 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器单元及其驱动方法、栅极驱动电路、显示装置 Download PDF

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Publication number
WO2016029569A1
WO2016029569A1 PCT/CN2014/091685 CN2014091685W WO2016029569A1 WO 2016029569 A1 WO2016029569 A1 WO 2016029569A1 CN 2014091685 W CN2014091685 W CN 2014091685W WO 2016029569 A1 WO2016029569 A1 WO 2016029569A1
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WIPO (PCT)
Prior art keywords
signal
thin film
signal input
film transistor
gate
Prior art date
Application number
PCT/CN2014/091685
Other languages
English (en)
French (fr)
Inventor
王世君
陈小川
王磊
薛艳娜
姜文博
李月
包智颖
吕振华
肖文俊
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Filing date
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/764,066 priority Critical patent/US9715296B2/en
Priority to EP14882170.5A priority patent/EP3188190B1/en
Publication of WO2016029569A1 publication Critical patent/WO2016029569A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G06F3/04184—Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit and a driving method thereof, a gate driving circuit, and a display device.
  • a touch detection technology in which the touch drive signal is an AC signal appears, that is, the touch drive electrode alternately transmits the high potential touch drive during the touch period of one time period.
  • the signal (Tx_H) and the low-level touch driving signal (Tx_L) are used to implement the touch detection function of the touch screen.
  • the potential of the common electrode signal is about 0.1 V
  • the potential of the touch driving signal is between 0 V and 10 V. This causes a large voltage difference between the common electrode signal and the touch driving signal, resulting in the common electrode and The coupling capacitance occurs between the touch driving electrodes, so that the display brightness of the individual pixel units is affected, which affects the display effect of the touch screen during the touch phase.
  • the existing common electrode signal is provided by a separately provided driving chip (Drive IC), and the existing driving chip (Drive IC) cannot realize the control of the common electrode signal at different stages at different stages, so the touch
  • the amplitude of the control drive signal has a relatively large limitation, which affects the display effect of the touch screen.
  • the present disclosure provides a shift register unit and a driving method thereof, a gate driving circuit, and a display device, which can output a signal received by a common electrode by a shift register unit, so that it is possible to separately provide a driving for providing a common electrode signal in the display device.
  • the chip simplifies the structure of the display device and reduces the cost of the display device.
  • Embodiments of the present disclosure provide a shift register unit disposed in an in-cell touch panel, the in-cell touch panel including a substrate having a common electrode; the shift register unit including a pre-charge module , a pull-up module, a pull-down holding module, a reset module, and a first signal output control module, wherein:
  • the pull-down holding module is respectively connected with the first control signal input end, the reset signal input end, the third signal input end, the fourth signal input end, the pull-up node, and the gate signal output end, and is used for pulling down the pull-up node and the gate a potential of the signal output end, wherein the pull-up node is a connection point between the pre-charging module and the pull-up module;
  • the reset module is respectively connected to the second control signal input end, the gate signal output end, and the fourth signal input end, and is used for controlling the potential of the output signal of the gate signal output end in a touch phase of one frame time. Setting the potential of the fourth signal input to the fourth signal input terminal;
  • the first signal output control module is respectively connected to the first control signal input end, the second control signal input end, the first common electrode signal input end, the first signal input end and the first signal output end, for one frame time a display stage, controlling the first signal output end to output the first common electrode signal input by the first common electrode signal input end, and controlling the first signal output end to output the first signal during a touch period of one frame time
  • the first signal input by the input end, the first signal being a signal input to the common electrode connected to the shift register unit during the touch phase.
  • the first signal is a second common electrode signal
  • the potential value of the second common electrode signal is an average value of a potential value of the high potential touch driving signal and a potential value of the low potential touch driving signal.
  • the first signal is a touch driving signal.
  • the first signal output control module includes a first thin film transistor and a second thin film crystal Body tube, where:
  • a first pole of the first thin film transistor is connected to the first common electrode signal input end, a gate of the first thin film transistor is connected to the first control signal input end, and a second pole of the first thin film transistor is connected to the first signal output end;
  • the first pole of the second thin film transistor is connected to the first signal input end
  • the gate of the second thin film transistor is connected to the second control signal input end
  • the second pole of the second thin film transistor is connected to the first signal output end.
  • the pre-charging module is respectively connected to the start signal input end, the second signal input end, and the pull-up node, and is configured to charge the pull-up node by using the second signal input by the second signal input end ;
  • the pull-up module is respectively connected to the clock signal input end, the pull-up node and the gate signal output end, and is used for controlling the gate signal output end to output the gate drive signal;
  • the pull-down holding module is configured to pull down the potential of the pull-up node and the gate signal output end, and maintain the potential of the pull-up node and the gate signal output end in the next period.
  • the pre-charging module includes:
  • the third thin film transistor has a first pole connected to the second signal input terminal, a third thin film transistor connected to the start signal input terminal, and a second thin film transistor connected to the pull-up node.
  • the pull-up module includes:
  • the first pole of the fourth thin film transistor is connected to the clock signal input end, the gate of the fourth thin film transistor is respectively connected to the pull-up node, the first end of the storage capacitor, and the second pole of the fourth thin film transistor is respectively connected with the gate signal The output end and the second end of the storage capacitor are connected.
  • the pull-down holding module includes:
  • a first pole of the fifth thin film transistor is connected to the pull-up node, a gate of the fifth thin film transistor is connected to the reset signal input end, and a second pole of the fifth thin film transistor is connected to the third signal input end;
  • the first pole of the sixth thin film transistor is connected to the pull-up node, and the gate of the sixth thin film transistor is respectively Connected to the gate of the seventh thin film transistor, the first pole of the eighth thin film transistor, the second pole of the eleventh thin film transistor, and the second pole of the sixth thin film transistor is connected to the fourth signal input end;
  • a first pole of the seventh thin film transistor is connected to the gate signal output end, and a second pole of the seventh thin film transistor is connected to the fourth signal input end;
  • the gate of the eighth thin film transistor is connected to the pull-up node, and the second pole of the eighth thin film transistor is connected to the fourth signal input end;
  • the first pole of the ninth thin film transistor is respectively connected to the second pole of the tenth thin film transistor and the gate of the eleventh thin film transistor, the gate of the ninth thin film transistor is connected to the pull-up node, and the second pole of the ninth thin film transistor is connected Connected to the fourth signal input terminal;
  • a first pole and a gate of the tenth thin film transistor are connected to the first control signal input end;
  • the first pole of the eleventh thin film transistor is connected to the first control signal input terminal.
  • the reset module includes:
  • the first pole of the twelfth thin film transistor is connected to the gate signal output end, the gate of the twelfth thin film transistor is connected to the second control signal input end, and the second pole of the twelfth thin film transistor is connected to the fourth signal input end .
  • the thin film transistor is an N-type thin film transistor, a first source of the thin film transistor, and a second drain of the thin film transistor.
  • the second signal input terminal inputs a high level signal
  • the third signal input terminal inputs a low level signal
  • the second signal input terminal inputs a low level signal
  • the third signal input terminal inputs a high level signal.
  • the fourth signal is a low level signal.
  • the embodiment of the present disclosure further provides a shift register unit driving method, the shift register unit being disposed in an in-cell touch panel, the in-cell touch panel including a substrate having a common electrode;
  • the method includes:
  • the pre-charging module charges the pull-up node by using the second signal input by the second signal input terminal;
  • the pull-up module controls the gate signal output terminal to output a gate drive signal
  • the pull-down holding module discharges the pull-up node and the gate signal output terminal
  • the pull-down holding module maintains a potential of the pull-up node and the gate signal output terminal
  • the method further includes:
  • the first signal output control module controls the first signal output end to output the first common electrode signal input by the first common electrode signal input end;
  • the first signal output control module controls the first signal output end to output a first signal input by the first signal input end, where the first signal is input to the touch phase during the touch phase of the one frame time.
  • the first signal is a second common electrode signal
  • the potential value of the second common electrode signal is an average value of a potential value of the high potential touch driving signal and a potential value of the low potential touch driving signal.
  • the first signal is a touch driving signal.
  • the start signal input end inputs a high level signal
  • the clock signal input end and the reset signal input end input a low level signal
  • the gate signal output end outputs a low level signal
  • the clock signal input end inputs a high level signal
  • the start signal input end and the reset signal input end input a low level signal
  • the gate signal output end outputs a high level signal
  • the reset signal input end inputs a high level signal
  • the start signal input end and the clock signal input end input a low level signal
  • the gate signal output end outputs a low level signal
  • the clock signal input end inputs a high level signal
  • the start signal input end and the reset signal input end input a low level signal
  • the gate signal output end outputs a low level signal
  • the first control signal input terminal inputs a high level signal
  • the second control signal input terminal inputs a low level signal
  • the first control signal input terminal inputs a low level signal
  • the second control signal input terminal inputs a high level signal
  • the embodiment of the present disclosure further provides a gate driving circuit, which may specifically include a plurality of cascaded shift register units provided by the above embodiments of the present disclosure, wherein:
  • the start signal input end of each of the shift register units is connected to the signal output end of the adjacent one stage shift register unit;
  • the reset signal input terminals of each of the shift register units are connected to the signal output terminals of the adjacent stage shift register unit adjacent thereto.
  • the embodiment of the present disclosure further provides a display device, which may specifically include the gate driving circuit provided by the above embodiments of the present disclosure.
  • the shift register unit and the driving method thereof, the gate driving circuit and the display device provided in the present disclosure are provided with a pull-down node and a gate signal output terminal.
  • a potential pull-down holding module for resetting the potential of the output signal of the gate signal output terminal to the potential of the fourth signal during the touch phase of one frame time; for the display phase of one frame time, Controlling the first signal output end to output the first common electrode signal, and controlling the first signal output end to output the first signal output control signal of the first signal input end of the first signal input end during a touch period of one frame time
  • the first signal is a first signal output control module that inputs a signal to a common electrode connected to the shift register unit during the touch phase. Therefore, the signal received by the common electrode can be outputted by the shift register unit, so that it is not necessary to provide a driving chip for separately providing the common electrode signal in the display device, thereby simplifying the structure of the display device and reducing the cost of the display device.
  • FIG. 1 is a schematic structural diagram 1 of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a first signal output control module in a shift register unit according to an embodiment of the present disclosure
  • FIG. 3 is a timing diagram 1 of a signal provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram 2 of a shift register unit according to an embodiment of the present disclosure.
  • FIG. 5A is a schematic flowchart 1 of a method for driving a shift register unit according to an embodiment of the present disclosure
  • FIG. 5B is a schematic flowchart of a method for driving a shift register unit according to an embodiment of the present disclosure two;
  • FIG. 6 is a timing diagram 2 of a signal provided by an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a shift register unit that is disposed in an in-cell touch screen that includes a substrate having a common electrode.
  • the shift register unit may specifically include a first signal output control module 1 , a pre-charging module 2 , a pull-up module 3 , a pull-down holding module 4 , and a reset module 5 , where:
  • the pull-down holding module 4 is respectively connected with a first control signal (GCH) input terminal, a reset signal (RESET) input terminal, a third signal input terminal, a fourth signal input terminal, a pull-up node (PU), and a gate signal output terminal (
  • GCH first control signal
  • REET reset signal
  • the OUTPUT connection is used to pull down the potential of the pull-up node and the gate signal output end, and the pull-up node is the connection point of the pre-charging module 2 and the pull-up module 3;
  • the reset module 5 is respectively connected to the second control signal (GCL) input end, the gate signal output end, and the fourth signal input end, and is used for outputting the signal at the gate signal output end during the touch phase of one frame time.
  • the potential is reset to the potential of the fourth signal input by the fourth signal input terminal;
  • the first signal output control module 1 is respectively connected to the first control signal input end, the second control signal input end, the first common electrode signal (VcomL) input end, the first signal input end and the first signal output end, and is used for In a display phase of one frame time, controlling the first signal output end to output a first common electrode signal input by the first common electrode signal input end, and controlling the first signal output end output stage during the touch phase of the one frame time a first signal input by the first signal input terminal, wherein the first signal is a signal input to a common electrode connected to the shift register unit during the touch phase.
  • VcomL first common electrode signal
  • the shift register unit provided by the embodiment of the present disclosure can output a signal received by the common electrode, thereby eliminating the need to provide a driving chip separately providing the common electrode signal in the display device, simplifying the structure of the display device, and reducing the cost of the display device. .
  • the first signal output control module 1 and the pull-down holding module 4 multiplex the first control signal input end, and the first signal output control module 1 and the reset module 5 are complex.
  • the second control signal input terminal can reduce the number of signal input terminals required for the shift register unit, simplify the mechanism setting of the shift register unit, reduce the manufacturing process and cost of the shift register unit, and further reduce the display device. the cost of.
  • the first common electrode signal involved in the above embodiments of the present disclosure may specifically be a normal common electrode signal, that is, a low potential common electrode signal for providing a pixel-driven reference common electrode voltage, for example, -0.1V.
  • the first signal involved in the embodiment of the present disclosure may specifically be a second common electrode signal (VcomH), that is, a high potential common electrode signal, and the potential value of the second common electrode signal is a high potential touch driving signal (Tx_H).
  • VcomH second common electrode signal
  • Tx_L high potential touch driving signal
  • the shift register unit provided in the embodiment of the present disclosure
  • the technical solution reduces the potential difference between the common electrode signal and the touch driving signal, thereby reducing or even avoiding the public
  • the possibility of coupling capacitance between the common electrode and the touch driving electrode is avoided to avoid the display effect of the touch screen during the touch phase due to the charging of the pixel unit during the touch phase, and the display effect of the display device during the touch phase is ensured.
  • the shift register unit provided by the embodiment of the present disclosure may also be applied to a touch screen product in which a common electrode and a touch driving electrode are multiplexed.
  • the common electrode according to the embodiment of the present disclosure is multiplexed with the touch driving electrode, and specifically refers to a common electrode disposed in a touch screen, and receives a common electrode signal in a display phase of one frame time, so that the common electrode is provided for implementation.
  • the pixel is normally displayed to drive the reference common electrode voltage, that is, the first common electrode signal having a potential of 0.1 V according to the embodiment of the present disclosure, and the common electrode receives the touch driving signal (TX) during the touch phase of one frame time.
  • the first signal input by the first signal input end is a touch driving signal, so that the common electrode exists as a touch driving electrode, and interacts with the touch sensing electrode disposed at the intersection of the space to realize the touch detection. Test function.
  • the shift register unit provided by the embodiment of the present disclosure adopts a time-division driving manner in the touch and display stages
  • the display driving including the generation of the common electrode signal and the gate driving signal
  • the touch driving can be performed on the one hand (
  • the chip of the touch driving signal is integrated to reduce the production cost of the display device; on the other hand, the time-division driving can also reduce mutual interference between the display driving and the touch detection, and improve the picture quality and the touch accuracy.
  • the first signal output control module 1 in the embodiment of the present disclosure may specifically include:
  • the first pole of the first thin film transistor T1 is connected to the first common electrode signal input end, the gate of the first thin film transistor T1 is connected to the first control signal input end, and the second pole of the first thin film transistor T1 and the first signal output End connection
  • the first pole of the second thin film transistor T2 is connected to the first signal input end, the gate of the second thin film transistor T2 is connected to the second control signal input end, and the second pole of the second thin film transistor T2 is connected to the first signal output end. .
  • the shift register unit driving method provided by the embodiment of the present disclosure may output the first signal based on the signal timing diagram as shown in FIG.
  • the control module 1 performs control.
  • the first control signal input terminal inputs a high level signal
  • the second control signal input terminal inputs a low level signal, so that the first thin film transistor T1 is in an on state, and the second thin film transistor T2 is in an off state.
  • the signal outputted by the signal output terminal is a first common electrode signal input by the first common electrode signal input end, and the first common electrode signal can be used to implement normal display of the pixel unit;
  • the first control signal input terminal inputs a low level signal
  • the second control signal input terminal inputs a high level signal, so that the first thin film transistor T1 is in an off state, and the second thin film transistor T2 is in an on state.
  • the signal outputted by the first signal output terminal is a first signal input by the first signal input end, and the first signal may be a second common electrode signal having a potential value of (Tx_H+Tx_L)/2, or may be a touch drive. signal.
  • the pre-charging module 2 may be specifically connected to an input signal (INPUT) input terminal, a second signal input terminal, and a pull-up node, respectively, for using the second signal input.
  • the second signal input to the terminal is charging the pull-up node.
  • the pull-up module 3 may be specifically connected to a clock signal (CLK) input terminal, a pull-up node, and a gate signal output terminal, respectively, for controlling a gate signal output end.
  • CLK clock signal
  • the pull-down holding module 4 in addition to pulling down the potential of the pull-up node and the gate signal output terminal, is also used to maintain the potential of the pull-up node and the gate signal output terminal in the next period.
  • the pre-charging module 2 involved in the embodiment of the present disclosure may specifically include:
  • the third thin film transistor T3, the first electrode of the third thin film transistor T3 is connected to the second signal input end, the gate of the third thin film transistor T3 is connected to the start signal input end, and the second electrode of the third thin film transistor T3 is connected to the top Pull the node to connect.
  • the pull-up module 3 involved in the embodiment of the present disclosure may specifically include:
  • the first electrode of the fourth thin film transistor T4 is connected to the clock signal input end, the gate of the fourth thin film transistor T4 is connected to the pull-up node, the first end of the storage capacitor C1, and the fourth thin film transistor T4
  • the two poles are respectively connected to the gate signal output end and the second end of the storage capacitor C1.
  • the pull-down holding module 4 involved in the embodiment of the present disclosure may specifically include:
  • a fifth thin film transistor T5 a sixth thin film transistor T6, a seventh thin film transistor T7, an eighth thin film transistor T8, a ninth thin film transistor T9, a tenth thin film transistor T10, and an eleventh thin film transistor T11;
  • the first pole of the fifth thin film transistor T5 is connected to the pull-up node, the gate of the fifth thin film transistor T5 is connected to the reset signal input end, and the second pole of the fifth thin film transistor T5 is connected to the third signal input end;
  • the first electrode of the sixth thin film transistor T6 is connected to the pull-up node, the gate of the sixth thin film transistor T6 is respectively connected to the gate of the seventh thin film transistor T7, the first electrode of the eighth thin film transistor 8, and the eleventh thin film transistor T11. a second pole connection, the second pole of the sixth thin film transistor T6 is connected to the fourth signal input end;
  • a first pole of the seventh thin film transistor T7 is connected to the gate signal output end, and a second pole of the seventh thin film transistor T7 is connected to the fourth signal input end;
  • the gate of the eighth thin film transistor T8 is connected to the pull-up node, and the second pole of the eighth thin film transistor T8 is connected to the fourth signal input end;
  • the first pole of the ninth thin film transistor T9 is respectively connected to the second electrode of the tenth thin film transistor T10 and the gate of the eleventh thin film transistor T11, and the gate of the ninth thin film transistor T9 is connected to the pull-up node, and the ninth thin film transistor is connected.
  • the second pole of T9 is connected to the fourth signal input end;
  • a first pole and a gate of the tenth thin film transistor T10 are connected to the first control signal input end;
  • the first pole of the eleventh thin film transistor T11 is connected to the first control signal input terminal.
  • the reset module 5 may specifically include: a twelfth thin film transistor T12. among them,
  • the first pole of the twelfth thin film transistor T12 is connected to the gate signal output end, the gate of the twelfth thin film transistor T12 is connected to the second control signal input end, and the second and fourth signals of the twelfth thin film transistor T12 are connected.
  • the input is connected.
  • the thin film transistor according to the embodiment of the present disclosure may be an N-type thin film transistor.
  • the first electrode of the thin film transistor may be a source, and the second electrode of the thin film transistor may be a drain.
  • the second signal input end is specifically configured to input a high level signal, such as a DC high level signal VDD
  • the third signal input end is specifically configured to input a low level signal, such as a DC low level signal.
  • VSS thereby implementing a forward scan of the touch screen, such as a touch screen up and down.
  • the second signal input terminal can also be used to input a low level signal
  • the third signal input end can also be used to input a high level signal, thereby implementing a reverse of the touch screen, such as a touch screen to the bottom. Scan drive on.
  • the fourth signal involved in the embodiment of the present disclosure is a low level signal, such as VGL, that is, a low level signal input terminal at which the fourth signal input terminal is a fixed potential.
  • the gate signal output terminal outputs The signal is the fourth signal input by the fourth signal end. Since the fourth signal can be a low level signal of a fixed potential, the gate signal output terminal outputs a low level signal during the touch phase, thereby avoiding pixels.
  • the charging and illuminating of the unit during the touch phase affects the display effect of the touch screen during the touch phase, further ensuring the display effect of the display device during the touch phase.
  • the method may further include:
  • the pre-charging module 2 uses the second signal input by the second signal input terminal to charge the pull-up node;
  • the pull-up module 3 controls the gate signal output terminal to output a gate driving signal
  • the pull-down holding module 4 discharges the pull-up node and the gate signal output terminal;
  • the pull-down holding module 4 maintains the potential of the pull-up node and the gate signal output.
  • the method may further include:
  • the first signal output control module controls the first signal output end to output the first common electrode signal input by the first common electrode signal input end;
  • the first signal output control module controls the first signal output during the touch phase of the one frame time
  • the terminal outputs a first signal input by the first signal input end, and the first signal is a signal input to a common electrode connected to the shift register unit during a touch phase.
  • the first signal input end is the second common electrode signal input end, that is, the first signal is the second common electrode signal, and the second common electrode signal in FIG. 6 is the high potential common electrode signal.
  • the second signal input terminal inputs a high level signal
  • the third signal input terminal inputs a low level signal.
  • the start signal input terminal inputs a high level signal
  • the reset signal input terminal inputs a low level signal
  • the clock signal input terminal inputs a low level signal.
  • the second signal input to the second signal input terminal for example, a DC high level signal VDD, is Pull the node, that is, the storage capacitor C1 is charged.
  • the pull-up node controls the fourth thin film transistor T4 to be in an on state, but the clock signal input terminal inputs a low level signal, so that the signal outputted by the gate signal output terminal in the first period is input to the clock signal input end. Low level signal.
  • the twelfth thin film transistor T12 Since the second control signal input terminal is always in a low potential state during the display phase, the twelfth thin film transistor T12 is always in an off state during the display phase.
  • the reset signal input terminal inputs a low level signal, thereby causing the fifth thin film transistor T5 to be in an off state.
  • the clock signal input terminal inputs a high level signal
  • the start signal input terminal and the reset signal input terminal input a low level signal
  • the third thin film transistor T3 Since the start signal input terminal inputs a low level signal, the third thin film transistor T3 is turned off.
  • the pull-up node is still at a high level, and the clock signal input terminal inputs a high-level signal. Due to the bootstrap effect of the storage capacitor, the fourth thin film transistor T4 continues to be in an on state, then the gate signal output terminal at this period
  • the output signal is a high level clock signal, that is, a gate drive signal, so that the corresponding gate line is turned on.
  • the start signal input terminal and the clock signal input terminal input a low level signal
  • the reset signal input terminal inputs a high level signal
  • the third thin film transistor T3, the fourth thin film transistor T4, the eighth thin film transistor T8, and the ninth thin film transistor T9 are in an off state, and the fifth to seventh thin film transistors are in an on state, thereby utilizing the third signal input terminal.
  • the input third signal and the fourth signal input to the fourth signal input discharge the pull-up node and the gate signal output terminal, so that the gate signal output terminal outputs a low-level signal.
  • the clock signal input terminal inputs a high level signal
  • the start signal input terminal and the reset signal input terminal input a low level signal
  • the third thin film transistor T3, the fourth thin film transistor T4, and the fifth thin film transistor T5 are in an off state, and the sixth thin film transistor T6, the seventh thin film transistor T7, the tenth thin film transistor T10, and the eleventh thin film transistor T1. It is in an on state, so that the potentials of the pull-up node and the gate signal output remain unchanged.
  • the gate signal output end is output during the touch phase.
  • the signal is the fourth signal input to the fourth signal terminal, that is, the low level signal. In the touch phase, there is no signal input at the start signal input end, the reset signal input end, and the clock signal input end.
  • the shift register unit provided in the embodiment of the present disclosure can be realized not only
  • the function of the gate signal output and the signal shift register can also control the common electrode signal to have different potential values in the display phase and the touch phase, thereby ensuring the display effect of the touch screen in the touch phase.
  • the embodiment of the present disclosure may further provide a gate driving circuit.
  • the start signal input end of each of the shift register units is connected to the signal output end of the adjacent one stage shift register unit;
  • the reset signal input terminals of each of the shift register units are connected to the signal output terminals of the adjacent stage shift register unit adjacent thereto.
  • the gate driving circuit provided by the embodiment of the present disclosure includes a plurality of cascaded shift register units, and several of the shift register units may be set as required by the embodiments of the present disclosure as needed.
  • the bit register unit, the other shift register unit can be the same as in the prior art, for example, by the touch driving electrodes corresponding to the plurality of rows of gate lines, only one shift register unit can be set in the embodiment of the present disclosure. Shift register unit.
  • the embodiment of the present disclosure may further provide a display device, which may specifically include the gate driving circuit provided by the above embodiments of the present disclosure.
  • the display device may specifically be a display device such as a liquid crystal panel, a liquid crystal television, a liquid crystal display, an OLED (Organic Light Emitting Diode) panel, an OLED display, a plasma display, or an electronic paper.
  • a display device such as a liquid crystal panel, a liquid crystal television, a liquid crystal display, an OLED (Organic Light Emitting Diode) panel, an OLED display, a plasma display, or an electronic paper.
  • the shift register unit, the gate driving circuit and the display device provided by the embodiments of the present disclosure are particularly suitable for the GOA circuit requirements under the LTPS (Low Temperature Polysilicon Technology) process, and are also applicable to the GOA circuit under the amorphous silicon process.
  • LTPS Low Temperature Polysilicon Technology
  • the shift register unit provided by the embodiments of the present disclosure can be applied to a thin film transistor of a process of amorphous silicon, polysilicon, oxide, etc., and it should be noted that although the above embodiment uses a single N-type thin film transistor as an example. Illustrated, however, the above circuit can be easily modified to use a single P-type thin film transistor or CMOS (Complementary Metal Oxide Semiconductor) tube circuit.
  • CMOS Complementary Metal Oxide Semiconductor
  • the pull-down holding module is configured to reset the potential of the output signal of the gate signal output end to the resetting module of the potential of the fourth signal during the touch phase of one frame time; for the display phase of one frame time, the control part a signal output end outputs a first common electrode signal, and a first signal output control module that controls the first signal output end to output the first signal input by the first signal input end during a touch period of one frame time,
  • the first signal is a first signal output control module that inputs a signal to a common electrode connected to the shift register unit during the touch phase.
  • the structure setting of the shift register unit provided by the embodiment of the present disclosure can also reduce the manufacturing process and cost of the shift register unit, ensure the display effect of the display device in the display stage and the touch stage, and realize the screen display and touch.
  • the perfect combination of control detection can also reduce the manufacturing process and cost of the shift register unit, ensure the display effect of the display device in the display stage and the touch stage, and realize the screen display and touch. The perfect combination of control detection.

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Abstract

本公开文本提供一种移位寄存器单元及其驱动方法、栅极驱动电路、显示装置。该移位寄存器单元中设置有用于拉低上拉节点以及栅极信号输出端的电位的下拉保持模块，用于在一帧时间的触控阶段，将栅极信号输出端输出信号的电位重置为第四信号的电位的重置模块；用于在一帧时间的显示阶段，控制第一信号输出端输出第一公共电极信号，以及在一帧时间的触控阶段，控制第一信号输出端输出所述第一信号输入端输入的第一信号的第一信号输出控制模块，所述第一信号为在所述触控阶段输入到与所述移位寄存器单元连接的公共电极的信号的第一信号输出控制模块。

Description

移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
相关申请的交叉引用
本申请主张在2014年8月28日在中国提交的中国专利申请号No.201410433475.X的优先权，其全部内容通过引用包含于此。
技术领域
本公开文本涉及显示技术领域，具体可以涉及一种移位寄存器单元及其驱动方法、栅极驱动电路、显示装置。
背景技术
随着人们的生活水平的日益提高，对显示产品的要求也越来越高，例如显示质量以及薄型化等。
目前大多数显示产品普遍采用一体化触控式(OGS)或者外挂式(on Cell Touch)触摸屏，但是，上述这些触摸屏均不利于显示产品的薄型化，因此，采用更有利于显示产品薄型化的内置式(In Cell Touch)触摸屏，成为显示产品发展趋势。
在目前采用内置式触摸屏的显示产品中，出现了一种触控驱动信号为交流信号的触控侦测技术，即在一时间周期的触控阶段，触控驱动电极交替传输高电位触控驱动信号(Tx_H)和低电位触控驱动信号(Tx_L)，以实现触摸屏的触控侦测功能。
通常公共电极信号的电位为0.1V左右，而触控驱动信号的电位在0V-10V之间，这样就导致公共电极信号与触控驱动信号之间可能出现较大的电压差，致使公共电极与触控驱动电极之间出现耦合电容，从而使个别像素单元出现显示发光的情况下，影响了触摸屏在触控阶段的显示效果。
目前，现有的公共电极信号由单独设置的驱动芯片(Drive IC)提供，而现有的驱动芯片(Drive IC)无法实现对公共电极信号在不同阶段处于不同的幅值的控制，所以对触控驱动信号的幅值有了比较大的限制，影响了触控屏的显示效果。
发明内容
本公开文本提供一种移位寄存器单元及其驱动方法、栅极驱动电路、显示装置，可由移位寄存器单元输出公共电极接收的信号，从而可无需在显示装置中单独设置提供公共电极信号的驱动芯片，简化了显示装置的结构，降低了显示装置的成本。
本公开文本提供方案如下：
本公开文本实施例提供了一种移位寄存器单元，该移位寄存器单元设置于内嵌式触摸屏中，所述内嵌式触摸屏包括具有公共电极的基板；所述移位寄存器单元包括预充电模块、上拉模块、下拉保持模块、重置模块以及第一信号输出控制模块，其中：
下拉保持模块，分别与第一控制信号输入端、复位信号输入端、第三信号输入端、第四信号输入端、上拉节点、栅极信号输出端连接，用于拉低上拉节点以及栅极信号输出端的电位，所述上拉节点为所述预充电模块与所述上拉模块的连接点；
重置模块，分别与第二控制信号输入端、栅极信号输出端、第四信号输入端连接，用于在一帧时间的触控阶段，将所述栅极信号输出端输出信号的电位重置为第四信号输入端输入的第四信号的电位；
第一信号输出控制模块，分别与第一控制信号输入端、第二控制信号输入端、第一公共电极信号输入端、第一信号输入端以及第一信号输出端连接，用于在一帧时间的显示阶段，控制第一信号输出端输出所述第一公共电极信号输入端输入的第一公共电极信号，以及在一帧时间的触控阶段，控制第一信号输出端输出所述第一信号输入端输入的第一信号，所述第一信号为在所述触控阶段输入到与所述移位寄存器单元连接的公共电极的信号。
可选的，所述第一信号为第二公共电极信号，所述第二公共电极信号的电位值为高电位触控驱动信号的电位值与低电位触控驱动信号的电位值的均值。
可选的，当所述公共电极与触摸屏中的触摸驱动电极复用时，所述第一信号为触控驱动信号。
可选的，所述第一信号输出控制模块包括第一薄膜晶体管和第二薄膜晶 体管，其中：
第一薄膜晶体管的第一极与第一公共电极信号输入端连接，第一薄膜晶体管的栅极与第一控制信号输入端连接，第一薄膜晶体管的第二极与第一信号输出端连接；
第二薄膜晶体管的第一极与第一信号输入端连接，第二薄膜晶体管的栅极与第二控制信号输入端连接，第二薄膜晶体管的第二极与第一信号输出端连接。
可选的，所述预充电模块分别与起始信号输入端、第二信号输入端、上拉节点连接，用于利用所述第二信号输入端输入的第二信号为所述上拉节点充电；
上拉模块，分别与时钟信号输入端、上拉节点、栅极信号输出端连接，用于控制栅极信号输出端输出栅极驱动信号；
所述下拉保持模块，用于拉低上拉节点以及栅极信号输出端的电位，并在下一时段，保持上拉节点以及栅极信号输出端的电位。
可选的，所述预充电模块包括：
第三薄膜晶体管，第三薄膜晶体管的第一极与第二信号输入端连接，第三薄膜晶体管的栅极与起始信号输入端连接，第三薄膜晶体管的第二极与上拉节点连接。
可选的，所述上拉模块包括：
第四薄膜晶体管和存储电容；
第四薄膜晶体管的第一极与时钟信号输入端连接，第四薄膜晶体管的栅极分别与上拉节点、存储电容的第一端连接，第四薄膜晶体管的第二极，分别与栅极信号输出端、存储电容的第二端连接。
可选的，所述下拉保持模块包括：
第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管；其中：
第五薄膜晶体管的第一极与上拉节点连接，第五薄膜晶体管的栅极与复位信号输入端连接，第五薄膜晶体管的第二极与第三信号输入端连接；
第六薄膜晶体管的第一极与上拉节点连接，第六薄膜晶体管的栅极分别 与第七薄膜晶体管的栅极、第八薄膜晶体管的第一极、第十一薄膜晶体管的第二极连接，第六薄膜晶体管的第二极与第四信号输入端连接；
第七薄膜晶体管的第一极与栅极信号输出端连接，第七薄膜晶体管的第二极与第四信号输入端连接；
第八薄膜晶体管的栅极与上拉节点连接，第八薄膜晶体管的第二极与第四信号输入端连接；
第九薄膜晶体管的第一极分别与第十薄膜晶体管的第二极、第十一薄膜晶体管的栅极连接，第九薄膜晶体管的栅极与上拉节点连接，第九薄膜晶体管的第二极与第四信号输入端连接；
第十薄膜晶体管的第一极和栅极，与第一控制信号输入端连接；
第十一薄膜晶体管的第一极与第一控制信号输入端连接。
可选的，所述重置模块包括：
第十二薄膜晶体管；
第十二薄膜晶体管的第一极与栅极信号输出端连接，第十二薄膜晶体管的栅极与第二控制信号输入端连接，第十二薄膜晶体管的第二极与第四信号输入端连接。
可选的，所述薄膜晶体管为N型薄膜晶体管，所述薄膜晶体管的第一极为源极，所述薄膜晶体管的第二极为漏极。
可选的，所述第二信号输入端输入高电平信号，所述第三信号输入端输入低电平信号；或者
所述第二信号输入端输入低电平信号，所述第三信号输入端输入高电平信号。
可选的，所述第四信号为低电平信号。
本公开文本实施例还提供了一种移位寄存器单元驱动方法，所述移位寄存器单元设置于内嵌式触摸屏中，所述内嵌式触摸屏包括具有公共电极的基板；
所述方法包括：
在一帧时间的显示阶段的第一时段，预充电模块利用第二信号输入端输入的第二信号为上拉节点充电；
在所述显示阶段的第二时段，上拉模块控制栅极信号输出端输出栅极驱动信号；
在所述显示阶段的第三时段，下拉保持模块为所述上拉节点和栅极信号输出端放电；
在所述显示阶段的第四时段，下拉保持模块保持上拉节点和栅极信号输出端的电位；
所述方法还包括：
在所述一帧时间的显示阶段，第一信号输出控制模块控制第一信号输出端输出第一公共电极信号输入端输入的第一公共电极信号；
在所述一帧时间的触控阶段，第一信号输出控制模块控制第一信号输出端输出第一信号输入端输入的第一信号，所述第一信号为在所述触控阶段输入到与所述移位寄存器单元连接的公共电极的信号。
可选的，所述第一信号为第二公共电极信号，所述第二公共电极信号的电位值为高电位触控驱动信号的电位值与低电位触控驱动信号的电位值的均值。
可选的，当部分所述公共电极与触摸屏中的触摸驱动电极复用时，所述第一信号为触控驱动信号。
可选的，在所述第一时段，起始信号输入端输入高电平信号，时钟信号输入端和复位信号输入端输入低电平信号，栅极信号输出端输出低电平信号；
在所述第二时段，时钟信号输入端输入高电平信号，起始信号输入端和复位信号输入端输入低电平信号，栅极信号输出端输出高电平信号；
在所述第三时段，复位信号输入端输入高电平信号，起始信号输入端和时钟信号输入端输入低电平信号，栅极信号输出端输出低电平信号；
在所述第四时段，时钟信号输入端输入高电平信号，起始信号输入端和复位信号输入端输入低电平信号，栅极信号输出端输出低电平信号；
在显示阶段，第一控制信号输入端输入高电平信号，第二控制信号输入端输入低电平信号；
在触控阶段，第一控制信号输入端输入低电平信号，第二控制信号输入端输入高电平信号。
本公开文本实施例还提供了一种栅极驱动电路，该栅极驱动电路中具体可以包括多个级联的、上述本公开文本实施例提供的移位寄存器单元，其中：
除第一级移位寄存器单元外，其余每个移位寄存器单元的起始信号输入端连接于其相邻的上一级移位寄存器单元的本级信号输出端；
除最后一级移位寄存器单元外，其余每个移位寄存器单元的复位信号输入端与其相邻的下一级移位寄存器单元的本级信号输出端相连接。
本公开文本实施例还提供了一种显示装置，该显示装置具体可以包括上述本公开文本实施例提供的栅极驱动电路。
从以上所述可以看出，本公开文本提供的移位寄存器单元及其驱动方法、栅极驱动电路、显示装置，该移位寄存器单元中设置有用于拉低上拉节点以及栅极信号输出端的电位的下拉保持模块，用于在一帧时间的触控阶段，将栅极信号输出端输出信号的电位重置为第四信号的电位的重置模块；用于在一帧时间的显示阶段，控制第一信号输出端输出第一公共电极信号，以及在一帧时间的触控阶段，控制第一信号输出端输出所述第一信号输入端输入的第一信号的第一信号输出控制模块，所述第一信号为在所述触控阶段输入到与所述移位寄存器单元连接的公共电极的信号的第一信号输出控制模块。从而可由移位寄存器单元输出公共电极接收的信号，使显示装置中无需设置单独提供公共电极信号的驱动芯片，进而简化了显示装置的结构，降低了显示装置的成本。
附图说明
图1为本公开文本实施例提供的移位寄存器单元结构示意图一；
图2为本公开文本实施例提供的移位寄存器单元中第一信号输出控制模块结构示意图；
图3为本公开文本实施例提供的信号时序图一；
图4为本公开文本实施例提供的移位寄存器单元结构示意图二；
图5A为本公开文本实施例提供的移位寄存器单元驱动方法流程示意图一；
图5B为本公开文本实施例提供的移位寄存器单元驱动方法流程示意图 二；
图6为本公开文本实施例提供的信号时序图二。
具体实施方式
为使本公开文本实施例的目的、技术方案和优点更加清楚，下面将结合本公开文本实施例的附图，对本公开文本实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开文本的一部分实施例，而不是全部的实施例。基于所描述的本公开文本的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开文本保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开文本所属领域内具有一般技能的人士所理解的通常意义。本公开文本专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
本公开文本实施例提供了一种移位寄存器单元，该移位寄存器单元设置于内嵌式触摸屏中，所述内嵌式触摸屏包括具有公共电极的基板。
如图1所示，该移位寄存器单元具体可以包括第一信号输出控制模块1、预充电模块2、上拉模块3、下拉保持模块4以及重置模块5，其中：
下拉保持模块4，分别与第一控制信号(GCH)输入端、复位信号(RESET)输入端、第三信号输入端、第四信号输入端、上拉节点(PU)、栅极信号输出端(OUTPUT)连接，用于拉低上拉节点以及栅极信号输出端的电位，上拉节点为预充电模块2与上拉模块3的连接点；
重置模块5，分别与第二控制信号(GCL)输入端、栅极信号输出端、第四信号输入端连接，用于在一帧时间的触控阶段，将栅极信号输出端输出信号的电位重置为第四信号输入端输入的第四信号的电位；
第一信号输出控制模块1，分别与第一控制信号输入端、第二控制信号输入端、第一公共电极信号(VcomL)输入端、第一信号输入端以及第一信号输出端连接，用于在一帧时间的显示阶段，控制第一信号输出端输出第一公共电极信号输入端输入的第一公共电极信号，以及在所述一帧时间的触控阶段，控制第一信号输出端输出所述第一信号输入端输入的第一信号，所述第一信号为在所述触控阶段输入到与所述移位寄存器单元连接的公共电极的信号。
本公开文本实施例所提供的移位寄存器单元，可输出公共电极接收的信号，从而使显示装置中无需设置单独提供公共电极信号的驱动芯片，简化了显示装置的结构，降低了显示装置的成本。
而且，本公开文本实施例所提供的移位寄存器单元中，第一信号输出控制模块1与下拉保持模块4复用第一控制信号输入端，第一信号输出控制模块1与重置模块5复用第二控制信号输入端，从而可减少移位寄存器单元所需设置信号输入端的数量，简化了移位寄存器单元的机构设置，降低了移位寄存器单元的制作工艺和成本，进一步降低了显示装置的成本。
上述本公开文本实施例所涉及的第一公共电极信号具体可为正常的公共电极信号，即低电位公共电极信号以用于提供像素驱动的基准公共电极电压，例如-0.1V。
本公开文本实施例所涉及的第一信号，具体可为第二公共电极信号(VcomH)，即高电位公共电极信号，且该第二公共电极信号的电位值为高电位触控驱动信号(Tx_H)的电位值与低电位触控驱动信号(Tx_L)的电位值的均值，即VcomH＝(Tx_H+Tx_L)/2。
以低电位触控驱动信号电位为1伏(V)，高电位触控驱动信号的电位为9V为例，那么，在触控阶段，本公开文本实施例所提供的移位寄存器单元中的第一信号输出端输出的第二公共电极信号的电位值即可为(1V+9V)/2＝5V，从而使第二公共电极信号相较于低电位触控驱动信号和高电位触控驱动信号均具有4V的电位差，那么相较于第一公共电极信号(0.1V)与高电位触控驱动信号(9V)的电压差(9V-0.1V＝8.9V)，本公开文本实施例提供的技术方案缩小了公共电极信号与触控驱动信号之间的电位差，从而可降低甚至避免公 共电极与触控驱动电极之间产生耦合电容的可能性，以避免由于像素单元在触控阶段充电发光而影响触控阶段触摸屏的显示效果，确保显示装置在触控阶段的显示效果。
在本公开文本一具体实施例中，本公开文本实施例所提供的移位寄存器单元还可适用于公共电极与触控驱动电极复用的触摸屏产品中。
本公开文本实施例所涉及的公共电极与触控驱动电极复用，具体可指一触摸屏中所设置的公共电极，在一帧时间的显示阶段接收公共电极信号，以使公共电极提供用于实现像素正常显示驱动的基准公共电极电压，即本公开文本实施例所涉及的具有0.1V电位的第一公共电极信号，而该公共电极在一帧时间的触控阶段接收触控驱动信号(TX)，即第一信号输入端输入的第一信号为触控驱动信号，以使该公共电极作为触控驱动电极存在，并通过与隔空相交设置的触控感应电极相互作用，以实现触控侦测功能。
由于本公开文本实施例提供的移位寄存器单元，在触控和显示阶段采用分时驱动的方式，一方面可以将显示驱动(包括公共电极信号以及栅极驱动信号的生成)和触控驱动(触控驱动信号的生成)的芯片整合为一体，降低显示装置的生产成本；另一方面，分时驱动也能够降低显示驱动和触控侦测的相互干扰，提高画面品质和触控准确性。
在一具体实施例中，如附图2所示，本公开文本实施例所涉及的第一信号输出控制模块1内具体可以包括：
第一薄膜晶体管T1和第二薄膜晶体管T2，其中：
第一薄膜晶体管T1的第一极与第一公共电极信号输入端连接，第一薄膜晶体管T1的栅极与第一控制信号输入端连接，第一薄膜晶体管T1的第二极与第一信号输出端连接；
第二薄膜晶体管T2的第一极与第一信号输入端连接，第二薄膜晶体管T2的栅极与第二控制信号输入端连接，第二薄膜晶体管T2的第二极与第一信号输出端连接。
那么，针对如图2所示的第一信号输出控制模块1电路结构，本公开文本实施例所提供的移位寄存器单元驱动方法可基于如图3所示的信号时序图，对第一信号输出控制模块1进行控制。
具体的：
在显示阶段，第一控制信号输入端输入高电平信号，第二控制信号输入端输入低电平信号，从而使第一薄膜晶体管T1处于导通状态，第二薄膜晶体管T2处于截止状态，第一信号输出端输出的信号为第一公共电极信号输入端输入的第一公共电极信号，该第一公共电极信号可用于实现像素单元正常显不；
在触控阶段，第一控制信号输入端输入低电平信号，第二控制信号输入端输入高电平信号，从而使第一薄膜晶体管T1处于截止状态，第二薄膜晶体管T2处于导通状态，第一信号输出端输出的信号为第一信号输入端输入的第一信号，该第一信号具体可为具有(Tx_H+Tx_L)/2电位值的第二公共电极信号，也可以为触控驱动信号。
如图1所示，本公开文本实施例所涉及的预充电模块2，具体可分别与起始信号(INPUT)输入端、第二信号输入端、上拉节点连接，用于利用第二信号输入端输入的第二信号为上拉节点充电。
如图1所示，本公开文本实施例所涉及的上拉模块3，具体可分别与时钟信号(CLK)输入端、上拉节点、栅极信号输出端连接，用于控制栅极信号输出端输出栅极驱动信号。
另外，本公开文本实施例所涉及的下拉保持模块4，除用于拉低上拉节点以及栅极信号输出端的电位，还用于在下一时段，保持上拉节点以及栅极信号输出端的电位。
如图4所示，本公开文本实施例所涉及的预充电模块2具体可以包括：
第三薄膜晶体管T3，第三薄膜晶体管T3的第一极与第二信号输入端连接，第三薄膜晶体管T3的栅极与起始信号输入端连接，第三薄膜晶体管T3的第二极与上拉节点连接。
如图4所示，本公开文本实施例所涉及的上拉模块3具体可以包括：
第四薄膜晶体管T4和存储电容C1。
其中：
第四薄膜晶体管T4的第一极与时钟信号输入端连接，第四薄膜晶体管T4的栅极与上拉节点、存储电容C1的第一端连接，第四薄膜晶体管T4的第 二极，分别与栅极信号输出端、存储电容C1的第二端连接。
如图4所示，本公开文本实施例所涉及的下拉保持模块4具体可以包括：
第五薄膜晶体管T5、第六薄膜晶体管T6、第七薄膜晶体管T7、第八薄膜晶体管T8、第九薄膜晶体管T9、第十薄膜晶体管T10、第十一薄膜晶体管T11；其中：
第五薄膜晶体管T5的第一极与上拉节点连接，第五薄膜晶体管T5的栅极与复位信号输入端连接，第五薄膜晶体管T5的第二极与第三信号输入端连接；
第六薄膜晶体管T6的第一极与上拉节点连接，第六薄膜晶体管T6的栅极分别与第七薄膜晶体管T7的栅极、第八薄膜晶体管8的第一极、第十一薄膜晶体管T11的第二极连接，第六薄膜晶体管T6的第二极与第四信号输入端连接；
第七薄膜晶体管T7的第一极与栅极信号输出端连接，第七薄膜晶体管T7的第二极与第四信号输入端连接；
第八薄膜晶体管T8的栅极与上拉节点连接，第八薄膜晶体管T8的第二极与第四信号输入端连接；
第九薄膜晶体管T9的第一极分别与第十薄膜晶体管T10的第二极、第十一薄膜晶体管T11的栅极连接，第九薄膜晶体管T9的栅极与上拉节点连接，第九薄膜晶体管T9的第二极与第四信号输入端连接；
第十薄膜晶体管T10的第一极和栅极，与第一控制信号输入端连接；
第十一薄膜晶体管T11的第一极与第一控制信号输入端连接。
如图4所示，本公开文本实施例所涉及的重置模块5具体可以包括：第十二薄膜晶体管T12。其中，
第十二薄膜晶体管T12的第一极与栅极信号输出端连接，第十二薄膜晶体管T12的栅极与第二控制信号输入端连接，第十二薄膜晶体管T12的第二极与第四信号输入端连接。
上述本公开文本实施例所涉及的薄膜晶体管具体可为N型薄膜晶体管，那么，薄膜晶体管的第一极具体可为源极，薄膜晶体管的第二极具体可为漏极。
本公开文本实施例中，第二信号输入端具体可用于输入高电平信号，例如直流高电平信号VDD，而第三信号输入端具体可用于输入低电平信号，例如直流低电平信号VSS，从而实现触摸屏的正向例如触摸屏至上而下的扫描驱动。
而在另一具体实施例中，第二信号输入端还可以用于输入低电平信号，而第三信号输入端还可用于输入高电平信号，从而实现触摸屏的反向例如触摸屏至下而上的扫描驱动。
本公开文本实施例所涉及的第四信号为低电平信号，例如VGL，即第四信号输入端为固定电位的低电平信号输入端。
如图3所示，由于在触控阶段，第二控制信号输入端可输入高电平信号，从而使第十二薄膜晶体管T12即重置模块5处于导通状态，那么栅极信号输出端输出的信号为第四信号端输入的第四信号，由于第四信号具体可为固定电位的低电平信号，因此，在触控阶段，栅极信号输出端输出低电平信号，从而可避免像素单元在触控阶段充电发光而影响触控阶段触摸屏的显示效果，进一步确保了显示装置在触控阶段的显示效果。
那么，对应于对如图4所示的移位寄存器单元，本公开文本实施例所提供的移位寄存器单元驱动方法中，如图5A所示，具体还可以包括：
在一帧时间的显示阶段的第一时段，预充电模块2利用第二信号输入端输入的第二信号为上拉节点充电；
在显示阶段的第二时段，上拉模块3控制栅极信号输出端输出栅极驱动信号；
在显示阶段的第三时段，下拉保持模块4为上拉节点和栅极信号输出端放电；
在显示阶段的第四时段，下拉保持模块4保持上拉节点和栅极信号输出端的电位。
如图5B所示，该方法具体还可以包括：
在所述一帧时间的显示阶段，第一信号输出控制模块控制第一信号输出端输出第一公共电极信号输入端输入的第一公共电极信号；
在所述一帧时间的触控阶段，第一信号输出控制模块控制第一信号输出 端输出第一信号输入端输入的第一信号，所述第一信号为在触控阶段输入到与所述移位寄存器单元连接的公共电极的信号。
下面结合附图6所示的信号时序图，对本公开文本实施例所提供的移位寄存器单元驱动方法驱动如图4所示的移位寄存器单元的具体过程进行详细的说明。
需要说明的是，此实施例中，第一信号输入端为第二公共电极信号输入端，即第一信号为第二公共电极信号，图6中的第二公共电极信号为高电位公共电极信号，第二信号输入端输入高电平信号，第三信号输入端输入低电平信号。
由于图6所示的信号时序图中，第一控制信号和第二控制信号的时序与图3所示的信号时序图相同，因此，第一信号输出控制模块1的具体操作过程与上述技术方案说明类似，在此将不再赘述，以下仅对移位寄存器单元其他功能模块的具体操作过程进行详细说明：
在显示阶段的第一时段，起始信号输入端输入高电平信号，复位信号输入端输入低电平信号，时钟信号输入端输入低电平信号。
由于起始信号输入端输入高电平信号，从而使第三薄膜晶体管T3即预充电模块2处于导通状态，第二信号输入端输入的第二信号，例如直流高电平信号VDD，为上拉节点，即存储电容C1充电。
此时段中，上拉节点控制第四薄膜晶体管T4处于导通状态，但是时钟信号输入端输入低电平信号，从而使栅极信号输出端在第一时段输出的信号为时钟信号输入端输入的低电平信号。
由于第二控制信号输入端在显示阶段始终处于低电位状态，从而使第十二薄膜晶体管T12在显示阶段始终处于截止状态。
另外，此时段中，复位信号输入端输入低电平信号，从而使第五薄膜晶体管T5处于截止状态。
在显示阶段的第二时段，时钟信号输入端输入高电平信号，起始信号输入端和复位信号输入端输入低电平信号。
由于起始信号输入端输入低电平信号，从而使第三薄膜晶体管T3处于截止状态。
此时段上拉节点仍为高电平，时钟信号输入端输入高电平信号，由于存储电容的自举效应，从而使第四薄膜晶体管T4继续处于导通状态，那么此时段栅极信号输出端输出的信号为高电平的时钟信号，即栅极驱动信号，以使对应的栅线处于打开状态。
在显示阶段的第三时段，起始信号输入端和时钟信号输入端输入低电平信号，复位信号输入端输入高电平信号。
此时段中，第三薄膜晶体管T3、第四薄膜晶体管T4、第八薄膜晶体管T8、第九薄膜晶体管T9处于截止状态，第五至第七薄膜晶体管处于导通状态，从而利用第三信号输入端输入的第三信号以及第四信号输入端输入的第四信号，为上拉节点以及栅极信号输出端放电，以使栅极信号输出端输出低电平信号。
在第四阶段，时钟信号输入端输入高电平信号，起始信号输入端和复位信号输入端输入低电平信号。
由于此时段中，第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5处于截止状态，第六薄膜晶体管T6、第七薄膜晶体管T7、第十薄膜晶体管T10、第十一薄膜晶体管T1处于导通状态，从而使上拉节点和栅极信号输出端的电位保持不变。
另外，在触控阶段，由于第二控制信号输入端输入高电平信号，从而使第十二薄膜晶体管T12即重置模块5处于导通状态，那么栅极信号输出端在触控阶段输出的信号为第四信号端输入的第四信号，即低电平信号。而在触控阶段，起始信号输入端、复位信号输入端、时钟信号输入端无信号输入。
以上即为本公开文本实施例提供的移位寄存器单元在一帧时间的显示阶段和触控阶段的工作状态描述，那么可以看出，本公开文本实施例提供的移位寄存器单元，不但可以实现栅极信号输出以及信号移位寄存的功能，还可以控制公共电极信号在显示阶段和触控阶段具有不同的电位值，从而确保触摸屏在触控阶段的显示效果。
那么，基于本公开文本实施例提供的移位寄存器单元，本公开文本实施例还可以提供一种栅极驱动电路。
该栅极驱动电路中：
除第一级移位寄存器单元外，其余每个移位寄存器单元的起始信号输入端连接于其相邻的上一级移位寄存器单元的本级信号输出端；
除最后一级移位寄存器单元外，其余每个移位寄存器单元的复位信号输入端与其相邻的下一级移位寄存器单元的本级信号输出端相连接。
需要说明的是，本公开文本实施例提供的栅极驱动电路包括的多个级联的移位寄存器单元，可以根据需要将其中的几个移位寄存器单元设置为本公开文本实施例提供的移位寄存器单元，其他移位寄存器单元可以与现有技术中的相同，例如由对应多行栅线的触控驱动电极，可以只将一种一个移位寄存器单元设置为本公开文本实施例中的移位寄存器单元。
基于本公开文本实施例提供的栅极驱动电路，本公开文本实施例还可以提供一种显示装置，该显示装置具体可以包括上述本公开文本实施例提供的栅极驱动电路。
该显示装置具体可以为液晶面板、液晶电视、液晶显示器、OLED(有机发光二极管)面板、OLED显示器、等离子显示器或电子纸等显示装置。
本公开文本实施例所提供的移位寄存器单元、栅极驱动电路与显示装置特别适合LTPS(低温多晶硅技术)制程下的GOA电路需求，也可适用于非晶硅工艺下的GOA电路。
本公开文本实施例所提供的移位寄存器单元可适用于非晶硅、多晶硅、氧化物等工艺的薄膜晶体管，同时需指出的是，尽管上述实施例中，以单一采用N型薄膜晶体管为例进行了说明，然而，上述电路还可以轻易的改成采用单一的P型薄膜晶体管或CMOS(互补金属氧化物半导体)管电路。
以上描述可以看出，本公开文本提供的移位寄存器单元及其驱动方法、栅极驱动电路、显示装置，该移位寄存器单元中设置有用于拉低上拉节点以及栅极信号输出端的电位的下拉保持模块，用于在一帧时间的触控阶段，将栅极信号输出端输出信号的电位重置为第四信号的电位的重置模块；用于在一帧时间的显示阶段，控制第一信号输出端输出第一公共电极信号，以及在一帧时间的触控阶段，控制第一信号输出端输出所述第一信号输入端输入的第一信号的第一信号输出控制模块，所述第一信号为在所述触控阶段输入到与所述移位寄存器单元连接的公共电极的信号的第一信号输出控制模块。因 而，可由移位寄存器单元输出公共电极接收的信号，使显示装置中无需设置单独提供公共电极信号的驱动芯片，近而简化了显示装置的结构，降低了显示装置的成本。
并且，本公开文本实施例所提供的移位寄存器单元的结构设置，还可以降低移位寄存器单元的制作工艺和成本，确保显示装置在显示阶段和触控阶段的显示效果，实现画面显示与触控侦测的完美结合。
以上所述仅是本公开文本的实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开文本原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开文本的保护范围。

Claims (18)

  1. 一种移位寄存器单元，该移位寄存器单元设置于内嵌式触摸屏中，所述内嵌式触摸屏包括具有公共电极的基板，其中，所述移位寄存器单元包括预充电模块、上拉模块、下拉保持模块、重置模块以及第一信号输出控制模块，其中：
    下拉保持模块，分别与第一控制信号输入端、复位信号输入端、第三信号输入端、第四信号输入端、上拉节点、栅极信号输出端连接，用于拉低上拉节点以及栅极信号输出端的电位，所述上拉节点为所述预充电模块与所述上拉模块的连接点；
    重置模块，分别与第二控制信号输入端、栅极信号输出端、第四信号输入端连接，用于在一帧时间的触控阶段，将所述栅极信号输出端输出信号的电位重置为第四信号输入端输入的第四信号的电位；
    第一信号输出控制模块，分别与第一控制信号输入端、第二控制信号输入端、第一公共电极信号输入端、第一信号输入端以及第一信号输出端连接，用于在一帧时间的显示阶段，控制第一信号输出端输出所述第一公共电极信号输入端输入的第一公共电极信号，以及在一帧时间的触控阶段，控制第一信号输出端输出所述第一信号输入端输入的第一信号，所述第一信号为在所述触控阶段输入到与所述移位寄存器单元连接的公共电极的信号。
  2. 如权利要求1所述的移位寄存器单元，其中，所述第一信号为第二公共电极信号，所述第二公共电极信号的电位值为高电位触控驱动信号的电位值与低电位触控驱动信号的电位值的均值。
  3. 如权利要求1所述的移位寄存器单元，其中，当所述公共电极与触摸屏中的触摸驱动电极复用时，所述第一信号为触控驱动信号。
  4. 如权利要求1所述的移位寄存器单元，其中，所述第一信号输出控制模块包括第一薄膜晶体管和第二薄膜晶体管，其中：
    第一薄膜晶体管的第一极与第一公共电极信号输入端连接，第一薄膜晶体管的栅极与第一控制信号输入端连接，第一薄膜晶体管的第二极与第一信号输出端连接；
    第二薄膜晶体管的第一极与第一信号输入端连接，第二薄膜晶体管的栅极与第二控制信号输入端连接，第二薄膜晶体管的第二极与第一信号输出端连接。
  5. 如权利要求1所述的移位寄存器单元，其中，所述预充电模块分别与起始信号输入端、第二信号输入端、上拉节点连接，用于利用所述第二信号输入端输入的第二信号为所述上拉节点充电；
    上拉模块，分别与时钟信号输入端、上拉节点、栅极信号输出端连接，用于控制栅极信号输出端输出栅极驱动信号；
    所述下拉保持模块，用于拉低上拉节点以及栅极信号输出端的电位，并在下一时段，保持上拉节点以及栅极信号输出端的电位。
  6. 如权利要求5所述的移位寄存器单元，其中，所述预充电模块包括：
    第三薄膜晶体管，第三薄膜晶体管的第一极与第二信号输入端连接，第三薄膜晶体管的栅极与起始信号输入端连接，第三薄膜晶体管的第二极与上拉节点连接。
  7. 如权利要求5所述的移位寄存器单元，其中，所述上拉模块包括：
    第四薄膜晶体管和存储电容；
    第四薄膜晶体管的第一极与时钟信号输入端连接，第四薄膜晶体管的栅极分别与上拉节点、存储电容的第一端连接，第四薄膜晶体管的第二极，分别与栅极信号输出端、存储电容的第二端连接。
  8. 如权利要求5所述的移位寄存器单元，其中，所述下拉保持模块包括：
    第五薄膜晶体管、第六薄膜晶体管、第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管、第十薄膜晶体管、第十一薄膜晶体管；其中：
    第五薄膜晶体管的第一极与上拉节点连接，第五薄膜晶体管的栅极与复位信号输入端连接，第五薄膜晶体管的第二极与第三信号输入端连接；
    第六薄膜晶体管的第一极与上拉节点连接，第六薄膜晶体管的栅极分别与第七薄膜晶体管的栅极、第八薄膜晶体管的第一极、第十一薄膜晶体管的第二极连接，第六薄膜晶体管的第二极与第四信号输入端连接；
    第七薄膜晶体管的第一极与栅极信号输出端连接，第七薄膜晶体管的第二极与第四信号输入端连接；
    第八薄膜晶体管的栅极与上拉节点连接，第八薄膜晶体管的第二极与第四信号输入端连接；
    第九薄膜晶体管的第一极分别与第十薄膜晶体管的第二极、第十一薄膜晶体管的栅极连接，第九薄膜晶体管的栅极与上拉节点连接，第九薄膜晶体管的第二极与第四信号输入端连接；
    第十薄膜晶体管的第一极和栅极，与第一控制信号输入端连接；
    第十一薄膜晶体管的第一极与第一控制信号输入端连接。
  9. 如权利要求5所述的移位寄存器单元，其中，所述重置模块包括：
    第十二薄膜晶体管；
    第十二薄膜晶体管的第一极与栅极信号输出端连接，第十二薄膜晶体管的栅极与第二控制信号输入端连接，第十二薄膜晶体管的第二极与第四信号输入端连接。
  10. 如权利要求4至9任一项所述的移位寄存器单元，其中，所述薄膜晶体管为N型薄膜晶体管，所述薄膜晶体管的第一极为源极，所述薄膜晶体管的第二极为漏极。
  11. 如权利要求5至9任一项所述的移位寄存器单元，其中，所述第二信号输入端输入高电平信号，所述第三信号输入端输入低电平信号；或者
    所述第二信号输入端输入低电平信号，所述第三信号输入端输入高电平信号。
  12. 如权利要求5至9任一项所述的移位寄存器单元，其中，所述第四信号为低电平信号。
  13. 一种移位寄存器单元驱动方法，所述移位寄存器单元设置于内嵌式触摸屏中，所述内嵌式触摸屏包括具有公共电极的基板，其中，所述方法包括：
    在一帧时间的显示阶段的第一时段，预充电模块利用第二信号输入端输入的第二信号为上拉节点充电；
    在所述显示阶段的第二时段，上拉模块控制栅极信号输出端输出栅极驱动信号；
    在所述显示阶段的第三时段，下拉保持模块为所述上拉节点和栅极信号 输出端放电；
    在所述显示阶段的第四时段，下拉保持模块保持所述上拉节点和栅极信号输出端的电位；
    所述方法还包括：
    在所述一帧时间的显示阶段，第一信号输出控制模块控制第一信号输出端输出第一公共电极信号输入端输入的第一公共电极信号；
    在所述一帧时间的触控阶段，第一信号输出控制模块控制第一信号输出端输出第一信号输入端输入的第一信号，所述第一信号为在所述触控阶段输入到与所述移位寄存器单元连接的公共电极的信号。
  14. 如权利要求13所述的方法，其中，所述第一信号为第二公共电极信号，所述第二公共电极信号的电位值为高电位触控驱动信号的电位值与低电位触控驱动信号的电位值的均值。
  15. 如权利要求13所述的方法，其中，当部分所述公共电极与触摸屏中的触摸驱动电极复用时，所述第一信号为触控驱动信号。
  16. 如权利要求13所述的方法，其中，在所述第一时段，起始信号输入端输入高电平信号，时钟信号输入端和复位信号输入端输入低电平信号，栅极信号输出端输出低电平信号；
    在所述第二时段，时钟信号输入端输入高电平信号，起始信号输入端和复位信号输入端输入低电平信号，栅极信号输出端输出高电平信号；
    在所述第三时段，复位信号输入端输入高电平信号，起始信号输入端和时钟信号输入端输入低电平信号，栅极信号输出端输出低电平信号；
    在所述第四时段，时钟信号输入端输入高电平信号，起始信号输入端和复位信号输入端输入低电平信号，栅极信号输出端输出低电平信号；
    在显示阶段，第一控制信号输入端输入高电平信号，第二控制信号输入端输入低电平信号；
    在触控阶段，第一控制信号输入端输入低电平信号，第二控制信号输入端输入高电平信号。
  17. 一种栅极驱动电路，包括多个级联的如权利要求1至12任一项所述的移位寄存器单元；
    除第一级移位寄存器单元外，其余每个移位寄存器单元的起始信号输入端连接于其相邻的上一级移位寄存器单元的本级信号输出端；
    除最后一级移位寄存器单元外，其余每个移位寄存器单元的复位信号输入端与其相邻的下一级移位寄存器单元的本级信号输出端相连接。
  18. 一种显示装置，包括如权利要求17所述的栅极驱动电路。
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