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WO2008111406A1 - コンフィギュラブル回路およびコンフィギュレーション方法 - Google Patents

コンフィギュラブル回路およびコンフィギュレーション方法 Download PDF

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Publication number
WO2008111406A1
WO2008111406A1 PCT/JP2008/053592 JP2008053592W WO2008111406A1 WO 2008111406 A1 WO2008111406 A1 WO 2008111406A1 JP 2008053592 W JP2008053592 W JP 2008053592W WO 2008111406 A1 WO2008111406 A1 WO 2008111406A1
Authority
WO
WIPO (PCT)
Prior art keywords
logic blocks
wires
signal transmission
program
programmable
Prior art date
Application number
PCT/JP2008/053592
Other languages
English (en)
French (fr)
Inventor
Shogo Nakaya
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to US12/526,344 priority Critical patent/US7919980B2/en
Priority to JP2009503963A priority patent/JP5170079B2/ja
Priority to CN2008800075299A priority patent/CN101627541B/zh
Priority to EP08721040A priority patent/EP2157697B1/en
Publication of WO2008111406A1 publication Critical patent/WO2008111406A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

　本発明のコンフィギュラブル回路は、複数のロジックブロック４と複数のロジックブロック４の接続をプログラム可能なプログラマブルバスとを有する。プログラマブルバスは、複数のロジックブロック４に対応して信号伝送範囲毎に設けられた複数の配線１１＿ｘと、隣接する信号伝送範囲の配線同士を直接に接続するか遮断するかをプログラム可能な配線直結スイッチ７１１＿ｘと、複数の配線のうちいずれか一つの配線との接続がプログラム可能で、接続される配線の信号をロジックブロック４に供給する入力選択器３０＿ｘと、信号伝送範囲毎に設けられ、複数の配線のそれぞれについて隣接する信号伝送範囲に対応する配線とバッファを介して接続するか遮断するかをプログラム可能なプログラマブルスイッチ４０＿ｘとを含み、複数のロジックブロック４のうち少なくとも一つに対してプログラマブルスイッチ４０＿ｘが複数設けられている。
PCT/JP2008/053592 2007-03-09 2008-02-29 コンフィギュラブル回路およびコンフィギュレーション方法 WO2008111406A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US12/526,344 US7919980B2 (en) 2007-03-09 2008-02-29 Configurable circuit and configuration method
JP2009503963A JP5170079B2 (ja) 2007-03-09 2008-02-29 コンフィギュラブル回路およびコンフィギュレーション方法
CN2008800075299A CN101627541B (zh) 2007-03-09 2008-02-29 可配置电路以及配置方法
EP08721040A EP2157697B1 (en) 2007-03-09 2008-02-29 Configurable circuit and configuration method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-060353 2007-03-09
JP2007060353 2007-03-09

Publications (1)

Publication Number Publication Date
WO2008111406A1 true WO2008111406A1 (ja) 2008-09-18

Family

ID=39759349

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/053592 WO2008111406A1 (ja) 2007-03-09 2008-02-29 コンフィギュラブル回路およびコンフィギュレーション方法

Country Status (5)

Country Link
US (1) US7919980B2 (ja)
EP (1) EP2157697B1 (ja)
JP (1) JP5170079B2 (ja)
CN (1) CN101627541B (ja)
WO (1) WO2008111406A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013105388A1 (ja) * 2012-01-11 2013-07-18 日本電気株式会社 双方向バッファ及びその制御方法
JP2013236365A (ja) * 2012-04-13 2013-11-21 Semiconductor Energy Lab Co Ltd アイソレータ回路及び半導体装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11353152A (ja) * 1998-06-04 1999-12-24 Nec Corp プログラマブル機能ブロック
JP2005057452A (ja) * 2003-08-01 2005-03-03 Matsushita Electric Ind Co Ltd プログラマブル論理回路
JP2005101535A (ja) 2003-08-27 2005-04-14 Nec Corp 半導体装置
JP2005158815A (ja) * 2003-11-20 2005-06-16 Kumamoto Technology & Industry Foundation プログラマブル論理回路およびプログラマブル論理回路の配線構造
JP2005317978A (ja) 2004-04-28 2005-11-10 Internatl Business Mach Corp <Ibm> ＦｉｎＦＥＴ半導体構造およびその製造方法
JP2007060353A (ja) 2005-08-25 2007-03-08 Nec Corp 携帯電話装置、携帯電話システム、電源ユニット、電源ユニット認証方法、およびプログラム

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3496661B2 (ja) 2000-06-15 2004-02-16 日本電気株式会社 データパスに適したプログラマブル相互接続網を有する再構成可能デバイス
US6469540B2 (en) 2000-06-15 2002-10-22 Nec Corporation Reconfigurable device having programmable interconnect network suitable for implementing data paths
US6580289B2 (en) * 2001-06-08 2003-06-17 Viasic, Inc. Cell architecture to reduce customization in a semiconductor device
JP2003273336A (ja) * 2002-03-13 2003-09-26 Nec Electronics Corp 汎用ロジックセルアレイ及びこれを用いたａｓｉｃ
US7330050B2 (en) * 2004-11-08 2008-02-12 Tabula, Inc. Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements
US7825684B2 (en) * 2005-03-15 2010-11-02 Tabula, Inc. Variable width management for a memory of a configurable IC
US7765249B1 (en) * 2005-11-07 2010-07-27 Tabula, Inc. Use of hybrid interconnect/logic circuits for multiplication
US7797497B1 (en) * 2006-03-08 2010-09-14 Tabula, Inc. System and method for providing more logical memory ports than physical memory ports
US7928761B2 (en) * 2007-09-06 2011-04-19 Tabula, Inc. Configuration context switcher with a latch

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11353152A (ja) * 1998-06-04 1999-12-24 Nec Corp プログラマブル機能ブロック
JP2005057452A (ja) * 2003-08-01 2005-03-03 Matsushita Electric Ind Co Ltd プログラマブル論理回路
JP2005101535A (ja) 2003-08-27 2005-04-14 Nec Corp 半導体装置
JP2005158815A (ja) * 2003-11-20 2005-06-16 Kumamoto Technology & Industry Foundation プログラマブル論理回路およびプログラマブル論理回路の配線構造
JP2005317978A (ja) 2004-04-28 2005-11-10 Internatl Business Mach Corp <Ibm> ＦｉｎＦＥＴ半導体構造およびその製造方法
JP2007060353A (ja) 2005-08-25 2007-03-08 Nec Corp 携帯電話装置、携帯電話システム、電源ユニット、電源ユニット認証方法、およびプログラム

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2157697A4 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013105388A1 (ja) * 2012-01-11 2013-07-18 日本電気株式会社 双方向バッファ及びその制御方法
JPWO2013105388A1 (ja) * 2012-01-11 2015-05-11 日本電気株式会社 双方向バッファ及びその制御方法
US9106231B2 (en) 2012-01-11 2015-08-11 Nec Corporation Bidirectional buffer and control method thereof
JP2013236365A (ja) * 2012-04-13 2013-11-21 Semiconductor Energy Lab Co Ltd アイソレータ回路及び半導体装置

Also Published As

Publication number Publication date
JPWO2008111406A1 (ja) 2010-06-24
CN101627541A (zh) 2010-01-13
EP2157697A4 (en) 2011-01-26
JP5170079B2 (ja) 2013-03-27
EP2157697A1 (en) 2010-02-24
EP2157697B1 (en) 2013-02-27
US20100321062A1 (en) 2010-12-23
CN101627541B (zh) 2013-04-10
US7919980B2 (en) 2011-04-05

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