TW202505699A - Quad flat non-leaded package and manufacturing method thereof - Google Patents

Abstract

A QFN package includes a lead frame, a plurality of conductive pillars, a chip and a molding compound. The lead frame includes a die pad and a plurality of leads. The conductive pillars are disposed on and electrically connected to the leads. Each of the conductive pillars includes a base portion and a pillar portion connecting the base portion. A maximum outer diameter of the base portion is substantially greater than a maximum outer diameter of the pillar portion. The chip is disposed on the die pad and electrically connected to the leads. The molding compound covers the chip, the lead frame and the conductive pillars. The molding compound exposes bottom surfaces of the leads and top surfaces of the conductive pillars.

Description

Quad flat no-lead package and manufacturing method thereof

The present disclosure relates to a quad flat no-lead package and a method for manufacturing the same.

As electronic products become smaller, the market for handheld products continues to expand. Driven primarily by the mobile phone and digital assistant markets, manufacturers of these devices are facing the challenge of product size compression and the need for more personal computer functions. The additional functions can only be achieved through high-performance logic integrated circuits combined with increased memory capacity. In response to this challenge, smaller printed circuit boards will put pressure on surface mount component manufacturers to design products.

In today's handheld product market, many widely used components are beginning to transition from pinned to pinless forms. This has led to electronic components being designed to save printed circuit board space. The extra space saved can be used to configure components required for additional device functions.

Most of the widely used leadless package structures such as Quad Flat No Leads (QFN) or Dual Flat No-Lead (DFN) have electrical connection pads on one side as terminals for external connections. Therefore, they can only perform planar (2D) package mounting operations, but cannot perform three-dimensional (3D) stacking settings, making it difficult to further expand the functions and performance of this package structure.

The present disclosure provides a semiconductor package and a manufacturing method thereof, which can achieve the purpose of three-dimensional stacking of the original lead frame type semiconductor package and can also improve the function and performance of the semiconductor package.

A square flat leadless package disclosed herein includes a lead frame, a plurality of conductive pillars, a chip, and a packaging resin. The lead frame includes a chip seat and a plurality of pins. The plurality of conductive pillars are arranged on the plurality of pins and electrically connected to the plurality of pins, wherein each of the plurality of conductive pillars includes a base portion and a column portion connected to the base portion, and the maximum outer diameter of the base portion is substantially larger than the maximum outer diameter of the column portion. The chip is arranged on the chip seat and electrically connected to the plurality of pins. The packaging resin covers the chip, the lead frame, and the plurality of conductive pillars, wherein the packaging resin exposes the lower surfaces of the plurality of pins and the top surfaces of the plurality of conductive pillars.

The present invention discloses a manufacturing method of a quad flat no-lead package, comprising the following steps: providing a lead frame, wherein the lead frame comprises a chip seat and a plurality of leads; forming a conductive column on one of the plurality of leads by a wire bonding device, wherein the conductive column comprises a base portion and a column portion connected to the base portion, and the maximum outer diameter of the base portion is substantially greater than the maximum outer diameter of the column portion; placing a chip on the chip seat and electrically connecting the chip to the plurality of leads; and forming a packaging resin to cover the chip, the lead frame and the conductive column.

Based on the above, the quad flat leadless package disclosed in the present invention forms conductive posts on corresponding pins with a wire bonding device, so that the configuration of the conductive posts can have the characteristics of selectivity and adjustability according to the needs of electrical connection, and is formed on the pins of the lead frame according to needs, and the chip is placed on the chip seat of the lead frame, and the packaging colloid exposes the lower surface of the pins and the top surface of the conductive posts. In this configuration, the lower surface of the pins and the top surface of the conductive posts exposed by the packaging colloid can be electrically connected to other components respectively, so that the quad flat leadless package can be stacked with other substrates or packaging components on the upper and lower sides of the packaging colloid respectively to achieve the purpose of three-dimensional stacking, and can also improve the function and performance of the semiconductor package.

The above-mentioned and other technical contents, features and effects of the present disclosure will be clearly presented in the detailed description of each embodiment with reference to the drawings below. The directional terms mentioned in the following embodiments, such as "up", "down", "front", "back", "left", "right", etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used for explanation, not for limiting the present disclosure. In addition, in the following embodiments, the same or similar components will adopt the same or similar reference numerals.

Figures 1 to 6 are schematic cross-sectional views of a process of manufacturing a quad flat leadless package according to an embodiment of the present disclosure. In some embodiments, the method for manufacturing a semiconductor package may include the following steps. First, please refer to Figure 1, and provide a lead frame 110, wherein the lead frame 110 includes a chip base 112 and a plurality of pins 114. In this embodiment, the pins 114 can surround the chip base 112 and be arranged on the periphery of the chip base 112. In one embodiment, the lead frame 110 can be formed into a patterned lead frame by performing an etching process on a metal layer.

Next, referring to FIG. 2 , a chip 140 is placed on the chip base 112, and the chip 140 is electrically connected to the corresponding pins 114. In one embodiment, the chip 140 may include a plurality of contacts 142, which may be formed on the active surface S1 of the chip 140. In this embodiment, the chip 140 may include a display driver circuit integrated circuit (IC), an image sensor integrated circuit, a memory integrated circuit, a logic integrated circuit, an analog integrated circuit, an ultra-high frequency (UHF) integrated circuit, or a radio frequency (RF) integrated circuit, but the present disclosure is not limited thereto.

Next, please refer to FIG. 3 . In the present embodiment, the chip 140 may be disposed on the lead frame 110 and electrically connected to the corresponding pins 114 by, for example, wire bonding. Specifically, the semiconductor package may further include a plurality of wires 150, wherein the chip 140 includes an active surface S1 having a plurality of contacts 142 and a back surface S2 opposite to the active surface S1, and the chip 140 is disposed on the chip base 112 with the back surface S2, and the wires 150 are connected between the contacts 142 of the chip 140 and the pins 114 of the lead frame 110 to electrically connect the chip 140 and the lead frame 110. In the present embodiment, the chip 140 may be attached to the chip base 112 via a die attach film (DAF). Of course, the present disclosure does not limit the method of placing the chip 140 on the chip base 112 and electrically connecting the chip 140 to the corresponding pins 114 .

Next, please refer to FIG. 4 . In the present embodiment, a conductive column 120 is formed on at least one of the plurality of pins by a wire bonding device 105, and the conductive column 120 is electrically connected to the corresponding pin 114. In the present embodiment, the conductive column 120 includes a base portion 122 and a column portion 124 connected to the base portion 122, and the maximum outer diameter D1 of the base portion 122 is substantially greater than the maximum outer diameter D2 of the column portion 124. The conductive column 120 may include a suitable conductive material such as copper, gold, silver, titanium, tungsten, aluminum and/or the like. In the present embodiment, the conductive column 120 is a copper wire or an aluminum wire formed by the wire bonding device 105. For example, in this embodiment, the method of forming the conductive pillar 120 may include first forming a base portion 122 on the pin 114 using a wire bonding device 105, and moving the wire bonding device 105 away from the pin 114 by a predetermined distance to form a column portion 124 connected to the base portion 122 and extending the predetermined distance. In other words, the base portion 122 of the conductive pillar 120 may be an initial solder joint in the wire bonding process, and the column portion 124 may be a solder wire formed in the wire bonding process. Therefore, the outer diameter D1 of the base portion 122 is greater than the outer diameter D2 of the column portion 124. For example, the maximum outer diameter D2 of the column portion 124 is substantially greater than or equal to 10 mils, but the present disclosure is not limited thereto.

In one embodiment, the conductive pillar 120 may further include a top portion 126 connected to the pillar portion 124, and the maximum outer diameter D3 of the top portion 126 is substantially greater than the maximum outer diameter D2 of the pillar portion 124. For example, in this embodiment, after the pillar portion 124 is formed by the wire bonding device 105, the top portion 126 may be formed on the pillar portion 124 by the wire bonding device 105. In other words, the base portion 122 of the conductive pillar 120 may be an initial solder joint in the wire bonding process, the pillar portion 124 may be a solder wire formed in the wire bonding process, and the top portion 126 may be a terminal solder joint in the wire bonding process. Therefore, the outer diameter D2 of the top portion 126 is larger than the outer diameter D2 of the column portion 124 , and the column portion 124 is connected between the base portion 122 and the top portion 126 .

It is worth noting that in the aforementioned embodiment, the chip 140 is first placed on the chip base 112, and then the wire bonding device 105 is used to perform wire bonding to electrically connect the chip 140 to the pin 114, and then the wire bonding device 105 is used to form the conductive pillar 120 on the corresponding pin 114, but the present disclosure is not limited to this. In other feasible embodiments, the process sequence of the chip 140, the conductive pillar 120 and the wire bonding process can be adjusted as needed. For example, the present disclosure can first place the chip 140 on the chip base 112, and then the wire bonding device 105 is used to form the conductive pillar 120 on the corresponding pin 114, and then the wire bonding device 105 is used to perform wire bonding to electrically connect the chip 140 to the pin 114. This also falls within the scope of application of the present disclosure.

Next, please refer to FIG. 5 , a packaging body 160 is formed to cover the chip 140, the lead frame 110, and the conductive pillar 120. The packaging body 160 can be formed, for example, by a molding process. In the present embodiment, the wire 150 is also encapsulated in the packaging body 160. For example, the packaging body 160 may include an epoxy resin. In the present embodiment, the packaging body 160 at this stage may be to fully cover the chip 140, the wire 150, and the conductive pillar 120 (including the top portion 126), and the bottom surface 164 of the packaging body 160 exposes the lower surface of the chip base 112 and the lead 114.

Next, please refer to FIG. 6 , the packaging colloid 160 is thinned so that the packaging colloid 160 exposes the top surface of the conductive pillar 120. In this embodiment, the packaging colloid 160 can be thinned by chemical mechanical polishing, laser thinning and/or grinding using a thinning tool 50 until the packaging colloid 160 exposes the top surface of the top end 126. It is worth noting that for the convenience of explanation, the grinding thinning method is used as an example in the drawings of this embodiment. In other words, the present embodiment can utilize a thinning process such as chemical mechanical polishing or laser thinning to remove the encapsulation resin 160 above the top surface of the conductive pillar 120, so that the top surface of the conductive pillar 120 is substantially coplanar with the upper surface 162 of the encapsulation resin 160. In this way, the encapsulation resin 160 can expose at least the bottom surface of the lead 114 and the top surface of the conductive pillar 120.

In this embodiment, the thinning process such as grinding can be performed to remove a portion of the top portion 126. The outer diameter D3 of the ground top portion 126 is substantially larger than the outer diameter D2 of the column portion 124, thereby increasing the area of the conductive column 120 exposed to the outside, thereby increasing the bonding area when electrically connected to an external electronic component. At this point, the manufacturing method of the quad flat no-lead package 100 can be substantially completed.

It must be noted here that the quad flat no-pin package of each subsequent embodiment is similar to the quad flat no-pin package of the aforementioned embodiment, and therefore, each subsequent embodiment uses the component numbers and part of the content of the aforementioned embodiment, wherein the same number is used to represent the same or similar components, and the description of the same technical content is omitted. The description of the omitted part can refer to the aforementioned embodiment, and each embodiment will not be repeated.

FIG7 is a cross-sectional view of a quad flat no-lead package according to an embodiment of the present disclosure. In this embodiment, the method of forming the conductive pillar 120a may include forming a plurality of (sub) conductive pillars 1201 and 1202 stacked on each other on the corresponding pins 114 using a wire bonding device, wherein each of the plurality of conductive pillars 1201 and 1202 includes a base portion 122 and a column portion 124 connected to the base portion 122, and the maximum outer diameter D1 of the base portion 122 is substantially greater than the maximum outer diameter D2 of the column portion 124. For example, in this embodiment, the conductive pillar 120a can be formed by first forming the base portion 122 of the conductive pillar 1201 on the lead 114 using a wire bonding device, and then moving the wire bonding device a predetermined distance away from the lead 114 to form the column portion 124 of the conductive pillar 1201 connected to the base portion 122 and extending the predetermined distance. Then, the base portion 122 of the conductive pillar 1202 is formed on the column portion 124 of the conductive pillar 1201 using a wire bonding device, and then moving the wire bonding device a predetermined distance away from the base portion 122 to form the column portion 124 of the conductive pillar 1202 connected to the base portion 122 and extending the predetermined distance. This embodiment only shows two stacked sub-conductive pillars 1201 and 1202, however, in other embodiments, the conductive pillar 120a may be formed by stacking more than two sub-conductive pillars. The number of sub-conductive pillars may depend on the height of the quad flat no-lead package 100a, and the present disclosure is not limited thereto.

FIG8 is a schematic cross-sectional view of a square flat no-pin package according to an embodiment of the present disclosure. FIG8A is a schematic top view of a portion of the square flat no-pin package of FIG8 . It must be noted here that the number of conductive posts disclosed in the following figures is only shown as a group in the schematic diagram for the convenience of explanation, and is not used to limit the number of conductive posts disclosed in the present disclosure. Please refer to FIG8 and FIG8A at the same time. In the present embodiment, the method of forming the conductive post 120b shown in FIG8 includes forming a base portion 122 on the corresponding pin with a wire bonding device, and moving a predetermined distance away from the corresponding pin 114 to form a first column portion 1241, and then moving back to the corresponding pin 114 to form a bend portion 1242 and a second column portion 1243. Thus, the column portion extends upward from the base portion 122 for a predetermined distance and then bends and extends downward to the corresponding pin 114. In detail, from a structural point of view, the base portion 122 is disposed on the corresponding pin 114, and the column portion extends upward from the base portion 122 to the upper surface of the packaging body 160, and then bends and extends downward from the upper surface of the packaging body 160 to the corresponding pin 114. In this embodiment, the outer diameter D1 of the base portion 122 is substantially larger than the outer diameter D2 of the column portions 1241 and 1243. Furthermore, after the encapsulation adhesive 160 is formed, a thinning process may be performed on the encapsulation adhesive 160 so that the encapsulation adhesive 160 exposes the top surface of the bent portion 1242 of the conductive pillar 120b.

Fig. 8B is a cross-sectional schematic diagram of a quad flat no-lead package according to an embodiment of the present disclosure. Fig. 8C is a partial top view schematic diagram of the quad flat no-lead package of Fig. 8B.

Please refer to FIG. 8B and FIG. 8C at the same time. In this embodiment, the packaging glue 160 and the conductive column of the packaging structure shown in FIG. 8 can be further thinned until the bent portion 1242 shown in FIG. 8 is removed to expose the top surfaces of the column portions 1241 and 1243. From a structural perspective, the base portion of the conductive column 120c includes a first base portion 122 and a second base portion 125, the column portion includes a first column portion 1241 connected to the first base portion 122 and a second column portion 1243 connected to the second base portion 125, and the packaging glue 160 exposes the top surfaces of the first column portion 1241 and the second column portion 1243. Furthermore, the maximum outer diameters of the first base portion 122 and the second base portion 125 are substantially larger than the maximum outer diameters of the first column portion 1241 and the second column portion 1243. It is worth noting that the top surfaces of the first column portion 1241 and the second column portion 1243 are exposed on the surface of the packaging gel 160 and can be used as conductive terminals for product 3D stacking or further manufacturing of redistribution wiring (RDL) processes. The actual application can be determined according to product requirements and is not limited thereto.

FIG9 is a cross-sectional schematic diagram of a square flat leadless package according to an embodiment of the present disclosure. In this embodiment, the packaging resin 160 and the conductive column of the packaging structure shown in FIG6 can be further thinned until the entire top end 126 of the conductive column is removed to expose the top surface of the column portion 124. From a structural perspective, the base portion 122 is disposed on the corresponding lead 114, and the column portion 122 extends upward from the base portion 122 to the upper surface exposed to the packaging resin 160. In this embodiment, the outer diameter D1 of the base portion 122 is substantially larger than the outer diameter D2 of the column portion 124.

FIG10 is a cross-sectional view of a semiconductor package structure having a quad flat no-lead package according to an embodiment of the present disclosure. The conductive posts after FIG10 are all depicted in the conductive post type of FIG6 , but a person skilled in the art should understand that the conductive post types of all the aforementioned embodiments can be applied to all quad flat no-lead packages taught in the following.

6 and 10, in some embodiments, the packaging body 160 of the quad flat no-lead package 100 formed by the above process exposes at least the lower surface of the pin 114 and the top surface of the conductive column 120, so that the quad flat no-lead package 100 can be electrically connected to other components at its upper and lower sides. For example, in the embodiment of FIG. 10, the substrate 200 can be further arranged on the bottom surface of the packaging body 160 of the quad flat no-lead package 100 and form an electrical connection with the pin 114. In one embodiment, the substrate 200 includes a plurality of electrical contacts 232, which are respectively connected to the lower surface of the pin 114 exposed by the packaging body 160 to form the semiconductor package 10 as shown in FIG. 10.

In the present embodiment, the substrate 200 may further include a plurality of electrical vias 234 and a plurality of electrical contacts 236, wherein the electrical contacts 232 and the electrical contacts 236 may be respectively disposed on two opposite surfaces of the substrate 200, and the electrical vias 234 may extend through the substrate 200 to electrically connect between the electrical contacts 232 and the electrical contacts 236. Thus, the electrical contacts 232, the electrical vias 234, the electrical contacts 236 and other conductive elements may together form an electrical conductive path 230 to electrically connect two opposite surfaces of the substrate 200. In the present embodiment, the substrate 200 may include electronic elements such as a circuit board, an interposer, and a wafer that may be electrically connected to a package.

FIG11 is a cross-sectional schematic diagram of a semiconductor package structure having a quad flat no-lead package according to an embodiment of the present disclosure. In this embodiment, the semiconductor package structure 10a may further include a package 100', which is disposed on the top surface of the packaging colloid 160, and the package 100' includes a plurality of electrical contacts 170, which are respectively connected to the top surfaces of the conductive posts 120 exposed by the packaging colloid 160. In this embodiment, the package 100' may be substantially similar to the structure of the quad flat no-lead package 100 (also including components such as a lead frame, a chip, wires, and a packaging colloid). However, in other embodiments, the package 100' may also be a package with a structure completely different from the quad flat no-lead package 100, as long as its electrical contacts 170 can be electrically connected to the conductive posts 120 of the quad flat no-lead package 100.

FIG. 12 is a schematic cross-sectional view of a semiconductor package structure having a quad flat no-lead package according to an embodiment of the present disclosure. In this embodiment, the package 300 of the semiconductor package 10b may be a package having a structure completely different from that of the quad flat no-lead package 100. The package 300 may include components such as an upper substrate 310, an upper chip 320, an upper bump 330, and an upper packaging colloid 340. Specifically, the upper chip 320 is disposed on the upper substrate 310 and may be electrically connected to the upper substrate 310 through the upper bump 330, for example, by flip chip bonding. The upper packaging colloid 340 is disposed on the upper substrate 310 and encapsulates the upper chip 320 and the upper bump 330 therein.

In one embodiment, the package 300 stacked on the quad flat no-lead package 100 may include, for example, a semiconductor device such as a memory device, which may be used, for example, to provide stored data to the chip 140 in the quad flat no-lead package 100. In such an embodiment, the chip 140 may include a memory control module, which may provide control functions for the memory device of the package 300. However, this embodiment is only used for illustration, and the present disclosure does not limit the types and functions of the package stacked on the quad flat no-lead package 100.

FIG13 is a schematic top view of some components of a quad flat leadless package according to an embodiment of the present disclosure. Referring to FIG13 , in this embodiment, the pins 114 include a plurality of first pins 1141 and at least one second pin 1142, wherein a plurality of conductive posts 120 are formed on the plurality of first pins 1141, respectively. In one embodiment, the conductive posts 120 are not formed on the second pins 1142. In other words, the conductive posts 120 are not disposed on all the pins 114, but are selectively disposed on some of the pins 114 according to actual electrical requirements, and have adjustable flexibility in circuit design. In addition, in the present embodiment, the contacts 142 of the chip 140 may be disposed along two opposite sides of the chip 140, and the pins 114 and the corresponding conductive pillars 120 may also be disposed correspondingly on two opposite sides of the chip 140, so that they may be connected to the corresponding contacts 142 via the wires 150. However, in other embodiments, the contacts 142 of the chip 140 may also be disposed around all edges of the chip 140, for example, along four sides of the chip 140. In this way, the pins 114 and the corresponding conductive pillars 120 may also be disposed correspondingly around the four sides of the chip 140, so that they may be connected to the corresponding contacts 142 via the wires 150. The present disclosure is not limited thereto.

FIG. 14 is a cross-sectional schematic diagram of a quad flat leadless package according to an embodiment of the present disclosure. Please refer to FIG. 14 first. In this embodiment, a chip 140 is disposed on a chip seat 112a by flip chip bonding. Specifically, the chip seat 112a is composed of a plurality of extension portions 112a extending from a plurality of pins 114a to a central area of a lead frame 110a, and a plurality of contacts of the chip 140 are respectively connected to the plurality of extension portions 112a. In other words, the lead frame 110a includes a plurality of pins 114a disposed around a center point of the lead frame 110a, and each pin 114a includes an extension portion 112a extending in a direction toward the center point. These extension portions 112a surrounding the center point together constitute a chip seat 112a for the chip 140 to be disposed. In this way, the chip 140 can be placed on the chip base 112 via the plurality of bumps 180 in a flip chip bonding manner.

FIG. 15 is a cross-sectional schematic diagram of a quad flat leadless package according to an embodiment of the present disclosure. Referring to FIG. 15 , in the present embodiment, the chip disposed on the lead frame 110a may include a plurality of chips 140a, 140b stacked on each other. Moreover, the chips 140a, 140b are stacked on each other and disposed on the chip seat 112a of the lead frame 110a, for example, by flip chip bonding. In the present embodiment, the chip 140a is bonded to the chip seat 112a (a plurality of extensions of a plurality of pins 114a) via a plurality of bumps 180, and the chip 140b is bonded to the chip 140a via a plurality of bumps 180. Of course, the present disclosure does not limit the method by which the chips 140a, 140b are disposed on the chip seat 112a.

In summary, the quad flat leadless package disclosed herein forms conductive posts on corresponding pins with a wire bonding device, so that the configuration of the conductive posts can be selective and adjustable according to the needs of electrical connection, and is formed on the pins of the lead frame as required, and a chip is placed on the chip seat of the lead frame, and the packaging colloid exposes the lower surface of the pins and the top surface of the conductive posts. With such a configuration, the lower surface of the pins and the top surface of the conductive posts exposed by the packaging colloid can be electrically connected to other components respectively, so that the quad flat leadless package can be stacked with other substrates or packaging components on the upper and lower sides of the packaging colloid respectively to achieve the purpose of three-dimensional stacking, and can also enhance the function and performance of the semiconductor package.

10, 10a, 10b: semiconductor package 50: thinning tool 100, 100a, 100b, 100c, 100d, 100e: quad flat leadless package 100', 300: package 105: wire bonding device 110, 110a: lead frame 112, 112a: wafer base 112a: extension part 114, 114a: lead 1141: first lead 1142: second lead 120, 120a, 120b, 120c: conductive column 1201, 1202: sub-conductive column, conductive column 122: base part, first base part 124: column part 1241: first column part, column part 1243: second column part, column part 1242: bending part 125: second base part 126: top end part 140, 140a, 140b: chip 142: contact point 150: wire 160: packaging plastic 162: upper surface 164: bottom surface 180: bump 200: substrate 230: electrical conduction path 232, 236, 170: electrical contact 234: electrical conduction hole 310: upper substrate 320: upper chip 330: upper bump 340: upper packaging plastic S1: active surface S2: back surface D1, D2, D3: outer diameter

Figures 1 to 6 are schematic cross-sectional views of a manufacturing method of a quad flat pinless package according to an embodiment of the present disclosure. Figure 7 is a schematic cross-sectional view of a quad flat pinless package according to an embodiment of the present disclosure. Figure 8 is a schematic cross-sectional view of a quad flat pinless package according to an embodiment of the present disclosure. Figure 8A is a partial top view of the quad flat pinless package of Figure 8. Figure 8B is a schematic cross-sectional view of a quad flat pinless package according to an embodiment of the present disclosure. Figure 8C is a partial top view of the quad flat pinless package of Figure 8B. Figure 9 is a schematic cross-sectional view of a quad flat pinless package according to an embodiment of the present disclosure. Figures 10 to 12 are schematic cross-sectional views of semiconductor package structures having quad flat no-lead packages according to different embodiments of the present disclosure. Figure 13 is a schematic top view of some components of a quad flat no-lead package according to an embodiment of the present disclosure. Figures 14 and 15 are schematic cross-sectional views of quad flat no-lead packages according to different embodiments of the present disclosure.

50: Thinning tool

100:Quad Flat No-Pin Package

110: Conductor frame

112: Wafer holder

114: Pins

120: Conductive column

122: Base part

124: Column part

126: Top end

140: Chip

150: Conductor wire

160: Packaging colloid

162: Upper surface

164: Bottom surface

D1, D2, D3: outer diameter

Claims (23)

A quad flat leadless package includes: a lead frame including a chip seat and a plurality of leads; a plurality of conductive posts disposed on the plurality of leads and electrically connected to the plurality of leads, wherein each of the plurality of conductive posts includes a base portion and a column portion connected to the base portion, and the maximum outer diameter of the base portion is substantially greater than the maximum outer diameter of the column portion; a chip disposed on the chip seat and electrically connected to the plurality of leads; and a packaging colloid covering the chip, the lead frame and the plurality of conductive posts, wherein the packaging colloid exposes the lower surfaces of the plurality of leads and the top surfaces of the plurality of conductive posts. A quad flat no-lead package as described in claim 1, wherein the base portion is disposed on the corresponding pin, and the column portion extends upward from the base portion to be exposed on the upper surface of the packaging colloid. A quad flat no-lead package as described in claim 1, wherein each of the plurality of conductive pillars further includes a top portion, the pillar portion is connected between the top portion and the base portion, and the packaging colloid exposes the top surface of the top portion, wherein the maximum outer diameter of the top portion is substantially larger than the maximum outer diameter of the pillar portion. A quad flat no-lead package as described in claim 1, wherein each of the plurality of conductive pillars comprises a plurality of sub-conductive pillars stacked on top of each other. A quad flat no-pin package as described in claim 1, wherein the base portion is disposed on the corresponding pin, and the column portion extends upward from the base portion to the upper surface of the packaging colloid, and then bends and extends downward from the upper surface of the packaging colloid to the corresponding pin. A quad flat no-pin package as described in claim 1, wherein the base portion includes a first base portion and a second base portion, the column portion includes a first column portion connected to the first base portion and a second column portion connected to the second base portion, and the packaging glue exposes the top surfaces of the first column portion and the second column portion. The quad flat no-pin package as described in claim 1 further includes a plurality of wires, wherein the chip includes an active surface having a plurality of contacts and a back surface relative to the active surface, and the chip is disposed on the chip seat with the back surface, and the plurality of wires are respectively connected between the plurality of contacts and the plurality of pins of the chip. A quad flat no-lead package as described in claim 1, wherein the chip base is composed of a plurality of extensions extending from the plurality of pins toward the central area of the lead frame, and a plurality of contacts of the chip are respectively connected to the plurality of extensions. A quad flat no-lead package as described in claim 1, wherein the chip includes multiple chips stacked on each other. The quad flat leadless package as described in claim 1 further comprises: A substrate is disposed on the bottom surface of the packaging body, and the substrate includes a plurality of first electrical contacts, which are respectively connected to the bottom surface of the plurality of leads exposed by the packaging body; and A packaging component is disposed on the top surface of the packaging body, and the packaging component includes a plurality of second electrical contacts, which are respectively connected to the top surface of the plurality of conductive posts exposed by the packaging body. A quad flat no-lead package as described in claim 1, wherein the plurality of pins include a plurality of first pins and at least one second pin, wherein the plurality of conductive posts are respectively disposed on the plurality of first pins. A quad flat no-lead package as described in claim 1, wherein the plurality of conductive posts are copper wires or aluminum wires. A quad flat no-lead package as described in claim 1, wherein the maximum outer diameter of the column portion is substantially greater than or equal to 10 mils. A manufacturing method of a quad flat no-lead package, comprising: providing a lead frame, wherein the lead frame comprises a chip seat and a plurality of leads; forming a conductive column on one of the plurality of leads by a wire bonding device, wherein the conductive column comprises a base portion and a column portion connected to the base portion, and the maximum outer diameter of the base portion is substantially greater than the maximum outer diameter of the column portion; placing a chip on the chip seat and electrically connecting the chip to the plurality of leads; and forming a packaging colloid to cover the chip, the lead frame and the conductive column. The manufacturing method of the quad flat no-lead package as described in claim 14, wherein forming the conductive column on one of the plurality of pins by the wire bonding device further comprises: Forming the base portion on one of the plurality of pins by the wire bonding device, and moving a predetermined distance away from the one of the plurality of pins to form a column portion connected to the base portion and extending the predetermined distance, wherein the maximum outer diameter of the base portion is substantially larger than the maximum outer diameter of the column portion. The manufacturing method of the quad flat no-lead package as described in claim 15, wherein forming the conductive column on one of the plurality of pins by the wire bonding device further comprises: forming a top portion on the column portion by the wire bonding device, wherein the maximum outer diameter of the top portion is substantially larger than the maximum outer diameter of the column portion. The manufacturing method of the quad flat no-lead package as described in claim 14, wherein forming the conductive column on one of the plurality of pins by the wire bonding device comprises: Forming a plurality of conductive columns stacked on one of the plurality of pins by the wire bonding device, wherein each of the plurality of conductive columns comprises a base portion and a column portion connected to the base portion, and the maximum outer diameter of the base portion is substantially larger than the maximum outer diameter of the column portion. The manufacturing method of the quad flat no-lead package as described in claim 14, wherein the forming of the conductive column on one of the plurality of pins by the wire bonding device comprises: Forming the base portion on one of the plurality of pins by the wire bonding device, and moving a predetermined distance away from the one of the plurality of pins and then moving back to the one of the plurality of pins to form a column portion, wherein the column portion extends upward from the base portion by the predetermined distance and extends downward to the corresponding pin after bending. The manufacturing method of the quad flat leadless package as described in claim 14 further includes: Performing a thinning process on the packaging colloid so that the packaging colloid exposes the conductive column. A method for manufacturing a quad flat no-lead package as described in claim 19, wherein the thinning process of the package colloid includes laser thinning and grinding processes. A method for manufacturing a quad flat no-lead package as described in claim 14, wherein the plurality of pins include at least one first pin and at least one second pin, and wherein the conductive column is formed on the at least one first pin. The manufacturing method of the quad flat leadless package as described in claim 14 further includes: Disposing a substrate on the bottom surface of the packaging colloid, and the substrate includes a plurality of first electrical contacts, which are respectively connected to the bottom surfaces of the plurality of pins exposed by the packaging colloid, and Disposing a packaging component on the top surface of the packaging colloid, and the packaging component includes a plurality of second electrical contacts, which are respectively connected to the top surfaces of the plurality of conductive posts exposed by the packaging colloid. A method for manufacturing a quad flat no-lead package as described in claim 14, wherein the chip is bonded to the chip base by wire bonding or flip chip bonding.

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