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TW201110310A - Method for forming an integrated circuit structure and integrated circuit structure - Google Patents

Method for forming an integrated circuit structure and integrated circuit structure Download PDF

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Publication number
TW201110310A
TW201110310A TW099122431A TW99122431A TW201110310A TW 201110310 A TW201110310 A TW 201110310A TW 099122431 A TW099122431 A TW 099122431A TW 99122431 A TW99122431 A TW 99122431A TW 201110310 A TW201110310 A TW 201110310A
Authority
TW
Taiwan
Prior art keywords
wafer
integrated circuit
trenches
forming
die
Prior art date
Application number
TW099122431A
Other languages
English (en)
Other versions
TWI502724B (zh
Inventor
Hsin-Hui Lee
William Cheng
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of TW201110310A publication Critical patent/TW201110310A/zh
Application granted granted Critical
Publication of TWI502724B publication Critical patent/TWI502724B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Dicing (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

201110310 六、發明說明： 【發明所屬之技術領域】 本發明大致關於半導體裝置的製造，且特別關於晶 圓級晶片模壓封裝（wafer level chip molded packaging)的 結構與方法。 【先前技術】 於半導體工業中，為響應減少半導體封裝之厚度、 φ 增加晶片速度及高密度製造的目標，進行減少半導體晶 圓厚度的努力。於堆疊之晶圓製造中，具有積體電路形 成於其中之兩個或多個半導體晶圓互相連接。在相對於 含有圖案形成化電路系統之表面的表面上，藉由所謂半 導體晶圓之背面研磨來執行厚度減少。由於經薄化之晶 圓傾向具有不足的強度且較易變形，例如彎曲及/或扭 曲，所以在使用一切割製程將晶圓分成個別之晶片封裝 體前，通常執行一封住步驟，於其中將晶圓之一表面封 鲁 在一成形化合物（molding compound)(例如，熱固化環氧 樹脂（thermocuring epoxy resin))中。之後將這些個別之 晶片封裝體固定於一基板上，例如一印刷電路板(printed circuit board, PBC)。 然而，並無法進行一般堆疊晶圓製程而無其缺陷。 有時，在晶圓遭受溫度循環測試(temperature cycle test) 之處，例如成形化合物會變成自其所貼附之晶圓鬆開或 脫層（delamination)。成形脫層（molding delamination)對於 製造製程有害且易減低整體製程產率並會降低所生產之 0503-A34472TWF/daphne 3 201110310 晶片封裝體的品質與可靠程度。料， 形?層之處，於隨後之切割製程與相關處理期:二= 之日日片的邊緣更易受到破裂、形 影響。由於料理由及_㈣ 及/或腐飿性環境 ^ 由及根據閱讀以下之詳細敘述合聞私 其他理由’需要-晶圓級晶片製造的;= 法/、避免一般晶圓結合製程的缺點。 提供 【發明内容】 本發明提供—卿成積體f路結構的方法，包括： 一晶 111，廿 θ *- - * 圓 其具有一晶片側與一非晶片側， 包括複數個半導體晶片；提供複數個晶粒，各 =至該複數個半導體晶片之一；形成一或多個溝；於 ::::該晶片側上’·將該晶圓之該晶片側與該複二固 日日粒封住，且實質卜J ^ 頁買上以一保濩材料填入該一 ::以及切割該晶圓以將該晶圓分成個別的半導：裝* 括種:=路結構的方法，包 片側包括複數個半導體晶片；提供複數個晶粒，各t 晶粒結合至該複數個半導體晶片之-；將-高能束^ 晶片側上以形成一或多個溝槽；將該晶圓 之該S曰片側與該複數個晶粒封住，並以 該-或多個溝槽趣保護材料以固化該保 以及切割該，圓以將該晶圓分成個別的半導體封裝體。 本發明還提供-種積體電路結構，包括：一半導體 0503-A34472TWF/daphne 4 201110310 晶片，其具有一晶粒側與一非粒片側，該晶粒側具有一 或多個溝槽形成於其中；至少一個晶粒，結合至該半導 體晶片的該晶粒側；以及一保護材料封住該至少一晶粒 且實質上填入該一或多個溝槽。 為了讓本發明之上述和其他目的、特徵、和優點能 更明顯易懂，下文特舉較佳實施例，並配合所附圖示， 作詳細說明如下： 【實施方式】 第1圖為一積體電路結構10之一實施例於其製造階 段期間的一剖面圖。晶粒20結合於晶圓22之上。晶粒 20可包括記憶體晶片（memory chip)、射頻（radio frequency，RF)晶片、邏輯晶片（logic chip)或其他晶片。 晶粒20各具有一正表面30與一背表面40。各個晶粒20 包括半導體基板50，其中晶粒20的背表面40也為分別 之半導體基板50的背表面。 晶圓22包括複數個半導體晶片70。晶圓22包括半 導體晶圓，例如石夕、珅化鎵、水晶晶圓（rock crystal wafer)、藍寶石（sapphire)、玻璃等。晶片70可包括記憶 體晶片、射頻晶片、邏輯晶片或其他晶片。在本發明之 一實施例中，各個晶粒20結合至晶片70之一。或者， 一晶片70可具有大於一個晶粒20結合於其上。在一些 實施例中，晶粒20與晶片70為面對面（face-to -face)結 合，其中結合方法包括一般使用之方法，例如氧化物至 氧化物（oxide-to-oxide)結合、氧化物至石夕（oxide-to-silicon) 0503-A34472TWF/daphne 5 201110310 結合、銅至銅（copper-to-copper)結合、附著結合（adhesive bonding)等。在一實施例中’各個晶粒20藉由焊料凸塊 (solder bump)35結合至複數個晶片之一。在一些實施例 中’可使用底膠材料（underfill material)25以填入介於複 數個晶粒20之一與複數個晶片70之一間的一缺口，底 膠材料實質上封住焊料凸塊35。結合至一相同之晶片7〇 的晶粒20可各具有相同或不同的電路設計或尺寸。 晶圓22可具有一正表面80與一背表面90，其中接 合墊（未顯示）及/或其他内連線結構（未顯示）為接近 正表面80,而背表面90為一半導體基板背表面。積體電 路（未顯示）包括主動與被動裝置，例如電晶體、電阻 器、電容器等’且形在於晶圓22的正表面8〇。在本發明 一實施例中’半導體晶片70包括一或多個穿透石夕通孔 (through-silicon via，TSV)(未顯示），其自正表面 8〇往 下延伸進入晶圓22，其中穿透矽通孔連接至一或多個曰 粒20。 然後參見第2圖’於晶圓22之正表面8〇上形成_ 或多個溝（geoove)或溝槽（trench)60。溝槽6〇可藉由一妒 雷射切割（laser scribing)技術或其他適合裁切方法來开^ 成’其中一高能束(high energy beam) ’如雷射光束了 被使用來例如穿過或切除晶圓22之正表面8〇的—部 份。溝槽60代表一體積，其藉由溝槽之底部的寬度乘以 側壁的高度乘以於晶圓22之正表面80中所製成之、、籌槽 的長度所定義。溝槽60之體積代表藉由一雷射切割機二 或其他適合裁切工具自晶圓表面所移除之；g夕的量。 0503-A34472TWF/daphne 6 201110310 要被使用於一切割製程中之適合的雷射裝備可為任 何那些市售可得之雷射。例如，可適合地使用具有能量 等級介於1與2 watts之間的一連續Nd/YAG雷射。熟悉 此技藝人士瞭解可適合地調整雷射的能量以僅移除所需 之矽層的深度、寬度及/或長度。熟悉此技藝人士也暸解 深度應夠深以允許一之後要被沈積之成形化合物 (later-to-be deposited molding compound)被形成於溝槽 60中以可充分附著或固定至下方晶圓22以使在溫度循環 鲁測試(temperature cycle test)或切割步驟期間，例如成形化 合物不會自晶圓變形或脫層（delaminate)。於相同意義 下，在由於溝槽60形成而在於矽層中建立應力之處，深 度應不那麼深。在本發明一實施例中，形成溝槽60至介 於約100A至約150,000 A之間的一深度。在另一實施例 中，形成溝槽60至介於約1，〇〇〇 A至約50,000 A之間的 一深度。 如第2圖中所示，形成一或多個溝槽60於晶圓22 # 之正表面上介於複數個晶粒20之任兩個之間。然後參見 第3圖，將一成形化合物或保護材料100塗覆於晶圓22 之正表面80上、於複數個晶粒20上，及實質上於溝槽 60中。保護材料100係由一可固化材料，例如一聚合物 材料、樹脂材料、聚亞醯胺、氧化石夕、環氧樹脂、苯並 環丁烯（Benzocyclobutene，BCB)、SILKTM (Dow Chemical) 或其組合所形成。為了避免晶圓22或要被研磨之本體 (body)在一研磨製程中扭曲，例如，在保護材料1〇〇固化 後，保護材料較佳具有充分地高剛度（stiffness)與撓 0503-A34472TWF/daphne 7 201110310 曲剛性（flexural rigidity)。可於晶圓22上形成保護材料 100至厚度大於晶粒20的高度以封住晶粒20。保護材料 2〇之厚度並無特別限制’只要其可確保一後製程（later process) ’例如晶圓22或要被研磨之本體之研磨，所需 的厚度一致。然而’為了在基板之研磨後，獲得所需之 厚度一致’保護材料100之厚度較佳為一致。 使用製程’如射出成形（injection molding)、壓縮成 形（compression molding)、鋼板印刷（stencii printing)、旋 塗（spin-on coating)或未來發展之成形製程（m〇lding process)可將保護材料1〇〇提供至積體電路結構1〇。在保 護材料100的塗覆之後與一後來的晶圓薄化或切割製程 之前，執行一固化或烘烤步驟以固化保護材料1〇〇。在本 發明一貫施例中，於一加熱腔室中在自約1〇〇£>c至約2〇〇 C的溫度下，以自約3〇分鐘至約8小時的時間，烘烤保 護材料100。在固化保護材料1〇〇後’晶圓22的非晶片 側可接受一進一步之薄化製程來研磨非晶片側以減少晶 圓的厚度。 一—回到溝槽60形成的討論上，第6圖顯示根據本發明 貫施例，一積體電路結構10的剖面圖，其中溝槽60 乂成於阳粒20之周圍（但在晶粒切割線區内）且實質上 被以成形㈣1GG填人。第5 目同之積體電路結 構但為一上視圖，其中成形材料形成於溝槽中。 為了 '月楚說明’未顯示成形材料100形成於晶粒20、底 膠：料25或晶圓22之部分之上。帛5圖顯示根據發明 貫把例，溝槽60為一環繞晶粒20之連續溝槽。然而， 0503-A34472TWF/daphne 201110310 ί =實施例中，溝槽6G可為—非連續溝槽，換句話說， 钵：—〇可包括一或多個獨立且分離之溝槽，其實質上連 、λ 者晶粒20的周圍。
8 ®顯不根據本發明—實施例，積體電路結構⑺ 曰剖面圖’其中溝槽6G形成在晶粒2G的周圍但較接近 晶粒20，且實質上被以成形化合物ι〇〇填入。第7圖顯 ㈣體電路結構的上視圖，其中顯示成形化合物剛形 成於溝槽60中。再者，為了清楚之目的，於第7圖中未 *、"示成幵y化5物1 〇〇形成於晶粒2〇、底膠材料或晶圓 22之部分之上。第7圖顯示根據本發明一實施例，溝槽 =為形成於晶粒2 〇之周_ —連續溝槽。然而，在一些 實知例中’溝槽6G可為-非連續溝槽，其意指，溝槽6〇 可包括-些個別分離之溝槽，其實質上連續沿著晶粒加 的周圍在些實施例中，溝槽形成於晶圓Μ中實 質上連續沿著晶圓之一或多個晶粒切割線。 雖然顯示於第5至8圖中之溝槽60具有矩形的形 狀，然而可以瞭解的是，根據依照所實施之製造製程的 設計選擇’溝槽6〇可包括任何形狀。例如，溝槽6〇可 具有一圓形、卵形、矩形、三角形、正方形、五邊形、 六邊形、七邊形、八邊形、星形、十字形或橢圓形的形 狀。第10與9圖顯示根據一實施例，包括一矩形、圓形 (各種尺寸）與十字形之形狀的溝槽。 然後參見第4圖，一般在晶圓已接受一晶圓等級測 試程序後，接著將晶圓22倒置且固定至切割膠帶（dicing tape)ll〇或一晶粒模（die frame)，其為之後以一般方式沿 0503-A34472TWF/daphne 9 201110310 著切割線93被切割以將經封住的晶圓分成用於固定於一 基板，例如印刷電路板（Printedcircuitboard,PCB)上之個 別的半導體封裝體。 第11圖顯示一形成積體電路結構之方法200的一實 施例。經由提供一晶圓’其具有一晶片側與一非晶片側’ 晶片侧包括複數個半導體晶片，方法200開始於步驟 202。於步驟204，提供複數個晶粒，各個晶粒結合至複 數個半導體晶片之一。於步驟206，一或多個溝槽形成於 晶圓之晶片侧上。於步驟208 ’將晶圓之晶片侧與複數個 晶粒以一保護材料封住，保護材料實質上填入一或多個 溝槽。於步驟210，切割晶圓以將其分成用於固定於一基 板（例如，印刷電路板）上之個別的半導體封裝體。 可將根據本發明實施例之形成晶圓級晶片模壓封裝 (wafer level chip molded package)的方法實施於廣大範圍 之封裝應用。由於具有成形化合物嵌入於下方晶圓中， 增強了介於成形化合物與晶圓之間的附著。此避免了可 起因於溫度循環測試的可能脫層，而在溫度循環測試 中，例如熱膨脹係數（coefficient of thermal Expansion, CTE)變成一議題。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍内，當可作些許之更動與潤飾，因此本發明 之保護範圍當視後附之申請專利範圍所界定者為準。 0503-A34472TWF/daphne 201110310 【圖式簡單說明】 第1至10圖顯示一積體電路結構之一實施例於其各 種製造階段期間的剖面圖。 第11圖顯示形成積體電路結構之方法之一實施例的 一流程圖。 【主要元件符號說明】 10〜積體電路結構； φ 20〜晶粒； 22〜晶圓， 25〜底膠材料(underfill material); 30〜晶粒20之正表面； 35〜焊料凸塊； 40〜晶粒20之背表面； 50〜半導體基板； 60〜溝或溝槽； • 70〜晶片； 80〜晶圓22之正表面； 90〜晶圓22之背表面； 93〜切割線； 100〜成形化合物或保護材料； 110〜切割膠帶（dicing tape); 200〜形成一積體電路結構之方法； 202 ' 204 ' 206、208 ' 210〜步驟 ° 0503-A34472TWF/daphne 11

Claims (1)

  1. 201110310 七、申請專利範圍： 1. 種形成積體電路結構的方法，包括： 該晶 片側包括複數個半導體晶片 提供複數個晶粒，各個該晶粒結合至該複數個半導 晶片之一. 提供-晶圓，其具有一晶片側與一非晶片側 體 形成一或多個溝槽於該晶圓之該晶片側上； 將該晶圓之該晶片側與該複數個晶粒封住， 上以一保護材料填入該一或多個溝槽， ·以及 切割該晶圓以將該晶圓分成個別的半導體封襄體。 構的2方法如專欠利範㈣1項所述之形成積體電路結 冓的方法〜、中各個該複數個晶粒係藉 士人 至該複數個半導體晶片之一。 Id、，《口 3.如申料·圍第2項所述 構的方法，其中形成一底膠材料以 == 粒之一與該複數個晶片之nf "於該複數個晶 質上封住該㈣凸塊。日’的-缺口’該底膠材料實 構的4方法如專利範圍第1項所述之形成積體電路結 冓的方法，其中形成一或多個溝槽於該曰 上介於該複數個晶粒之任兩個之間。°“日L片側 5.如申請專利範圍第4 你·、+、〜 構的方法，其中該一或多個/4之形成積體電路結 〆、Τ 4 或多個溝槽係Μ ά ^ &上 energy beam)形成。 9 南月b 束（high 6.如申請專利範㈣！項所述之 構的方法，其中該一或多個溝 /積體電路結 苒僧係使用1射切割技術 〇503-A34472TWF/daphne 12 201110310 形成。 7. 如申請專利範圍第〗項 構的方法，其中該—或多個、—34之形成積體電路結 之-的-周隨形成於該晶圓中日貫#上連續沿著該晶粒 8. 如申請專利範圍第7項 構的方法，其中該一或多個溝:被斤:之形成積體電路結 粒切割線區内。 v成於該日日圓之一晶 9. 如申請專利範圍第1項所、+、 構的方法，其中該—或多個、㈣之形成積體電路結 之-晶粒切割線被形成於該二貫f上連·^ 10·如申請專利範圍第1 項所述之形成積體電路結 :==:切㈣圓的步驟前烘烤該保護 11· 一種形成積體電路結構的方法，包括： 提供一晶圓，其具有一 B t； ^日丨如 μ ^, 虿曰日片側與一非晶片側，該晶 片側包括複數個半導體晶片； 提供複數個晶粒，各個該晶粒結合至該複數個半導 晶片之一： 將一面能束聚焦於該晶圓之該晶片側上以形成一或 多個溝槽； 將該晶圓之該晶片侧與該複數個晶粒封住，並以一 保護材料填入該一或多個溝槽； 烘烤該保護材料以固化該保護材料；以及 切割該晶圓以將該晶圓分成個別的半導體封裝體。 12. —種積體電路結構，包括： 0503-A34472TWF/daphne 13 201110310 晶 粒側：：體晶片，其具有-晶粒側與-非粒片側，該 #側了有一或多個溝槽形成於其t ; 以及至少—個晶粒’結合至該半導體晶片的該晶粒側； 晶粒且實質上填入該一或 一保濩材料封住該至少一 多個溝槽。 申明專利範圍第12項所述之積體電路結構， 八中該一或多個溝槽被形成至介於約100 A至約150 〇〇〇 人之間的一深度。 ’ 如申請專利範圍第12項所述之積體電路結構， 其中該一或多個溝槽連續沿著該晶粒的一周圍被形成於 該晶圓中。 15.如申請專利範圍第14項所述之積體電路結構， 其中該一或多個溝槽被形成於該半導體晶片之一切割線 區内。 σ、 0503-A34472TWF/daphne 14
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