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TW200801891A - Dynamic timing adjustment in a circuit device - Google Patents

Dynamic timing adjustment in a circuit device

Info

Publication number
TW200801891A
TW200801891A TW096104207A TW96104207A TW200801891A TW 200801891 A TW200801891 A TW 200801891A TW 096104207 A TW096104207 A TW 096104207A TW 96104207 A TW96104207 A TW 96104207A TW 200801891 A TW200801891 A TW 200801891A
Authority
TW
Taiwan
Prior art keywords
circuit device
clock signal
delay
input
latch
Prior art date
Application number
TW096104207A
Other languages
English (en)
Other versions
TWI442213B (zh
Inventor
Anis M Jarrar
Colin Macdonald
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200801891A publication Critical patent/TW200801891A/zh
Application granted granted Critical
Publication of TWI442213B publication Critical patent/TWI442213B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
TW096104207A 2006-03-08 2007-02-06 電路裝置之動態時序調整 TWI442213B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/371,142 US7716511B2 (en) 2006-03-08 2006-03-08 Dynamic timing adjustment in a circuit device

Publications (2)

Publication Number Publication Date
TW200801891A true TW200801891A (en) 2008-01-01
TWI442213B TWI442213B (zh) 2014-06-21

Family

ID=38480317

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096104207A TWI442213B (zh) 2006-03-08 2007-02-06 電路裝置之動態時序調整

Country Status (7)

Country Link
US (1) US7716511B2 (zh)
EP (1) EP1999538B1 (zh)
JP (1) JP4827932B2 (zh)
KR (1) KR101334630B1 (zh)
CN (1) CN101535917A (zh)
TW (1) TWI442213B (zh)
WO (1) WO2007120957A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI509407B (zh) * 2012-11-09 2015-11-21 Mediatek Inc 關鍵路徑仿真裝置

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8050781B2 (en) * 2007-06-29 2011-11-01 Emulex Design & Manufacturing Corporation Systems and methods for ASIC power consumption reduction
US8161431B2 (en) * 2008-10-30 2012-04-17 Agere Systems Inc. Integrated circuit performance enhancement using on-chip adaptive voltage scaling
US8560875B2 (en) * 2009-09-17 2013-10-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Apparatus for clock calibrating a less precise second clock signal with a more precise first clock signal wherein the first clock signal is inactive during a sniff mode and the second clock signal is active during a sniff mode
US8954017B2 (en) 2011-08-17 2015-02-10 Broadcom Corporation Clock signal multiplication to reduce noise coupled onto a transmission communication signal of a communications device
KR20130048650A (ko) * 2011-11-02 2013-05-10 에스케이하이닉스 주식회사 집적회로 시스템 및 메모리 시스템
US9207693B1 (en) * 2014-05-29 2015-12-08 Infineon Technologies Ag Method and apparatus for compensating PVT variations
FR3024619B1 (fr) * 2014-08-01 2016-07-29 Pyxalis Circuit integre photorepete avec compensation des retards de propagation de signaux, notamment de signaux d'horloge
US9664737B2 (en) * 2014-08-19 2017-05-30 Mediatek Inc. Method for providing an on-chip variation determination and integrated circuit utilizing the same
US9413344B2 (en) 2014-09-08 2016-08-09 Qualcomm Incorporated Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems
CN105718402B (zh) * 2016-01-13 2021-04-20 福州瑞芯微电子股份有限公司 可编程时序发生器
KR102565184B1 (ko) * 2018-07-09 2023-08-08 에스케이하이닉스 주식회사 디지털 회로를 모델링하는 회로 모듈 및 이를 포함하는 시뮬레이션 장치
JP7422066B2 (ja) * 2020-12-28 2024-01-25 ルネサスエレクトロニクス株式会社 半導体装置
JP2023122380A (ja) * 2022-02-22 2023-09-01 キオクシア株式会社 半導体装置及びメモリシステム

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6570944B2 (en) * 2001-06-25 2003-05-27 Rambus Inc. Apparatus for data recovery in a synchronous chip-to-chip system
US5498977A (en) * 1995-03-03 1996-03-12 Hewlett-Packard Company Output driver having process, voltage and temperature compensation for delay and risetime
US6127865A (en) * 1997-05-23 2000-10-03 Altera Corporation Programmable logic device with logic signal delay compensated clock network
US6535988B1 (en) * 1999-09-29 2003-03-18 Intel Corporation System for detecting over-clocking uses a reference signal thereafter preventing over-clocking by reducing clock rate
US6643787B1 (en) * 1999-10-19 2003-11-04 Rambus Inc. Bus system optimization
US6829715B2 (en) * 2000-05-31 2004-12-07 Broadcom Corporation Multiprotocol computer bus interface adapter and method
US6668346B1 (en) * 2000-11-10 2003-12-23 Sun Microsystems, Inc. Digital process monitor
US6566924B2 (en) * 2001-07-25 2003-05-20 Hewlett-Packard Development Company L.P. Parallel push algorithm detecting constraints to minimize clock skew
KR100446291B1 (ko) * 2001-11-07 2004-09-01 삼성전자주식회사 카스 레이턴시를 이용하여 락킹 레졸루션 조절이 가능한지연동기 루프 회로
US7483508B2 (en) * 2001-11-27 2009-01-27 Texas Instruments Incorporated All-digital frequency synthesis with non-linear differential term for handling frequency perturbations
EP1476801A2 (en) * 2002-02-15 2004-11-17 Multigig Limited Electronic circuits
US6943610B2 (en) * 2002-04-19 2005-09-13 Intel Corporation Clock distribution network using feedback for skew compensation and jitter filtering
KR100470995B1 (ko) * 2002-04-23 2005-03-08 삼성전자주식회사 클럭수신 동기회로를 갖는 멀티클럭 도메인 데이터 입력처리장치 및 그에 따른 클럭신호 인가방법
US7054971B2 (en) * 2002-08-29 2006-05-30 Seiko Epson Corporation Interface between a host and a slave device having a latency greater than the latency of the host
US6985400B2 (en) * 2002-09-30 2006-01-10 Infineon Technologies Ag On-die detection of the system operation frequency in a DRAM to adjust DRAM operations

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI509407B (zh) * 2012-11-09 2015-11-21 Mediatek Inc 關鍵路徑仿真裝置

Also Published As

Publication number Publication date
KR101334630B1 (ko) 2013-12-02
WO2007120957A2 (en) 2007-10-25
TWI442213B (zh) 2014-06-21
JP2009529296A (ja) 2009-08-13
EP1999538A2 (en) 2008-12-10
KR20080098524A (ko) 2008-11-10
CN101535917A (zh) 2009-09-16
JP4827932B2 (ja) 2011-11-30
EP1999538B1 (en) 2018-08-22
EP1999538A4 (en) 2014-01-08
US20070214377A1 (en) 2007-09-13
WO2007120957A3 (en) 2009-04-09
US7716511B2 (en) 2010-05-11

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