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TW200733124A - Embedded memory and repairing methods thereof - Google Patents

Embedded memory and repairing methods thereof

Info

Publication number
TW200733124A
TW200733124A TW096105261A TW96105261A TW200733124A TW 200733124 A TW200733124 A TW 200733124A TW 096105261 A TW096105261 A TW 096105261A TW 96105261 A TW96105261 A TW 96105261A TW 200733124 A TW200733124 A TW 200733124A
Authority
TW
Taiwan
Prior art keywords
defective
cell array
memory
memory block
data
Prior art date
Application number
TW096105261A
Other languages
English (en)
Other versions
TWI328233B (en
Inventor
Jong-Doo Joo
Cheol-Ha Lee
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200733124A publication Critical patent/TW200733124A/zh
Application granted granted Critical
Publication of TWI328233B publication Critical patent/TWI328233B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0401—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals in embedded memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/104—Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
TW096105261A 2006-02-24 2007-02-13 Embedded memory TWI328233B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060018424A KR100675015B1 (ko) 2006-02-24 2006-02-24 스캔 기능 및 컬럼 리던던시를 포함하는 내장형 메모리장치, 리던던시 리페어 및 스캔 방법

Publications (2)

Publication Number Publication Date
TW200733124A true TW200733124A (en) 2007-09-01
TWI328233B TWI328233B (en) 2010-08-01

Family

ID=38015004

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096105261A TWI328233B (en) 2006-02-24 2007-02-13 Embedded memory

Country Status (3)

Country Link
US (1) US7518943B2 (zh)
KR (1) KR100675015B1 (zh)
TW (1) TWI328233B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2669872C1 (ru) * 2015-03-10 2018-10-16 Тосиба Мемори Корпорейшн Устройство памяти и способ управления им
KR102345541B1 (ko) * 2016-09-13 2021-12-31 삼성전자주식회사 리던던시 칼럼 및 리던던시 주변 로직을 포함하는 메모리 장치
KR102704904B1 (ko) * 2020-06-05 2024-09-09 삼성전자주식회사 Ddi 칩 및 디스플레이 장치

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3614993B2 (ja) * 1996-09-03 2005-01-26 株式会社ルネサステクノロジ テスト回路
US6732229B1 (en) * 1999-02-24 2004-05-04 Monolithic System Technology, Inc. Method and apparatus for memory redundancy with no critical delay-path
US6671834B1 (en) * 2000-07-18 2003-12-30 Micron Technology, Inc. Memory redundancy with programmable non-volatile control
JP3594891B2 (ja) * 2000-09-12 2004-12-02 沖電気工業株式会社 半導体記憶装置およびその検査方法
US6480428B2 (en) * 2000-12-19 2002-11-12 Winbond Electronics Corporation Redundant circuit for memory device
US6469949B1 (en) 2001-05-11 2002-10-22 International Business Machines Corp. Fuse latch array system for an embedded DRAM having a micro-cell architecture
JP3863400B2 (ja) 2001-09-28 2006-12-27 株式会社東芝 半導体集積回路
US6603690B1 (en) * 2002-03-06 2003-08-05 International Business Machines Corporation Low-power static column redundancy scheme for semiconductor memories
US6667918B2 (en) * 2002-05-01 2003-12-23 Mellanox Technologies Ltd. Self-repair of embedded memory arrays
KR100472460B1 (ko) * 2002-07-04 2005-03-10 삼성전자주식회사 메모리의 결함 복구 방법 및 그에 적합한 장치
US6807114B2 (en) * 2003-01-17 2004-10-19 Micron Technology, Inc. Method and system for selecting redundant rows and columns of memory cells
JP4012474B2 (ja) 2003-02-18 2007-11-21 富士通株式会社 シフト冗長回路、シフト冗長回路の制御方法及び半導体記憶装置
US6992937B2 (en) * 2003-07-28 2006-01-31 Silicon Storage Technology, Inc. Column redundancy for digital multilevel nonvolatile memory
US6816420B1 (en) * 2003-07-29 2004-11-09 Xilinx, Inc. Column redundancy scheme for serially programmable integrated circuits
US20050144516A1 (en) * 2003-12-30 2005-06-30 Gonzalez Carlos J. Adaptive deterministic grouping of blocks into multi-block units
KR100608592B1 (ko) * 2004-01-27 2006-08-03 삼성전자주식회사 플래시 메모리의 데이터 관리 장치 및 방법
US7263642B1 (en) * 2005-09-15 2007-08-28 Azul Systems, Inc Testing replicated sub-systems in a yield-enhancing chip-test environment using on-chip compare to expected results for parallel scan chains testing critical and repairable sections of each sub-system
US7286380B2 (en) * 2005-09-29 2007-10-23 Intel Corporation Reconfigurable memory block redundancy to repair defective input/output lines

Also Published As

Publication number Publication date
US7518943B2 (en) 2009-04-14
KR100675015B1 (ko) 2007-01-29
US20070201289A1 (en) 2007-08-30
TWI328233B (en) 2010-08-01

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