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TW200539465A - Chip heat sink device and method - Google Patents

Chip heat sink device and method Download PDF

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Publication number
TW200539465A
TW200539465A TW094116456A TW94116456A TW200539465A TW 200539465 A TW200539465 A TW 200539465A TW 094116456 A TW094116456 A TW 094116456A TW 94116456 A TW94116456 A TW 94116456A TW 200539465 A TW200539465 A TW 200539465A
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Taiwan
Prior art keywords
wafer
heat sink
chip
heat dissipation
item
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Application number
TW094116456A
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English (en)
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TWI290374B (en
Inventor
Kuo-Wei Lin
Hsaio-Ping Chang
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Taiwan Semiconductor Mfg
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Publication of TW200539465A publication Critical patent/TW200539465A/zh
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Publication of TWI290374B publication Critical patent/TWI290374B/zh

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2924/0001—Technical content checked by a classifier
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

200539465 ， 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體積體電路之覆晶封裝，牲 讨万j有關於一種新 式之改良晶片散熱座裝置以及於ic晶片運作中之散熱方法。 【先前技術】 半導體積體電路的最後製程之-為多層級封裝，其方法包括增加ic曰 片之電極距離’保護以免於機械與外界應力；提供適t之熱途 晶^引導散熱並形成電性連接。晶片封裝之方法決定了龍晶^整^ 私化費、功能以及可罪度以及挺供封裳之系統。 “ 1C晶片封裝-般可廣泛地分類為二：一是將晶片封裝於一陶变封農以 藉由真空密封與外界隔絕。此雜為典型喊並應用於高效能需求。另一 晶片封裝於-瓣封裝，換句話說由於封膠主要係由環氧樹脂^成，因此 晶片並非完全與外界環賴絕。所以朋空氣會渗透封包並對晶片產生不 良影響。然而最近改良塑膠封裝已將其翻及運耻力擴大。由於塑_ 裝之製程有助於自動整批處理因此較符合經濟效益。 、 ，球栅_(BGA)封裝為最近發kIC晶片封裝，其可利用陶曼封裝或 塑膠封裝並可為不同種類之積體封裝結構。球柵P車列(BGA)封裝係使用辟錫 球或凸塊以韻及機_連接W至其他微電子裝置。晶粒自晶圓分割 後，通常藉由軸觸凸塊於電路；或晶粒上，轉護連接至電路板之 1C晶片並紐連接晶片電路至形成於電路板上之導細案。BGA技術屬於 覆晶技術之領域。 ' 覆晶封裝技術可用於連接不_類之電路板，包括喊基板、印刷電 路板、軟性電路板以歸基板。麟凸塊—般設置於覆晶厢，藉由導電 連接墊以紐喊接覆晶±之電路。由於覆晶之微電路提供多種功能，因 此通常需要較多之銲錫凸塊。覆晶尺寸—般為每邊13絲以沿覆晶邊緣塞
0503-A30174TWF 5 200539465 .滿銲錫凸塊。因此覆晶導電_由多個各別之導體城，其中該 距約〇·1毫米或更小。 ㈣<间 請參照第1A圖其係顯示_般覆晶26之剖面圖，其包括例如—上 電層16與下層導電層22透過-絕緣層叫目互分隔。下層之複數個導^ 22猎由絕緣層18彼此分隔。轉電層‘料過穿過絕緣層以之導電介 ，18及導電層22係以傳統方式依序沉積 郷成複_ 1C晶片或晶粒沉積於單—半導體晶圓基板％上之後， 餘24會切魏__。細目觸凸塊1G歸直接焊接至連續之 塾14的上表面，其中每—銲錫塾14外型呈矩形，且部分被保護 層12復盍。凸塊墊14周圍由介電層15(例如：基板％中之氧化物)環繞。 此外同^日思第1A圖，每一銲錫墊14皆與上導電層㈣成電性接觸。 請參照第1B圖’於覆晶26上形成銲錫凸塊1G後，將晶片26反轉(_ ，稱之為覆晶)而銲錫凸塊1G連接至基板·如：印刷電路板)之導電端。 取t將曰金屬散熱座3〇裝設於覆晶％之基板24背面25，以於積體電路裝置 (而覆晶26係其中的一部分)操作時散熱。散熱座3〇包括複數個散熱縫二， 亚利用含有銀粒之塗膠Μ連接於基板背面Μ。一般在塗膠％以及基板背 • 面25之間會設置一層金屬蓋36。 利用傳統方式裝設散熱座於晶體電路晶片具有幾項缺點。其中之—係 於晶，分割及封裝後，裝設散熱座至每-封裝晶粒需要高成本，另—是晶 片封破尺寸大。因此業界返需一種新的改良式晶片散熱座裝置及方法以 低成本及其封裝尺寸。 本^明之一目的在於提供一種新的散熱座以應用於積體電路晶片。 本考X明之另一目的在於提供一種新汇晶片散熱座以減小封裝尺寸。 本卷明之再一目的在於提供一種新的IC晶片散熱座以將低成本。 本卷明之又—目的在於提供一種新的1C晶片散熱座以使晶片之每單位
0503-A30174TWF 6 200539465 面積具有高速的熱傳遞。 士本發明之又-目的在於提供一種新的Ic晶片散熱座及方法，以利用連 續之製程步驟同時形成在所有IC w或晶粒於晶圓基板上。 【發明内容】
根據上述及其他目的’本發明提供—_的1C晶4散熱座，其具有低 成本、每單位面積具有有效的熱傳雜及具有小尺寸之U封裝。血型之 實施例係先沉積-金屬晶種層辨導體晶圓麵，以形成1〇晶片散熱座， 其中半導體上具有細目L賴沉積—絲層於該晶種層上並 圖案化之以絲複數個光_口。f齡屬於光_口以形成複數個散熱 柱於晶種上。最後除去晶種層上之光㈣定義複數個散熱柱使其自晶種層 延伸以及一網狀散熱通道延伸於該些散熱柱之間。 >本發明更包括於電子產品操作中產品巾之IC晶片的散熱方法。典型實 方法包括：提供—轉體晶圓；形成複數個1c晶片於該晶圓上；沉 積=晶種層於晶圓背面；沉積光阻層於晶種層上；圖案化複數個光阻開 ^於_層中；沉積金屬於光阻開对及晶種層上；清除晶種層上之光阻 ’其中1C晶片散熱座留在每—晶片背片，·將每—晶片封 衣於電子U;以及於電子產品運辦透職紐使晶片散孰。 為=侧之上述和其他目的、特徵、和伽能更嶋雜，下文特 牛出施例，並配合所_式，鱗細綱如下·· 【實施方式】 請參照第2、3圖，其係繪示本發明一 -t, 4〇. 〇 40 ^: IC ίΓί "
作丰·夕W木化表面44a覆盍-保護層50。於製 作h體之過程中，積體電路(未顯示)逐漸地形成於圖案化表面输上。利 0503-A30174TWF 7 200539465 .用熟習此技藝人士之技術形成銲錫凸塊46，以各別透過於圖案化 之凸塊墊48電性連接積體電路(ICs)。 ' -般於封裝擁巾在製作频電路晶面散熱 轉並於其上形成銲錫凸塊以電 /、上後將。亥曰曰片42翻 產品中。一η利用生接觸基板54，例如印刷電路板以用於電子 μ板心來固定IC晶片42於基板54上。接著提 L基板54 祕凸塊56紐躺電子^之其 據熟=技藝人士之技術進行封裝以及組合步驟。 （未為）。根 路晶之Γ晶片賴座58係由高熱傳導金屬形成。適用於製作體電 I …、坐之金屬包括銅、銀以及鈦但亦可包括其他全屬。IC日片鸯 柱62彼此相互間隔鄰接並自_㈣面種層6〇 ° _固散熱 桩糾Μ ^ 盾表垂直延伸。如第3圖所示，鄰 、，、柱2以父錯之行74及列％之陣列排列以 64網。如第2圖所示，每一散敎 Bd、通道 散熱柱寬80約_微米。 政熱“ 78至少約副微米而其 於第4A 4Γ第A4Gil，其係顯不製作積體電路散熱座於1C晶片42上。 簡單地顯示單—lc “42，細根據本發财法於將 曰曰員刀剔成各自獨立之晶片前，於整個半導體晶圓44背面铷形成1C曰 片散熱座58。因此於下;十、击 » 曰曰 具找晶繼座別。 割與分割後，每—IC晶片42上便 根據本發明方法，JC B y ji々為片* &丨如 ^ 曰曰片政…、座之典型製法如下。整個半導體费作方 接作積體電路(未顯示)於半導體晶圓44之圖案化表面44a上。
=珠供連接塾以電性接觸每一 IC晶片虹之積體電 圖’銲錫凸塊46對應地形成於連接塾上。 ’，、、弟4A 接著請參照第4B圖，— 於製作IC W广 積於圖案化表面44a上，以 足以η:月、、、坐58時覆蓋並保護鋅錫凸塊46。保護層薄板66之厚度 錫凸塊46 ’並可彻《此技藝人士所知之傳統化學氣相沉積
0503-A30174TWF 200539465 技術沉積保護層薄板66於圖案化表面44a上。 请麥照第4C圖，接著將晶片42翻轉並於半導體晶片44之背面4你沉 積金屬曰曰種層60。在此金屬晶種層6〇可為銅、銀、鈦或其他導熱金屬。其 中曰曰種層60係利用傳統之物理氣相沉積濺鍍步驟形成於晶背4牝上。 凊荼到第4D圖，沉積一光阻層68於金屬晶種層6〇上，其中光阻層 68 -般為乾膜光阻。細層·從之厚度以至少、1〇〇微米較佳，接著將光 阻層68圖案化以於晶種層6〇上形成尺寸大小及位置符合各個散熱柱62(如 第2圖)之複數個光阻開口 7〇。每一光阻開〇 7〇之一般寬度7〇a约ι〇_ι〇〇 微米。
月ί…、弟4E圖，沉積金屬層72於晶種層上6〇以填充光阻層gg之光 阻開口 70。其中金屬層η係68利用傳統電化學電鐘技術沉積，而金屬層 72厚度與光阻層之厚度實質上相同。完成電麟，化學機械研磨法平 坦化金屬層72並依所需移除過量之金屬層72。 請參照第4F圖，接著移除晶種層6〇上的光阻層68以完成忙晶片散 熱座58之製作。因此IC晶片散熱座％之散熱柱自晶種層6〇延伸，並大 抵與晶種層60絲垂直。同時保護層驗％會自半導體晶圓a之圖宰化 表面純移除。或者保護層層壓層％亦可於另外的製程步驟中自半導體晶 圓44移除。 完成上述之憾座製程步驟後，連續散熱座S8覆蓋於整個半導體晶 圓44月面’包括先厨形成於晶圓μ上之所有ic晶片c背面。接著將製 作於半導體晶圓44上之複數個1C晶片42藉由晶圓的切割而彼此分開且散 熱座58順著_線(未顯示）。於w分簡程後，“散熱座％留在 母一晶片42背面。 請參照第4G圖，藉由將每-IC晶片42之觸凸塊你貼附至基板％ 上以完成每-覆晶4G之裝配’貼附方式—般係利用環氧樹脂2。接著根據 熟習此技藝人士之技術，鍾晶4G錢於電子產品竹未齡）。
0503-A30174TWF 9 200539465 “ 〃請參照第5圖，其係顯示根據本發明方法之製程步驟之流程圖。步驟！， 係先將ic裝置製作於半導體晶圓上。步驟2，係形成連接塾以電性連接忙 裝置與形餘凸上之觸減。步驟3係於觸凸塊上形成保護層薄 板’以於後續散熱座製作過程中保護銲錫凸塊。 步驟4係沉積金屬晶種層於晶圓背面。步驟5於晶種層上層壓並圖案 化-光阻層。步驟6係電鐘金屬於晶種層上以及光阻開口中。步驟7係除 去晶圓上之光阻與保護層。步驟8 晶粒分割製程，縣前形成於晶圓 f之複數個IC W彼此分隔，其巾每—IC “ #面具有散熱座。於步驟9 70成日日片封衣製私’每一1C晶片連接至基板(例如：印刷電路板)並將覆晶 •裝配成電子產品。 曰曰 請參照第6圖，其係顯示根據本發明另一方法之製程步驟之流程圖。 製程步驟1_3與上述第5圖之步驟U相同。然而製程步驟&係沉積金屬 層於晶圓背面。製程步驟兄係沉積一光阻層於金屬層上以圖案化形成光阻 開口來定義散熱通道之尺寸與構造以於後續蝕刻金屬層。製程步驟如係蝕 刻透過光阻開口所露出之部分金屬層以於金屬層中形成網狀散熱通道。而 製程步驟7、8、9與上述第5圖之步驟7、8、9相同。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任 • 何熟習此項技藝者，在不脫離本發明之精神和範圍内，當可作更動與潤飾， 因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 0503-A30174TWF 10 200539465 【圖式簡單說明】 第1A圖係顯示半導體晶圓基板之部份剖面圖， 拇陣列(黯心峨結構之方式傳= 板上之導電層； 連接>儿積於基 背面=係顯示傳之封細統提她 片背^圖係顯示一積體電路覆晶剖面圖，根據本發明其具有散熱座於晶 ㈣係顯示第2一圖之部分區域之忙晶片散熱座的上視圖； 弟4A-4G圖係顯示積體電路霜曰 方法製作散熱座娜背面之連續蝴，細解說雜據本發明 弟5圖係择頁不根據本發明之—方、土] 士 第6圖係顯示根據本發日月之/之連績製程步驟的流程圖； 万法之連續製程步驟的流程圖。 U〜保護層； 15〜介電層； 18〜絕緣層； 22〜導電層； 25〜背面； 28〜基板； 32〜散熱縫； 36〜金屬蓋； 42〜1C晶片； 44a〜圖案化表面； 【主要元件符號說明】 10〜銲錫凸塊； 14〜凸塊墊； 16〜導電層； 20〜導電介層孔； 24〜碎基板； 26〜基板； 30〜散熱座； 34〜塗膠； 40〜覆晶； 44〜半導體晶圓；
0503-A30174TWF 11 200539465 44b〜背面； 48〜凸塊墊； 52〜環氧樹脂； 56〜銲錫凸塊； 60〜光阻層； 64〜散熱通道； 68〜光阻層； 70〜光阻開口； 72〜金屬層； 7 6〜列； 80〜散熱柱寬； 46〜銲錫凸塊； 50〜保護層； 54〜基板； 58〜散熱座； 62〜散熱柱； 66〜保護層薄板； 68a〜厚度， 70a〜寬度； 74〜行； 78〜散熱柱高； 1〜製作裝置於晶圓上； 2〜提供連接墊及銲錫凸塊於晶圓上； 3〜提供保護層於銲錫凸塊上； 4〜沉積金屬晶種層於晶圓背面， 5〜沉積並圖案化光阻層於晶種層上； 6〜電鍍金屬於光阻層開口； 7〜自晶圓上移除光阻層及保護層； 8〜分割晶片， 9〜封裝晶片； 4a〜沉積金屬層於晶背上； 5a〜沉積並圖案化光阻層於金屬層上； 6a〜钱刻散熱通道於金屬層中； 7a〜自金屬層上移除光阻層。 0503-A30174TWF 12

Claims (1)

  1. 200539465 . 十、申請專利範圍： 1. 一種晶背上具有整合散熱座之晶圓級封裝，包括： 半‘體晶圓，具有一晶背以及一圖案化表面； 複數個1C晶片於該晶圓之圖案化表面上；以及 一散熱座於該晶背上以熱傳導每一該汇晶片。 2·如申請專利範圍第丨項所述之晶背上具有整合散熱座之晶圓級封 裝’其中於該晶背之散熱座係利用沉積散熱材料於該晶背上並經由姓刻而 成。 3·如申請專利範圍第1項所述之m具有整合散熱座之晶圓級封 春裝’其巾於該晶背之散熱座包括—金屬晶種層於該晶背以及—金屬層於該 晶種層上。 4.如申請專利範圍第i項所述之晶背上具有整合散熱座之晶圓級封 裝，其找韻座包括概錄胁錢—離散舰道延伸㈣些散熱 柱之間。 5·如申請專利範圍帛】項所述之晶背上具有整合散熱座之晶圓級封 裝，更包括複數個銲錫凸塊於該圖案化表面上以電性接觸該忙晶片。 6. 如申請專利範圍第丨項所述之晶背上具有整合散熱座之晶圓級封 籲裝，其中該散熱座係導熱金屬其擇自由銅、銀以及鈦所組成之族群。 7. 如巾請翻範圍第丨項所述之㈣上具有整合餘座之晶圓級封 裝，其中該複數個該1C晶片係覆晶晶片。 8· —種1C晶片之散熱方法，包括·· 提供一半導體晶圓，具有一晶背以及一圖案化表面； 提供複數個1C晶片於該晶圓上，其係藉由製作積體電路於該圖案化 面上； 〆、 又 形成一散熱座於該晶背上；以及 將每一 1C晶片相互分割，以使該散熱座形成於每一該圯晶片上。 0503-A30174TWF 13 200539465 '9·如帽專利綱第8項所述之1之散熱方法，其中形成該散敎 座於該晶背上包括提供-金屬晶_於該晶背上，然後提供—醉化光阻 層於該晶種層上，再沉積-金屬於該晶種層上以及移除該晶種層上之該光 阻層。 / H).如申請專利範圍第8項所述之IC晶片之散熱方法，其中該散教座 包括複數個散熱柱以及一網狀散熱通道延伸於該些散熱桎之間。 、η•如申請專利範圍第8項所述之IC晶片之散熱方法，其曰中該散熱座係 熱金屬其係擇自由銅、銀以及欽所組成之族群。 /2·如巾請細贿8項所述之1之散熱方法，其中於該散熱 ^ 座係利用沉積散熱材料於該晶背並經由蝕刻而成。 13.如申請專利範圍第8項所述晶片之散熱方法，更包括提供複 數個銲錫凸胁顧案化絲以於職雜熱胁該㈣ 電路電性接觸。 14· 一種1C晶片之散熱方法，包括： 提供一半導體晶圓，具有-晶背以及-圖案化表面； 提供複數個1C晶片於該純上，其係藉由製作積體電路於該圖案 面上； 、 ^ Φ 形成一散熱座於該晶背上.； 將每-1C晶片相互分割，以使該散熱座形成於每一該體電路晶片上； 以及 ’ 封裝每-該1C晶片，其係藉由提供複數個基板並個別連接該此 該些基板上。 U二日日乃主 15.如申請專利範圍第14項所述之1(：晶片之散熱方法， 熱座於該晶背上之方法包括提供—金屬晶種層於該晶背上，然後提 轉除該晶種層 0503-A30174TWF 14 200539465 ‘ 16.如申請專利範圍第14項所述之1C晶片之散熱方法，其中於該晶背 形成散熱座包括於該晶背提供一金屬層並钱刻該金屬層而成。 17.如申請專利範圍第14項所述之1C晶片之散熱方法，其中該散熱座 包括複數個散熱柱以及一網狀散熱通道延伸於該些散熱柱之間。
    0503-A30174TWF 15
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