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SG11201606392UA - High mobility strained channels for fin-based nmos transistors - Google Patents

High mobility strained channels for fin-based nmos transistors

Info

Publication number
SG11201606392UA
SG11201606392UA SG11201606392UA SG11201606392UA SG11201606392UA SG 11201606392U A SG11201606392U A SG 11201606392UA SG 11201606392U A SG11201606392U A SG 11201606392UA SG 11201606392U A SG11201606392U A SG 11201606392UA SG 11201606392U A SG11201606392U A SG 11201606392UA
Authority
SG
Singapore
Prior art keywords
fin
nmos transistors
high mobility
strained channels
based nmos
Prior art date
Application number
SG11201606392UA
Inventor
Stephen M Cea
Roza Kotlyar
Harold W Kennel
Glenn A Glass
Anand S Murthy
Willy Rachmady
Tahir Ghani
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of SG11201606392UA publication Critical patent/SG11201606392UA/en

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/62Fin field-effect transistors [FinFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H10D30/0245Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET] by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/751Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113Isolations within a component, i.e. internal isolations
    • H10D62/115Dielectric isolations, e.g. air gaps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40Crystalline structures
    • H10D62/405Orientations of crystalline planes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82Heterojunctions
    • H10D62/822Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/017Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85Complementary IGFETs, e.g. CMOS
    • H10D84/853Complementary IGFETs, e.g. CMOS comprising FinFETs
SG11201606392UA 2014-03-27 2014-03-27 High mobility strained channels for fin-based nmos transistors SG11201606392UA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2014/032039 WO2015147836A1 (en) 2014-03-27 2014-03-27 High mobility strained channels for fin-based nmos transistors

Publications (1)

Publication Number Publication Date
SG11201606392UA true SG11201606392UA (en) 2016-09-29

Family

ID=54196153

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201606392UA SG11201606392UA (en) 2014-03-27 2014-03-27 High mobility strained channels for fin-based nmos transistors

Country Status (7)

Country Link
US (3) US10153372B2 (en)
EP (1) EP3123518A4 (en)
KR (2) KR20210005324A (en)
CN (1) CN106030818B (en)
SG (1) SG11201606392UA (en)
TW (1) TWI637508B (en)
WO (1) WO2015147836A1 (en)

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US10269968B2 (en) * 2015-06-03 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structures and manufacturing method thereof
US10361219B2 (en) * 2015-06-30 2019-07-23 International Business Machines Corporation Implementing a hybrid finFET device and nanowire device utilizing selective SGOI
US9859430B2 (en) * 2015-06-30 2018-01-02 International Business Machines Corporation Local germanium condensation for suspended nanowire and finFET devices
US9905649B2 (en) * 2016-02-08 2018-02-27 International Business Machines Corporation Tensile strained nFET and compressively strained pFET formed on strain relaxed buffer
CN107104144B (en) * 2016-02-22 2019-12-27 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method for manufacturing the same
US20170250268A1 (en) * 2016-02-25 2017-08-31 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and method for fabricating the same
US9917154B2 (en) 2016-06-29 2018-03-13 International Business Machines Corporation Strained and unstrained semiconductor device features formed on the same substrate
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US11088033B2 (en) * 2016-09-08 2021-08-10 International Business Machines Corporation Low resistance source-drain contacts using high temperature silicides
TW202425084A (en) * 2016-12-12 2024-06-16 美商應用材料股份有限公司 Method of forming strained channel layer
US10340384B2 (en) 2017-11-30 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing fin field-effect transistor device
CN110047926B (en) 2018-01-15 2023-08-29 联华电子股份有限公司 Semiconductor device and manufacturing method thereof
US10665770B2 (en) * 2018-03-06 2020-05-26 Intel Corporation Fin strain in quantum dot devices
US11054748B2 (en) 2018-09-21 2021-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy insertion for improving throughput of electron beam lithography
US11094597B2 (en) * 2018-09-28 2021-08-17 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device with fin structures
CN109671779B (en) * 2018-11-22 2022-05-10 长江存储科技有限责任公司 Semiconductor device and forming method thereof
US11569231B2 (en) 2019-03-15 2023-01-31 Intel Corporation Non-planar transistors with channel regions having varying widths
US11670551B2 (en) 2019-09-26 2023-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Interface trap charge density reduction
DE102020131030A1 (en) 2020-05-12 2021-11-18 Taiwan Semiconductor Manufacturing Co., Ltd. SILICON CHANNEL STARTING
US11670723B2 (en) * 2020-05-12 2023-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon channel tempering
US20230095191A1 (en) * 2021-09-24 2023-03-30 Intel Corporation Transistors with reduced epitaxial source/drain span via etch-back for improved cell scaling
US12261203B2 (en) * 2021-10-14 2025-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device structure with gate stack and method for forming the same

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Also Published As

Publication number Publication date
KR20210005324A (en) 2021-01-13
US10854752B2 (en) 2020-12-01
CN106030818A (en) 2016-10-12
US10153372B2 (en) 2018-12-11
KR20160136296A (en) 2016-11-29
US20190115466A1 (en) 2019-04-18
WO2015147836A1 (en) 2015-10-01
TW201543667A (en) 2015-11-16
KR102201112B1 (en) 2021-01-12
EP3123518A1 (en) 2017-02-01
US20160351701A1 (en) 2016-12-01
CN106030818B (en) 2020-09-01
EP3123518A4 (en) 2017-11-22
TWI637508B (en) 2018-10-01
US20200381549A1 (en) 2020-12-03

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