KR950034626A - 반도체 장치 제조 방법 - Google Patents
반도체 장치 제조 방법 Download PDFInfo
- Publication number
- KR950034626A KR950034626A KR1019950012349A KR19950012349A KR950034626A KR 950034626 A KR950034626 A KR 950034626A KR 1019950012349 A KR1019950012349 A KR 1019950012349A KR 19950012349 A KR19950012349 A KR 19950012349A KR 950034626 A KR950034626 A KR 950034626A
- Authority
- KR
- South Korea
- Prior art keywords
- heat treatment
- melting point
- high melting
- point metal
- inert gas
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (13)
- 표면이 노출된 확산층과 표면이 노출된 폴리실리콘층 중 적어도 한층을 구비한 반도체 기판상에 고융점 금속막을 형성하는 단계와; 상기 고융점 금속이 실리콘과 반응하게 하기 위해 열처리실에서의 가열에 의해 상기 확상층과 상기 폴리실콘층 중 적어도 한 층 상에 고융점 금속 규화물층을 형성하는 단계와; 상기 고융점 금속 규화물의 저 저항성을 위해 열처리실에서의 가열에 의해 상기 확산층 및 상기 폴리실콘층 중 적어도 한 층상에 상기 고융점 금속 규화물층의 상 천이를 유도하는 단계 및; 상기 반도체기판이 상기 열처리실로부터 인출되고 산소를 포함한 환경에 노출되는 온도가 300℃이하로 설정되게 상기 열처리실로부터 상기 반도체 기판을 인출하는 단계를 포함하는 것을 특징으로 하는 반도체장치제조 방법.
- 제1항에 있어서, 상기 열처리가 램프 어니얼링 장치를 사용해서 수행되는 것을 특징으로 하는 반도체 장지 제조 방법.
- 제1항에 있어서, 상기 열처리가 불활성 가스환경에서나 또는 진공 상태에서수행되는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제3항에 있어서, 상기 열처리가 불활성 가스가 질소인 것을 특징으로 하는 반도체 장치 제조 방법.
- 제3항에 있어서, 상기 불활성 가스가 알곤인 것을 특징으로 하는 반도체 장치 제조 방법.
- 제2항에 있어서, 상기 열처리가 불활성 가스 환경에서나 또는 진공 상태에서 수행되는 것을 특징으로 하는 반도체 장치 제조 방법.
- 표면이 노출된 확산층과 표면이 노출된 폴리실리콘층 중 적어도 한층을 구비한 반도체 기판상에 고융점 금속막을 형성하는 단계와; 상기 고융점 금속이 실리콘과 반응하게 하기 위해 열처리실에서의 가열에 의해 상기 확산층 및 상기 폴리실리콘층 중 적어도 한 층상에 고융점 금속 규화물층을 형성하는 단계 및: 상기 반도체 기판이 상기 열처리실로부터 인출되고 산소를 포함하는 환경에 노출되는 온도가 300℃이하로 설정되게 상기 열처리실로부터 상기 반도체기판을 인출하는 단계를 포함하는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제6항에 있어서, 상기 열처리가 램프 어니얼링 장치를 사용하여 수행되는 것을 특징으로하는 반도체 장치 제조 방법.
- 제6항에 있어서, 상기 열처리가 불활성 가스 환경에서나 또는 진공 상태에서 수행되는 것을 특징으로하는 반도체 장치 제조 방법.
- 제8항에 있어서, 상기 불활성 가스가 질소 또는 알곤인 것을 특징으로 하는 반도체 장치 제조 방법.
- 제7항에 있어서, 상기 열처리가 불활성 가스환경에서나 또는 진공 상태에서 수행되는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제1항에 있어서, 상기 고융점 금속막이 티타늄으로 만들어지는 것을 특징으로 하는 반도체 장치 제조 방법.
- 제6항에 있어서, 상기 고융점 금속막이 티타늄으로 만들어지는 것을 특징으로 하는 반도체 장치 제조 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP94-128095 | 1994-05-19 | ||
JP6128095A JP2713165B2 (ja) | 1994-05-19 | 1994-05-19 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950034626A true KR950034626A (ko) | 1995-12-28 |
KR100196974B1 KR100196974B1 (ko) | 1999-06-15 |
Family
ID=14976278
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950012349A KR100196974B1 (ko) | 1994-05-19 | 1995-05-18 | 반도체 장치 제조 방법 |
Country Status (3)
Country | Link |
---|---|
US (1) | US5883003A (ko) |
JP (1) | JP2713165B2 (ko) |
KR (1) | KR100196974B1 (ko) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20190064517A (ko) * | 2017-11-30 | 2019-06-10 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 막의 가변 온도 어닐링 및 이것에 의해 형성된 구조체 |
US11244823B2 (en) | 2017-11-30 | 2022-02-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Varying temperature anneal for film and structures formed thereby |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0974195A (ja) * | 1995-07-06 | 1997-03-18 | Mitsubishi Electric Corp | 半導体装置および半導体装置の製造方法 |
KR19980051516A (ko) * | 1996-12-23 | 1998-09-15 | 김영환 | 반도체소자의 워드라인 형성방법 |
KR100443352B1 (ko) * | 1996-12-30 | 2004-10-14 | 주식회사 하이닉스반도체 | 반도체장치의실리사이드막형성방법 |
KR100430687B1 (ko) * | 1996-12-31 | 2004-08-02 | 주식회사 하이닉스반도체 | 반도체소자의금속배선형성방법 |
KR100266328B1 (ko) * | 1997-12-23 | 2000-10-02 | 김규현 | 티타늄실리사이드형성방법및이를이용한티타늄실리사이드의형성온도보정방법 |
KR100528451B1 (ko) * | 1998-04-06 | 2006-01-27 | 삼성전자주식회사 | 리플로우 장치 및 이 장치를 사용한 반도체 웨이퍼의 열처리 방법 |
JP4585464B2 (ja) * | 1998-12-24 | 2010-11-24 | 株式会社東芝 | 半導体装置の製造方法 |
US6214679B1 (en) * | 1999-12-30 | 2001-04-10 | Intel Corporation | Cobalt salicidation method on a silicon germanium film |
JP2003253482A (ja) * | 2002-03-01 | 2003-09-10 | Ngk Insulators Ltd | チタン系膜及びチタン酸化物の除去方法 |
US7153772B2 (en) | 2003-06-12 | 2006-12-26 | Asm International N.V. | Methods of forming silicide films in semiconductor devices |
US7015076B1 (en) * | 2004-03-01 | 2006-03-21 | Advanced Micro Devices, Inc. | Selectable open circuit and anti-fuse element, and fabrication method therefor |
JP5581642B2 (ja) * | 2009-10-05 | 2014-09-03 | 住友電気工業株式会社 | 半導体装置の製造方法 |
CN101964220A (zh) * | 2010-08-13 | 2011-02-02 | 江西赛维Ldk太阳能高科技有限公司 | 一种多晶硅氢化炉用的绝缘材料 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4109372A (en) * | 1977-05-02 | 1978-08-29 | International Business Machines Corporation | Method for making an insulated gate field effect transistor utilizing a silicon gate and silicide interconnection vias |
JPS5834916A (ja) * | 1981-08-25 | 1983-03-01 | Toshiba Corp | 半導体装置の製造方法 |
JPH01205446A (ja) * | 1988-02-10 | 1989-08-17 | Nec Corp | 半導体装置の製造方法 |
US5231038A (en) * | 1989-04-04 | 1993-07-27 | Mitsubishi Denki Kabushiki Kaisha | Method of producing field effect transistor |
JP2508851B2 (ja) * | 1989-08-23 | 1996-06-19 | 日本電気株式会社 | 液晶表示素子用アクティブマトリクス基板とその製造方法 |
US5266136A (en) * | 1989-12-19 | 1993-11-30 | Canon Kabushiki Kaisha | Process for producing a roll stamper for molding a substrate sheet for information recording mediums |
JP2984068B2 (ja) * | 1991-01-31 | 1999-11-29 | 株式会社日立製作所 | 半導体装置の製造方法 |
KR100214036B1 (ko) * | 1991-02-19 | 1999-08-02 | 이데이 노부유끼 | 알루미늄계 배선형성방법 |
US5086017A (en) * | 1991-03-21 | 1992-02-04 | Industrial Technology Research Institute | Self aligned silicide process for gate/runner without extra masking |
US5180689A (en) * | 1991-09-10 | 1993-01-19 | Taiwan Semiconductor Manufacturing Company | Tapered opening sidewall with multi-step etching process |
US5240880A (en) * | 1992-05-05 | 1993-08-31 | Zilog, Inc. | Ti/TiN/Ti contact metallization |
US5352631A (en) * | 1992-12-16 | 1994-10-04 | Motorola, Inc. | Method for forming a transistor having silicided regions |
-
1994
- 1994-05-19 JP JP6128095A patent/JP2713165B2/ja not_active Expired - Lifetime
-
1995
- 1995-04-25 US US08/428,673 patent/US5883003A/en not_active Expired - Lifetime
- 1995-05-18 KR KR1019950012349A patent/KR100196974B1/ko not_active IP Right Cessation
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20190064517A (ko) * | 2017-11-30 | 2019-06-10 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 막의 가변 온도 어닐링 및 이것에 의해 형성된 구조체 |
US10748760B2 (en) | 2017-11-30 | 2020-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Varying temperature anneal for film and structures formed thereby |
US11244823B2 (en) | 2017-11-30 | 2022-02-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Varying temperature anneal for film and structures formed thereby |
US11715637B2 (en) | 2017-11-30 | 2023-08-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Varying temperature anneal for film and structures formed thereby |
US12176206B2 (en) | 2017-11-30 | 2024-12-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Varying temperature anneal for film and structures formed thereby |
Also Published As
Publication number | Publication date |
---|---|
US5883003A (en) | 1999-03-16 |
JPH07321066A (ja) | 1995-12-08 |
KR100196974B1 (ko) | 1999-06-15 |
JP2713165B2 (ja) | 1998-02-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR950034626A (ko) | 반도체 장치 제조 방법 | |
US5093710A (en) | Semiconductor device having a layer of titanium nitride on the side walls of contact holes and method of fabricating same | |
KR930018648A (ko) | 반도체 장치 제조방법 | |
JPS61142739A (ja) | 半導体装置の製造方法 | |
KR890002999A (ko) | 드라이에칭 방법과 그 방법에 사용되는 장치 | |
KR960005801A (ko) | 반도체 장치 제조방법 | |
JP2751223B2 (ja) | 半導体装置およびその製造方法 | |
KR940010194A (ko) | 반도체장치의 배선층 형성방법 | |
KR950001931A (ko) | 반도체 기판의 열처리 방법 | |
KR940020550A (ko) | 반도체장치의 제조방법 | |
JP2752457B2 (ja) | 半導体装置の製造方法 | |
KR0171948B1 (ko) | 반도체 소자의 장벽 금속 형성방법 | |
KR960026384A (ko) | 반도체 장치의 티타늄 실리사이드층 형성방법 | |
JP2008066436A (ja) | 半導体素子とその製造方法 | |
KR950021102A (ko) | 반도체 소자의 금속배선 형성방법 | |
KR960002881A (ko) | 반도체 소자의 비.피.에스.지 막 제조방법 | |
KR980005545A (ko) | 반도체 소자의 제조방법 | |
KR970063484A (ko) | 반도체 소자의 베리어 금속층 형성방법 | |
JPS63133622A (ja) | 半導体装置の製造方法 | |
KR870009448A (ko) | 박막형성방법 | |
KR19990002644A (ko) | 반도체 소자의 폴리사이드 게이트 형성 방법 | |
KR970052107A (ko) | 반도체 장치의 제조 방법 | |
KR910010629A (ko) | 금속 배선막 형성방법 | |
KR980005455A (ko) | 반도체 소자의 게이트 전극 형성 방법 | |
KR970060363A (ko) | 반도체 소자의 확산 방지막 형성 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19950518 |
|
PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19950518 Comment text: Request for Examination of Application |
|
PG1501 | Laying open of application | ||
E902 | Notification of reason for refusal | ||
PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 19980528 Patent event code: PE09021S01D |
|
E701 | Decision to grant or registration of patent right | ||
PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 19981130 |
|
GRNT | Written decision to grant | ||
PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 19990223 Patent event code: PR07011E01D |
|
PR1002 | Payment of registration fee |
Payment date: 19990224 End annual number: 3 Start annual number: 1 |
|
PG1601 | Publication of registration | ||
PR1001 | Payment of annual fee |
Payment date: 20020214 Start annual number: 4 End annual number: 4 |
|
FPAY | Annual fee payment |
Payment date: 20030206 Year of fee payment: 5 |
|
PR1001 | Payment of annual fee |
Payment date: 20030206 Start annual number: 5 End annual number: 5 |
|
LAPS | Lapse due to unpaid annual fee | ||
PC1903 | Unpaid annual fee |
Termination category: Default of registration fee Termination date: 20050111 |