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KR930022510A - 테스트 접촉부만을 가지는 반도체 장치 제조 방법 - Google Patents

테스트 접촉부만을 가지는 반도체 장치 제조 방법

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Publication number
KR930022510A
KR930022510A KR1019930005518A KR930005518A KR930022510A KR 930022510 A KR930022510 A KR 930022510A KR 1019930005518 A KR1019930005518 A KR 1019930005518A KR 930005518 A KR930005518 A KR 930005518A KR 930022510 A KR930022510 A KR 930022510A
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South Korea
Prior art keywords
pads
package substrate
test
semiconductor device
semiconductor die
Prior art date
Application number
KR1019930005518A
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English (en)
Inventor
제이. 멘니트 티모시
피. 워런 존
더블유. 슬로안 제임스
Original Assignee
빈센트 비. 인그라시아
모토로라 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 빈센트 비. 인그라시아, 모토로라 인코포레이티드 filed Critical 빈센트 비. 인그라시아
Publication of KR930022510A publication Critical patent/KR930022510A/ko

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    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
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    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2924/153—Connection portion
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

반도체 장치는 불필요한 외부 접촉부를 제거하며 장치의 크기를 축소하도록 테스트 접촉부만을 가진다. 본 발명의 한 형태에 있어서, 반도체 장치(30)는 장치 작동을 위해 필요한 반도체 다이(20)의 그 부분에 전기연결된 솔더볼(26)을 제공한다. 이 장치는 또한 단지 제조업자의 테스트 용도만을 위해 필요한 다이의 그 부분에 전기 연결된 패키지 기판(12)위에 형성된 테스트 패드(32)를 포함한다. 다른 형태에 있어서, 반도체 장치(10)는 예를 들면, 경계(A,B)사이의 솔더볼인, 패키지 기판의 주변부를 따라서 외부 테스트 솔더볼만을 포함한다. 테스팅이 완료된 후에, 이 패키지 기판은 경계 A를 따라서 절단되므로서, 장치 사용자에게는 필요치 않는 솔더 볼을 제거한다. 상기 두 기술의 조합도 사용될 수 있다.

Description

테스트 접촉부만을 가지는 반도체 장치 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 오우버-몰드 패드 어레이 캐리어(over-molded pad array carrier, OMPAC)반도체 장치의 평면도.
제2도는 제1도의 반도체 장치의 배면도.
제3도는 3-3라인을 따라 취한 제1도의 반도체 장치의 횡단면도.
제4도는 본 발명에 따른 경계A를 따라서 패키지 기판 스트립으로부터 절단 되어진 후의 제1도의 반도체 장치의 사시도.
제5도는 상부측 테스트 패드를 포함하는 본 발명에 따른 OMPAC 반도체 장치의 평면도.

Claims (2)

  1. 테스트 접촉부만을 가지는 반도체 장치(10,30,50)제조 방법에 있어서, 집적 회로와 집적 회로에 전기 연결된 다수의 본드 패드를 반도체 다이(20)를 제공하는 단계와, 상부 표면 및 하부 표면을 가지며 복수의 작동 접촉부 및 복수의 테스트 접촉부만을 가지는 패키지 기판 재료(12)를 제공하는 단계와, 상기 패키지 기판의 상부 표면상에 반도체 다이를 장착하는 단계와, 상기 반도체 다이의 복수의 본드 패드를 복수의 작동 접촉부 및 복수의 테스트 접촉부만 전기 연결하기 위한 수단(23)을 제공하는 단계와, 상기 패키지 기판의 상부 표면 일부분 및 반도체 다이를 캡슐화시키는 단계와, 핀(58) 또는 솔더 볼(26)중의 어느 하나를 각각 복수의 작동 접촉부에만 부착시키는 단계를 포함하는 것을 특징으로 하는 반도체 장치 제조 방법.
  2. 테스트 접촉부만을 가지는 반도체 장치(10, 30) 제조방법에 있어서, 다이위에 형성된 집적 회로를 가지하는 반도체 다이(20)를 제공하는 단계와, 상부 표면, 하부 표면, 예비 결정된 경계(A)를 가지는 어레이내에 배열된 복수의 작동 패드와, 사용자 패드의 어레이의 경계 외부에 배열된 복수 텍스트 패드만을 가지는 패키지 기판(12)을 제공하는 단계와, 상기 패키지 기판의 상부표면상에 반도체 다이를 위치 설정하는 단계와, 상기 반도체 다이를 복수의 작동 패드 및 복수의 테스트 패드만을 전기 연결시키기 위한 수단(23)을 제공하는 단계와, 적어도 복수의 테스트 패드만을 사용하여 집적회로를 전기 테스트 하는 단계와, 복수의 작동 패드를 그대로 놔둔채 복수의 태스트 패드만을 가지는 패키지 기판 부분을 제거시키는 단계를 포함하는 것을 특징으로 하는 테스트 접촉부만을 가지는 반도체 장치 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930005518A 1992-04-06 1993-03-31 테스트 접촉부만을 가지는 반도체 장치 제조 방법 KR930022510A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US864,246 1992-04-06
US07/864,246 US5334857A (en) 1992-04-06 1992-04-06 Semiconductor device with test-only contacts and method for making the same

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KR930022510A true KR930022510A (ko) 1993-11-24

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EP (1) EP0564865A1 (ko)
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