KR20250029817A - Magnetic random access memory device - Google Patents

Abstract

A magnetoresistive memory device with reduced power consumption and improved performance is provided. A magnetoresistive memory device including a read circuit for sensing data stored in a plurality of memory cells, wherein the read circuit includes a sense amplifier, first and second transistors, a first switch for short-circuiting between a first node and a second node, a second switch for short-circuiting between the first node and a third node, a third transistor for receiving a first read current and having one end connected to one of the plurality of memory cells, a fourth transistor for receiving a second read current and having one end connected to a reference resistor, a fifth transistor for receiving the first read current and having one end connected to the reference resistor, and a sixth transistor for receiving the second read current and having one end connected to one of the plurality of memory cells, and provides a first voltage formed at the second node and a second voltage formed at the third node to the sense amplifier.

Description

{MAGNETIC RANDOM ACCESS MEMORY DEVICE}

The present disclosure relates to a magnetoresistive memory device.

Recently, the demand for reliability, high-speed operation, and low power consumption of memory devices has been increasing. To meet these demands, a type of random access memory, magnetic random access memory (MRAM), has been proposed. MRAM has been attracting attention as a next-generation semiconductor memory device because it has characteristics such as high-speed operation and non-volatility.

In general, MRAM can store data using a magnetic tunnel junction (MTJ) element. The magnetic tunnel junction element can include two magnetic materials and an insulating film interposed therebetween. The resistance value of the magnetic tunnel junction element can vary depending on the magnetization directions of the two magnetic materials. For example, if the magnetization directions of the two magnetic materials are antiparallel, the magnetic tunnel junction element can have a large resistance value, and if the magnetization directions of the two magnetic materials are parallel, the magnetic tunnel junction element can have a small resistance value. MRAM can write and read data by utilizing the difference in the resistance value.

In addition, AI applications that process large amounts of data have recently emerged, and AI processors that perform AI applications predominantly perform read operations on memory devices due to the nature of AI applications. Therefore, research is being conducted on memory devices that can perform fast read operations while consuming low power during continuous read operations, which are highly utilized in AI applications or similar work environments.

The problem to be solved by the present invention is to provide a magnetoresistive memory device with reduced power consumption and improved performance during continuous read operation.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

According to some embodiments of the present disclosure for achieving the above-described problem, a magneto-resistive memory device includes a read circuit for sensing data stored in a plurality of memory cells, wherein the read circuit includes a sense amplifier for amplifying a difference between voltages received, a first transistor having one end connected to a power supply voltage terminal and receiving a first read current, a second transistor having one end connected to the power supply voltage terminal and receiving a second read current, a first switch for short-circuiting between a first node connected to gate terminals of the first and second transistors and a second node connected to the other end of the first transistor, a second switch for short-circuiting between the first node and a third node connected to the other end of the second transistor, a third transistor for receiving the first read current and having one end connected to one of the plurality of memory cells, a fourth transistor for receiving the second read current and having one end connected to a reference resistor, a fifth transistor for receiving the first read current and having one end connected to the reference resistor, and a sixth transistor for receiving the second read current and having one end connected to one of the plurality of memory cells, and a first voltage formed at the second node and a second voltage formed at the third node. Provides voltage to the sense amplifier.

Specific details of other embodiments are included in the detailed description and drawings.

Figure 1 is a block diagram illustrating a nonvolatile memory device.
Figure 2 is a drawing for explaining a memory cell.
FIGS. 3 and 4 are drawings for explaining data stored according to the magnetization direction of the memory cell of FIG. 2.
Figure 5 is a distribution diagram for explaining the reference resistance value of a memory cell.
Figure 6 is a circuit diagram for explaining a data read method of a memory cell.
Figure 7 is a circuit diagram explaining the lead circuit.
Figure 8 is a graph for explaining the voltage development time according to the operation of the lead circuit shown in Figure 7.
Figure 9 is a circuit diagram for explaining the lead circuit.
Fig. 10 is a graph for explaining the voltage development time according to the operation of the lead circuit shown in Fig. 9.
Figure 11 is a circuit diagram for explaining the lead circuit.
Fig. 12 is a circuit diagram for explaining the first lead operation of the lead circuit of Fig. 11.
Fig. 13 is a circuit diagram for explaining the second lead operation of the lead circuit of Fig. 11.
Figure 14 is a graph showing the magnitude of the first voltage and the second voltage over time.
Fig. 15 is a graph for explaining the voltage development time according to the operation of the lead circuit shown in Fig. 11.

Hereinafter, embodiments according to the technical idea of the present invention will be described with reference to the attached drawings.

Figure 1 is a block diagram illustrating a nonvolatile memory device.

Referring to FIG. 1, a memory system (1) may include a nonvolatile memory device (100) and a host (200). The nonvolatile memory device (100) may read or write data according to a request from the host (200).

Specifically, the nonvolatile memory device (100) can receive a command (CMD) and an address (ADDR) from the host (200). The command (CMD) can include a read command, a write command, etc. When the host (200) transmits a read command to the nonvolatile memory device (100), the nonvolatile memory device (100) can provide data (DATA) read from the memory cell array (110) to the host (200).

When the host (200) transmits a write command and data (DATA) to be written to the nonvolatile memory device (100), the nonvolatile memory device (100) can write the data (DATA) provided from the host (200) to the memory cell array (110).

A nonvolatile memory device (100) may include a memory cell array (110), an address decoder circuit (120), a bit line selection circuit (130), a write circuit (140), a read circuit (150), a data input/output circuit (160), and a control logic circuit (180). Of course, such a configuration is only exemplary, and some components may be omitted or new components may be added depending on a specific implementation purpose.

The memory cell array (110) may include a plurality of nonvolatile memory cells (MC) for storing data. The memory cells (MC) may include variable resistance elements, such as magnetic tunnel junction (MTJ) elements, having a resistance value corresponding to the value of stored data.

In some embodiments, the nonvolatile memory device (100) may be referred to as a resistive memory device, a resistive random access memory (RRAM) (or ReRAM) device. For example, the memory cell array (110) of the nonvolatile memory device (100) may include a structure such as a phase change random access memory (PRAM), a ferroelectric random access memory (FRAM), or a magnetic random access memory (MRAM) structure such as a spin-transfer torque magnetic random access memory (STT-MRAM), a spin-orbit torque magnetic random access memory (SOT-MRAM), or the like.

In the following, the nonvolatile memory device (100) will be described as an example of a magnetoresistive memory (MRAM) device, but the embodiments are not limited thereto.

The memory cell array (110) may include one or more memory cells (MC) in which data is recorded. Specifically, the memory cell array (110) may include memory cells (MC) arranged at points where a plurality of word lines (WL) and a plurality of bit lines (BL) correspond. A more specific description of these memory cells will be described later.

In some embodiments, the memory cell array (110) may include one or more sub-memory cell arrays, although not illustrated in detail, each of which includes a certain number of memory cells (MC). That is, a plurality of sub-memory cell arrays, each of which includes a certain number of memory cells (MC) and word lines (WL) and bit lines (BL) for controlling the memory cells (MC), may be assembled to form the illustrated memory cell array (110).

In some embodiments, these sub-memory cell arrays may be used as units for reading or writing data (DATA) from the host (200). In some embodiments, the nonvolatile memory device (100) may write or read data in units of four sub-memory cell arrays (e.g., memory bank units). However, the embodiments are not limited thereto, and may be modified and implemented as needed.

The address decoder circuit (120) can receive an address (ADDR) and decode it into a row address (raw address) and a column address. The address decoder circuit (120) can select one word line (WL) among a plurality of word lines (WL) according to the row address. In addition, in some embodiments, the address decoder circuit (120) can transmit a column address to a bit line selection circuit (130). For example, the address decoder circuit (120) can include components such as a row decoder, a column decoder, an address buffer, etc.

The bit line selection circuit (130) is connected to the memory cell array (110) through bit lines, and can be connected to the write circuit (140) and the read circuit (150). The bit line selection circuit (130) can operate in response to the control of the control logic circuit (180). The bit line selection circuit (130) can be configured to receive a decoded column address from the address decoder circuit (120).

Additionally, the bit line selection circuit (130) can select bit lines using the decoded column address. For example, during a write operation, the bit line selection circuit (130) can connect the selected bit lines (BL) to the data lines (DL) and thereby connect them to the write circuit (140). During a read operation, the bit line selection circuit (130) can connect the selected bit lines to the read circuit (150).

The light circuit (140) can operate under the control of the control logic circuit (180). The light circuit (140) can program the memory cells (MC) connected to the bit lines (BL) selected by the bit line selection circuit (130) and the word lines (WL) selected by the address decoder circuit (120). The light circuit (140) can generate current or voltage according to data input from the data input/output circuit (160) and output it to the selected bit lines (BL).

The lead circuit (150) can operate under the control of the control logic circuit (180). The lead circuit (150) can detect the bit lines (BL) selected by the bit line selection circuit (130) and the memory cells (MC) connected to the word lines selected by the address decoder circuit (120).

The read circuit (150) can read the memory cell (MC) by detecting the current flowing through the selected bit lines (BL) or the voltage applied to the selected bit lines (BL). The read circuit (150) can output the read data to the data input/output circuit (160).

The data input/output circuit (160) can operate under the control of the control logic circuit (180). The data input/output circuit (160) can transmit data input from the outside to the light circuit (140) and output data input from the read circuit (150) to the outside.

The control logic circuit (180) can control the overall operation of the nonvolatile memory device (100). For example, the control logic circuit (180) can control an address decoder circuit (120), a bit line selection circuit (130), a write circuit (140), a read circuit (150), a data input/output circuit (160), etc. Meanwhile, the control logic circuit (180) can operate in response to commands or control signals input from the outside.

Fig. 2 is a drawing for explaining a memory cell. Figs. 3 and 4 are drawings for explaining data stored according to the magnetization direction of the memory cell of Fig. 2.

Referring to FIG. 2, a memory cell (MC) may include a magnetic tunnel junction (MTJ) element and a cell transistor (CT). A gate of the cell transistor (CT) may be connected to a word line (WL). One electrode of the cell transistor (CT) may be connected to a bit line (BL) through the magnetic tunnel junction (MTJ) element. Additionally, the other electrode of the cell transistor (CT) may be connected to a source line (SL).

In some embodiments, the extension direction of the word line (WL) and the extension direction of the source line (SL) may be the same as each other, but the embodiments are not limited thereto. Meanwhile, in some other embodiments, the extension direction of the word line (WL) and the extension direction of the bit line (BL) may be perpendicular to each other, but the embodiments are not limited thereto.

A magnetic tunnel junction (MTJ) device may include a free layer (L1), a fixed layer (L3), and a barrier layer (L2) positioned therebetween. The magnetization direction of the fixed layer (L3) is fixed, and the magnetization direction of the free layer (L1) may be the same as or opposite to the magnetization direction of the fixed layer (L3) depending on conditions. In order to fix the magnetization direction of the fixed layer (L3), the magnetic tunnel junction (MTJ) device may further include an anti-ferromagnetic layer.

In some embodiments, the free layer (L1) may include a material having a changeable magnetization direction. The magnetization direction of the free layer (L1) may be changed by an electrical or magnetic factor provided from outside or inside the memory cell (MC). The free layer (L1) may include a ferromagnetic material including at least one of cobalt (Co), iron (Fe), and nickel (Ni). For example, the free layer (L1) may include at least one selected from FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, and Y3Fe5O12.

Meanwhile, the barrier layer (L2) may have a thickness thinner than the spin diffusion distance. The barrier layer (L2) may include a non-magnetic material. For example, the barrier layer (L2) may include at least one selected from oxides of magnesium (Mg), titanium (Ti), aluminum (Al), magnesium-zinc (MgZn), and magnesium-boron (MgB), and nitrides of titanium (Ti) and vanadium (V).

Meanwhile, the fixed layer (L3) may have a magnetization direction fixed by the antiferromagnetic layer. In addition, the fixed layer (L3) may include a ferromagnetic material. For example, the fixed layer (L3) may include at least one selected from CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, and Y3Fe5O12.

In some embodiments, the antiferromagnetic layer can include an anti-ferromagnetic material. For example, the antiferromagnetic layer can include at least one selected from PtMn, IrMn, MnO, MnS, MnTe, MnF2, FeCl2, FeO, CoCl2, CoO, NiCl2, NiO, and Cr.

During a read operation for a memory cell (MC), a high level (e.g., a logic high level) voltage may be provided to a word line (WL). At this time, a cell transistor (CT) may be turned on in response to the word line (WL) voltage. In addition, a read current (IREAD) may be provided from a bit line (BL) toward a source line (SL), or from the source line (SL) toward the bit line (BL), in order to measure a resistance value of a magnetic tunnel junction (MTJ) element. Data stored in the magnetic tunnel junction (MTJ) element may be determined according to the measured resistance value.

Meanwhile, the resistance value of the magnetic tunnel junction (MTJ) element varies depending on the magnetization direction of the free layer (L1). When a read current (IREAD) is supplied to the magnetic tunnel junction (MTJ) element, a data voltage is output according to the resistance value of the magnetic tunnel junction (MTJ) element. Since the intensity of the read current (IREAD) is much smaller than that of the write current, the magnetization direction of the free layer (L1) generally does not change due to the read current (IREAD).

Referring to FIG. 3 together, in some embodiments, the magnetization direction of the free layer (L1) of the magnetic tunnel junction (MTJ) element and the magnetization direction of the pinned layer (L3) may be arranged to be parallel (P). In this case, the magnetic tunnel junction (MTJ) element has a low resistance value (R_P). In this case, the data may be determined as, for example, '0'.

In contrast, referring also to FIG. 4, in some embodiments, the magnetization direction of the free layer (L1) of the magnetic tunnel junction (MTJ) element is arranged anti-parallel (AP) with respect to the magnetization direction of the pinned layer (L3). In this case, the magnetic tunnel junction (MTJ) element has a high resistance value (R_AP). In this case, the data can be determined as, for example, '1'.

Meanwhile, in FIG. 2, the free layer (L1) and the pinned layer (L3) of the magnetic tunnel junction (MTJ) device are illustrated as horizontal magnetic elements, but the embodiments are not limited thereto. In some other embodiments, the free layer (L1) and the pinned layer (L3) may be provided in the form of vertical magnetic elements.

Figure 5 is a distribution diagram for explaining the reference resistance value of a memory cell.

Fig. 5 shows a distribution of memory cells according to resistance values. Referring to Fig. 5, a reference resistance value (R_REF) for distinguishing data "0" and data "1" can be determined between a first resistance value (R_P) and a second resistance value (R_AP). Here, the first resistance value (R_P) corresponds to a resistance value of a memory cell (MC) when the magnetization direction of a free layer (L1) and the magnetization direction of a fixed layer (L3) in a magnetic tunnel junction (MTJ) device are parallel, and the second resistance value (R_AP) corresponds to a resistance value when the magnetization direction of the free layer (L1) of the magnetic tunnel junction (MTJ) device is antiparallel to the magnetization direction of the fixed layer (L3).

Figure 6 is a circuit diagram for explaining a data read method of a memory cell.

Referring to FIG. 6, in order to read data in the memory cell (MC), in other words, in order to sense the logic state of the memory cell (MC), a first read current (Iread1) may be applied to the memory cell (MC). By applying the first read current (Iread1) to the memory cell (MC), a data voltage (VDATA) may be developed across both ends of the memory cell (MC). In addition, a second read current (Iread2) having the same magnitude as the first read current (Iread1) may be applied to the reference resistor (Rref). By applying the second read current (Iread2) to the reference resistor (Rref), a reference voltage (VREF) may be developed across both ends of the reference resistor (Rref). The sense amplifier (151) may receive the data voltage (VDATA) and the reference voltage (VREF), and may determine the logic state of the memory cell (MC) by comparing the data voltage (VDATA) and the reference voltage (VREF).

Figure 7 is a circuit diagram explaining the lead circuit.

Referring to FIG. 7, the read circuit (150a) may include a first transistor (MP11) and a second transistor (MP12). The first and second transistors (MP11, MP12) may receive a first signal (S1) through their gate terminals. When a read operation of the memory cell (MC) is initiated, the first signal (S1) may turn on the first and second transistors (MP11, MP12) to provide read currents (Iread1, Iread2) to the memory cell (MC) and the reference resistor (Rref), respectively. The read circuit (150a) may further include a third transistor (MP13) and a fourth transistor (MP14). The fourth transistor (MP14) may have a gate terminal and a source/drain terminal that form a diode connection. Since the gate terminal and the source/drain terminal of the fourth transistor (MP14) form a diode connection, the third and fourth transistors (MP13, MP14) can form current mirrors. As a result, the sizes of the first and second read currents (Iread1, Iread2) flowing through the third and fourth transistors (MP13, MP14), respectively, can be substantially the same.

The third transistor (MP13) can be connected to the fifth transistor (MN11). The fourth transistor (MP14) can be connected to the sixth transistor (MN12). A first node (N11) can be formed between the third and fifth transistors (MP13, MN11). The third and fifth transistors (MP13, MN11) can be connected through the first node (N11). A second node (N12) can be formed between the fourth and sixth transistors (MP14, MN12). The fourth and sixth transistors (MP14, MN12) can be connected through the second node (N12). The fifth and sixth transistors (MN11, MN12) can receive a clamp voltage (VCLAMP) through their gate terminals. The clamp voltage (VCLAMP) can limit the size of the read current (Iread1, Iread2) to prevent the read current from modulating the magnetization direction of the magnetic tunnel junction (MTJ) element and disturbing the data stored in the memory cell.

The fifth transistor (MN11) can be connected to the seventh transistor (MN13). The sixth transistor (MN12) can be connected to the eighth transistor (MN14). The seventh transistor (MN13) can be connected to the memory cell (MC) through the bit line (BL1). The eighth transistor (MN14) can be connected to the reference resistor (Rref) through the bit line (BL2). The seventh and eighth transistors (NN13, MN14) can receive a second signal (S2) through their gate terminals. The second signal (S2) can be a signal that inverts the first signal (S1). When a read operation of the memory cell (MC) is initiated, the second signal (S2) can turn on the seventh and eighth transistors (NN13, MN14) to provide read currents (Iread1, Iread2) to the memory cell (MC) and the reference resistor (Rref), respectively.

A first read current (Iread1) may be applied to a memory cell (MC), so that a data voltage (VDATA) may be developed at a first node (N11). In addition, a second read current (Iread2) may be applied to a reference resistor (Rref), so that a reference voltage (VREF) may be developed at a second node (N12). A sense amplifier (151 of FIG. 6) may compare the data voltage (VDATA) formed at the first node (N11) with the reference voltage (VREF) formed at the second node (N12).

Figure 8 is a graph for explaining the voltage development time according to the operation of the lead circuit shown in Figure 7.

In the graph of Fig. 8, the X-axis represents time (in nanoseconds), and the Y-axis represents the bit error rate. Referring to Fig. 8, when the magnetic junction tunnel (MTJ) element is in the P (Parallel) state, the memory cell has a relatively low resistance value, and the magnitude of the voltage developed on the bit line can be relatively small. When the magnetic junction tunnel (MTJ) element is in the AP (Anti-Parallel) state, the memory cell has a relatively high resistance value, and the magnitude of the voltage developed on the bit line can be relatively large. That is, the time taken to develop the voltage on the bit line can be longer when the magnetic junction tunnel (MTJ) element is in the AP state than when it is in the P state ( .

In order to accurately sense data stored in a memory cell, the data voltage on the bit line needs to be sufficiently large to be comparable to the reference voltage. In other words, the time taken to develop the bit line can be defined as the time taken for the data voltage or reference voltage on the bit line to develop until a target bit error rate (10 ^-5 BER) can be secured. In order to secure the target bit error rate (10 ^-5 BER), for example, it may take about 2.6 ns when the magnetic tunnel junction (MTJ) element is in the AP state (tdev_ap) and about 1.1 ns when it is in the P state (tdev_p). The time taken to develop the voltage on the bit line in a read operation can account for a large proportion of the total read operation time. Therefore, it is necessary to reduce the time taken to develop the voltage on the bit line in order to improve the performance of the read operation. In addition, the total voltage development time in the read operation is based on the case where the magnetic tunnel junction (MTJ) element is in the AP state, which is a case that takes a longer time. Therefore, there is a need to alleviate the imbalance in the voltage development time when the magnetic tunnel junction (MTJ) device is in the AP state and the P state.

Figure 9 is a circuit diagram for explaining the lead circuit.

In Fig. 9, a detailed description of the overlapping content with Fig. 7 will be omitted. Referring to Fig. 9, the read circuit (150b) may further include an equalizing switch (SW_EQ). When the equalizing switch (SW_EQ) is closed, a short circuit may occur between the first node (N21) and the second node (N22). When the read operation of the memory cell (MC) is initiated, the equalizing switch (SW_EQ) may be closed during the equalizing time. Assuming that continuous read operations are performed, when the read operation of the memory cell (MC) is initiated, the equalizing switch (SW_EQ) may provide the reference voltage (VREF) formed in the previous read operation to the first node (N21).

Fig. 10 is a graph for explaining the voltage development time according to the operation of the lead circuit shown in Fig. 9.

In the graph of Fig. 10, the X-axis represents time (in nanoseconds), and the Y-axis represents the bit error rate. Referring to Figs. 9 and 10, in order to secure a target bit error rate (10 ^-5 BER), it may take about 1.9 ns both when the magnetic tunnel junction (MTJ) element is in the AP state (tdev_ap) and when it is in the P state (tdev_p), for example. Since the lead circuit (150b) has an equalizing switch, the imbalance when the magnetic tunnel junction (MTJ) element is in the AP state and the P state can be alleviated, but an equalization time (EQ Time) may be additionally required in the total time taken to develop a voltage on the bit line.

Figure 11 is a circuit diagram for explaining the lead circuit.

Referring to FIG. 11, the read circuit (150c) may include a first transistor (MP31) and a second transistor (MP32). The first and second transistors (MP31, MP32) may receive a first signal (S1) through their gate terminals. When a read operation of the first or second memory cell (MC2) is initiated, the first signal (S1) may turn on the first and second transistors (MP31, MP32) to provide a read current to the first or second memory cell (MC2) and the reference resistor (Rref). The read circuit (150c) may further include a third transistor (MP33) and a fourth transistor (MP34). The third and fourth transistors (MP33, MP34) may have gate terminals connected through the first node (N31).

The third transistor (MP33) can be connected to the fifth transistor (MN31). The fourth transistor (MP34) can be connected to the sixth transistor (MN32). A second node (N32) can be formed between the third and fifth transistors (MP33, MN31). The third and fifth transistors (MP33, MN31) can be connected through the second node (N32). A third node (N33) can be formed between the fourth and sixth transistors (MP34, MN32). The fourth and sixth transistors (MP34, MN32) can be connected through the third node (N33). The fifth and sixth transistors (MN31, MN32) can receive a clamp voltage (VCLAMP) through their gate terminals. The clamp voltage (VCLAMP) can limit the size of a read current to prevent the read current from disturbing data stored in a memory cell.

A first switch (SW_L) may be arranged between a first node (N31) and a second node (N32). A second switch (SW_R) may be arranged between the first node (N31) and a third node (N33). The first switch (SW_L) may be toggled according to a second signal (S2). When the first switch (SW_L) is closed, a short circuit may be created between the first node (N31) and the second node (N32). The second switch (SW_R) may be toggled according to a third signal (S3). When the second switch (SW_R) is closed, a short circuit may be created between the first node (N31) and the third node (N33). The third signal (S3) may be an inverted signal of the second signal (S2). That is, when the first switch (SW_L) is closed, the second switch (SW_R) is opened, and when the first switch (SW_L) is opened, the second switch (SW_R) can be closed. When the first switch (SW_L) is closed, the gate terminal and the source/drain terminals of the third transistor (MP33) can form a diode connection. Since the gate terminal and the source/drain terminals of the third transistor (MP33) form a diode connection, the third and fourth transistors (MP33, MP34) can form current mirrors. Due to this, the magnitudes of the lead currents flowing in the third and fourth transistors (MP33, MP34) can be the same. Similarly, when the second switch (SW_R) is closed, the gate terminal and the source/drain terminals of the fourth transistor (MP34) can form a diode connection.

The fifth transistor (MN31) can be connected to the seventh transistor (MN33) and the ninth transistor (MN35). The sixth transistor (MN32) can be connected to the eighth transistor (MN34) and the tenth transistor (MN36). The seventh transistor (MN33) can be connected to the first memory cell (MC1) selected in the first read operation through the bit line. The ninth transistor (MN35) can be connected to the second memory cell (MC2) selected in the second read operation through the first bit line (BL1). The eighth and tenth transistors (MN34, MN36) can be connected through the reference resistor (Rref) and the second bit line (BL2). The seventh and eighth transistors (MN33, MN34) can receive the third signal (S3) through the gate terminal. The ninth and tenth transistors (MN35, MN36) can receive the second signal (S2) through the gate terminals. As described above, the third signal (S3) may be an inverted signal of the second signal (S2). Therefore, when the seventh and eighth transistors (MN33, MN34) are turned on, the ninth and tenth transistors (MN35, MN36) may be turned off. Conversely, when the seventh and eighth transistors (MN33, MN34) are turned off, the ninth and tenth transistors (MN35, MN36) may be turned on. Here, the signal received by the seventh and eighth transistors (MN33, MN34) is described as being the same as the signal (S2) received by the second switch (SW_R), but may be different depending on the embodiment of the invention. This may also be applied to the ninth and tenth transistors (MN35, MN36).

Fig. 12 is a circuit diagram for explaining the first lead operation of the lead circuit of Fig. 11.

Referring to FIG. 12, when the first read operation is initiated, the first switch (SW_L) may be opened and the second switch (SW_R) may be closed by the second and third signals (S3). When the second switch (SW_R) is closed, a short circuit may occur between the first node (N31) and the third node (N33). In addition, the seventh and eighth transistors (MN33, MN34) may be turned on and the ninth and tenth transistors (MN35, MN36) may be turned off by the second and third signals (S2, S3). The read circuit (150c) may be connected to the first memory cell (MC1) selected in the first read operation and the reference resistor (Rref) through the first and second bit lines (BL1, BL2). Specifically, the second node (N32) may be connected to the first memory cell (MC1) through the fifth and seventh transistors (MN31, MN33). The third node (N33) may be connected to the reference resistor (Rref) through the sixth and eighth transistors (MN32, MN34). A first voltage (VL) may be formed at the second node (N32) by the first memory cell (MC1). In addition, a second voltage (VR) may be formed at the third node (N33) by the reference resistor (Rref). In the first read operation, the first voltage (VL) may be provided to the sense amplifier as a data voltage (VDATA), and the second voltage (VR) may be provided to the sense amplifier as a reference voltage (VREF).

Fig. 13 is a circuit diagram for explaining the second lead operation of the lead circuit of Fig. 11.

The second read operation may be a read operation preceding the first read operation, or may be a read operation subsequent to the first read operation. In other words, the first read operation and the second read operation may be performed alternately. Referring to FIG. 13, when the second read operation is initiated, the first switch (SW_L) may be closed and the second switch (SW_R) may be opened by the second and third signals (S3). The first switch (SW_L) may be closed to short-circuit the first node (N31) and the second node (N32). In addition, the seventh and eighth transistors (MN33, MN34) may be turned off and the ninth and tenth transistors (MN35, MN36) may be turned on by the second and third signals (S2, S3). The read circuit (150c) can be connected to the second memory cell (MC2) selected in the second read operation and the reference resistor (Rref) through the first and second bit lines (BL1, BL2). Specifically, the second node (N32) can be connected to the reference resistor (Rref) through the fifth and ninth transistors (MN31, MN35). The third node (N33) can be connected to the second memory cell (MC2) through the sixth and tenth transistors (MN32, MN36). A second voltage (VR) can be formed at the third node (N33) by the second memory cell (MC2). In addition, a first voltage (VL) can be formed at the second node (N32) by the reference resistor (Rref). In the second read operation, the second voltage (VR) can be provided to the sense amplifier as a data voltage (VDATA), and the first voltage (VL) can be provided to the sense amplifier as a reference voltage (VREF).

Figure 14 is a graph showing the magnitude of the first voltage and the second voltage over time.

In the graph of Fig. 14, the X-axis represents time, and the Y-axis represents voltage magnitude. Referring to Fig. 14, the first and third reads (First Read, Third Read) may perform the first read operation, and the second and fourth reads (Second Read, Fourth Read) may perform the second read operation. In Fig. 14, it is assumed that the logic state of the memory cell (specifically, the magnetic junction device (MTJ)) that is the read target in the first and fourth reads (First Read, Fourth Read) is P (Parallel), and the logic state of the memory cell that is the read target in the second and third reads (Second Read, Third Read) is AP (Anti-Parallel). In the first read (First Read), the VL value may be a reference voltage value due to the reference resistance (Rref), and the VR value may be a voltage value lower than the reference voltage due to the memory cell in the P state. In the second read following the first read, the VL value may be a voltage value higher than the reference voltage due to the memory cell in the AP state, and the VR value may be a reference voltage value due to the reference resistor (Rref).

According to some embodiments, in the read circuit (150c) of FIG. 11, a reference voltage or a data voltage is developed alternately to a second node (N32) and a third node (N33), and when developing the data voltage, since the reference voltage developed in a previous read operation is utilized, the data voltage can be developed from the reference voltage without discharging a bit line when developing. Accordingly, a magnetoresistive memory device with reduced power consumption can be provided. In addition, since the data voltage is developed from the reference voltage when developing, the time taken to develop the data voltage is reduced, and the imbalance between when the state of the memory cell is AP and when it is P can be alleviated. Accordingly, a magnetoresistive memory device with improved read performance can be provided.

Fig. 15 is a graph for explaining the voltage development time according to the operation of the lead circuit shown in Fig. 11.

In the graph of Fig. 15, the X-axis represents time (in nanoseconds), and the Y-axis represents the bit error rate. Referring to Fig. 15, the time taken for a data voltage or a reference voltage to be developed on a bit line until a target bit error rate (10 ^-5 BER) can be secured is determined by the slowest time (tdev_worst) among the four cases illustrated, and may take, for example, about 1.3 ns. That is, the voltage development time of the read circuit (150c) illustrated in Fig. 11 may be faster than the read circuit (150a) illustrated in Fig. 7 and the read circuit (150b) illustrated in Fig. 9. Accordingly, a magnetoresistive memory device with improved read performance can be provided.

Although the embodiments of the present invention have been described with reference to the attached drawings, the present invention is not limited to the embodiments described above, but can be manufactured in various different forms, and a person having ordinary skill in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

Memory System: 1 Non-volatile memory devices: 100
Address decoder circuit: 120 Bitline select circuit: 130
Light circuit: 140 Lead circuit: 150
Data input/output circuits: 160 Control logic circuits: 180
Host: 200

Claims (10)

A magnetoresistive memory device comprising a lead circuit for sensing data stored in a plurality of memory cells,
The above lead circuit,
A sense amplifier that amplifies the difference between the voltages it receives;
A first transistor connected to the power supply voltage terminal and receiving the first lead current;
A second transistor connected to the above power voltage terminal and receiving a second lead current;
A first switch for short-circuiting between a first node connected to the gate terminals of the first and second transistors and a second node connected to the other terminal of the first transistor;
A second switch for short-circuiting between the first node and a third node connected to the other terminal of the second transistor;
A third transistor receiving the first lead current and having one end connected to one of the plurality of memory cells;
A fourth transistor receiving the second lead current and having one end connected to a reference resistor;
A fifth transistor receiving the first lead current and having one end connected to the reference resistor; and
A sixth transistor is included, which receives the second lead current and has one end connected to one of the plurality of memory cells;
A magnetoresistive memory device providing a first voltage formed at the second node and a second voltage formed at the third node to the sense amplifier. In the first paragraph,
A magnetoresistive memory device, wherein the first switch is toggled in accordance with a first signal, and the second switch is toggled in accordance with a second signal which is an inverted signal of the first signal. In the second paragraph,
A magnetoresistive memory device, wherein the third and fourth transistors are turned on in response to a third signal, and the fifth and sixth transistors are turned on in response to a fourth signal which is an inverted signal of the third signal. In the third paragraph,
A magnetoresistive memory device, wherein the third signal is identical to the first signal, and the fourth signal is identical to the second signal. In the first paragraph,
A magnetoresistive memory device, wherein the magnitudes of the first lead current and the second lead current are the same. In the first paragraph,
The above lead circuit,
A seventh transistor receiving the first lead current and receiving a clamp voltage through a gate terminal; and
A magnetoresistive memory device further comprising an eighth transistor receiving the second lead current and receiving the clamp voltage through a gate terminal. In the first paragraph,
The above lead circuit,
During the first lead operation, the first switch is opened and the second switch is closed to short-circuit between the first node and the third node,
A magnetoresistive memory device, wherein the first switch is closed and the second switch is opened during a second read operation following the first read operation to short-circuit between the first node and the second node. In Article 7,
A magnetoresistive memory device in which the above lead circuit alternately and repeatedly performs the first lead operation and the second lead operation. In Article 7,
The above lead circuit,
Turning on the third and fourth transistors during the first lead operation,
A magnetoresistive memory device which turns on the fifth and sixth transistors during the second read operation. In Article 9,
The above lead circuit,
During the first read operation, the first voltage is provided as a data voltage and the second voltage is provided as a reference voltage to the sense amplifier,
A magnetoresistive memory device, wherein the first voltage is provided as a reference voltage and the second voltage is provided as a data voltage to the sense amplifier during the second read operation.

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