KR20160083395A - Thin film transistor substrate and touch device of using the same - Google Patents

Abstract

The present invention relates to a thin film transistor substrate which is capable of improving an aperture ratio. The thin film transistor substrate according to the present invention includes first and second thin film transistors formed on two pixel areas, respectively, which are vertically adjacent to each other and connected to the same gate line; a protective film having a pixel contact hole through which a drain electrode of each thin film transistor formed on each of the two pixel areas vertically adjacent to each other is exposed; pixel electrodes connected to the first and second thin film transistors respectively, and separated from each other by pixel; and a connecting pattern for electrically connecting the exposed drain electrode and the pixel electrode. Thus, an aperture ratio may be improved, in comparison with a conventional thin film transistor substrate having a pixel contact hole formed on each pixel area. Furthermore, a display device with high resolution can be realized since the thin film transistor substrate has an improved aperture ratio.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a thin film transistor substrate,

The present invention relates to a thin film transistor substrate and a touch device using the thin film transistor substrate. More particularly, the present invention relates to a thin film transistor substrate capable of improving an aperture ratio.

The image display device that realizes various information on the screen is a core technology of the information communication age and it is becoming thinner, lighter, more portable and higher performance. Accordingly, a flat panel display device capable of reducing weight and volume, which is a disadvantage of a cathode ray tube (CRT), has attracted attention.

Among the flat panel display devices, a liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal by an electric field formed between the pixel electrode connected to the thin film transistor and the common electrode.

In the display device, the resolution is defined as the number of pixels per unit area (PPI), and the high resolution product generally refers to a product having a pixel per inch (PCPI) or more.

In order to realize a high resolution in a display device, the number of pixel areas to be realized per unit area must be increased. To realize this, it is necessary to reduce the size of each pixel area. To reduce the size of the pixel area, however, The aperture ratio of the pixel region, and the like must be considered.

In particular, in the case of a liquid crystal display field in a display device, the aperture ratio is a very important factor for realizing a high resolution, and a high aperture ratio characteristic should be secured preferentially for realizing a high resolution product.

Since one pixel contact hole is provided in each pixel region P, the aperture ratio is reduced.

Accordingly, a structure has been proposed in which the pixel contact holes are formed one by one for two pixel regions adjacent to each other in the upper and lower directions.

However, in the conventional thin film transistor substrate having the above-described structure, there is a problem that defective and aperture ratio are lowered when a pixel electrode formed in the upper and lower sides is implemented.

Referring to FIG. 1, if the mask is designed by a distance M2 equal to the minimum distance d1 required for preventing defects between neighboring pixel electrodes 12, the pixel electrodes formed in the pixel contact holes are patterned The distance d3 between the actual pixel regions becomes smaller than the minimum distance due to the step difference (d3 < d1).

Accordingly, in order to solve the problem of shorting between the pixel electrodes 12 formed in the upper and lower portions of FIG. 1, if the margin is added and the distance (M2 + a) is formed at the time of designing the mask, the area of the pixel contact holes shared vertically becomes larger A problem of reducing the aperture ratio may occur.

SUMMARY OF THE INVENTION The present invention provides a thin film transistor substrate and a touch device using the same that can improve the aperture ratio.

In order to achieve the above object, a thin film transistor substrate according to the present invention includes first and second thin film transistors formed in two adjacent pixel regions connected to the same gate line, A protective film having a pixel contact hole for exposing a drain electrode of each formed thin film transistor, a pixel electrode connected to each of the first and second thin film transistors and formed separately for each pixel, and a connection for electrically connecting the exposed drain electrode to the pixel electrode Pattern.

And the connection pattern is formed on at least one of the first and second thin film transistors formed in two adjacent pixel regions.

And the gate lines each include a gate electrode formed by vertically branching. Wherein the pixel contact holes are vertically overlapped with the gate lines.

The second embodiment of the thin film transistor substrate is characterized in that the connection pattern is formed as a double layer.

And the upper electrode and the lower electrode of the double layer are patterned to have the same area.

The thin film transistor substrate according to the present invention has a structure in which pixel contact holes are formed one by one for two neighboring pixel regions, and among the constituent elements constituting each thin film transistor, the source electrode is a data line And has an effect of improving the aperture ratio in comparison with a conventional thin film transistor substrate in which drain contact holes are provided for each pixel region and the source electrode is formed in the data wiring.

Further, the thin film transistor substrate according to the present invention has an advantage of realizing a high-resolution display device by improving the aperture ratio.

In the thin film transistor substrate according to the present invention, since the connection pattern is formed in the pixel contact hole, it is possible to minimize the area of the pixel contact hole and to prevent a short circuit between adjacent pixel electrodes. Accordingly, in the present invention, since the minimum area pixel contact hole is formed, the amount of exposure of the protective film can be reduced, and the process time can be reduced.

In addition, since the connection pattern is formed of the same metal as that used for forming the touch sensing line, the area to be formed is different, thereby providing no additional metal layer and mask for the connection pattern, thereby reducing manufacturing cost.

In addition, since the thin film transistor substrate according to the present invention has a semiconductor layer of polysilicon as one component, the carrier mobility characteristic of the thin film transistor substrate is improved compared to a thin film transistor substrate having amorphous silicon as a semiconductor layer, The present invention has an effect of suppressing the increase of the off current value due to the leakage current by implementing the double gate structure while forming the thin film transistor.

1 is a cross-sectional view showing a conventional thin film transistor substrate.
2 is a plan view showing a thin film transistor substrate according to a first embodiment of the present invention.
3 is a cross-sectional view showing a thin film transistor substrate cut along the line "I-I" in Fig.
FIGS. 4A and 4E are cross-sectional views illustrating a method of manufacturing the thin film transistor substrate shown in FIG.
5 is a cross-sectional view illustrating a thin film transistor substrate according to a second embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a plan view showing a thin film transistor substrate according to the present invention, and FIG. 3 is a cross-sectional view showing a thin film transistor substrate taken along the line "I-I" in FIG.

The thin film transistor substrate shown in FIGS. 2 and 3 includes a thin film transistor, a connection pattern, a common electrode, a touch sensing line, and a pixel electrode.

The gate line 102 and the data line 104 intersect each other with the interlayer insulating film 116 therebetween to define respective pixel regions. The gate line 102 supplies a scan signal to the gate electrode 106 of the thin film transistor in each pixel region and the data line 104 supplies a data signal to the source electrode 108 of the thin film transistor in each pixel region.

The thin film transistor substrate includes first and second thin film transistors connected to the same gate line in vertically adjacent pixel regions.

The thin film transistor causes the data signal of the data line 104 to be charged and held in the pixel electrode 122 in response to the scan signal of the gate line 102. To this end, the thin film transistor comprises gate electrodes 106A and 106B, a source electrode 108, a drain electrode 110 and an active layer 114,

The gate electrode includes a plurality of gate electrodes included in the gate line 102. In the present invention, two gate electrodes, that is, first and second gate electrodes 106A and 106B will be described as an example.

The first gate electrode 106A overlaps the first channel region 114A of the active layer and the second gate electrode 106B overlaps the second channel region 114B of the active layer.

The gate electrode is supplied with a scan signal from the gate line. The gate electrode overlaps the channel region of the active layer with the gate insulating film 112 therebetween.

The source electrode 108 is formed as a part of the data line 104 and is connected to the active layer through a source contact hole 124S penetrating the interlayer insulating film 116 and the gate insulating film 112. [

The drain electrode 110 is connected to the active layer through the interlayer insulating film 116 and the drain contact hole 124D passing through the gate insulating film 112. [ The drain electrode 110 is connected to the pixel electrode through a connection pattern 155 formed in the pixel contact hole 142H.

The active layer 114 forms a channel between the source electrode 108 and the drain electrode 110. The active layer 114 may be formed on the buffer film 126 as shown in FIG. 2 in the form of "a" or "a", or may be formed in another form. Since the active layer 114 is formed of a polysilicon thin film, mobility characteristics are improved compared to the amorphous silicon thin film.

The buffer film 126 is formed as a single layer or a multilayer structure of silicon oxide or silicon nitride on a substrate 101 formed of a plastic resin such as glass or polyimide (PI) or the like. The buffer layer 126 serves to prevent the diffusion of moisture or impurities generated in the substrate 101 and to control the transfer rate of heat during crystallization so that the crystallization of the active layer 114 can be performed well.

 The protective film improves the aperture ratio and protects the thin film transistor by blocking the inflow of moisture from the outside. The protective film is formed in a multi-layer structure. In the present invention, the first and second inorganic protective films 118 and 138 and the organic protective film 128 are described.

The first and second inorganic protective films 118 and 138 are formed of an inorganic insulating material having a denser bonding structure than the organic insulating material of the coarse bonding structure. The first inorganic protective film 118 is formed of an inorganic insulating material such as SiNx or SiOx and shields moisture flowing from the outside through the organic protective film 128 formed of a spongy organic insulating material, Thereby preventing corrosion of the electrodes. The organic protective layer 128 is formed of an organic insulating material such as PAC to planarize the lower substrate and shield the moisture from the outside together with the first inorganic protective layer 118, Thereby insulating the common electrodes 130 from each other.

At this time, a pixel contact hole 142H exposing the drain electrode 110 of each thin film transistor formed in the pixels adjacent to the upper and lower sides of the first inorganic protective film and the organic protective films 118 and 128 is provided. The pixel contact hole 142H provided in the first inorganic protective film and the organic protective film 118 and 128 is formed only for two pixel regions which are vertically adjacent to each other.

One pixel contact hole 142H formed for the two pixel regions P1 and P2 positioned in the vertical direction is larger than the area of one pixel contact hole provided in each pixel region of the conventional thin film transistor substrate, Hole area of the pixel region is smaller than the area of the two pixel contact holes in the pixel region, the aperture ratio of the display region is improved compared to the conventional thin film transistor substrate.

The connection pattern 155 is formed in the pixel contact hole 142H and formed in at least one of the first and second thin film transistors. The connection pattern 155 prevents an increase in the area of the pixel contact hole 142H while preventing a short circuit between the pixel electrodes 122 formed in the upper and lower neighboring pixels, thereby further improving the aperture ratio.

In the present invention, since the minimum area pixel contact hole is formed, the amount of exposure of the protective film can be reduced, and the process time can be shortened.

Since the connection pattern is formed of the same metal as that used for forming the touch sensing line but the formed region is different, a separate metal layer for the connection pattern and a mask are not added, thereby providing a manufacturing cost reduction effect.

In addition, the connection pattern 155 is formed on at least one of the first and second thin film transistors.

The pixel electrode connected to the connection pattern in the pixel contact hole is shorter than the pixel electrode adjacent to the pixel electrode. The pixel electrode connected to the drain contact hole of the first transistor is connected to the drain contact hole of the second TFT And has a short length in comparison with a pixel electrode to be connected.

The pixel electrode 122 is formed on the second inorganic protective film 138 of each pixel region provided at the intersection of the gate line 102 and the data line 104. The pixel electrode 122 is electrically connected to the drain electrode 110 exposed through the pixel contact hole 142H. Here, the pixel contact hole 142H is formed to penetrate the first and second inorganic protective films 118 and 138 and the organic passivation film 128 to expose the drain electrode 110. Further, the pixel electrode has a plurality of finger-shaped finger portions.

Specifically, the pixel electrode 122 of one pixel of the first and second thin film transistors is electrically connected to the connection pattern exposed through the pixel contact hole 142H, and the pixel electrode 122 of the other pixel is electrically connected to the pixel contact hole 142H. And is electrically connected to the drain electrode 110 exposed through the through hole 142H.

The common electrode 130 is formed on the organic protective film 128 in regions other than the region where the pixel contact hole 142H is formed. Accordingly, the common electrode 130 is electrically connected to the common electrode 136 of the adjacent pixel region in an integrated manner without a separate common line. The common electrode 130 overlaps the pixel electrode 122 with the second inorganic protective film 138 therebetween to form a fringe field in each pixel region. The common electrode 130, to which the common voltage is supplied, forms a fringe field with the pixel electrode 122 through which the pixel voltage signal is supplied through the thin film transistor, Molecules are rotated by dielectric anisotropy. The transmittance of light passing through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing the gradation.

The touch sensing line 150 is formed in direct contact with the common electrode 130 on the common electrode 130. The touch sensing line 150 electrically connects the common electrodes 130 of neighboring pixel regions to enable the common electrode 130 to be used as a touch sensing electrode in a non-display period.

That is, the common electrodes 130 of the respective pixel regions connected by the touch sensing line 150 are driven by the touch sensing electrodes during the non-display period to sense a change in capacitance due to the user's touch. Then, the touch position is detected by comparing the touch capacitance according to the user's touch with the reference capacitance.

4A to 4E are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to the present invention. A method of manufacturing a thin film transistor substrate according to the present invention will be described with reference to the thin film transistor substrate shown in the drawing.

The thin film transistor causes the data signal of the data line 104 to be charged and held in the pixel electrode 122 in response to the scan signal of the gate line 102. To this end, the thin film transistor comprises gate electrodes 106A and 106B, a source electrode 108, a drain electrode 110 and an active layer 114,

Referring to FIG. 4A, a buffer film 126 is formed on a substrate, and active layers 114A and 114B are formed thereon.

Specifically, the buffer film 126 and the amorphous silicon thin film are sequentially formed on the substrate through a method such as LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition). Then, the amorphous silicon thin film is crystallized to form a polysilicon thin film. Then, the active layers 114A and 114B are formed by patterning the polysilicon thin film by a photolithography process and an etching process.

The gate insulating film 112 is formed on the buffer film 126 on which the active layer is formed and the gate line 102 including the first and second gate electrodes 106A and 106B is formed thereon.

An interlayer insulating film 116 having a source contact hole 124S and a drain contact hole 124D is formed on the gate insulating film 112 on which the gate line 102 including the first and second gate electrodes 106A and 106B is formed .

Specifically, an interlayer insulating film 116 is formed on the gate insulating film 112 on which the gate line 102 is formed by a method such as PECVD. Then, the interlayer insulating film 116 and the gate insulating film 112 are patterned through a photolithography process and an etching process, thereby forming a source contact hole 124S and a drain contact hole 124D at the same time. Here, the drain contact hole 124D penetrates the interlayer insulating film 116 and the gate insulating film 112 to expose the active layers 114A and 114B.

A source electrode 108, a drain electrode 110, and a data line 104 are formed on the interlayer insulating film 116.

Specifically, a source / drain metal layer is formed on the interlayer insulating film 116 having the source contact hole 124S and the drain contact hole 124D by a deposition method such as sputtering. As the source / drain metal layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr or an alloy thereof may be used as a single layer, or may be used as a multi-layer structure by using them. Then, the source electrode 108, the drain electrode 110, and the data line 104 are formed on the interlayer insulating film 116 by patterning the source / drain metal layer through the photolithography process and the etching process.

The thin film transistor substrate includes first and second gate electrodes connected to the same gate line in vertically adjacent pixel regions and first and second thin film transistors connected to the same gate line in vertically adjacent pixel regions .

4B, a pixel contact hole 142H is formed on the interlayer insulating film 116 in which the source electrode 108, the drain electrode 110, and the data line 104 of the first and second thin film transistors adjacent to each other are formed. A first inorganic protective film 118 and an organic protective film 128 are formed.

More specifically, the first inorganic protective film 118 is formed by completely depositing an inorganic insulating material such as SiNx or SiOx on the interlayer insulating film 116 on which the source electrode 108, the drain electrode 110 and the data line 104 are formed do. Then, an organic insulating material such as photo-acryl or the like is coated on the first inorganic protective film 118 to form an organic protective film 128. Then, the organic passivation layer 128 is selectively patterned through a photolithography process and an etching process. The first inorganic protective film 118 and the organic protective film 128 are formed of materials having different characteristics so that the first inorganic protective film 118 and the organic protective film 128 are patterned under different process conditions to form the pixel contact holes 142H ). Here, the pixel contact hole 142H exposes the drain electrode of the first and second thin film transistors through the organic protective film 128 and the first inorganic protective film 118 of the first and second thin film transistors which are vertically adjacent .

Referring to FIG. 4C, a common electrode 130 is formed on the organic passivation layer 128.

Specifically, a transparent metal layer such as ITO is formed on the organic protective film 128 by a deposition method such as sputtering. The common electrode 130 is formed by patterning the transparent metal layer except the region where the pixel contact hole 142H is formed through the photolithography process and the etching process.

4D, a connection pattern 155 is formed in the touch sensing line 150 and the pixel contact hole 142H on the common electrode 130. Referring to FIG.

Specifically, an opaque metal layer is formed by a vapor deposition method such as sputtering. The metal layer may be a single layer of a metal such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof, or may be used as a multi-layered structure. Then, the touch sensing line 150 and the connection pattern 155 are formed by patterning the metal layer through the etching process using the photoresist pattern formed by the photolithography process.

4E, the second inorganic protective layer 138 is formed on the substrate having the touch sensing line 150 and the connection pattern 155 formed thereon, and then the pixel electrode 122 is formed.

Specifically, an inorganic insulating material such as SiNx or SiOx is entirely coated on the substrate on which the touch sensing line 150 and the connection pattern 155 are formed, thereby forming the second inorganic protective film 138. Then, a pixel contact hole 142H for exposing the drain electrode 110 and the connection pattern 155 is formed through an etching process using a photoresist pattern formed by a photolithography process.

Subsequently, a pixel electrode 122 is formed on the second inorganic protective film 138.

Specifically, a transparent metal layer such as ITO is formed on the second inorganic protective film 138 by a vapor deposition method such as sputtering. Then, the transparent metal layer is patterned through the photolithography process and the etching process, thereby forming the pixel electrode 122. [ The pixel electrode 122 of one pixel of the first and second thin film transistors is electrically connected to the connection pattern exposed through the pixel contact hole 142H and the pixel electrode 122 of the other pixel is electrically connected to the pixel contact hole 142H. The drain electrode 110 and the drain electrode 110 are electrically connected to each other.

5 is a cross-sectional view illustrating a thin film transistor substrate according to a second embodiment of the present invention.

The thin film transistor substrate shown in FIG. 5 has the same components as those of the thin film transistor substrate shown in FIG. 2 except that the connection pattern is formed as a double layer. Accordingly, detailed description of the same constituent elements will be omitted.

The active layers 114A and 114B, the first and second gate electrodes 106A and 106B, and the source / drain electrodes 108 and 108 are formed on the buffer film 126 in each pixel region of the substrate 101, 110, and a connection pattern, a common electrode, a touch sensing line, and a pixel electrode.

A transparent conductive material and an opaque conductive material are sequentially formed on the pixel contact hole 142H and the second passivation layer 128 which expose the drain electrode 110 on the substrate on which the first and second thin film transistors are formed. The opaque conductive material and the transparent opaque material are simultaneously patterned to form a connection pattern 155. The opaque conductive material is patterned to form the touch sensing electrode 150. The transparent conductive material is patterned to form a common electrode (130). At this time, it is preferable to use a halftone mask.

Specifically, a transparent conductive material and an opaque conductive material are sequentially formed on the second passivation layer 128. The transparent conductive material may be a material such as a tin oxide (TO), an indium tin oxide (ITO), an indium zinc oxide (IZO), an indium tin zinc oxide (ITZO) to be. The opaque conductive material is Mo, Ti, u, AlNd, Al, r, Mo alloy, u alloy, Al alloy and the like.

Then, a first photoresist pattern is formed on the opaque conductive material using a halftone mask. The first photoresist pattern is formed so as to correspond only to the regions where the common electrode 130 and the connection pattern 155 are to be formed.

Then, using the first photoresist pattern as a mask, the exposed opaque conductive material and the transparent conductive material are removed. Then, the first photoresist pattern is ashed to form a second photoresist pattern remaining only in a region where the touch sensing electrode 150 is to be formed. Then, the exposed opaque conductive material is removed using the second photoresist pattern as a mask to form a common electrode 130 made of a transparent conductive material. Then, the second photoresist pattern is removed to form a connection pattern 155.

Specifically, the connection pattern 155 is connected to the drain electrode 110 exposed through the drain contact hole 124D, and is formed in a tubular electrode shape. The connection pattern 155 connects the drain electrode 110 and the pixel electrode 122 exposed by the drain contact hole 124D to the upper electrode 157 and the lower electrode 137). &Lt; / RTI &gt;

Although the present invention has been described by taking a fringe field type liquid crystal display panel as an example, it is applicable to all liquid crystal display panels in which a common electrode such as a horizontal electric field and a pixel electrode are located on the same substrate.

The foregoing description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the spirit of the present invention. Therefore, the embodiments disclosed in the specification of the present invention do not limit the present invention. The scope of the present invention should be construed according to the following claims, and all the techniques within the scope of equivalents should be construed as being included in the scope of the present invention.

155: connection pattern 122: pixel electrode
110: drain electrode 136: common electrode
150: Touch sensing electrodes 114A and 114B:
142H: Pixel contact hole

Claims (9)

A gate line and a data line defining a pixel region;
First and second thin film transistors connected to the same gate line among the gate lines;
An organic passivation layer covering the first and second thin film transistors and exposing drain electrodes of the thin film transistors to one pixel contact hole;
A pixel electrode connected to the first and second thin film transistors and separated for each pixel;
A thin film transistor substrate having a connection pattern for electrically connecting at least one drain electrode of the first and second thin film transistors to the pixel electrode; The method according to claim 1,
Wherein a pixel electrode connected to a connection pattern in the pixel contact hole is shorter than a pixel electrode adjacent to the pixel electrode. The method according to claim 1,
Wherein the pixel electrode connected to the drain contact hole of the first transistor is shorter in length than the pixel electrode connected to the drain contact hole of the second thin film transistor. The method of claim 3,
And the drain contact holes have the same distance above and below the gate line, respectively. The method according to claim 1,
A common electrode which forms an electric field with the pixel electrode;
And a touch sensing line which is formed to be in direct contact with the common electrode and connects common electrodes of adjacent pixels so that the common electrode is driven as a touch sensing electrode. The method according to claim 1,
Wherein the connection pattern is made of the same material as the touch sensing line, and the lower electrode is the same material as the common electrode. The method according to claim 1,
A thin film transistor substrate having an organic protective film covering the first and second thin film transistors and exposing drain electrodes of the thin film transistors to one pixel contact hole, The method according to claim 1,
Wherein the gate line has a gate electrode that is vertically branched. A gate line and a data line defining a pixel region;
First and second thin film transistors connected to the same gate line among the gate lines;
An organic passivation layer covering the first and second thin film transistors and exposing drain electrodes of the thin film transistors to one pixel contact hole;
A pixel electrode connected to the first and second thin film transistors and separated for each pixel;
A thin film transistor substrate having a connection pattern for electrically connecting at least one drain electrode of the first and second thin film transistors to the pixel electrode;
A common electrode which forms an electric field with the pixel electrode;
And a touch sensing line formed to be in direct contact with the common electrode and connecting common electrodes of adjacent pixels so that the common electrode is driven as a touch sensing electrode.

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