JPS63283035A - Circuit board - Google Patents
Circuit boardInfo
- Publication number
- JPS63283035A JPS63283035A JP62117903A JP11790387A JPS63283035A JP S63283035 A JPS63283035 A JP S63283035A JP 62117903 A JP62117903 A JP 62117903A JP 11790387 A JP11790387 A JP 11790387A JP S63283035 A JPS63283035 A JP S63283035A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- elements
- chip
- circuit
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004820 Pressure-sensitive adhesive Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920006267 polyester film Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は回路基板の構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to the structure of a circuit board.
本発明は回路基板の構造において、後工程でＩｌｌに可
能な裏打ち板又はフィルムを貼合せた構造であり、ＩＣ
及び素子類を実装した後に前記裏打ち板を剥がすことが
できることにより、ＩＣ及び素子類の実装高さを最小限
に押え、容易に実装の行なえる超薄型回路モジュールを
提供するものである。The present invention is a circuit board structure in which a possible backing plate or film is attached to the Ill in a later process, and the IC
And by being able to peel off the backing plate after mounting the elements, the mounting height of the IC and elements can be kept to a minimum and an ultra-thin circuit module that can be easily mounted is provided.
従来の回路基板の構造は第２図、第３図の様に回路基板
上にＩＣチップを固定するか、回路基板の一部を座ぐり
加工をはとこした構造になっており、そこへＩＣチップ
を固定しワイヤーボンディング等により回路基板上の配
線パターンとＩＣチップの端子パッドとを接続させ、樹
脂等により封止を行なうものであった。As shown in Figures 2 and 3, the conventional circuit board structure is such that an IC chip is fixed on the circuit board, or a part of the circuit board is counterbore-processed, and the IC chip is placed there. The chip is fixed, the wiring pattern on the circuit board is connected to the terminal pad of the IC chip by wire bonding, etc., and the IC chip is sealed with resin or the like.
しかし、前述の従来技術では薄型回路モジュールを提供
するためには、回路基板を薄クシ、ＩＣチップのチップ
厚を薄＜シ、樹上封止の封止厚を薄くするという様に構
成部品の厚みを薄くするというものであり、さらに薄型
を要求される回路モジュールに対しては、それぞれの部
品及び封止厚みの積算された厚み以下にすることができ
ない。However, in order to provide a thin circuit module with the above-mentioned conventional technology, it is necessary to reduce the thickness of the component parts by making the circuit board thinner, making the IC chip thinner, and reducing the sealing thickness of the tree-top sealing. This is to reduce the thickness, and for circuit modules that are required to be even thinner, the thickness cannot be reduced to less than the sum of the thicknesses of each component and the sealing thickness.
そこで本発明は、この様な問題点を解決するもので、そ
の目的とするところは、超薄型回路モジュールを提供す
るところにある。The present invention is intended to solve these problems, and its purpose is to provide an ultra-thin circuit module.
本発明の回路基板の構造は、半導体素子及び集積回路用
チップ素子の設置部を穴構造とし、回路モジュールの前
記素子部の厚みを薄くする様にし前記素子設置時に素子
を保持し、電気的接続及び樹脂による封止等実装を行な
った後に、剥離可能な裏打ち板もしくは裏打ちフィルム
を貼付けたことを特徴とする。The structure of the circuit board of the present invention has a hole structure in the installation part of the semiconductor element and the integrated circuit chip element, and the thickness of the element part of the circuit module is made thin to hold the element when installing the element and to make electrical connections. A removable backing plate or backing film is attached after sealing with resin or other mounting.
第１図は本発明の実施例における回路基板の断面図であ
る。この実施例において回路基板１は半導体素子を配置
する位置に素子を埋設させるに十分な穴加工を施しであ
る。又回路基板の半導体素子と回路パターン５を接続さ
せる面と反対側の面には半導体素子を固定させ又、保持
させるための裏打ち板もしくは裏打ちフィルムを貼り付
ける。FIG. 1 is a sectional view of a circuit board in an embodiment of the present invention. In this embodiment, the circuit board 1 has sufficient holes to embed the semiconductor elements at the positions where the semiconductor elements are to be placed. Further, on the surface of the circuit board opposite to the surface where the semiconductor element and the circuit pattern 5 are connected, a backing plate or a backing film for fixing and holding the semiconductor element is pasted.
裏打ちフィルムとしては、たとえば後工程で熱を受ける
場合は接着剤付きのポリイミドフィルム等の耐熱フィル
ム、熱の影響がない様な場合はポリエステルフィルム等
が考えられる。又、貼り付ける部分については素子部に
限らず回路基板と同一の形状で貼り付けることも考えら
れる。特に素子が数箇所にある様な場合を効である。裏
打ちフィルムに使用する接着剤については比較的接着力
の弱いタイプの接着剤又は粘着剤を用いて、実装後に回
路基板から剥離する際回路基板側に応力を与えない様に
したものである。素子を配置する部分の裏打ちフィルム
の接着剤は素子の仮固定に使用することができる様に残
す場合もある。As the backing film, for example, a heat-resistant film such as a polyimide film with an adhesive may be used if the film will be subjected to heat in a post-process, and a polyester film may be used if the film will not be affected by heat. Further, the part to be pasted is not limited to the element part, but it is also conceivable to paste it in the same shape as the circuit board. This is particularly effective when the elements are located in several locations. The adhesive used for the backing film is a type of adhesive or pressure-sensitive adhesive with relatively weak adhesive strength, so that stress is not applied to the circuit board side when it is peeled off from the circuit board after mounting. In some cases, the adhesive of the backing film on the part where the element is placed is left so that it can be used for temporary fixing of the element.
第５図は集積回路用チップ素子を実装した回路基板の構
造であり第６図は回路基板に多層配線板を用いた基板に
より得られる回路モジュールの図であり、裏打ちフィル
ムを剥がしたものである。Figure 5 shows the structure of a circuit board on which chip elements for integrated circuits are mounted, and Figure 6 shows a circuit module obtained by using a multilayer wiring board as a circuit board, with the backing film removed. .
第７図は第５図により得られた回路モジュールの図であ
る。FIG. 7 is a diagram of the circuit module obtained from FIG. 5.
以上述べたように発明によれば回路基板の半導体素子及
び集積回路用チップ素子を固定し保持するだめの基材の
厚さを減らすことができ、又そのために前記素子を実装
した高さを最小限にし、なおかつ実装を行なう工程につ
いては従来の座ぐり基板、又は回路基板上への実装と変
わりなく行なうことができる。これらにより超薄型の回
路モジュールを提供できるという効果を存する。As described above, according to the invention, it is possible to reduce the thickness of the base material for fixing and holding the semiconductor elements and integrated circuit chip elements of the circuit board, and for this purpose, the height of the mounted elements can be reduced to a minimum. Furthermore, the mounting process can be carried out in the same way as mounting on a conventional counterbore board or circuit board. These have the effect that an ultra-thin circuit module can be provided.
第１図は本発明の回路基板の一実施例を示す主要断面図
。
第２図、第３図は従来技術の実装方法を示す主要断面図
。
第４図、第６図、第７図は本発明の実装方法により得ら
れた回路モジュールの断面図。
第５図は本発明のチップ素子の場合の実装方法を示す主
要断面図である。
１・・・・・・回路基板
２・・・・・・裏打ちフィルム
３・・・・・・半導体素子
４・・・・・・導体
５・・・・・・回路パターン
６・・・・・・封止樹脂
７・・・・・・絶縁用レジスト
８・・・・・・集積回路用チップ素子
９・・・・・・半田
１０・・・・・・回路基板（多層配線板）以 上
出願人 セイコーエプソン株式会社
第１図
第２図
第ｆ図
第〆図FIG. 1 is a main sectional view showing an embodiment of the circuit board of the present invention. FIGS. 2 and 3 are main sectional views showing a conventional mounting method. 4, 6, and 7 are cross-sectional views of circuit modules obtained by the mounting method of the present invention. FIG. 5 is a main cross-sectional view showing a mounting method for the chip element of the present invention. 1... Circuit board 2... Backing film 3... Semiconductor element 4... Conductor 5... Circuit pattern 6... - Sealing resin 7... Insulating resist 8... Integrated circuit chip element 9... Solder 10... Circuit board (multilayer wiring board) and above Applicant: Seiko Epson Corporation Figure 1 Figure 2 Figure f Figure 1.
Claims (1)
なう回路基板の前記素子を埋没設置する穴に対して、前
記素子の仮固定を行なうための裏打ち板もしくは裏打ち
フィルムが、前記素子の実装の後に剥離できることを特
徴とする回路基板。After the elements are mounted, a backing plate or a backing film for temporarily fixing the elements is provided in a hole in which the elements are buried in a circuit board for electrically connecting semiconductor elements and chip elements for integrated circuits. A circuit board characterized by its ability to be peeled off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62117903A JPS63283035A (en) | 1987-05-14 | 1987-05-14 | Circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62117903A JPS63283035A (en) | 1987-05-14 | 1987-05-14 | Circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63283035A true JPS63283035A (en) | 1988-11-18 |
Family
ID=14723050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62117903A Pending JPS63283035A (en) | 1987-05-14 | 1987-05-14 | Circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63283035A (en) |
-
1987
- 1987-05-14 JP JP62117903A patent/JPS63283035A/en active Pending
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