JPS63201725A - signal processing circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] In order to improve utilization efficiency by enabling a signal processing circuit with a pipeline processing configuration to perform sequential processing, the frequency of the pipeline processing clock is divided, and the processing time for one instruction is reduced to 1. A multi-phase clock corresponding to the number of processing stages of the cycle is generated, and from the first phase clock of this multi-phase clock, the clock for pipeline processing is sequentially transferred from the first stage processing register to the next stage processing register. It is added by switching instead of .

[Industrial application field]

The present invention provides a method for executing instructions at high speed in an electronic computer.
This invention relates to improvements in signal processing circuits with pipeline processing configurations.

For example, when debugging a program that is thought to have an error, if you debug it using a signal processing circuit with a pipeline processing configuration, a status flag will be set indicating that there is an error in the program and that, for example, division by 0 has been performed, and the process will be debugged. Even if you stop the process, the pipeline processing is already processing one after another, so it is not an appropriate time to stop it, and it is too late.

In such a case, instead of using a separate signal processing circuit for sequential processing, it is possible to easily switch this signal processing circuit to perform sequential processing.
Utilization efficiency improves.

Therefore, it is desired that signal processing circuits having a pipeline processing configuration can be easily switched to perform sequential processing and improve utilization efficiency.

[Conventional technology]

A conventional example will be explained below using figures.

FIG. 4 is a bronc diagram of a conventional example, and FIG. 5 is a time chart in the case of FIG.

, FIG. 5(A) shows the clock Φ for pipeline processing.

To explain the operation, at the address from the program counter (a type of register) 1 output at the timing shown in FIG. 5(B), the instruction R is output at the timing shown in FIG. 5(C).
OMII is accessed and instructions are read out, as shown in Figure 5 (D
) is stored in the instruction register 2 at a timing one clock later than the timing shown in (B).

Among these instructions, in the RAM address calculation instruction, RA
The M address calculation unit 12 performs address calculation at the timing shown in FIG. 5(E), and stores it in the address register 3-1 at a timing one clock later than the timing shown in FIG. 5(F) (D). This address allows RAM
Read the data from 13 and input the calculation data input register 1.
6 to store the data.

On the other hand, the instruction register 3 contains (F) shown in FIG. 5(G).
At the same timing as the timing shown in FIG. The data is transferred to the arithmetic unit 17 via the control unit 14.

On the other hand, the command register 4 contains the information shown in FIG. 5 (1).
At the same timing as H), instruction register 2
, 3, the arithmetic instruction is stored, and the arithmetic unit 17 performs the arithmetic operation via the arithmetic control unit 15, at a timing one clock later than the timing (1) shown in FIG. 5(J). The calculation result is stored in the calculation result register 18, and a flag is set in the status flag register 5 to indicate whether the calculation at that time was normal, but there was an abnormality such as overflow, underflow, division by 0, etc., and the flag is sent to the control unit. If so, issue an alarm.

In this way, calculations are performed by pipeline processing.

[Problem that the invention seeks to solve]

However, as a matter of course in pipeline processing, there is a difference of 4 clocks in the timing at which an alarm is issued by the flag in the status flag register 5 compared to the operation timing of the program counter 1 in FIG. Corresponding processes are performed one after another, so if there is an abnormality, it will be missed.

Therefore, for example, a program that is considered to have an error,
Conventionally, this has been done because errors can be detected appropriately by applying the signal to another sequential processing signal processing circuit, but this method has the problem of inefficient use of the pipelined signal processing circuit.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention.

In a signal processing circuit having a pipeline processing configuration, a clock Φ for pipeline processing is divided by a frequency divider 10, and 1
A multiphase clock Φ corresponding to the number of processing stages in one cycle until the end of instruction processing. 1φ1. φ2. ...is generated.

The first clock Φ of this polyphase clock. More sequentially,
From register 1 of the first stage processing to register 2.3 of the next stage processing. ..., switch and add it instead of the clock φ for pipeline processing.

This allows sequential processing.

[Operation] According to the present invention, in a signal processing circuit having a pipeline processing configuration, registers 1 for processing in the first stage are transferred from registers 2, 3 . . . . ■ A multi-phase clock Φ corresponding to the number of processing stages in one cycle until the end of instruction processing. 1Φ1. Φ2. ...
is the first phase clock φ.

Since the instructions are added more sequentially, one instruction is completed in one cycle of the clock, resulting in a signal processing circuit for sequential processing.

Therefore, in this way, a signal processing circuit with a pipeline processing configuration can easily become a signal processing circuit for sequential processing. For example, when debugging a program that is thought to have an error, this signal processing circuit can be It is only necessary to switch to the signal processing circuit for processing, and it is possible to improve the usage efficiency of the signal processing circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a time chart when the signal processing circuit of FIG. 2 is switched to sequential processing.

The difference between FIG. 2 and FIG. 4 is that the clock Φ for pipeline processing is frequency-divided, and a multiphase clock corresponding to the number of processing stages (in FIG. Since the number of stages is four, a frequency divider 10 that generates four phases is installed, and registers 1, 2, 3, and 3 for each stage of pipeline processing are installed.
-1.4.5 (first stage entrance), the first phase clock Φ is set according to the processing stage by switching with the selectors 20 to 25. , 1st and 3rd phase clock φ in the 2nd phase crofter
2. Switching to the fourth phase clock Φ3 enables sequential processing.

Therefore, since pipeline processing is performed in the same manner as in the conventional example, the operation will be described below for the case where the selectors 20 to 25 are switched to the sequential processing clock.

The frequency divider 10 divides the pipeline processing clock Φ shown in FIG.
AI) 4-phase clock Φ shown in (A2) (A3) (A4). ,Φ1. Φ2. Φ3 is generated and the first phase clock Φ. is set to program counter 1 and 2 for the first stage of processing.
The phase clock Φ1 is sent to the instruction register 2 of the second stage processing, the third phase clock Φ2 is sent to the instruction register 3 and address register 3-1 of the third stage processing, and the fourth phase clock Φ
3 is added to the instruction register 4 of the fourth stage of processing.

Status flag register 5 only needs to be processed in the first stage, so
1st phase clock Φ. Add.

In this way, the timing of the processing at each stage is as shown in Figure 3, and the registers at each stage of the pipeline processing are supplied with clocks that have the same period but are delayed for each phase, and the timing chart is as shown in Figure 3. The result will be as shown below.

That is, the instruction ROM 11 is accessed at the timing shown by diagonal lines in FIG. 3(C) using the address output from the program counter 1 at the timing shown in FIG. 3(B), and the instruction is read out. D) is stored at a timing one phase later than the timing of (B).

According to the RAM address calculation instruction among these instructions, the RAM address calculation unit 12 performs address calculation at the timing shown by diagonal lines in FIG. 3(E), and at the timing shown by diagonal lines (D) in FIG. It is stored in the address register 3-1 at a timing that is one phase behind the timing, and the RA
Data is read from M13 and stored in the calculation data input register 16.

On the other hand, a transfer instruction is stored in the instruction register 3 through the instruction register 2 at the same timing as the shaded timing in (F) shown in FIG. , indicated by diagonal lines in Figure 3 (H) (G
) is transferred to the arithmetic unit 17 via the transfer control unit 14 at a timing that is one phase behind the timing.

On the other hand, an arithmetic instruction is stored in the instruction register 4 through the instruction registers 2 and 3 at the same timing as the hatched timing (H) in FIG.
The arithmetic unit 17 performs the arithmetic operation via the arithmetic unit 17, and the arithmetic result is stored in the arithmetic result register 18 at a timing one phase later than the hatched timing (1) in FIG. 3 (J). A flag is set in the register 5 to indicate whether the calculation at that time was normal or whether there was an abnormality such as overflow, underflow, division by 0, etc., and the flag is sent to the control unit and an alarm is issued if there is an abnormality.

If an alarm occurs here, it is possible to stop outputting the next address from the program counter 1, so that appropriate measures can be taken in the event of an abnormality.

〔Effect of the invention〕

As explained in detail above, according to the present invention, a signal processing circuit with a pipeline processing configuration can be easily changed to a signal processing circuit with sequential processing, so that it can also be used for signal processing with sequential processing, and has the effect of improving utilization efficiency. There is.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a time chart when the signal processing circuit in Fig. 2 is switched to sequential processing, and Fig. 4 is a conventional An example block diagram, FIG. 5 is a time chart for the case of FIG. In the figure, 1 is a program counter and a register, 2 to 4 are instruction registers, 5 is a status flag register, 10 is a frequency divider, and 11 is an instruction ROM. 12 is a RAM address calculation section, and 13 is a RAM. 14 is a transfer control unit, 15 is an arithmetic control unit, 16 is an arithmetic data input register, 17 is an arithmetic unit, 18 is an arithmetic result register, and 20 to 25 are selectors. -e-< gu go ζ ゝ″″ ″ -1ku 5 also X \], -

Claims (1)

[Claims] In a signal processing circuit having a pipeline processing configuration, a clock (Φ) for pipeline processing is divided by a frequency divider (10), and the number of processing stages is one cycle until the end of processing one instruction. A corresponding multi-phase clock (Φ_0, Φ_1, Φ_2, ...) is generated, and from the first phase clock (Φ_0) of this multi-phase clock, successive stages are generated from the first stage processing register (1). A signal processing circuit that enables sequential processing by switching and adding a clock (Φ) to the processing registers (2, 3, . . . ) instead of a pipeline processing clock (Φ).