JPS63183730U - - Google Patents
Info
- Publication number
- JPS63183730U JPS63183730U JP7566587U JP7566587U JPS63183730U JP S63183730 U JPS63183730 U JP S63183730U JP 7566587 U JP7566587 U JP 7566587U JP 7566587 U JP7566587 U JP 7566587U JP S63183730 U JPS63183730 U JP S63183730U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- analog adder
- output
- difference
- target frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Noise Elimination (AREA)
Description
第1図は本考案の一実施例の構成図、第2図は
本考案に利用するリミツタ回路の入出力特性図、
第3図は本考案に於ける信号検出範囲の説明図、
第4図は従来回路の構成図、第5図は従来回路の
信号検出範囲の説明図である。
1……入力端子、2……帯域通過フイルタ、3
,9……検波器、4……アナログ加算器、5……
比較器、6……判定電圧、7……出力端子、8…
…帯域除去フイルタ、10……リミツタ回路。
Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is an input/output characteristic diagram of a limiter circuit used in the present invention,
FIG. 3 is an explanatory diagram of the signal detection range in the present invention,
FIG. 4 is a configuration diagram of a conventional circuit, and FIG. 5 is an explanatory diagram of a signal detection range of the conventional circuit. 1...Input terminal, 2...Band pass filter, 3
, 9...detector, 4...analog adder, 5...
Comparator, 6... Judgment voltage, 7... Output terminal, 8...
... Band removal filter, 10... Limiter circuit.
Claims (1)
みを通過させる帯域通過フイルタを通し、更にリ
ミツタ回路により出力制限を行つた後アナログ加
算器のプラス側に加え、又他方を目的周波数の信
号を除去する帯域除去フイルタを通し、前記アナ
ログ加算器のマイナス側に加えて両者の差をとり
、該差分出力と判定電圧との比較結果により目的
とする単一周波数信号が有効に入力したか否かを
判定し検出することを特徴とする単一周波数検出
回路。 The input signal is divided into two, one is passed through a band pass filter that passes only the signal of the target frequency, and the output is limited by a limiter circuit, and then added to the positive side of the analog adder, and the other is used to remove the signal of the target frequency. The difference between the two is taken in addition to the negative side of the analog adder through a band rejection filter, and the result of comparing the difference output with the judgment voltage determines whether or not the intended single frequency signal has been effectively input. A single frequency detection circuit characterized by determining and detecting.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7566587U JPS63183730U (en) | 1987-05-19 | 1987-05-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7566587U JPS63183730U (en) | 1987-05-19 | 1987-05-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63183730U true JPS63183730U (en) | 1988-11-25 |
Family
ID=30922023
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7566587U Pending JPS63183730U (en) | 1987-05-19 | 1987-05-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63183730U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0370241A (en) * | 1989-08-09 | 1991-03-26 | Toa Corp | On-hook detector in telephone set |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5344109A (en) * | 1976-10-02 | 1978-04-20 | Nippon Telegr & Teleph Corp <Ntt> | Signal receiver |
-
1987
- 1987-05-19 JP JP7566587U patent/JPS63183730U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5344109A (en) * | 1976-10-02 | 1978-04-20 | Nippon Telegr & Teleph Corp <Ntt> | Signal receiver |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0370241A (en) * | 1989-08-09 | 1991-03-26 | Toa Corp | On-hook detector in telephone set |
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