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JPS62296431A - Method for connecting flip chip - Google Patents

Method for connecting flip chip

Info

Publication number
JPS62296431A
JPS62296431A JP13926286A JP13926286A JPS62296431A JP S62296431 A JPS62296431 A JP S62296431A JP 13926286 A JP13926286 A JP 13926286A JP 13926286 A JP13926286 A JP 13926286A JP S62296431 A JPS62296431 A JP S62296431A
Authority
JP
Japan
Prior art keywords
flip chip
bumps
circuit board
adhesive agent
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13926286A
Other languages
Japanese (ja)
Inventor
Takao Tanaka
孝夫 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Priority to JP13926286A priority Critical patent/JPS62296431A/en
Publication of JPS62296431A publication Critical patent/JPS62296431A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To simplify a connecting process by a method wherein metal bumps built on a flip chip and ITO patterns are connected with each other by electroless metal plating. CONSTITUTION:Bumps 12 on a flip chip 11 are so positioned as to meet, respectively, their corresponding ITO patterns 14, and the flip chip 11 is bonded immovable to a circuit substrate 13 by an adhesive agent 15. The adhesive agent 15 should already be on the circuit substrate 13 or the flip chip 11 prior to the process. The bumps 12 or ITO patterns 14 should be clear of the adhesive agent 15, and the bumps 12 should be in close contact with the ITO patterns 14. The adhesive agent 15 should preferably be of an epoxy-based type capable of hardening at a room temperature. Next, following the hardening of the adhesive agent 15, the substrate 13 mounted with the flip-chip 11 is placed in an electroless plating liquid. In this process, the ITO patterns 14 and bumps 12 are coated with an Ni plate, which coating establishes electrical connection between the bumps 12 and ITO patterns 14.

Description

【発明の詳細な説明】 ３、発明の詳細な説明 〔発明の利用分野〕 本発明は電子回路装置に備えられるフリップチップの回
路基板への接続方法に関する。Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a method of connecting a flip chip provided in an electronic circuit device to a circuit board.

〔従来の技術〕[Conventional technology]

マイクロ接続技術の一つとして高密度実装が可能なフリ
ップチップポンディングがある。これはフリップチップ
を直径０．２■程度の複数の微細な半田、すなわち半田
バンプを介して回路基板に接続するものである。Flip-chip bonding is one of the micro-connection technologies that enables high-density packaging. In this method, a flip chip is connected to a circuit board through a plurality of fine solders, ie, solder bumps, each having a diameter of about 0.2 square meters.

このようなフリップチップの回路基板のＩＴＯパターン
への接続方法の説明図を第２図に示す。An explanatory diagram of a method of connecting such a flip chip to an ITO pattern on a circuit board is shown in FIG.

図面において１はフリップチップ、２は該フリップチッ
プ１に設けられた半田バンプ、３は例えばＬＣＤを搭載
したガラス基板等よりなる回路基板、４は該回路基板３
上に形成されたＩＴＯパターンである。回路基板３上に
フリップチップ１を接続するには、まずパターン４上に
無電解メッキ或は蒸着によりＮｉ、Ｃｕ、Ａｕ等の導電
性の金属膜５を形成し、その上にフラックス又はクリー
ム半田を塗布した後、半田バンプ２を対応するＩＴＯパ
ターン４上に位置合せを行い、その後、基板３の両側に
加温装置として一対のホットガスヒータ６．７を配置し
、これ等のホットガスヒータ６．７から半田バンブ２部
分の温度が３３０〜３５０℃の温度になるよう′／Ｃ高
温ガス８を７リツプチツプ１に与える。この時、回路基
板ｌを構成するガラスの熱衝撃をやわらげながらフリッ
プチップ１の半田バンプ２及び回路基板３上の予備半田
を溶融させ、この溶融した半田を介してフリッブチツブ
１を回路基板３に接続するものである。In the drawing, 1 is a flip chip, 2 is a solder bump provided on the flip chip 1, 3 is a circuit board made of, for example, a glass substrate on which an LCD is mounted, and 4 is the circuit board 3.
This is the ITO pattern formed on top. To connect the flip chip 1 to the circuit board 3, first, a conductive metal film 5 of Ni, Cu, Au, etc. is formed on the pattern 4 by electroless plating or vapor deposition, and then flux or cream solder is applied thereon. After coating the solder bumps 2, the solder bumps 2 are aligned on the corresponding ITO patterns 4, and then a pair of hot gas heaters 6.7 are placed as heating devices on both sides of the substrate 3, and these hot gas heaters 6.7 are placed on both sides of the substrate 3. A/C high-temperature gas 8 is applied to the 7 lip chip 1 so that the temperature of the solder bump 2 from 7 becomes 330 to 350 DEG C. At this time, the solder bumps 2 of the flip chip 1 and the preliminary solder on the circuit board 3 are melted while softening the thermal shock of the glass constituting the circuit board 1, and the flip chip 1 is connected to the circuit board 3 via the melted solder. It is something to do.

なお、上記したホットガスヒータ６．７のうちの図示下
方に位置するホットガスヒータ７を省略した方法もある
。Note that there is also a method in which the hot gas heater 7 located at the lower part of the figure among the hot gas heaters 6 and 7 described above is omitted.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで、上記した方法は下記の如き問題点がある。 However, the above method has the following problems.

（１）　Ｉ　ＯＴパターン４上に金属膜５を形成する工
程と、該金属膜５に半田バンプ２を半田付けする工程が
別々に行われるため工程数が多くなる。(1) The number of steps increases because the step of forming the metal film 5 on the IOT pattern 4 and the step of soldering the solder bumps 2 to the metal film 5 are performed separately.

（２）半田付は工程があるのでフラックスを使用せねば
ならず、フラックスの残渣による回路接続の信頼性の低
下が起りやすい。(2) Since soldering requires the use of flux, the reliability of circuit connections is likely to deteriorate due to flux residue.

（３）ホットガスヒータ６．７から放出された高温ガス
８がフリップチップ１の周囲に分散し、フリップチップ
１の近傍の加熱をしてはならない部分、例えば回路基板
３上のＬＣＤを加熱するおそれがあり、このため当該加
熱をしてはならない部分を冷却する冷却装置を要し、こ
の実装作業が煩雑になるととも釦、製作費も高くなる不
具合がある。(3) There is a risk that the high temperature gas 8 released from the hot gas heater 6.7 will disperse around the flip chip 1 and heat parts of the flip chip 1 that should not be heated, such as the LCD on the circuit board 3. For this reason, a cooling device is required to cool the part that should not be heated, which complicates the mounting work and increases the manufacturing cost of the button.

（４）回路基板３の材料は、該基板３が部分加熱される
ので、耐熱性を要し、有機フィルム等より成る耐熱性の
低い基板３への７リツプチツプ１の実装は困難である。(4) The material of the circuit board 3 must be heat resistant since the board 3 is partially heated, and it is difficult to mount the 7-lip chip 1 on the board 3, which has low heat resistance and is made of an organic film or the like.

本発明は上記の如き従来の問題点を解消せんとするもの
であり、本発明の目的は接続信頼性の向上と、接続作業
の簡易化と製作費の低減と併せて回路基板として耐熱性
の低い材料の使用を可能ならしめんとするものである。The present invention aims to solve the above-mentioned conventional problems, and the purpose of the present invention is to improve the connection reliability, simplify the connection work, reduce manufacturing costs, and provide a heat-resistant circuit board. The purpose is to enable the use of low-cost materials.

〔問題点を解決するための手段〕[Means for solving problems]

この目的を達成するために本発明は、フリップチップを
ＩＴＯパターンを有する回路基板に接続するフリップチ
ップの接続方法において、フリップチップに設けた金属
バンプとＩＴＯパターンとを導電性の金属の無電解メッ
キにより接続する構成にしである。To achieve this object, the present invention provides a flip chip connection method for connecting a flip chip to a circuit board having an ITO pattern, in which metal bumps provided on a flip chip and an ITO pattern are electrolessly plated with a conductive metal. This is the configuration where the connection is made.

〔作　用〕[For production]

本発明は、従来のような高温処理やフラックスを必要と
する半田付工程の代わりに、フリップチップの金属バン
プとＩＴＯパターンとに無電解メッキによる金属メッキ
膜を形成することにより、フリップチップとＩＴＯパタ
ーンとを電気的に接続したものである。In the present invention, a metal plating film is formed by electroless plating on the metal bumps of the flip chip and the ITO pattern, instead of the conventional soldering process that requires high temperature treatment and flux. The pattern is electrically connected to the pattern.

このため、本発明は、高温処理やフラックスを必要とし
ないフリップチップの接続方法となる。Therefore, the present invention provides a flip chip connection method that does not require high temperature treatment or flux.

〔実施例〕〔Example〕

以下本発明の７リツプチツプの接続方法の一実施例を説
明する。An embodiment of the seven-lip chip connection method of the present invention will be described below.

第１図（イ）、仲）は本発明のフリップチップの接続方
法の一実施例を示す説明図である。FIG. 1A and FIG. 1B are explanatory diagrams showing an embodiment of the flip-chip connection method of the present invention.

第１図において１１はフリップチップ、１２は７リツブ
チツプ１１に設けられたＡｕ、Ｃｕ、Ｎｉ等ヨり成る金
属バンプ、１３は回路基板（例えばＬＣＤを搭載したガ
ラス基板）、１４は該回路基板１３上に形成されたＩＴ
Ｏパターンである。回路基板１３がＬＣＤを搭載した基
板においては、予めフリップテップ１１のバンプ１２以
外の部分は液晶の配向膜としてｓｉｏ＊等の無機膜、或
いはポリイミド等の有ａ膜が形成されている。この回路
基板１３を塩化パラジウム水溶液（約０．１％）ＶＣ。In FIG. 1, 11 is a flip chip, 12 is a metal bump made of Au, Cu, Ni, etc. provided on the 7-rib chip 11, 13 is a circuit board (for example, a glass substrate on which an LCD is mounted), and 14 is the circuit board 13. IT formed on
This is an O pattern. In a circuit board 13 on which an LCD is mounted, an inorganic film such as SIO* or an aluminium film such as polyimide is formed in advance on the portions of the flip-tip 11 other than the bumps 12 as an alignment film for the liquid crystal. This circuit board 13 was treated with a palladium chloride aqueous solution (approximately 0.1%) VC.

浸漬してバンプ１２部分の活性化を行う。The bump 12 portion is activated by dipping.

一方、フリップチップ１１のバンプ１２に対応してＩＴ
Ｏパターン１４が形成された回路基板１３を塩化パラジ
ウム及び塩化第一錫水溶液に浸漬処理し、ＩＴＯパター
ン１４のみを活性化しておく。On the other hand, corresponding to the bump 12 of the flip chip 11, the IT
The circuit board 13 on which the O pattern 14 is formed is immersed in an aqueous solution of palladium chloride and stannous chloride to activate only the ITO pattern 14.

次に、第１図（イ）Ｋ示す如くフリップチップ１１の各
バンプ１２が、対応するＩＴＯパターン１４上にくる様
に位置合せし、接着剤１５にてフリップチップ１１と回
路基板１３とを固定する。この時、接着剤１５は基板１
３側、或いはフリップチップ１１′側に予め塗布してお
く。また接着剤１５はバンプ１２及びＩＴＯパターン１
４に付着してはならス、かつバンプ１２はＩＴＯパター
ン１４へ密着する様にする。上記の接着剤１５はヱボキ
シ系常温硬化型が望ましい。Next, as shown in FIG. 1(a) K, the bumps 12 of the flip chip 11 are aligned so that they are on the corresponding ITO patterns 14, and the flip chip 11 and the circuit board 13 are fixed with adhesive 15. do. At this time, the adhesive 15 is applied to the substrate 1.
3 side or the flip chip 11' side in advance. Also, the adhesive 15 is applied to the bump 12 and the ITO pattern 1.
The bumps 12 should not be attached to the ITO pattern 14, and the bumps 12 should be in close contact with the ITO pattern 14. The adhesive 15 described above is desirably an eboxy-based room-temperature curing type.

次に接着剤１５の硬化後、チップ１１の付いた基板１３
を無電解メッキ液に浸漬する。これＫより第１図（ロ）
に示す如＜ＩＴＯパターン１４上とバンプ１２上にＮｉ
メッキが行われ、バンプ１２とＩＴＯパターン１４がこ
のＮｉよりなる金ＪＡ膜１６により電気的に接続される
。Next, after the adhesive 15 has hardened, the substrate 13 with the chip 11
immersed in electroless plating solution. Figure 1 (b) from this K
As shown in <Ni on the ITO pattern 14 and the bump 12.
Plating is performed, and the bumps 12 and the ITO pattern 14 are electrically connected by the gold JA film 16 made of Ni.

この後洗浄、乾燥し、フリップチップ１１の全周囲をヱ
ボキシ系樹脂などの封止剤１７により封止してフリップ
チップ１１を保護する。Thereafter, the flip chip 11 is washed and dried, and the entire periphery of the flip chip 11 is sealed with a sealant 17 such as an epoxy resin to protect the flip chip 11.

上記のように構成した実施例にあっては、上述したよう
にＩＴＯパターン１４及びバンプ１２上に金属膜１６の
形成が同時に行われて、回路基板１３と７リツプチツプ
１１の接続が一工程で行われるので、従来に比し製造工
程が簀略化される。In the embodiment configured as described above, the metal film 16 is formed on the ITO pattern 14 and the bumps 12 at the same time as described above, and the circuit board 13 and the 7-lip chip 11 are connected in one step. Therefore, the manufacturing process is simplified compared to the conventional method.

また、半田付は工程がないので、フラックスの残渣によ
る回路接続の信頼性の低下はない。Furthermore, since there is no soldering process, there is no reduction in the reliability of circuit connections due to flux residue.

また、半田工程がないことによって、従来必要とした加
温装置、冷却装置を必要とせず、接続作業が簡易化され
ると共に製作費も安くなる。Moreover, since there is no soldering process, there is no need for heating devices and cooling devices that were conventionally required, which simplifies the connection work and reduces manufacturing costs.

更にまた、回路基板１３は従来の如く部分加熱すること
がないので、耐熱性を必要とせず、有機イルム等耐熱性
の低い材料を使用出来、例えばフィルムＬＣＤを構成す
るフィルム上のＩＴＯパターン１４にフリップチップ１
１を実装することも可能である。Furthermore, since the circuit board 13 is not partially heated as in the conventional case, it does not require heat resistance, and materials with low heat resistance such as organic films can be used. flip chip 1
It is also possible to implement 1.

〔発明の効果〕〔Effect of the invention〕

本発明の７リツプチツプの接続方法は上記の如く構成し
であることから、フリップチップの金属バンプの金属膜
の形成と、フリップチップと回路基板の接続が同時に出
来、また、半田付は工程がないので加温装置等を必要と
せず、従って接続作業が簡易化されると共に製作費も従
来に比し安く出来る。Since the 7-lip chip connection method of the present invention is configured as described above, the formation of the metal film of the metal bump of the flip chip and the connection of the flip chip and the circuit board can be performed simultaneously, and there is no soldering step. Therefore, no heating device or the like is required, which simplifies the connection work and lowers the manufacturing cost compared to the conventional method.

これに伴って回路基板は従来例の如く加熱されることが
ないので、耐熱性を必要とせず、回路基板として有機フ
ィルム等の耐熱性の低い材料の使用が可能となると同時
にたとえばＬＣＤなとの加熱してはならない部分を有す
る回路基板であっても何等影響を及ぼすことがない。更
に従来のようなフラックスの残渣による接続の信頼性低
下も発生しないなど種々の効果を有する。Along with this, the circuit board is not heated as in the conventional case, so it does not require heat resistance, and it is possible to use materials with low heat resistance such as organic films as the circuit board. Even if the circuit board has parts that should not be heated, it will not have any effect. Furthermore, there are various effects such as no deterioration in connection reliability due to flux residue as in the prior art.

【図面の簡単な説明】[Brief explanation of drawings]

ｚ４〜；発明のフリップチップの接続方法の一実施例を
示す説明図、第２図は従来のフリップチップの接続方法
を示す説明図である。 １１・・・・・・ン’　Ｉｙ、　す９６１２−・−金属
バンプ、１３・・・・・・回路基板、１４・・・・・・
ＩＴＯパターン、１５・・・・・・接着剤、１６・・・
・・・金属膜、１７・・・・・・封止剤。 第１図 とイノ Ｃロノz4~: An explanatory diagram showing an embodiment of the flip chip connection method of the invention. FIG. 2 is an explanatory diagram showing a conventional flip chip connection method. 11...N'Iy, 9612--Metal bump, 13...Circuit board, 14...
ITO pattern, 15...Adhesive, 16...
...metal film, 17... sealing agent. Figure 1 and Ino C Rono

Claims (1)

【特許請求の範囲】[Claims] 　フリップチップをＩＴＯパターンを有する回路基板に
接続するフリップチップの接続方法において、フリップ
チップに設けた金属バンプとＩＴＯパターンとを導電性
の金属の無電解メッキにより接続したことを特徴とする
フリップチップの接続方法。In a flip chip connection method for connecting a flip chip to a circuit board having an ITO pattern, the flip chip is characterized in that the metal bumps provided on the flip chip and the ITO pattern are connected by electroless plating of a conductive metal. Connection method.
JP13926286A 1986-06-17 1986-06-17 Method for connecting flip chip Pending JPS62296431A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13926286A JPS62296431A (en) 1986-06-17 1986-06-17 Method for connecting flip chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13926286A JPS62296431A (en) 1986-06-17 1986-06-17 Method for connecting flip chip

Publications (1)

Publication Number Publication Date
JPS62296431A true JPS62296431A (en) 1987-12-23

Family

ID=15241189

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13926286A Pending JPS62296431A (en) 1986-06-17 1986-06-17 Method for connecting flip chip

Country Status (1)

Country Link
JP (1) JPS62296431A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0459493A2 (en) * 1990-06-01 1991-12-04 Kabushiki Kaisha Toshiba A semiconductor device using a lead frame and its manufacturing method
US5556810A (en) * 1990-06-01 1996-09-17 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device wherein a semiconductor chip is connected to a lead frame by metal plating
EP0898305A3 (en) * 1997-08-20 1999-08-25 Oki Electric Industry Co., Ltd. Structure and method for packaging semiconductor chip

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0459493A2 (en) * 1990-06-01 1991-12-04 Kabushiki Kaisha Toshiba A semiconductor device using a lead frame and its manufacturing method
EP0459493A3 (en) * 1990-06-01 1994-02-23 Toshiba Kk
US5556810A (en) * 1990-06-01 1996-09-17 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device wherein a semiconductor chip is connected to a lead frame by metal plating
US5654584A (en) * 1990-06-01 1997-08-05 Kabushiki Kaisha Toshiba Semiconductor device having tape automated bonding leads
EP0898305A3 (en) * 1997-08-20 1999-08-25 Oki Electric Industry Co., Ltd. Structure and method for packaging semiconductor chip
US6130480A (en) * 1997-08-20 2000-10-10 Oki Electric Industry Co., Ltd. Structure for packaging semiconductor chip

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