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JPS62229973A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS62229973A
JPS62229973A JP61072859A JP7285986A JPS62229973A JP S62229973 A JPS62229973 A JP S62229973A JP 61072859 A JP61072859 A JP 61072859A JP 7285986 A JP7285986 A JP 7285986A JP S62229973 A JPS62229973 A JP S62229973A
Authority
JP
Japan
Prior art keywords
metallic layer
layer
metal layer
semiconductor device
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61072859A
Other languages
English (en)
Inventor
Shigeo Hachiman
八幡　重夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP61072859A priority Critical patent/JPS62229973A/ja
Publication of JPS62229973A publication Critical patent/JPS62229973A/ja
Pending legal-status Critical Current

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 【発明の目的コ （産業上の利用分野） 本発明は、半導体装置に関する。
（従来の技術） 従来、パワートランジスタ、ジャイアントトランジスタ
、パワーＭＯ８）ランジスタ等の個別半導体素子は、銅
板或は銅薄がバター二／グされたセラミック板上に、半
導体素子をその裏直に半田を介して固着し、表面側の動
作領域にＡＩ電極を設は九構造になっている。而して、
アセンブリ工程では電極端子と半導体素子の電極とをＡ
ｌ線でボンディング接続するものが多い。特に電力容置
の大きいものでは、銅薄パターン部が半導体素子電極か
らアルミボンディング線のボンディング接続部と、製品
のターミナル端子を半田で接続する部分とが、兼用され
ている。このため銅板或はセラミック基板が非常に大き
な面積を占めている。
また、複数個のアルミポンディング線を接続するボンデ
ィング工程が必要であシ、アセンブリ工程そのものが複
雑になる。
すなわち、例えばパワーデバイスのジャイアントトラン
ジスタのモジュールについて考えると、セラミック基板
の面積はペレット面積の占める割合に対して、約５倍の
面積を占有している。同時に、製品の外枠もその分だけ
大きくなっている。
このためエンキャップ材やモールド材の使用量が非常に
多くなる。
また、大電流容量を持つ半導体素子をアセンブリする場
合、半導体素子をタングステン（ロ）の台と直接溶着す
るものがある。この場合、高温で圧着溶接するために、
半導体素子の圧着面は数１０μｍ以上必要となる。すな
わち、通常素子が動作する上で必要となる温度以上で圧
着するため、電極の不純物が拡散する。このため、拡散
する不純物が素子の動作上問題を起こさないように、深
いディメンジョンの構造にしなければならない。このた
め、かかる手段は現状では超大型の素子にしか適用でき
ない。
また、小信号のダイオードでは、Ａｕを主体としたｔ極
構造にすることによシ、半田でリードフレームと半導体
素子とを直接接続するパ／プ構造のものがある。この場
合、Ａｕ自体の膜ストレスが非常に大きいことが原因で
、膜厚を１μｍ以上にできず、小信号のダイオードにし
か適用できない。
かかる従来技術の中で、パワーデバイスのジャイアント
トランジスタのモジュールのように、複数の半導体素子
を一つの基板にへイブリッド構成することが要望されて
いる。
（発明が解決しようとする問題点） 本発明は、アセンブリ工程を簡略化し、アルミボンディ
ング線の廃止、セラミック基板の縮小化、エンキャップ
材及びモールド材の使用量の削減を達成して製造コスト
を低減させることができる半導体装置を提供することを
その目的とするものである。
〔発明の構成］ （問題点を解決するための手段） 本発明は、半導体基板上の所定領域上に形成され、ＡＪ
　、　Ｐｔ　、Ｍｏ８ｉ２　、Ｍｏ　、　ＴｉＮ、Ｔｉ
Ｃ、ＴａＮ。
ＴａＣ，ＨｆＮ　、ＺｒＮ　、　ＺｒＣの少なくとも何
れか一種からなる第一層金属層と、該第−は金属層上に
形成され、Ｔａ　、　Ｔｉ　、Ｖ、　Ｃｖ　、　Ｚｒ　
、）（ｆ　、の少なくとも何れか一種からなる第三層金
属層と、該第二層金属層上に形成され、ＴｊＮ　、　Ｔ
ｉＣ、ＴａＮ　、　ＴａＣ、ＨｆＮ。
ＨｆＣ、ＺｒＮ　、　ＺｒＣの少なくとも何れか一種か
らなる第三層金属層と、該第三層金属層上に形成され、
Ｎｉ　、　Ｃｏ　、　Ｓｎ　、Ｃｕ、　Ｆｅ　、＾ｇ、
Ａｕの少なくとも一種からなる第四層金属層とを具備す
ることを特徴とする半導体装置である。
ここで、第一層〜第四層の各々の金属層の形成方法とし
ては、ＣＶ　Ｄ　（（：ｈｅｍｉｃａｌ　Ｖａｐｏｒ　
Ｄｅｐｏｓｉｔｉｏｎ）法、スパッタ法、リアクティブ
スパッタ法、蒸着法、イオン注入法、イオンビーム法等
を適宜採用することができる。
また、第一ノΔ金属／１及び第四層金属層を設定するこ
とによシ、第二ノー、第三層の金属ノーの成分を所定の
ものに設定することができる。
（作用） 本発明に係る半導体装置によれば、第一層金属層が所定
のオーミックコンタクト或はシロットキーコンタクトを
示し、第二層金属層及び第三層金属層がバリアメタル作
用と各層間の密着性の向上を図る。そして第一層金属層
及び第三層金属層を所定のものにすることにより、第三
層、第二層の金属層の成分を所定のものに設定すること
ができる。これらの結果、本発明の半導体装置によれば
、アセンブリ工程を簡略化し、アルミボンディング線の
廃止、セラミック基板の縮小化、エンキャップ材及びモ
ールド材の使用量を削減して、製造コストを低減させる
ことができる。
（実施例） 以下、本発明の実施例について図面を参照して説明する
。第１図は、本発明の一実施列の概略構成をその製造工
程に従って示す説明図である。
第１因（Δ）中１は、コレクタＮ　領域ｌａ上にコレク
タＮ−領域１ｂが設けられ、コレクタＮ−領域ｌｂ内に
ベース領域１ｃ、ベース領域ＩＣ内にエミッタ領域１ｄ
を形成した半導体基板である。半導体基板１上には、絶
縁膜２が形成され、絶縁膜２には、ベース領域ＩＣ１エ
ミツタ領域１ｄに通じるコンタクトホール２ａ、２ｂが
夫々開口さｈている。このようにコンタクトホール２ａ
　、　２ｂを開口した半導体基板Ｉ上に直流放電を用い
たＣＶＤ法によシ次の反応に従って連続的に例えば＾ｌ
からなる第一層金！ｊｔ４層３、Ｔ１からなる第二贋金
ＰＡ／ｄ４、ＴｉＮからなる第三層金属層５を形成する
。
２　Ａ　ｌＩｃｌ５　＋３Ｈｔ→２Ａｌｌ＋３ＭＣＩＴ
　ｉ　Ｃ１＋＋　２　Ｈｌ−＋Ｔ　ｉ　＋４　ＭＣＩＴ
　：Ｃ１４＋　ＮＨｓ　＋　４　Ｈｓ→Ｔ　ｉ　Ｎ＋４
　ＨＣＩここで、各金属層３，４．５を形成する際の真
空度は例えば３．０Ｔｏｒｒであ）、温度は５５０℃に
設定した。次いで、各金属層３，４．５を写真蝕刻法に
てパターニングした後、５７０℃で３０分閣Ｈｔ　’Ｅ
囲気中でアニールを施す。この場合、各金属層３，４．
５のストレスが互に打ち消し合う様に働くために、半導
体基板１０反応を極めて小さくすることができる。因み
に、第一層金Ｘｌ５Ｍ３の厚さが４．０　μｍｓ　Ｊ二
層合札ノＪ４の厚１が２５０ＯＡ。
第三７ＩＱ金属層５の厚さが６００ＯＡで半導体基板１
が４インチφのウニ八を構成している場合の反応は３０
μｍ以下である。
次に、第１図（Ｂ）に示す如く、第三層金属層５を含む
絶縁膜２上に例えばＮ＋からなる第四層金属層６及びそ
の上にＡｕ層２をスパッタ法にて形成し、これらに写真
蝕刻法にてパターニングを施す。
然る後、これに３００℃で約２０分間Ｈｚ’Ｊ囲気中で
焼成を施す。
次に、第１図（Ｃ）に示す如く、Ａｕ層７を含む絶縁膜
２上にプラズマ８１．Ｎ、膜８を厚さ約０．８μｍ形成
し、これに写真蝕刻法にて所定のパターニングを施す。
次に、半導体基板ｌに裏面加工を施し、所定の厚さにし
た後、例°えばスパッター法によｆｉ　Ｖ／Ｎｌ／　Ａ
　ｕの３層からなる８面電極９を形成する。
然る後、半導体基板１にダイシング加工を施し、個々の
牛導体累子に分割した後、これをアセンブリして半導体
装置を得る。
このように構成された半導体装置では、第Ｒｉ金！Ａ層
３はオーミックコンタクトを形成している。
また、第二層金鵜層４は、大′シ流特性の電流バランス
（低抵抗）を考慮して、第一層金属層３と第三Ｍ金！Ｕ
Ｎｓとのバリアメタルとなっている６また、第四層金属
層６は、半田のダイレクトマウント用のメタルとなって
いる。なお、第四層金属層６−ヒのＡｕ層７は、Ｎ１か
らなる第四層金属層６が非常に酸化されやすいので、半
田のぬれ性を損わないように積層されたものである。
このように構成された半導体装置２０は、第２図に示す
如く、例えばヒートン／り２１上に設けられたセラミッ
ク基板２２上に半田層２３を介して裏面電極９を装着す
ることができる。また、半導体装置２０のＡｕ層７上に
半田層２３を介して他の半導体装置２４を装着すること
ができる。ま九、半導体装置２０の他のＡｕ層２上にリ
ードフレームからのアルミボンディングｆｆｆＡ２５を
取付けることができる。このような構成の半導体装置２
０の組立てを実現できるので、アセンブリ工程を節略化
し、不要なアルミボンディング線を廃止し、セラミック
基板２２を縮小化すると共に、エンキャップ材及びモー
ルド材の使用量を少なくして＄４ｉコストを低減させる
ことができる。
なお　３２図中２４ａは他の半導体装置２４を構成する
コレクタＮ領域、２４ｂはコレクタＮ−領域、２４Ｃは
ベース領域、２４ｄはエミッタ領域、２６は、実施例の
ものと同様の第一層〜第四層からなる本発明の多層電極
構造を示している。
因みに、第２図に示した半導体装ｆｌｔ２０の組立て構
造によるものでは、同様の機能を備えた従来の構造のも
のに比べて、セラミック基板２２０面積を約１／２に縮
小し、エンキャップ材及びモールド材の使用量を約５０
％削減して、コストパフォーマンスを約４０％低減でき
ることが実験的に１誌されている。
また、本発明の多層゛ば極構造を有するトランジスタと
、バイポーラＩＣを所定の素子上に装着したパイグリッ
ド構造のものを組立てることも可能である。同様に本発
明の多層成極構造を有するトランジスタ、ダイオード、
Ｐ−ＭＯＳの少なくとも１つの素子上に、トランジスタ
、ダイオード、Ｐ−Ｎ０８、バイポーラＩＣ％ＭＵ８Ｌ
ＳＩを接続したへイブリッド構造を組立てることも可能
である。
［−発明の効果コ 以上説明した如く、本発明に係る半導体装置によれば、
アセンブリ工程を簡略化し、アルミボンディング紗の廃
止、セラミック基板の縮小化、エンキャップ材及びモー
ルド材の使装置の削減を達成して製造コストを低減させ
ることができるものである。
【図面の簡単な説明】
第１図は、本発明の概略イ３成を製造工程に従って示す
説明図、第２図は、本発明の効果を示す説明図である。 ！・・・半導体基板、Ｚ８・・・コレクタＮ　領域、１
ｂ…コレクタＮ　領域、１ｃ・・・ベース領域、Ｉｄ・
・・エミッタ領域、２・・・絶縁膜、２ａ、２ｂ・・・
コンタクトホール、３・・・第一１−金ＩＡ層、４・・
・第二層金属層、５・・・第三層金属島、６・・・ｋ５
四層金属層、２・・・ＡｕＱ、８・・・プラズマ８４．
Ｎ、膜、９・・・裏面電極、２０・・・半導体装置。

Claims (1)

    【特許請求の範囲】
  1. 半導体基板上の所定領域上に形成され、Ａｌ、Ｐｔ、Ｍ
    ｏＳｉ＿２、Ｍｏ、ＴｉＮ、ＴｉＣ、ＴａＮ、ＴａＣ、
    ＨｆＮ、ＺｒＮ、ＺｒＣの少なくとも何れか一種からな
    る第一層金属層と、該第一層金属層上に形成され、Ｔａ
    、Ｔｉ、Ｖ、Ｃｖ、Ｚｒ、Ｈｆ、の少なくとも何れか一
    種からなる第二層金属層と、該第二層金属層上に形成さ
    れ、ＴｉＮ、ＴｉＣ、ＴａＮ、ＴａＣ、ＨｆＮ、ＨｆＣ
    、ＺｒＮ、ＺｒＣの少なくとも何れか一種からなる第三
    層金属層と、該第三層金属層上に形成され、Ｎｉ、Ｃｏ
    、Ｓｎ、Ｃｕ、Ｆｅ、Ａｇ、Ａｕの少なくとも一種から
    なる第四層金属層とを具備することを特徴とする半導体
    装置。
JP61072859A 1986-03-31 1986-03-31 半導体装置 Pending JPS62229973A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61072859A JPS62229973A (ja) 1986-03-31 1986-03-31 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61072859A JPS62229973A (ja) 1986-03-31 1986-03-31 半導体装置

Publications (1)

Publication Number Publication Date
JPS62229973A true JPS62229973A (ja) 1987-10-08

Family

ID=13501495

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61072859A Pending JPS62229973A (ja) 1986-03-31 1986-03-31 半導体装置

Country Status (1)

Country Link
JP (1) JPS62229973A (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5294486A (en) * 1990-10-22 1994-03-15 International Business Machines Corporation Barrier improvement in thin films
JP2011049382A (ja) * 2009-08-27 2011-03-10 Fujitsu Ltd 半導体装置及びその製造方法
JP2014232859A (ja) * 2013-04-30 2014-12-11 豊田合成株式会社 半導体装置およびその製造方法
JP2015070026A (ja) * 2013-09-27 2015-04-13 豊田合成株式会社 半導体装置およびその製造方法
CN109449271A (zh) * 2018-11-01 2019-03-08 佛山市国星半导体技术有限公司 一种具有焊料电极的led芯片及其制作方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5294486A (en) * 1990-10-22 1994-03-15 International Business Machines Corporation Barrier improvement in thin films
JP2011049382A (ja) * 2009-08-27 2011-03-10 Fujitsu Ltd 半導体装置及びその製造方法
JP2014232859A (ja) * 2013-04-30 2014-12-11 豊田合成株式会社 半導体装置およびその製造方法
US9437525B2 (en) 2013-04-30 2016-09-06 Toyoda Gosei Co., Ltd. Semiconductor device and manufacturing method thereof
JP2015070026A (ja) * 2013-09-27 2015-04-13 豊田合成株式会社 半導体装置およびその製造方法
CN109449271A (zh) * 2018-11-01 2019-03-08 佛山市国星半导体技术有限公司 一种具有焊料电极的led芯片及其制作方法
CN109449271B (zh) * 2018-11-01 2024-04-16 佛山市国星半导体技术有限公司 一种具有焊料电极的led芯片及其制作方法

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