JPS62114164A - PCM audio signal recording and playback device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an apparatus for recording and reproducing PCM audio signals together with video signals or alone using a rotating head scanner.
This is particularly suitable when the relationship between the sampling frequency and the field frequency of the video signal or the rotational frequency of the rotary head is asynchronous.

[Conventional technology]

Conventionally, as a method for recording and reproducing digitized audio using a rotary recording and reproducing device using a rotating head, there is a PCM recorder using Soba's VTR1, and this method is based on the Japan Electronics Machinery Industries Association Technical Standards CPZ. -105 "PCM Encoder/Decoder for Consumer Use" (established in September 1983), its specifications are shown. Furthermore, there is a rotary head type digital audio tape recorder (R-DAT) dedicated to recording audio, and this type is described in, for example, the ``Technical Standards for Rotating Head Type (H,-DAT)'' (Dempa Shimbun, Showa Part of the specifications were published in the October 7, 1960 issue, p. 48). In either case, the digitized audio signals are grouped into a predetermined number of bits, and then
This method records data as one block. At this time, if necessary, a synchronization signal that serves as a reference for signal detection and an error detection and correction circuit are added to each block, and these additional signals form one block. are doing. When recording on a hunting tape, a certain number of blocks are grouped together into one field (equivalent to one scan of a rotating head).
This method records data within a period of . In conjunction with such recording and reproduction of digital signals, interleaving and dinterleaving of digital data are performed in both methods. In other words, part of the digital data that is input chronologically during recording is stored in memory and read out from the memory according to a predetermined rule (interleaving).In accordance with this read order, the data of each block and furthermore the data of each field are formed. , recorded on tape. During playback, the data is sequentially stored in memory according to the order in which it was played, and then read out from memory according to predetermined rules (dinterleave).
, the original audio signal is obtained through digital-to-analog conversion. However, in the above process, due to tape dropouts, noise contamination during playback, etc., the data that should have been played back is not manually stored in the memory, and the data may be out of order when rewritten to the memory during playback. It is expected that this will happen. In consideration of this situation, especially in the R,-DAT method, an address signal indicating the relative order with respect to other blocks is added to each block, and this address, ! ! .

A method is used in which digital data is recorded at a predetermined address on memory according to a signal.

However, when recording a PCM audio signal together with a video signal using a rotating head helical scan VTR, if the video signal is of the 525760TV system, the sampling frequency (#
The PCM audio signal of Hoshi Broadcasting has a sampling frequency of fs -52K.
Hz, 48KHz) cannot be divided, so 1
The number of blocks per field is a fraction.

For this reason, a block group, which is a collection of a certain number of blocks subjected to signal processing such as interleaving and dinterleaving, becomes discontinuous between fields, causing a problem.

In R-DA'l', there is a certain relationship between the field frequency fv and the sampling frequency fs, and the field frequency a
The case where fS is uncorrelated is not considered, and
4 - The above conventional technology requires that there is a synchronous relationship between the audio signal sampling frequency and the field frequency, and if there is no synchronous relationship between the sampling frequency and the field frequency, For recording and reproducing systems where the number of data blocks in each field does not necessarily match, 11, and it was extremely difficult to directly record video signals and PCM audio as digital signals.

An object of the present invention is to realize a digital audio tape recorder that can record and reproduce video signals and audio signals simultaneously, even if there is no pressure synchronization relationship between the audio signal sampling frequency and the field frequency.

[Means for solving problems]

The above purpose is to divide a PCM audio signal into blocks, add a data block address signal indicating the relative order of this block and other blocks, complete the signal in a field cycle, and further perform signal processing such as interleaving and dinterleaving. An interleave block address signal indicating the relative order of this block and other blocks is added to each block of a block group in which a certain number of blocks to be processed are collected, and the blocks are completed at a period synchronized with the sampling frequency, and This is achieved by alternately attaching interleaved block address signals and identification signals to the blocks.

[Effect]

One block generated when recording a signal includes a data block address signal that is completed in one field, an interleave block address signal that is completed in a certain number of block groups that undergo signal processing such as interleaving, and an identification signal. There is.

During playback, this data block address signal is used to process one field at a time, and the interleave block address signal and identification signal are used to perform signal processing such as dinterleaving. Even if they do not necessarily match, malfunctions will not occur.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
The figure shows an example of the configuration of a PCM audio signal recording and reproducing apparatus according to the present invention.

For the self-recorded pressure, a two-channel H analog signal is input from input terminal 1. The input signal is amplified to a predetermined level by an amplifier circuit 2, band-limited by a filter 3, and then sampled by a sample hold circuit 4. The sampled input signal is sequentially input to the N-width converter 6 by the switching circuit 5 and converted into a PCM signal. The PCM signal converted by the converter 6 passes through the pass line 14 and is sent to the R and AM 15.

Then, the address generation circuits 17 to 19 and the address switching circuit 16 control the address of the FLA M2S, and arrange the PCM signal and add the error correction code.

Note that the addition of the entertainment correction code is performed using the error correction circuit 20.

Placement of PCM signal and addition of error correction code are performed, 7
.

After the data is stored, each data is stored in 'FLAM1' in block units.
5 and is converted into parallel data or serial data by the parallel-to-serial conversion circuit 23. Then, a control signal is added by a control signal generation circuit 24 and a selection circuit 25, and modulated by a modulation circuit 26 according to a predetermined modulation method. The modulated signal is amplified to a predetermined level by a recording amplifier 27, passed through a switching circuit 28, and is recorded on a magnetic tape 30 by a rotary head 29. At this time, the video circuit 3
A video signal inputted from one input terminal 32 is also recorded on the magnetic chip 30 by the rotary head 29. The magnetic head 64 is a recording/reproducing head for control. Further, the timing generation circuit 21 is a circuit that generates a timing signal using the clock generated by the rooting circuit 22.

During reproduction, the switching circuit 28 is switched to the reproduction side, and the signal reproduced by the rotary head 29 is input to the reproduction amplifier 65 and amplified. Further, a waveform equalization circuit 36 performs waveform equalization, and a demodulation circuit 37 demodulates the digital signal. This, 8.

A synchronization signal is extracted from the digital signal by a synchronization signal detection circuit 58, and this synchronization signal and a head switching signal 39 output from the head 34 are sent to the timing generation circuit 21 as a reference signal for a required timing during reproduction. On the other hand, among the digital signals, signals other than the synchronization signal are converted from serial data to parallel data by the stone conversion circuit 40, and the control signal added by the control signal generation circuit 24 is sent to the control signal processing circuit 41. The signal is pass line 14
sent to. The data on this pass line is then R
The data is stored in the AM 15, and the data is rearranged and error correction is performed by the error correction circuit 20. The PCM signals rearranged in chronological order are sequentially converted into analog signals by the D/A converter 12, and resampled by the sample and hold circuit 11 for each channel. The analog signal resampled in each channel is filtered by filter 1.
0 and is outputted from the output terminal 8 through the amplifier circuit 9.

Here, the control signal generation circuit 24 will be explained.

The control signal generation circuit 24 includes a synchronization signal generation circuit 42 that generates a synchronization signal, and an interleave block address (L
EI ADR) signal generation circuit 43 , data block address (NA ADR) signal generation circuit 44 , identification signal (ID code) generation circuit 45 , obscurity code (OP code) generation circuit 46 , and parity generation circuit 47
It consists of Each 4iT number generated by the control signal generation circuit 24 is selected and added to each block by a selection circuit 25 in accordance with a predetermined block format, together with the data sent out from the parallel-to-serial conversion circuit 23.

Next, one embodiment of the block format will be explained with reference to FIG. One block includes a synchronization signal 48, Wl (data block address signal and identification signal) 49, Wl (interleave address signal) 50, Wl 49 and W25.
It consists of a parity signal 51 generated from 0, digital data 52, and an error correction code 53. Synchronization signal 48
is made up of a specific 8-bit pattern that indicates the beginning of a block, and serves as a time reference when capturing data during playback. The data block address signal is a signal indicating the address on the RAM memory of digital data forming one block, and based on this signal, the reproduced digital data is stored at a predetermined address on the memory. , subsequent processing is performed.

Further, the identification signal indicates various information accompanying the audio signal to be recorded. The interleave block address signal 50 is a signal indicating an address on the memory in R and AM for performing processing such as interleaving and dinterleaving. Based on this signal, interleaving processing is performed, and furthermore, during playback, , based on this signal, performs a dinterleaving process on the digital data of the block written to a predetermined address by the data block address signal. The next parity signal 51 is a parity signal generated from the previous 16 bits, ie, Wl 49 and W250, and is generated by processing such as simple addition modulo 2, for example. This signal is Wl 4
9 and 11°W250 error detection and correction are performed to protect these signals from dropouts and noise.

The data 52 is, for example, digital audio data consisting of 224 bits, and the error correction code 53 is an error correction code of 32 bits in units of 8 bits, which constitutes, for example, a Reed-Solomon code generated from this digital audio data 52.

Next, an embodiment of Wl will be explained in detail with reference to FIG. Wl
data block address signal 54°55.5 to 57
and identification signals 58, 59, 60, and 61 are written alternately. During playback, the data block address signal and identification signal are detected using the MOB flag.

For example, if the MSB is ``0'', it is a data block address signal, and if it is @1'', it is an identification signal.The data block address signal is a block group corresponding to one scan (one field) period of the rotating head. For example, a cyclic code from O to N is used as an address signal.The identification signal consists of a 3-bit optional code and a 2-bit ID code.ID code There are eight types of information signals, for example, ID-1 of the job signal 58 contains format information, ID-2 contains emphasis information of the audio signal, and ID of the identification signal 59.
-3 is sampling frequency information, ID-4 is channel number information, ID-5 of identification signal 60 is quantization bit number information, ID-6 is tape speed information, and ID-7 of identification signal 61 is information. is the copy permission information, and ID-8 is the back data information. Detection of ID codes 1 to 8 corresponds to the lower bits of the data block address signal of the previous block. For example, if the lower 2 bits of the data block address signal of the previous block are "oo", it is determined as ID-1. I
D-2, @01'' ID-5 and ID-4, @1
0” is ID-5 and ID-6, and 11111 is 1D.
-7 and ID-8.

Next, one embodiment of Wl will be explained with reference to FIG. W
The interleaved block address signal of 1 consists of 8 bits, and the MSB flag indicates the PCM data of the block.
Indicates whether or not to import data. For example, @0'' means data is taken in, and 11'' means no data is taken in.

The remaining 7 bits indicate the relative order for the dinterleaving process of interleaving. For example, when interleaving is completed with 128 blocks, this address is a cyclic code that sequentially multiplies 1 bit at a time from 0 to 127. It is.

Another embodiment of the present invention will be described with reference to FIG.

An identification signal and a data block address signal are alternately input to Wl49, and are made to correspond to W250, that is, the lower three bits of the interleave block address signal. For example, W
Identification signal 49 when the lower 3 bits of 250 are 1000''
Enter -1. Furthermore, the lower bit of W250 is l'00
1″, data block address 49-2.@01
0'', the identification signal 49-3, @011'', the data block address 49-4, 100, the identification signal 49-5, '101'', the data block address 49-6, 1110", identification signal 49
-7, "111", enter data block address 49-8. At the time of playback, the bottom 3 of this W250
Depending on the bit, it is determined whether it is an identification signal or a data block address, and further KV/It signals 49-1, 49-3.
49-5.49-7.

Here, the identification signal 49-1 is the ID code ID code 1 and I
D code 2, frame address, and identification signal 49-3 are ID-5, ID4, frame address, and identification signal 49-3.
-5 is composed of ID-5, ID-6 and frame address, and identification signal 49-7 is composed of ID-7, ID-8 and frame address. The frame address is, for example, an address signal indicating the relative order of each scan (one frame) of the rotating head.

Next, another embodiment of the W250 will be described with reference to FIG. W250 is an interleaved block address signal consisting of 8 bits, and is completed every 12B block.

A flag identifying the block group before and after the 128 blocks (block group) is added to the MSB of this address signal. With this flag, for example, when M2R is lIO'', block group 50-2' is set to block group 50-1.11''.
By ItR.

For example, if the R-DAT format is used, M
OB@o ``yR-DAT's +azimuth track data MSB@1'' is made into R-DAT's 1 azimuth track data, so it can be identified.

One block configured in this manner is further collected into N blocks, and for example, 142 or 145 blocks are recorded within one field, that is, one scanning period of the rotary head.

Here, when using a data format that is completed with interleaved blocks as shown in FIG. A block address signal causes writing to a predetermined address in the memory for dinterleaving, and when the interleave block is completed, dinterleaving processing is performed.

, 16° 8 shows a specific embodiment of the control signal processing circuit 41, and the present invention will be explained in further detail.

The synchronization signal detection circuit 38 is the synchronization signal pattern extraction circuit 3
8-1 and a synchronization signal detection and protection circuit 38-2, and generates a block synchronization signal and a word synchronization signal.

In the control signal processing circuit 41, the block address latch 4
1-1. Interleaved block address latch 41-
2. ID signal latch 41-4. Block address detection protection circuit 41-4. Interleaved block address detection protection circuit 41-5 and ID signal detection protection circuit 41-6
41-7 is an ID signal output, which outputs control signals such as sampling frequency and emphasis. Here, the interleaved block address is protected by a block address signal or the like. This is to protect the interleaved block from errors or omissions that occur between fields because pressure waves between fields are discontinuous.

For example, various address data are sequentially advanced by a correction counter or the like in the event of a signal error, but this correction error can be checked and corrected by referring to the various address data.

Further, the number of samples in the field is extracted by the control signal processing circuit 41, and based on the same signal, the timing generation circuit 2
1 generates a control signal for the read address circuit 19 and controls the circuit 19.

〔Effect of the invention〕

According to the present invention, by adding each block pressure data block address signal and an interleave block address signal, even if the number of blocks in one field is not a constant number, ink + 13-b. Signal processing such as dinterleave is related to the field period. Therefore, it is effective in systems where the sampling frequency and the field frequency are not synchronized.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a PCM audio format showing an embodiment of the present invention, FIG. 3 is a diagram showing Wl in FIG. 2, FIG. 4 is a diagram showing W2 in FIG. 2, and FIG. 5 is a diagram showing Wl in FIG. , FIG. 6 is a diagram showing another embodiment of W2, and FIG. 7 is a diagram showing another embodiment of W2.
The figure shows an interleaved block format, and FIG. 8 is a configuration diagram of a control signal processing circuit. 24... Control signal generation circuit, 42... Synchronization signal generation circuit, 43... Interleave block address signal generation circuit, 44... Data block address signal generation circuit, 45... Identification signal (ID code) Generation circuit, 4
6...opinion (OP) code generation circuit, 47...
- Parity generation circuit, 48... synchronization signal, 49...
Data block address signal and identification signal, 50...
Interleave block address signal, 51... Parity signal, 53... Error correction code.

Claims (1)

[Claims] 1. In an apparatus for recording and reproducing a PCM audio signal using a rotary head scanner, the PCM audio signal is divided into blocks, and the relative order of each block with respect to other blocks is indicated. , and add a data block address signal that is completed in one track, and further collect a certain number of these blocks to form a block group to which signal processing is performed, and identify the identification signal that is completed in the block group and the data block address signal that is completed in one track. A PCM audio signal recording and reproducing apparatus characterized in that an interleave block address signal indicating a relative order is added to the block. 2. In claim 1, the data block address signal and the identification signal are placed alternately in one block, and the first flag is used to recognize the data block address signal and the identification signal. A PCM audio signal recording and reproducing apparatus characterized in that a signal is made to correspond to a lower flag of a data block address signal of a previous block. 3. A PCM audio signal recording and reproducing apparatus according to claim 1, characterized in that the data block address signal and the identification signal are input alternately in blocks and are made to correspond to the lower bits of the interleaved block address.