JPS62107496A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To decrease the area of a cell simultaneously read and write different in address and to obtain high density by constituting a memory cell of four pieces of MOSFET. CONSTITUTION:When a writing exclusive-use work line WW is turned on, an N channel MOSFETN1 is turned on. Next, a writing exclusive-use bit line WB is set to the signal level to be written, and an input capacity CM between an input electrode I of a CMOS inverter constituted by a P channel MOSFETP1 and an N channel MOSFETN2 and the channel is discharged or charged. At the time of reading exclusive-use wod line RW is turned on, the signal inverted and amplified to an inverter output O is read, and by turning on an N channel MOSFETN3, outputted to a reading exclusive exclusive-use bit line RB. By such constitution, the cell capacitor is made unnecessary and the high density can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor memory cells suitable for high-density semiconductor memories.

BACKGROUND OF THE INVENTION Semiconductor memories are widely used because of their high speed, high integration, and ease of use, but there is a demand for larger capacities and higher densities. Dynamic random access memory (dRAM) has fewer elements per cell than static random access memory (sRAM), so with the same process standard, it can achieve approximately 4 times the storage density. We are one step ahead in this respect. dR
As an AM memory cell, it is still very popular today (the cell used is a one-transistor, one-capacitor structure).

A conventional one-transistor/one-cavanter structure memory cell will be explained using circuits similar to the memory cell shown in FIG. As shown in FIG. 3, a conventional memory cell consists of one transistor T, one capantor C, and a bit line BL and word line WL connected to the transistor T. When writing a signal into a cell, first the bit line BL is charged or discharged to the signal level desired to be written, and the word line WL is selected by a decoder circuit (not shown) and a transistor is turned on. When T is turned on, cell capacitor C is charged or discharged to the signal level. When the write cycle is completed, T is turned off and a signal is stored in cell capacitor C.

In a read cycle, the word line WL is first selected, the transistor T is turned on, and the signal stored in the cell capacitor C charges or discharges the bit line BL. Subsequently, a sense amplifier (not shown) amplifies the potential change of the bit line and outputs a signal.

Problems to be Solved by the Invention Normally, a cell capacitor is formed from a 50A to several tens of OA silicon oxide film formed by thermally oxidizing a silicon substrate, a polycrystalline silicon electrode formed directly above the silicon oxide film, and a silicon substrate. As density increases, it is necessary to reduce the area of the capacitor, which occupies most of the cell area, but on the other hand, it is necessary to ensure that pit rewriting (soft errors) does not occur due to radiation and that there is sufficient capacity to charge the bit line capacitance during readout. In order to hold a certain amount of charge, the cell capacitor must have a capacitance of at least 30 to tsofF. Therefore, in order to reduce the area of the cell capacitor, methods of thinning the oxide film or replacing the oxide film with a thin film of a high dielectric constant material are being considered.

However, there is a limit to how thin an oxide film can be made, which is determined by its own withstand voltage, and it is considered difficult to reduce the thickness to below tsoX in practice. Furthermore, as for the high dielectric constant material to replace the oxide film, no suitable material has yet been found considering process stability as well. The first object of the present invention has been made in view of the problem that the area occupied by a cell capacitor cannot be sufficiently reduced in such a conventional memory cell structure.

Further, in the conventional memory cell structure, reading and writing cannot be performed at the same time even if the addresses are different. In application fields where high-speed operation is required, this is a major constraint on use.

A second object of the present invention is to improve the above-mentioned problems of conventional memory cells and to provide a semiconductor memory cell that can perform reading and writing at the same time if they are at different addresses.

Means for Solving the Problems The present invention does not use a conventional memory cell consisting of one transistor and one capacitor, but instead has three N-channel transistors, one P-channel transistor, a write-only word line, a write-only bus, and a read-only word line. By providing a cell with a line and a read-only bus, the above-mentioned problems are attempted to be solved. That is, a capacitor between an input electrode and a channel (silicon substrate) of a CMOS inverter is used instead of a cell capacitor, and the inverter output is output to a read-only bus.

Even if the working capacitance is small, the output is amplified by the CMOS inverter and a reliable signal is output.

Furthermore, since the write and read buses are separate, it is possible to read a signal from a memory cell at a different address while writing to a certain memory cell. Furthermore, in the memory cell of the present invention, the source of the P-channel transistor of the CMOS inverter is connected to the read-only word line, and the source of the N-channel transistor is connected to the write-only word line, so the ground line and power line are wired for each memory cell. The configuration is suitable for high-density memory.

EXAMPLE An example of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 shows a dRAM consisting of memory cells in which word lines RW and WW are polycide wires and buses WB and RB are mullion wires. To explain the configuration in more detail, the gate of the first N-channel MOSFET N1 is connected to the write-only word line Ww and the source and all the write-only bit lines WB, and the first N-channel MOSFET
]! : the drain of T N, and the second N channel M
The gate of OS FET N2 and the gate of the first P-channel M OS F E T P are commonly connected, and the source of the second N-channel M OS F E T N is connected to the write-only word line WW. and connects the source of the first P-channel MOS FET Pl to a read-only word line RW, and connects the drain of the second N-channel MO3FXTN2 and the source of the first P-channel MOS FET Pl to the read-only word line RW. drain and third
The sources of the N-channel MOSFET N3 are connected in common, the gate of the third N-channel MOSFET N3 is connected to the read-only word line RW, and the drain is connected to the read-only bit line RB. CM is the input electrode, and CM is the capacitance between the input electrode and the channel (silicon substrate) of the CMOS inverter.

FIG. 2 is a timing chart of the operation of this memory. First, at time t1, the write-only word line is turned on,
The memory cell enters a write cycle. Peck time t
In step 2, the write-only bit line WB is set to a signal level desired for writing (the o'v level in the figure), and the inverter input capacitor CM is discharged or charged (discharged in the figure). At time t3, WW is turned off and the write cycle ends. Next, at time t4, the read-only word line RW is turned on, and the inverted signal is read out to the inverter output 0.

At time t5, RW is turned off and the read cycle ends.

Effects of the Invention The memory cell of the present invention has twice the number of elements compared to a conventional one-transistor/one-capacitor cell, but the size of the transistor is a fraction of that of a capanta cell.
As miniaturization technology progresses, the memory cell of the present invention becomes more superior to conventional memory cells. Furthermore, since the word lines and bus lines are divided into write and read lines, it is possible to write a signal into one cell with a different address while reading the signal from the other cell. Furthermore, since the memory cell of the present invention does not require wiring of power supply lines and ground lines, the degree of freedom in arranging word lines and buses is increased, and it can be said that the structure is suitable for high density.

Although the memory cell of the present invention is formed on a silicon substrate in the embodiment, it is clear that part or all of it may be formed on a silicon-on-insulator (SOI) structure. Will. In particular, it is possible to reduce the area of a memory cell by forming an N-channel transistor (or P-channel transistor) on a silicon substrate and forming a P-channel transistor (or N-channel transistor) in an SOI layer above it. can.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit diagram for explaining the memory cell in one embodiment of the present invention, FIG. 2 is a timing chart diagram for explaining the operation of the memory cell of the present invention, and FIG. 3 is a conventional memory cell. FIG. 2 is an equivalent circuit diagram for explaining. N,, N, N1. ,...N4-Toritaru MnR++Tanso,...) Hook P1...P-channel MOS transistor, CM...Input capacitance of CMOS inverter, RW...Read-only word Line, WW・
...Write-only word line, WB...Write-only bus, RB...Read-only bus. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 tttz ts t4ts fT74 Figure 3 L

Claims (1)

[Claims] The gate of the first N-channel MOSFET is connected to a write-only word line, the source is connected to a write-only bit line,
The drain of the first N-channel MOSFET and the second
The gate of the N-channel MOSFET and the gate of the first P-channel MOSFET are commonly connected, and the gate of the second N-channel MOSFET is connected in common.
a source of a channel MOSFET connected to the write-only word line, and a source of the first P-channel MOSFET connected to the write-only word line;
a source of the second N-channel MOSFET is connected to a read-only word line, a drain of the second N-channel MOSFET, a drain of the first P-channel MOSFET, and a source of a third N-channel MOSFET are commonly connected; A semiconductor memory cell comprising a MOSFET whose gate is connected to the read-only word line and whose drain is connected to the read-only bit line.