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JPS61274332A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS61274332A
JPS61274332A JP60115681A JP11568185A JPS61274332A JP S61274332 A JPS61274332 A JP S61274332A JP 60115681 A JP60115681 A JP 60115681A JP 11568185 A JP11568185 A JP 11568185A JP S61274332 A JPS61274332 A JP S61274332A
Authority
JP
Japan
Prior art keywords
semiconductor chip
chip
electrode
lead
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60115681A
Other languages
English (en)
Inventor
Kimihiro Ikebe
池部　公弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60115681A priority Critical patent/JPS61274332A/ja
Publication of JPS61274332A publication Critical patent/JPS61274332A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
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    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
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    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置に係り、特に高密度に実装されたピ
ングリッドアレイ（ＰＧＡ）パッケージの半導体装置に
関する。
（発明の技術的背景とその問題点〕 第４図（ａ）、（ｂ）にそれぞれＰＧＡパッケージの従
来例の平面図および断面図を示す。これによれば多層あ
るいは単層のセラミック板からなるベース１の中央凹部
のマウント部に半導体チップ２がマウントされ、半導体
チップ２の上面と略同等の高さの段部１ａが半導体チッ
プ２の周囲に形成され、この段部１ａにタングステン、
モリブデン等の金属がリードパターン状に印刷、焼成式
れたメタライズ層３が形成されており、このメタライズ
層には各リードパターンに外部引き出し電極となるリー
ドピン４が例えばロウ付げにより接合されている。そし
て、半導体デツプ２の電極と、対応するメタライズ層の
リードパターンとがボンディングワイヤ５によって接続
されて構成されている。
このような半導体装置に対して、近年、高集積化が要求
され、半導体チップ上の電極およびパッケージのピン数
の増加により対処しているが、電極ピッチの縮小はワイ
ヤボンディングを著しく困難にする等の問題点があり、
十分な＾集積度は得られていない。
〔発明の目的〕
本発明は上記事情を考慮してなされたもので、高密度実
装により高集積化が可能なＰＧＡパッケージの半導体装
置を提供することを目的としている。
〔発明の概要〕
上記目的達成のため、本発明による半導体装置は一の半
導体チップの裏面と他の半導体チップの裏面とが接着さ
れた積層チップと、この積層チップのうちの下側の半導
体チップ表面上の電極と直接接続された第１の引出導体
および上側の半導体チップ表面上の電極とワイヤにより
接続された第２の引出導体とを有する積層チップ搭載用
のベースと、第１および第２の引出導体に接続され、ベ
ースから導出された外部接続ピンと、を備えている。こ
れにより単位面積あたりの実装密度が向上しａ１ｆ！積
化を図ることができる。
（発明の実施例〕 以下、本発明の一実施例を第１図および第２図を参照し
て具体的に説明する。
これらの図において、複数のセラミック板が積層されて
ベース１０が形成され、このベース１０の中央部分が低
くなってマウント部１０ａとなっており、このマウント
ｍ１０ａに半導体チップがマウントされるようになって
いる。この半導体チップは？！！極を上面側にした半導
体チップ１１の裏面と電極を下面側にした他の半導体チ
ップ１２の裏面とが金属ペーストあるいは絶縁性の両面
粘着テープ等を介して接合された積層チップとなってお
り、積層状態では上下両面に電極が位置するようになっ
ている。
ところでこのＷ４１ｉ！ｌチップ搭載前のベース１ｏは
第２図（ａ）の平面図、第２図（ｂ）の断面図に示され
ており、マウント部１０ａの上面にはタングステン、モ
リブデン等の金属を印刷、焼成してメタライズすること
により形成された電極１４が形成されている。この電極
１４は下側の半導体チップ１２の下面の電極に対応する
パターンとなっており、この電極１４はベース１０の下
方に突出するリードピン１３の一部に連結されている。
またマウント部１０ａの１１ｉｌｌＩｉｉにはマウン１
一部よりも高く形成された段部１０ｂが形成され、その
上面にはリードピンに連結されたメタライズされたリー
ドパターン１６が形成されている。この段部の高さはほ
ぼ積層チップの厚さに等しいことが望ましい。このため
にはベース１０は所望の−さのセラミックの板および枠
を積層して形成される。
積層チップのうち下側の半導体チップ１２上の電極には
はんだ等により突起（バンプ）１５が形成される。この
突起１５はマウント部１０ａの電極１４と対応しており
、これらを当接させて所定の加熱を行なうことにより積
層チップはベース１０上に固着される。次に上側の半導
体チップ１１上の電極と段部１０ｂ上に形成されたリー
ドパターン１６とがボンディングワイヤにより接続され
る。さらに、ベース１０上にシールキャップ１４が被せ
られて気密封止される。
第３図は本発明の別の実施例の断面図を示しており、フ
レーム２０に複数のマウント部２０ａ。
２０ｂ、２０ｃが形成され、各マウント部２０ａ。
２０ｂ、２０ｃに半導体チップ２１ａと２２８１２１ａ
と２２ｂ１２１ｃと２２ｃが接合された積層チップがマ
ウントされており、集積度をさらに向上させることがで
きるものである。
（発明の効果〕 以上のとおり本発明によれば、２′枚の半導体チップを
接合させた積層チップを使用したので、−半導体チップ
と引出導体との接続が立体的な２層構造となり、マウン
トピッチを縮小させることなく半導体装置の集積度を向
上させることができる。
【図面の簡単な説明】
第１図は本発明の一実施例による半導体装置の断面図、
第２図（ａ）、（ｂ）はそれぞれそのベースの平面図お
よび断面図、第３図は本発明の別の実施例の断面図、第
４図（ａ）、（ｂ）はそれぞれ従来装置の平面図および
断面図である。 １０・・・ベース、１１．１２・・・半導体チップ、１
３・・・リードピン、１５・・・突起電極、１４．１６
・・・メタライズ層、１７・・・ボンディングワイヤ。 出願人代理人　　猪　　股　　　　清 （０）　　　　　　　　　　　　　　　（ｂ）札２　図

Claims (1)

  1. 【特許請求の範囲】 １、一の半導体チップの裏面と他の半導体チップの裏面
    とが接着された積層チップと、 この積層チップのうちの下側の半導体チップ表面上の電
    極と直接接続された第１の引出導体および上側の半導体
    チップ表面上の電極とワイヤにより接続された第２の引
    出導体とを有する前記積層チップ搭載用のベースと、 前記第１および第２の引出導体に接続され、前記ベース
    から導出された外部接続ピンと、 を備えた半導体装置。 ２、ベースの第２の引出導体形成位置が、第１の引出導
    体形成位置よりも略積層チップの厚み分だけ高い段部と
    なっている特許請求の範囲第１項記載の半導体装置。 ３、第１の引出導体および第２の引出導体がメタライズ
    層である特許請求の範囲第１項記載の半導体装置。 ４、第１の引出導体と下側の半導体チップ表面上の電極
    とがバンプにより接合された特許請求の範囲第１項記載
    の半導体装置。
JP60115681A 1985-05-29 1985-05-29 半導体装置 Pending JPS61274332A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60115681A JPS61274332A (ja) 1985-05-29 1985-05-29 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60115681A JPS61274332A (ja) 1985-05-29 1985-05-29 半導体装置

Publications (1)

Publication Number Publication Date
JPS61274332A true JPS61274332A (ja) 1986-12-04

Family

ID=14668638

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60115681A Pending JPS61274332A (ja) 1985-05-29 1985-05-29 半導体装置

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2344217A (en) * 1998-11-27 2000-05-31 Nec Corp Multichip module comprising stacked semiconductor chips

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2344217A (en) * 1998-11-27 2000-05-31 Nec Corp Multichip module comprising stacked semiconductor chips

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