JPS61210975A - Electronic circuit testing method - Google Patents

Abstract

PURPOSE:To carry out an effective test by using a defect information by a first test result in a second test and masking a defect indication of the second test result. CONSTITUTION:An information giving a suitable indication to a digit correspond ing to a group sequence of a serial scanning vector is loaded in a memory position capable of addressing of a mask memory 104, before performing a test. When a comparator 112 performs an error indication, this indication is fed to an error controller 116 and an information relating to an error position in a matrix is accumulated in an error memory 120. In a completion of a first test, the contents of the memory 120 are converted into an information indicat ing a position in a matrix of the digit for giving the error indication and this information is loaded 118. When it is loaded, a second test is done under a further strict condition, and when a defect is identified, the outputs of a bit counter 124, a vector counter 126 and a pointer 128 are stored in the memory for an analysis afterward.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an input port for receiving an input vector, an output port for generating an output vector, and a serial scan port for generating a serial scan vector indicative of the state of a predetermined component. TECHNICAL FIELD The present invention relates to a method for testing an electronic circuit having a

[Prior art and problems] In the design of a complex integrated circuit (IC), the first step is
One is to prepare a mathematical model of the proposed circuit. Using this mathematical model, we simulate the operation of the proposed circuit to confirm whether the desired result can actually be obtained with this model IC. If the simulation shows that the IC operates as desired, the mathematical model is used to generate a manufacturing mask for the IC. Once a manufacturing mask is generated, a prototype IC can be manufactured.

microprocessor, computer interface,
Manufacturing complex ICs, such as complex logic circuit combinations, is very expensive and time consuming. Therefore, it is important to identify errors in IC design as soon as possible before manufacturing the product. Therefore, it is common to test a prototype IC by comparing its operation to that of a mathematical model. This comparison allows the IC design to be iterated if there are design flaws before resources are used to manufacture the product IC.

When generating a manufactured mask directly from a mathematical model, if the generating operation of the manufactured mask is performed appropriately and there are no manufacturing defects,
The prototype IC should operate accurately according to the mathematical model. However, the design system used to generate the mask may, for example, create a mask that does not have sufficient spacing tolerances between certain components of the IC. An IC with no manufacturing defects may function satisfactorily under ideal conditions of temperature, power supply voltage, clock frequency, etc., but may not function satisfactorily under more severe conditions. As operating conditions become increasingly severe, more and more latent design flaws become increasingly apparent.

Those skilled in the art will appreciate that thorough testing of complex ICs is time consuming. Tektronix S-3295
Using a conventional semiconductor test system, such as a mathematical model, a software simulator of the desired IC is created using a mathematical model, and input vectors generated with the aid of the mathematical model are supplied to the simulator. The simulator operates like a real IC in normal conditions and stores the output vectors generated by the IC. These two vector sequences form a database for prototype IC testing. The test system then tests the output ports by applying the same input vector sequence to the input ports of the circuit under test and using a simulator to compare the accurately obtained output vectors to the actual output vectors. This test system makes it possible to determine whether the prototype circuit is giving an accurate response according to the input vector, that is, whether the prototype circuit has any design flaws.

It will be appreciated that this type of testing does not generate very detailed information regarding the location of defective circuit components.

To alleviate this drawback, two different modes of operation,
That is, a complex IC is designed with a normal mode and a diagnostic mode. In this normal mode, the IC performs normal functions in conjunction with other circuits. Diagnostic mode also makes testing the IC particularly easy. One function that may be designed into such a circuit is a serial scan function. As shown in FIG. 2, the computer IC 2 receives an input vector from the 100 stop lines to the input port 4, performs various logical operations based on the digits of this input vector, and supplies an output vector to the output port. . If these logic operations can be stopped at several independent stages, first the input vector is transferred from the input port to the tenth stage 10.
supply to. This logic stage 1o performs a first series of logic operations and produces a first intermediate vector at its output, line 12. Since this intermediate vector is about 100 bits, the output of the 10th chic stage is about 100 lines. The output line of the tenth stage 10 is connected to the input of each cell of the shift register 14. Depending on the state of status pin 15, this shift register can operate as a parallel input/parallel output register (normal mode) or a parallel input (serial input)/serial output register. In normal mode, the first intermediate vector clocked into shift register 14 is immediately clocked into twentieth shift stage 12. The 20th chic stage operates logically on the first intermediate vector and produces a second intermediate vector on line 22 of its output port. Similarly, the second intermediate vector is also 100
It is about a bit. Clock the second intermediate vector into the second shift register 20. This 20th chic stage may generate the second intermediate vector and provide an auxiliary vector via line 24 to the 10th chic stage.

In normal mode, vectors clocked into shift register 20 are immediately clocked into the 30th shift stage. This 30th stage produces the final output vector of the IC at its output port.

For use in the logic operations of the first and 20th chic stages,
The 30th chic stage may supply one or more vectors via line 26 to the first and 20th chic stages.

This I(
Shift registers 14 and 20 are provided in ml'. Therefore, in diagnostic mode, status pin 15
When the voltage level applied to the shift register is applied to the shift register, the intermediate vector is available external to the IC by means of the serial scan port 28.

This can be done by connecting several shift registers in series, with the final cell connected to a single serial scan output pin, so that the intermediate vector is clocked serially through these registers and the bits of the vector are clocked serially through these registers. can be tested sequentially. Appropriate connections may be made to the IC's internal shift registers and specific vectors may be clocked into the IC to initialize these registers to a suitable state. This saves test time since very long input vector sequences are required to bring these registers to the same state.

Thus, by using the °scan test method, both register initialization and intermediate vector readout functions are obtained.

Although the intermediate vector may be clocked external to the IC via a single serial scan output pin, a more advantageous method is to clock the intermediate vector external to the IC via a single serial scan output pin.
Each register is connected to a respective dedicated serial scan pin of the boat 28, as shown in solid lines in the figure. Since each shift register is made up of over 100 cells, even if each shift register has a dedicated serial scan pin, the operation of transferring intermediate vectors from a shift register can be quite time consuming. . It is therefore preferred to divide each shift register into a number of segments, for example 16, with each segment connected to a dedicated pin of the serial scan port, as shown by the dotted lines in FIG. Obviously, it is desirable for each segment to contain approximately the same number of cells.

In the field of large scale IC design and manufacturing, the term "vector" refers to a digital word.

Thus, the input vector is a digital word that is applied to the input port of the IC. Generally, individual digits of the vector are present in parallel on each line of the plurality of line conductors. Similarly, the term "intermediate vector" refers to the digits that enter shift register 14 on line 12. However, when clocking these digits from the shift register in the IC's diagnostic mode, the digits are clocked in series rather than in parallel. Nevertheless,
Because of the origin of the digits, it is convenient to refer to them as vectors, specifically serial scan vectors.

Hereinafter, the term "serial scan vector" will be used to refer to a vector or part of a vector that occurs inside the IC, and the digits are available sequentially outside the IC.

As mentioned above, in order to test a circuit of the type shown in FIG. ) is applied in normal mode to the input port of the simulator comprising a shift register 14.20. Next, switch the register to diagnostic mode and clock the serial scan vector out of the IC. Additionally, the next intermediate vector may be scanned into the shift register from the scan input pin. The shift register is then returned to normal mode and one or more vectors are provided to the input ports. With the shift register in diagnostic mode, the serial scan port reclocks the serial scan vector 32 from the register. In this way, many input vectors can be applied to the input ports so that the input vectors and the serial scan vectors can be used to test the prototype IC.
form the base. Store the sequence of input vectors in force memory. In addition, force memory is I
It is so called because it is an input vector that forces a response by C. The serial scan vectors are also stored in a comparison memory. This comparison memory is so called because it contains the vectors generated by the simulator, which are compared with the actual vectors generated by the IC.

When testing a prototype IC, to identify defects, the test system provides the input vector sequence from the force memory to the IC and compares the serial scan vectors generated by the IC with the contents of the comparison memory. In order to confirm IC functionality not only under ideal conditions but also at the limits of evaluation standards, it is common to test ICs under progressively stricter conditions, such as temperature, voltage level, and clock speed. The same database may be used to perform different tests, or special databases may be created for specific tests. Testing under ideal conditions can be expected to find manufacturing flaws, while testing under more severe conditions can be expected to find flaws in design.

It will be appreciated that when the IC is in diagnostic mode, each group 34 of serial scan vectors clocked out of the IC is comprised of a matrix of digits. Note that the rows of this matrix are serial scan vectors, and the columns are I
is the set of digits available in consecutive clocks at the serial scan port of C. Also, because the register segments are not all the same length, some digits in the matrix are meaningless. However, there is a certain relationship between the digit positions of successive groups of serial scan vectors, such that the state of a particular cell (or segment) of the shift register is determined by the same digit of the same vector in successive groups of serial scan vectors. always appears within.

The ability to test the serial scan vector generated by an IC provides a high degree of discrimination when testing an IC and provides information regarding the location of potential design flaws.

Of course, it is also important to avoid obtaining false indications regarding defects. The data base thus includes, in addition to the force memory and the comparison memory, a third memory known as a mask memory. This mask memory identifies digits of the serial scan vector that do not need to be considered correct. This means that the value of the digit is ambiguous (1
or 0) or because its value is irrelevant to the particular part of the test. Thus, the information in the mask memory is used to prohibit the test system from providing an error or defect indication based on the comparison of specific digits of the serial scan vector generated by the prototype IC with corresponding digits in the comparison memory. .

Applying test vectors to a total of 100 or so pins of input ports is not a very effective method in identifying defects in an IC. By selecting test vectors appropriately, a wide range of tests can be performed using fewer vectors. Thus, some ICs are designed with diagnostic input ports having as few as 16 pins as well as having normal and diagnostic modes. In fact, some of these pins are typically input port pins,
Two types of internal connections (normal and diagnostic) are made depending on the voltage supplied to the status pin.

Even when the input vector is only 16 digits, the data base used for testing is very large.

Depending on the size of the database, it is very difficult for test engineers to detect errors in this database, and it is desirable not to modify the database during testing. If a manufacturing defect is identified during the first test under ideal conditions, the manufacturing defect must be tested in its original state, without eliminating it, before testing under more severe conditions to find the design defect. We should not continue to create new prototype ICs. However, if we continue to test a prototype IC with a design flaw, the existence of this flaw will cause problems in subsequent tests.
Multiple error indications result, and these double error indications obscure error indications regarding design flaws. To prevent double errors from occurring, the effects of manufacturing defects must be eliminated. Although this can be accomplished by changing the input vectors that the database generates, it is undesirable to change the database.

Also, when performing serial scan testing, groups of serial scan vectors are tested to identify digits within the group that indicate the presence of defects in the circuit. Traditionally, this identification involves the location of a digit indicating the presence of a defect in a group sequence of serial scan vectors generated during testing, i.e.
It is simply the form of an address in the compare memory that stores the corresponding digit value of the serial scan vector to which the defect is indicated. Since the sequence of serial scan vectors consists of on the order of 64 digits, it is difficult for the user to discern meaningful patterns from the error indications.

SUMMARY OF THE INVENTION The present invention includes an input port for receiving an input vector, an output port for generating an output vector, and generating at least one serial scan vector depending on the state of a predetermined component. A method for testing an electronic circuit of this type with a serial scan port is provided. The method provides at least one test vector to an input port, tests a serial scan vector after providing the test vector, and determines whether a portion of the serial scan vector indicates the presence of a defect in the circuit. First, perform the first test. A second test is then performed, using the information obtained in the first test regarding the presence of defects in the circuit.
testing should not indicate the presence of the same defect.

The portion of the serial scan vector that indicates the presence of a defect may be a single digit or a group of digits.

For example, if one of the components of logic stage 10 is defective, the digit clocked into the corresponding cell of shift register 14 may always be a zero. Also, the value of a single digit in the serial scan vector indicates the presence of a defect if the contents of the comparison memory indicate that this digit is actually a 1. Alternatively, if one of the cells of shift register 14 is defective, all digits clocked through this cell when the IC is in diagnostic mode will be O's.

In this case, the values of the multiple detents of the serial scan vector are I
It may indicate a defect in C.

Also in accordance with the invention, a sequence of test vectors is provided to the input port as a plurality of subsequences each containing at least one test vector, testing a serial scan vector after each subsequence, and testing the serial scan vectors after each subsequence. Determine if the part indicates the presence of a defect in the circuit. If a portion of the serial scan vector indicates the presence of a defect in the circuit, information indicating the number of previously tested serial scan vectors and identifying which portion of the serial scan vector indicates the presence of a defect in the circuit. information is stored separately.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a system utilizing the present invention to test a type of IC with a diagnostic input port and a serial scan port. The diagnostic input port has 16 pins and the serial scan port also has 16 pins. When the circuit under test is in diagnostic mode, a vector group of 16 serial scan vectors is clocked from the serial scan port. Of course, the invention is not limited to testing circuits with 16 input pins or 16 serial scan pins, and there need not be a relationship between the number of diagnostic input pins and the number of serial scan pins. The data base used for testing is composed of a force memory 1001, a comparison memory 102, and a mask memory 104. The force memory 100 is connected to a circuit under test (DUT).
), while the compare memory 102 stores the group sequence of serially scanned vectors that would be obtained if the DUT were defect-free. Mask memory 104 stores information regarding the particular digits of the serial scan vector on which no decisions are made. For example, the mathematical model may determine that certain digits of equal validity are 1 or 0, or that their values are independent of proper operation of the DUT.

Additionally, for devices with an I10 pin that is sometimes used as an input pin and other times as an output pin, the I
The driver channel associated with pin 10 is sometimes on and applying data to this I10 pin, and at other times it is
Inhibits testing of data from pin 10 and masks comparison of pin I10 while this driver channel is on.

Force memory 100, compare memory 102 and mask memory 104 interface with test station 106 via formatter 108. The formatter operates in a known manner to bring the information stored in memory into a format compatible with the test station. The test station itself includes multiple channel drivers to provide the input vectors stored in force memory 100 to the input ports of the DUT.

It also includes multiple channel comparisons 112, so that the serial scan vectors obtained from the DUT are stored in the comparison memory 102.
Compare with the contents of In the preferred embodiment of the invention, the input port has 16 pins, so driver 110 has 16 pins.
There are 6 channels.

Since force memory 100 is constructed of 16.times.64 K, a total of 64 input vectors of 16 bits each can be provided to the diagnostic input port of the DUT. Similarly, comparator 112 includes 16 channels, each associated with 16 pins of the serial scan port, so that the
For each clock pulse applied to the shift register when the comparator 11 is in diagnostic mode, one column of the matrix formed by the group of serial scan vectors is
2, this comparator 112 simultaneously compares the 16 digits of this column with the 16 digits stored in the corresponding storage location of compare memory 102. Thus, the 16 serial scan chains are each clocked into 16 comparator channels. Compare memory 102 is comprised of 16.times.64 K, so each serial scan vector may be 64 digits. (In the field of testing ICs with serial scanning capability,
A "serial scan chain" is a sequence of serial scan vectors applied to a given serial scan pin, ie, a sequence of vectors that correspond to like numbered rows of a continuous matrix. ) Test station 106 also includes a plurality of channel mask circuits 114. This mask circuit 114 is controlled by mask memory 104. Since this mask memory is a 16x64 memory, the number of addressable storage locations in this mask memory can be clocked externally to the DUT by the DUT's serial scan port and compared with the corresponding word in compare memory 102. Equal to the number of 16 digit words in the group sequence of serial scan vectors. One addressable storage location of the mask memory is associated with each 16 digit word of the group sequence of serial scan vectors.

Before testing, each addressable storage location of mask memory 104 is loaded with information indicating the appropriate indication for the corresponding digit of the group sequence of serial scan vectors. Each 16 digit word is fetched from the compare memory and set up for comparison with a 16 digit column clocked from the DUT's serial scan port 28. Thus, if we fetch the corresponding 16-digit word of mask memory and the digits in this word indicate that it does not carry an error indication, then
Mask circuit 114 prevents the appropriate channel of comparator 112 from providing an error indication.

When comparator 112 provides an error indication, this indication is provided to error controller 116 which stores information regarding the error location in the matrix in error memory 120. This 48-bit area of error memory is divided into serial scan vector group numbers, serial scan bit numbers, and error indication channel numbers. At the end of the test, the contents of the error memory are changed to information indicating the position in the matrix of digits to provide the error indication and this information is loaded into the shift chain mask memory 118.

The shift chain mask memory is a 16x4 memory that can be used to test more than 4 digits of ICs in each serial scan vector of a group of 16 scan vectors. Thus, one digit of the serial scan mask memory is allocated to each digit of the serial scan vector group. For each digit of the matrix representing a group of serially scanned vectors, the contents of the shift chain mask memory indicate whether a comparison of the value of this digit with the contents of the compare memory results in an error indication of the previous test.

Once the shift chain mask memory is loaded,
A second test is conducted under even more severe conditions.

As described above, in normal mode, one or more vectors are applied to the circuit under test, the circuit is placed in diagnostic mode, and a sequence of 16 digit words is read from the serial scan port. As each word is read from the serial scan port, the corresponding word is fetched from shift chain mask memory 118. If the digits of the subsequent word provided an error indication for the previous digit under test, mask circuit 114 inhibits the appropriate channel of comparator 412 from providing an error indication to the system operator. Thus, in successive tests, the system operator does not receive more than one error indication for each position of the matrix. For any digit in the matrix,
If the corresponding digit in compare memory 102 determines that an error indication should be made and this determination is not overridden by mask memory 104 and shift chain mask memory 118, then the error indication is sent to error controller 116.
give to

The shift chain mask memory II8 is loaded with mask information as well as information regarding the defect location to compensate for serial scan vectors of unequal length. If one serial scan vector is 10 digits shorter than the other, since the corresponding internal shift register contains 10 fewer cells than other internal registers, this does not affect the math mode and therefore the contents of macro memory 104. After shifting the actual accumulated digits into the short register, the shift °
Chain mask memory 118 is quartered to inhibit comparisons. This ensures that the attempted comparison does not give an error indication and is accomplished without changing the contents of the data base, particularly mask memory 104, and without introducing errors into this data base. It will be done.

Additionally, each vector group clocked from the serial scan port in the diagnostic mode of the circuit under test is comprised of 16 serial scan vectors. Each vector can consist of 4 bits, whereas one vector group is 64 bits. With this size of comparison memory 102,
The total number of bits of the generated vector group is 1024
For example, 16 vector groups each containing 64 bits can be tested.

To facilitate display and analysis of information regarding identified defects, error pointer 122 is comprised of two counters 124, 126 and a scan chain pointer 128. Bit counter 124 assigns a particular number to each pit location in the serial scan vector. E
When using CLIOK logic, the two's complement of the length of the serial scan vector, i.e. the number of the matrix column, is loaded into a bit counter and incremented each time a new bit (i.e. matrix column) is shifted out of the DUT. . When bit counter 124 counts out, it is reset to the initial count value and vector counter 126 is incremented. It will therefore be appreciated that the count accumulated in vector counter 126 represents the number of scan vectors that have been tested to that point.

Once a defect is identified, the outputs of vector counter 126 and bit counter 124 indicate which vector group and which bit position within the vector group were tested, respectively. Furthermore, the scan chain
A pointer 128 is connected to the comparator and generates a 16 bit word (each bit associated with each comparison channel) identifying the 16 channels of the comparator that gave an error indication.

The outputs of bit counter 124, vector counter 126, and scan chain pointer 128 are stored in error memory 120 for later analysis. This error memory is organized in 48x4. This 48-bit area is designated as a 16-bit serial scan vector group number, 1
A 6-bit serial scan bit number is divided into a 16-bit number indicating the channel giving the error indication.

By identifying the location of the defect with reference to the comparator channel, vector group number, and bit number, we can create a more regular pattern than simply recording the information by its location within the total number of bits in the vector group. It is clear that information regarding the occurrence of errors can be easily extracted. For example, if the input of the third cell of the shift register, which addresses channel 5 of the comparator, is defective, the error memory will be stored in each vector group, unless the correct value of that bit is equal to the value due to the defect. indicates that an error has been detected by channel 5 in the third bit of .

This pattern of information more easily indicates the presence and characteristics of defects than if the information were recorded in the comparison memory by bit position.

The system shown in FIG. 1 can be implemented using eight-domain hardware using blocks containing conventional logic. For this reason,
A detailed block diagram of the test system is omitted. Those skilled in the art will appreciate that the test system is comprised of, in addition to the blocks shown in FIG. 1, a controller that establishes the order and timing of various operations. The method of application of such a controller is conventional.

Although the preferred embodiments of the present invention have been described above, various modifications and changes can be made without departing from the gist of the present invention. For example, the present invention does not require an error controller, error memory, or error pointer. Also, the invention is not limited to systems using shift chain mask memories.

[Effects of the Invention] As described above, according to the present invention, in testing an electronic circuit under test that includes an input port, an output port, and a serial scanning port, defect information based on the first test result is used in the second test. Since the defect indication in the second test result is masked by using the second test result, an effective test can be performed. Further, since information on serial scan vectors for defects in the previous test of the circuit under test is accumulated, defect analysis is easy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a test system that utilizes the present invention;
FIG. 2 is a block diagram of a circuit under test to be tested according to the present invention, and FIG. 3 is a diagram showing a sequence of test vectors and serial scan vectors.

Claims (2)

[Claims] (1) In a method for testing an electronic circuit having an input port for receiving an input vector, an output port for generating an output vector, and a serial scan port for generating a serial scan vector indicative of the state of a predetermined component, the test vector is input as described above. port and test the serial scan vector,
performing first and second tests to determine whether the scan vector indicates the presence of a defect in the electronic circuit;
An electronic circuit testing method, characterized in that in the test, information from the first test regarding the presence of a defect in the electronic circuit is used to avoid indicating the presence of the same defect. (2) A method for testing an electronic circuit having an input port for receiving an input vector, an output port for generating an output vector, and a serial scan port for generating a serial scan vector indicative of the state of a predetermined component, wherein the test vector is input as described above. port and test the serial scan vector,
performing a test to determine whether the scan vector indicates the presence of a defect in the electronic circuit, and if the serial scan vector indicates the presence of a defect in the electronic circuit, information regarding the previously tested serial scan vector; and an electronic circuit testing method, comprising accumulating information on a portion of the serial scanning vector indicating a defect.