JPS61166157A - semiconductor storage device - Google Patents

Abstract

PURPOSE:To improve the withstand voltage feature of an insulating film by a method wherein an insulating film positioned between a pore-type capacitor and a word line is so designed as not to have an interface, in the direction of the film thickness, that may cause leak currents between the pore-type capacitor and the word line. CONSTITUTION:A polycrystalline silicon layer 10 is formed to cover the entire surface of a semiconductor substrate 1 to be developed into an insulating film to insulate a pore-type capacitor from a word line WL. Next, from a region planned for a MISFET, an conductive layer 7, silicon oxide film 8, and the polycrystalline silicon layer 10 are removed. A process follows wherein an insulating film 11 is formed by oxidizing the polycrystalline silicon layer 10 to provide insulation between the word line WL and pore-type capacitor. The polycrystalline silicon layer 10 is not positioned on the sides of the conductive layer 7 but, because the conductive layer 7 itself is made of polycrystalline silicon, the sides of the conductive layer 7 is also covered by the insulating film 11 after oxidation. The insulating film 11 is equipped with an excellent withstand voltage capability because it has no interface in the direction of the thickness of its film.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a 16-conductor memory device;
- 11 relates to a technique that is effective when applied to a DRAM equipped with a pore type capacitive element.

“Background technology” Dynamic random access memory (F, DRA)
In order to increase the degree of integration, it is necessary to miniaturize the capacitive element, and it is also necessary to sufficiently increase the capacitance value of the capacitive element. Therefore, a semiconductor substrate is etched in the depth direction from the surface to form a pore (1: ranch or moaL), an insulating film is provided on the inner wall of the pore, and a polycrystalline silicon layer that becomes an electrode is formed inside the pore. There is a technique for forming a pore-type capacitive element with a small element area and a large capacity value by providing a pore-type capacitive element. This pore type capacitive element is
By applying a potential of IT level, for example, 5 [V] to the electrode provided inside the pore, a capacitance value is obtained between the electrode and the semiconductor substrate. For this purpose, a part of the Mf electromechanical device (4) is provided on the semiconductor substrate J-, and is formed integrally with the electrode of the other pore-type container M=f' to form an electric gap terminal of l level. It is connected.

Since a word line is provided to extend in one part of this pore type capacitive element, it is necessary to provide an insulating film between the electrode and the 21- line. That is, the two 1- wire is provided extending to 11 of the insulating film.

As a result of saving the insulating film provided on the upper part of the pore type capacitor, the present inventor discovered that when forming this insulating film,
We have discovered a problem in that an unnecessary interface is formed between the pore-type capacitor and the word line, and this interface reduces the dielectric strength voltage of the insulating film.

The reason for this problem is that the first polycrystalline silicon layer, which becomes the electrode of the pore-type capacitive element, is formed thinly, and the surface of this layer is covered with a thin oxide film to form a buried part in the pore. It is in the structure notice that embeds the thin fL.

In the direction in which the line extends to the wire 1, the pore-type container, +3
-i'-The area where the adjacent MT S FET is to be formed is the region where the semiconductor board is exposed by removing the electrode and the insulating film thereon to form an opening. be.

Therefore, if the first polycrystalline silicon layer serving as the electrode of the pore-type capacitive element is too thick, the difference in level between the semiconductors j and li becomes significant, and the word line is likely to be disconnected.

Therefore, the polycrystalline silicon layer serving as the electrode is formed thin.

On the other hand, the embedded member is formed after forming the first polycrystalline silicon layer that will become the electrode on the entire surface of the semiconductor substrate.
A second polycrystalline silicon layer is again formed on the semiconductor substrate and etched from its surface so that this polycrystalline silicon layer remains only in the pores.

Since it is necessary to prevent the polycrystalline silicon layer that will become the electrode from being etched unnecessarily by the etching described above, an etching gas layer is interposed between the electrode and the polycrystalline silicon layer that will be the embedded member. It is necessary to do so. This etching stopper uses a silicon oxide film obtained by oxidizing the -1- layer of the first polycrystalline silicon layer which becomes the electrode.

For this reason, in the capacitive element before the insulating film is formed, a thin silicon oxide film surrounds the second polycrystalline silicon layer, and the first polycrystalline silicon layer surrounds the second polycrystalline silicon layer. It is surrounded by layers.

In this state, the exposed surfaces of the first and second polycrystalline silicon layers are thermally oxidized to obtain an insulating film for insulating the pore type capacitor and the word line.

Therefore, the insulating film includes a first silicon oxide film formed by oxidizing a first polycrystalline silicon layer used as an electrode, and a second silicon oxide film formed by oxidizing a second polycrystalline silicon layer used as a buried member. 2 and a silicon film. Therefore, an interface between the first and second silicon oxide films is formed on the silicon oxide film that serves as an etching stopper, and this interface reduces the dielectric strength voltage of the insulating film. It is.

Note that the semiconductor substrate is etched from the surface in the depth direction to form pores, an insulating film is formed on the inner wall of the pores, and a conductive layer used as an electrode is formed inside the pores. For example, the technology for forming a Tn type capacitive element is
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[Objective of the Invention] The object of the present invention is to insulate the pore type storage element from the word line extending from -1-.
It is an object of the present invention to provide a technology capable of improving the dielectric strength voltage of the insulation 11!4 provided for one day.

The above and other objects and novel features of the present invention will become clear from the description of this specification and the drawings.

[Summary of the Invention] Among the inventions disclosed in this application, a summary of typical inventions is as follows.

That is, a pore extending in the depth direction from the surface of the semiconductor substrate, a first insulating film provided covering the upper surface of the semiconductor substrate surrounding the pore and the inner wall of the pore, and a first insulating film covered with the first insulating film. a first conductive layer provided inside the pore and on the semiconductor substrate-1-; and an etching suppressor 1 (two members) provided covering the surface of the first conductive layer inside the pore; a pore-type container element having a embedding member attached to the pore and provided inside the pore; a word line extending a part of the pore-type container element; In a semiconductor memory device including a third insulating film provided between the word line and the word line, the third insulating film is arranged to prevent leakage between the porous capacitor element and the word line. By using an insulating film that does not have an interface in the 11φ thickness direction that would cause a current, the dielectric breakdown voltage between the pore type capacitive element and the word line is improved.

Hereinafter, the configuration of the present invention will be explained along with examples.

In all the figures for explaining the embodiments, parts having the same function are given the same reference numerals, and repeated explanations thereof will be omitted.

[Example] FIG. 1, FIG. 6, FIG. 9, and FIG. 1I are 1V side views of a memory cell in the manufacturing process of a DRAM according to an example of the present invention, and FIG. Figure 7 is a cross-sectional view taken along the ■-■ cutting line in Figure 6.
10 is a sectional view taken along the line XX in FIG. 9, and FIG. 12 is a sectional view taken along the line XII-XII in FIG. 11.

3, 4, 5, and 8 are cross-sectional views of a memory cell in the manufacturing process of a DRAM according to an embodiment of the present invention.

Note that the insulating film is not shown in order to make it easier to see the structure of the memory cell in all planes.

First, as shown in FIGS. 1 and 2, a field insulating film 2 and a type 1 channel 1 heparium region 3 are formed on a predetermined surface portion of a P- type semiconductor substrate l.

Next, a mask 5 for an etching process to form pores 4 in semiconductor substrate 1 is formed. This mask 5 is composed of a silicon oxide film 5A obtained by oxidizing the surface of a semiconductor substrate l, a silicon nitride film 5B obtained by, for example, CVD technology, and a phosphorus-1-glass film 5C obtained by CVD technology. do.

Note that the mask 5 is not illustrated in FIG.

Next, by anisotropic etching, the semiconductor substrate 1 is etched from its surface in the depth direction to form pores 4 having a depth of about 3 to 5 μm.

After removing the phosphosilicate glass film 5C, silicon nitride lli 5 B, and silicon oxide film 5A, the inner walls of the pores 4 and the second part of the semiconductor substrate 1 are oxidized by thermal oxidation technology to form a dielectric material. An insulating film 6 to be used as an insulator is formed. The insulating film 6 is a silicon oxide film formed by oxidizing the inner wall of the pore 4 and the −E portion of the semiconductor substrate 1, a silicon nitride film obtained by CVD technology, and a silicon nitride film obtained by oxidizing this silicon nitride film. It can also be composed of a silicon oxide film.

After this, as shown in FIG. 3, using a polycrystalline silicon layer obtained by, for example, CVD technology, a conductive layer 7, which will become one electrode of the pore-type capacitor, is formed on 42 parts of the semiconductor substrate 1 and in the thin film. It is formed to cover the inner wall of the hole 4. Then, a silicon oxide film 8, which is used as an etching stopper in the etching process for forming the filling member provided inside the pore 4, is formed by oxidizing the surface of the conductive layer 7.

Next, as shown in FIG. 4, a polycrystalline silicon layer obtained by, for example, CVD technology is formed on the entire surface of the semiconductor substrate l''2, and this polycrystalline silicon layer is gradually removed from the upper surface to form the pores 4. The embedded member 9 is formed by leaving only the inside of the embedding member 9.

In order to prevent the polycrystalline silicon layer used as the buried member 9 from remaining on the semiconductor substrate fffIf, over-etching is performed in the etching process, so that the two ends of the buried member 9 are etched to form four parts. . In this embodiment, the recessed portion is flattened by forming an insulating film to insulate the conductive layer 7 and the word line.

Moreover, the embedded member 9 can also be formed using phosphosilicate=1 to glass.

Next, as shown in FIG. 5, a polycrystalline silicon layer 10 used for forming an insulating film that insulates the pore type capacitor and the word line is deposited on the semiconductor substrate by, for example, CVD technology.
Form on the entire surface.

The thickness of the polycrystalline silicon layer IO varies depending on the voltage applied to the conductive layer 7 or the word line, etc., but the thickness of the insulating film is approximately 2000 angstroms (hereinafter referred to as [A]). to form. Specifically, the polycrystalline silicon layer 10 is formed to have a thickness of about 1000 [A].

Note that the silicon oxide film 8 of the semiconductor substrate 11 can be removed by, for example, etching before forming the polycrystalline silicon layer 10.

Next, as shown in FIGS. 6 and 7, the conductive layer 7, the silicon oxide film 8, and the polycrystalline silicon layer 10 in the region where the MI 5FET is formed are etched, for example, by anisotropic etching. Remove.

Next, as shown in FIG. 8, the polycrystalline silicon layer lO
By oxidizing the insulating film 11 for insulating the word line Wt and the pore type capacitor element. When the polycrystalline silicon layer 10 is oxidized, its volume becomes 11112
Double. Therefore, the polycrystalline silicon layer lO]OO
Since the insulating film 11 is formed to have a thickness of about 2
The film thickness is approximately 000 [A]. In addition, the conductive layer 7
Although the polycrystalline silicon layer 1o is not provided on the side surface of the conductive layer 7, since the conductive layer 7 is formed using polycrystalline silicon, the conductive layer 7 can be formed by oxidizing the side surface of the conductive layer 7. An insulating film 11 is also formed on the side portions.

The insulating film 11 can also be formed using, for example, a silicon oxide film obtained by CVD technology.

However, since the silicon oxide film obtained by CVD technology has a rough composition, it is difficult to provide a sufficient dielectric strength between the conductive layer 7 and the word line W[-]. To this end, in this embodiment, as described above, by forming a polycrystalline silicon layer IO and oxidizing it, CVD
The insulating film 11 has a denser composition and better dielectric strength than silicon oxide films obtained by other techniques.

By forming a polycrystalline silicon layer 1o on two parts of the conductive layer 7 and the embedded member 9, which will become the electrodes of the pore-type capacitive element, and oxidizing the polycrystalline silicon layer 10, the word line W1 and Since the insulating film 11 is formed to insulate it from the conductive layer 7, the insulating film 11 becomes an insulating film 11 with excellent dielectric strength and no interface in the film thickness direction.

This makes it possible to completely prevent leakage current from flowing between the word line WL and the pore type capacitor, thereby improving the electrical reliability of the DRAM.

Furthermore, since over-etching was performed in the etching process for forming the embedded member 9, the four parts unnecessary formed on the upper surface of the pore-type capacitive element are removed from the polycrystalline silicon layer 10.
By further oxidizing the polycrystalline silicon layer 10 to form an insulating film 11, the polycrystalline silicon layer 10 is flattened to some extent.

That is, the flatness on the pore type capacitive element can be improved.

Next, as shown in FIG. 10, after removing the silicon oxide film 6 by, for example, wet etching, the upper surface of the semiconductor substrate 1 is newly oxidized to form an MTSFE.
A T gate insulating film 12 is formed.

Next, as shown in FIG. 9 and FIG.
Alternatively, in order to form the conductive layer 13 used as the gate electrode of the MI S FET, a polycrystalline silicon layer obtained by, for example, CVD technology is formed over the entire surface of the semiconductor substrate 1. Then, in order to reduce the resistance value of the conductive layer 13, an n-type impurity 9 such as phosphorus is introduced into the polycrystalline silicon layer by, for example, a thermal diffusion technique.

Next, unnecessary portions of the polycrystalline silicon layer are selectively removed using, for example, an anisotropic etching technique to form the conductive layer 1.
form 3.

Next, as shown in FIGS. 11 and 12, MISFET
r used as the source or drain region of
In order to form the l+ type semiconductor region 14, an n-type impurity such as phosphorus is added to the semiconductor substrate l by ion implantation technology.
Introduce it to the surface of the A conductive layer 13 used as a gate electrode is used as a mask when performing the ion implantation. Then, by annealing the semiconductor substrate 1, the n-type impurity is diffused and a semiconductor region 14 is formed.

Next, the insulating film 15 is formed by forming a silicon oxide film obtained by, for example, CVD technology over the entire surface of the semiconductor substrate l.

Then, a connection hole 16, a conductive layer 17 used as a data line, and a protective film 18 are sequentially formed to form the DRA of this embodiment.
M is completed.

I) RAM of this embodiment is characterized in that the insulating film 11 that insulates the conductive layer 7 and the word line wr- has no interface in the film thickness direction, especially in the portion indicated by the dotted line. If the insulating film 11 has such an interface, the dielectric breakdown voltage of that portion will deteriorate; however, since the insulating film 11 does not have an interface as described above, the dielectric breakdown voltage of the insulating film 11 is oriented to −1−, and therefore It is possible to prevent leakage current from flowing between the conductive layer 7 and the word line W[-.

[Effects] According to the new technology disclosed by the present application, the following effects can be obtained.

(1) A polycrystalline silicon layer is formed on top of the conductive layer and the embedded member, which will become the electrode of the pore-type capacitive element, and the word line WL and the conductive layer are insulated by oxidizing the polycrystalline silicon layer. Since we have formed an insulating film to
The insulating film can be an insulating film with excellent dielectric strength and no interface in the film thickness direction.

(2) According to (1) above, it is possible to prevent leakage current from flowing between the word line WL and the pore type capacitive element, so that the electrical reliability of the DRAM can be improved.

(3) In order to form an insulating film provided between the conductive layer constituting the pore type capacitor and the word line, a polycrystalline silicon layer is formed on the upper surface of the conductive layer, and this polycrystalline silicon layer By oxidizing the insulating film and forming the insulating film, the four unnecessary parts formed on the surface of the pore type capacitor are flattened in the etching process to form a filling member for filling the inside of the pore. Therefore, the flatness on the pore type capacitive element can be improved.

Although the invention made by the present inventor has been specifically explained above using examples, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say.

[Brief explanation of the drawing]

1, 6, 9, and 11 are plan views of memory cells in the manufacturing process of a DRAM according to an embodiment of the present invention, and FIG. 2 is a plan view taken along the nn section line in FIG. 7 is a sectional view taken along the line ■-■ in FIG. 6, FIG. 10 is a sectional view taken along the line XX in FIG. 9, and FIG. 12 is a sectional view taken along the line It is a sectional view taken along the -xn cutting line. 3, 4, 5, and 8 are cross-sectional views of a memory cell in the manufacturing process of DRA, M according to an embodiment of the present invention. 1...Semiconductor substrate, 2...Field insulating film, 3...
・Channels 1-Brim region, 4・Pores, 5.5A, 5B
, 5C... mask, 6.15... insulating film, 7.13.
17. Conductive layer, 8. Silicon oxide film, 9. Embedded member, lO.. Polycrystalline silicon layer, 11.-Insulating film, 12. Gate insulating film, 14. Semiconductor region, 16.
- Connection hole, 18...protective film.

Claims (1)

[Claims] 1. A pore extending in the depth direction from the surface of a semiconductor substrate, a first insulating film provided covering the upper surface of the semiconductor substrate surrounding the pore and the inner wall of the pore, and 1. A first conductive layer deposited on an insulating film and provided inside the pore and on the semiconductor substrate, an etching inhibiting member provided covering the surface of the first conductive layer inside the pore, and the etching inhibiting member. a pore type capacitive element having a embedding member attached to the pore and provided inside the pore; a third insulating film provided on the pore type capacitive element; and a third insulating film provided on the pore type capacitive element; In the semiconductor memory device including a second conductive layer provided through a third insulating film and extending over a semiconductor substrate, the third insulating film prevents leakage between the pore type capacitor and the second conductive layer. A semiconductor memory device characterized by having no interface in the film thickness direction that would generate current. 2. The semiconductor memory device according to claim 1, wherein the first conductive layer is made of a polycrystalline silicon layer. 3. Claims characterized in that the etching inhibiting member is used as an etching stopper for preventing the first conductive layer from being etched unnecessarily during the etching process for forming the embedded member. 2. The semiconductor memory device according to item 1. 4. The semiconductor memory device according to claim 1, wherein the second conductive layer is a word line. 5. The semiconductor memory device according to claim 1, wherein the pore type capacitive element is electrically connected in series with a MISFET to constitute a DRAM memory cell. 6. The third insulating film is a silicon oxide film obtained by oxidizing a polycrystalline silicon layer newly formed on the semiconductor substrate so as to cover the first conductive layer and the buried member. A semiconductor memory device according to claim 1.