JPS6029141B2 - coupling device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a device for coupling two common busbars.

2. Description of the Related Art In recent years, so-called multiprocessor systems, in which a plurality of processors are combined and work cooperatively, have been attracting attention.

One method that has become popular in multiprocessor systems is to directly connect the respective bus lines so that a plurality of processors can freely access each other's memory 1/0 devices. Difficult problems arise when combining multiple busbars. That is, since each processor is operating independently, when one processor uses the bus of the other processor, a conflict in the use of the bus occurs. In such cases, the common method is to receive an access request from one bus, issue a usage request to the processor connected to the other bus, receive approval, and then access the bus. A method is adopted. However, if the processor that received the request does not accept the request for some reason, or accesses unimplemented memory etc. and does not receive a response, the processor that issued the request will be permanently suspended. Otherwise, there was a risk that it would occupy the bus line and render the other party's processor inoperable. The conventional method deals with danger by providing timer circuits at various locations and forcibly opening the bus bar when the inoperable state continues for a certain period of time. However, in this type of timer circuit system, once the bus is released due to a timeout, the device that was accessing up to that point will be stopped midway, so the control sequence being accessed will be read, and the access information will be lost. There was a drawback that the information was lost. The purpose of this invention is to connect two independently operating bus lines, and in a device that receives access from one bus line and accesses the other bus line, the processor performing the access stops the access midway through the access. An object of the present invention is to provide a coupling device having a means for retaining access information, continuing access to the other bus line, and notifying the access state and information to the accessing processor. According to the coupling device of the present invention, even if the processor accesses another bus and becomes inoperable for some reason, the access state at that time is maintained, so the access state can be restored by an appropriate processing program. This made it possible to easily realize a multiprocessor system.

The present invention will be explained in detail below using examples. FIG. 1 is a processor diagram showing the configuration of an embodiment of the present invention.
2 is the bus lines 1 and 2, 3 is a state control circuit, 4 is an access response circuit, 5 is a master access circuit, and 6 is an access hold transfer circuit.

When a specific address range is accessed on the bus 1, it is detected by the access response circuit 4, a read determination 214 or a write determination 224 is issued, and a pending state is entered. The master access circuit 5 makes read judgment 214 or write judgment 2
When 24 is input, access 16 is made to the bus 2, and when the access is started, a start signal 303 is issued, and when the access is completed, an end signal 205 is issued and the pending state of the access response circuit 4 is released. The access holding transmission circuit 6 holds the access information of the bus 1 when the write judgment 224 or the read judgment 214 is issued, and outputs the held information to the bus 2 when the access 16 is performed and the start signal 303 is issued. At the time of access determination 214, when the access end 205 comes, the access information of bus 2 is held, and the information is transmitted to bus 1 while being held. The state control circuit 3 is
It is connected to the bus 1, detects that a preset state control request has been issued on the bus 1, issues a command to the access retention transmission circuit 6 via the control command line group 14, and updates data, addresses, etc. of the access retention transmission circuit 6. The state of the master access circuit 5 is changed by presenting or changing information and a state change command RI. FIG. 2 is a block diagram showing one example of the structure of the access response circuit 4, in which 21 is an address comparison circuit, 22 is an address setting circuit, and 23 is an access response sequential circuit.

The address comparison circuit 21 is connected to the bus 1 and the address setting circuit 2.
When the set values 201 from 2 match, a match output 202 is notified to the access response sequential circuit 23. The access response sequential circuit determines read or write access based on the IJ code signal 207 of the bus 1, and makes a read determination 21.
4 or a write judgment 224 is output, the state is put into a hold state, and a hold signal 203 is output to the bus 1. An end signal 205 is obtained from the master access circuit 5 and the hold signal 203 is released. FIG. 3 is a block diagram showing one example of the configuration of the master access circuit 5.
It consists of two sequential circuits.

The circuit 5 is composed of one sequential circuit 51. When read determination 214 or write determination 224 is input, access 16 is performed to bus 2. Access 16 is performed as follows. A request line 301 included in the bus line 2 issues a request to use the bus line. Bus bar use approval signal 30 from bus bar 2
2, it outputs a start signal 303 and starts accessing. Upon receiving the end signal 304 from the bus 2, the end signal 205 is sent to the access response circuit 4 and the access hold transmission circuit 6. If the state control circuit 3 is the control command line group 14
When the state change RI is output, the master access circuit 5 forcibly outputs the end signal 205 and returns to the initial state.

FIG. 4 is a block diagram showing one example of the configuration of the state control circuit 3, in which 41 is an address comparison circuit, 42 is an address setting circuit, and 43 is a decoding circuit.

In FIG. 4, the address comparison circuit 41 compares the bus 1 with the address setting circuit 42, detects that there is a predetermined state control request on the bus 1, and notifies the decoding circuit 43. The decode circuit 43 decodes the state control request, generates set signals S3, S4 or enable signals E3, E4, E5, and transmits the aforementioned access...hold transmission circuit 6, and further transmits the state change command RI to the master access circuit 5. and control the state. FIG. 5 is a block diagram showing one example of the structure of the access holding transmission circuit 6, in which 51 and 53 are holding circuits, 52 and 56 are OR circuits, 58 and 59 are AND circuits, 54, 55, 57, 6
This is the output circuit. In FIG. 5, the operation when the write determination 224 is first output is as follows. The write determination 224 issues a holding command to the holding circuits 51 and 53 via the OR circuits 52 and 56, and the information in the address section 502 and data section 506 of the bus 1 is held. When the start signal 303 for the access 16 to the bus 2 is issued, the output circuit 60 is enabled and the address of the holding circuit 51 is output to the bus 2. At the same time, the AND circuit 58 performs AND with the write determination 224 to enable the output circuit 55 and output the data in the holding circuit 53 to the bus 2 . The next time the read determination 214 is output, the following will occur. First, the holding circuits 51 and 5 pass through the OR circuits 56 and 52.
3 set commands are generated and the address and data of bus 1 are held respectively. When the start signal 303 is issued, the address information of the holding circuit 51 is outputted to the bus 2 via the output circuit 60. When the end signal 205 is issued, a set command for the holding circuit 53 is generated via the AND circuit 59 and the OR circuit 56, and the data on the bus 2 is held and output to the bus 1 via the output circuit 54. Finally, when the state control circuit 3 detects state control access, the following five control signals are output. That is, the set signal S3 is set to the data holding circuit 53 from the bus 1 side, the set signal S4 is set to the address holding output circuit 51 from the bus 1 side, and the enable signals E3 and E4 are set to the data holding circuit 53 from the data selection output circuit 54. The enable signal E5 outputs the contents of the circuit 53 and the contents of the address holding output circuit 51 to the bus 1 side, and the status output circuit 57 outputs the end signal 205 coming from the master access circuit 5 to the bus 1 side. As described above in detail below, the present invention provides a system in which a plurality of processors connect each other's bus lines to perform processing, and when one processor accesses the bus line of another processor, the access A function to detect and respond to the access, a function to execute the access on the other bus in response to the access, and a function to retain the access information at that time.
It consists of a circuit that has the function of sending and receiving data between two buses and the state control function that allows the processors to know and update the access state later, and access interruption accidents occur when processors access each other. A coupling device capable of dealing with such failures is provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the configuration of an access response circuit used in the present invention, and FIG. 3 is a block diagram showing an example of the configuration of an access response circuit used in the present invention. FIG. 4 is a block diagram showing one example of the configuration of the master access circuit, FIG. 4 is a block diagram showing one example of the configuration of the state control circuit used in the present invention, and FIG. 5 is an access retention circuit used in the present invention. FIG. 2 is a block diagram showing one configuration example of a transfer circuit. 1, 2...Bus line, 3...State control circuit, 4...Access response circuit, 5...Master access circuit, 6. ．． ．． ．． ．． ．． access retention transmission circuit,
21...address comparison circuit, 22...address setting circuit, 23...access response sequence circuit, 4
1...address comparison circuit, 42...address setting circuit, 43...decoding circuit, 51
, 53... Holding circuit, 52, 56... OR circuit, 58, 59... AND circuit, 54, 55
, 60... Output circuit, 57... Status output circuit. Leopard 7 figure 2 figure 3 hair figure 4 chrysanthemum S figure

Claims (1)

[Claims] 1 A device that connects two bus lines, detects that a specific address range is accessed to one of the bus lines, determines read or write access, becomes a hold state, and transfers the hold state to the one bus line. a tentative access response circuit, which is activated by the determined read or write access from the access response circuit, performs the determined read or write access to the other bus line, and when the access is completed, the suspension of the access response circuit; a master access circuit that releases the state; and a master access circuit that is coupled to the two busbars to hold the access information of the one busbar when the write access is determined and to hold the access information of the one busbar when the write access is performed to the other busbar. When the read access is determined, the access information of the one bus is held, and when the read access is performed on the other bus, the held information is output and the read access ends. Then, an access holding transmission circuit holds and transfers the access information by holding the access information of the other bus and outputting the held access information to the one bus; and a state control circuit that detects a specified specific access and transmits the states of the master access circuit and the access holding transmission circuit to the one bus line or changes them based on information on the one bus line. A coupling device for