JPS59127871A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device including an FET having a gate electrode in metal-semiconductor contact.

Conventionally, GaAa MESPET (Metal Sem1
con-ductor Field Effect T
However, the parasitic resistance caused by the surface depletion layer between the gate, source, and drain, and the increase in gate wiring resistance due to the shortening of the gate length are ME8FET
Since the gate, source, and drain are not formed in self-alignment, the distance between the gate, source, and drain cannot be reduced very much.

Further, due to the controllability limits of conventional optical exposure technology and etching technology, it is difficult to control dimensions of 0.5 μm or less. Therefore, there is no effect of the surface depletion layer, the gate, source, and drain can be formed in self-alignment, the gate wiring resistance can be lowered, and a gate length of 0.5 μm or less can be easily achieved using conventional technology. A method is required.

FIG. 1 is a cross-sectional view of an example of a conventional MESFET.

This MESFET is manufactured by epitaxially growing an active layer 2 on a medium insulating substrate 1, forming a second metal film 4 on the active layer 2, processing it into the shape of a source electrode and a drain electrode, and coating the entire surface with a photoresist. The photoresist of the gate electrode portion is removed using the 7-off method, and the first metal film 3 is formed.The gate electrode is then manufactured by a 7-off method. In this conventional method, the gate, source, and drain are not formed in self-alignment, and it is difficult to reduce the dimensions.

MBSFET is a device that controls the current flowing from the source through the active layer to the drain by changing the channel width under the gate electrode. In the conventional structure shown in FIG. 1, the surface between the gate, source, and drain of the active layer 2 through which current flows is exposed.

In this portion, the surface depletion layer spreads inside the active layer, impeding current flow and increasing parasitic resistance. Also.

As the gate length is shortened, the gate wiring resistance increases inversely to the shortening of the gate length, which may even lead to disconnection of the gate metal. Therefore, in conventional manufacturing methods, high-speed operation MESFE
The disadvantage is that it is difficult to realize T2.

The object of the present invention is to eliminate the above-mentioned drawbacks, to provide a MESFE' which has no influence of the two-surface depletion layer, has a gate, source, and drain formed in cell 7 alignment, has low gate wiring resistance, and can easily shorten the gate length. An object of the present invention is to provide a method for manufacturing a semiconductor device including l'i.

According to the present invention, a step of forming a semiconductor layer of one conductivity type containing a high concentration of impurities on a semi-insulating substrate.

a step of fully depositing an insulating film on the semiconductor layer; and selectively removing limb regions forming gates of the insulating film and the semiconductor layer;
separating the entire semiconductor layer to form source and drain regions; and depositing and selectively removing a negative conductivity type semiconductor layer to form a region between the source region and the drain region and at least between the source region and the drain region. a step of forming an active layer in contact with the side surface, a step of forming a gate electrode of metal in Schottky contact with the active layer, and a step of forming the source and drain 7 regions b11. There is obtained a method for manufacturing a semiconductor device, which includes a step of completely forming a source electrode and a drain electrode using a metal that makes ohmic contact with the semiconductor device.

Next, five embodiments of the present invention will be described with reference to the drawings.

FIGS. 2(a) to 2(a) are cross-sectional views showing the steps in order to explain an embodiment of the present invention.

First, as shown in FIG. 2(a), a semiconductor layer 121'' containing impurities of one conductivity type at a high concentration is formed on the surface of a semi-insulating single crystal substrate 11, and a first insulating film 13 is formed thereon. The first insulating film 13 and the semiconductor layer 12 in the region below the gate electrode are selectively removed to separate the semiconductor layer 12 and form source and drain regions 12.

Next, as shown in FIG. 2(b), a semiconductor layer 14 of one conductivity type, which will become an active layer, is grown isotropically, and a metal layer 15 that makes Schottky contact with this semiconductor layer 14 is provided thereon.

The semiconductor layer 14 is a single crystal on the substrate 11 and the first insulating film 13
Above, it is polycrystalline.

Next, as shown in FIG. 2(C), remove 5 selections and move 5- Sakulayer 14. A gate electrode 15 is used.

Next, as shown in FIG. 2(d), a second insulating film 16 is deposited, and openings for connection to the source and drain regions 12 are provided.

Next, as shown in FIG. 2(e), the entire ohmic contact metal layer 17 is deposited.

Next, as shown in FIG. 2(f), the metal layer 17 is selectively removed to form source and drain electrodes 17. Then, the second insulating film 16 is selectively removed to expose the gate electrode 15.

In the above embodiment, the thickness of the semiconductor layer 12 is approximately 0.5 μm.
m, and the thickness of the active layer 14 is 't-0,1~0.2μ.
If the opening dimension i of the gate region is about 0.5 μm, the gate length will be 0.1 to 0.3 μm, and the gate length can be easily made short. The first insulating film 13 may be formed by oxidizing the semiconductor layer 12, or may be formed by evaporation or carbon dioxide.
V D (Chemical Vapor Deposit)
5iQz, f3 i 3N4, etc. may be formed by the ion method. Further, the active layer 14 is made of MBE (Molecular Beam Epi) which has excellent controllability of film thickness.
taxi) method 6- and MOCVD (Metal Organic CVD)
) method.

In the MESFET obtained by the present invention described above, the surface depletion layer that impedes the flow of carriers is the semiconductor layer 1.
2 is formed only in the portion in contact with the first insulating film 13, but the impurity concentration of the semiconductor layer 12 is 'Th1X10 cm
The thickness is less than the thickness of the surface depletion layer IooXu, which is negligible compared to the thickness of the semiconductor layer 12 (~0.5 μm). In addition, since the gate, source, and drain are formed by self-alignment, the distance between them is 0.1 to 0.
．． The length becomes as short as 2 μm. Since the active layer 14 with a low impurity concentration exists between the gate, source, and drain, the breakdown voltage is also high.

Furthermore, the structure of the gate electrode is such that the lower part of the gate electrode (gate length), which is involved in controlling the flow of carriers, is short and the upper part is wide.

Even if the gate length is shortened, the gate wiring resistance hardly increases. Use kl f as gate electrode, gate length 0.2
μm, the gate electrode structure has a gate electrode top length of 4 μm and a thickness of 1 μm, and the width per unit gate width is 8XlO-3Ω/
μm was obtained, and the gate length was 0.2 μm.

A gate wiring resistance of 2Ω or less can be obtained with a gate width of 300 μm. Furthermore, the parasitic capacitance between the gate, source, and drain is caused by the presence of the first insulating film and the active layer 14 formed on the first insulating film and having a higher resistance than polycrystalline film between them. small. Therefore, a MESFET capable of high-speed operation is obtained.

In the present invention, a substrate 11 and source and drain regions 12. Furthermore, it is clear that the active layer 14 and the active layer 14 may not be made of the same semiconductor but may be made of a different type of semiconductor. Further, the first insulating film 13 and the second insulating film 16 may be made of the same material or may be made of different materials.

According to one aspect of the present invention, as described in detail above.

The effect is significant because a semiconductor device having a MESFET in which the gate, source, and drain are self-aligned, the gate wiring resistance is low, and the gate length is short can be obtained.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of an example of a conventional MESFET, and Figure 2 (
Figures a) to ge) are sectional views shown in the order of steps for explaining an embodiment of the present invention. ■... Semi-insulating substrate, 2... Operating layer,
3...First metal film (gate electrode), 4...
...Second metal film (source and drain electrode), 11
... Semi-insulating substrate, 12 ... Source and drain region, 13 ... First insulating film, 14
......Active layer% 15...Gate electrode,
16... Second insulating film, 17... Source and drain electrodes. 9- Aji 1 (ν) (e) Homare 2 times

Claims (1)

[Claims] A step of forming a semiconductor layer of one conductivity type containing a high concentration of impurities on a semi-insulating substrate, a step of depositing an insulating film on the semiconductor layer, and the insulating film and the semiconductor layer. Select and remove the area where the gate will be formed. splitting the semiconductor layer to form source and drain regions; depositing and selectively removing a - conductivity type semiconductor layer between the source region and the drain region and at least the source region and the drain region; forming a gate electrode with a metal in Schottky contact with the active layer; and forming a source electrode and a drain electrode with a metal in ohmic contact with the source and drain regions. A method for manufacturing a semiconductor device, comprising: