JPS59121981A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, in particular, a method for manufacturing a semiconductor device, in particular, a method for manufacturing a semiconductor device, which achieves both reduction in ohmic contact resistance and source resistance and increase in gate withstand voltage and drain withstand voltage. The present invention relates to a method for manufacturing a compound semiconductor field effect transistor.

(b) Background of the technology Aiming to further improve the performance and cost performance of information processing devices, semiconductor devices are becoming faster, lower power consumption, and more highly integrated. Gallium arsenic (Ga
Many semiconductor devices using compound semiconductors such as As) have been proposed.

Due to the short lifetime of minority carriers in compound semiconductors, field effect transistors (hereinafter abbreviated as FETs) are currently the main target of development. Taking advantage of the advantage that floating volume can be reduced by using Schottky barrier junction type or p-n junction type F
ET is the mainstream.

(e) Prior art and problems Gallium-arsenic 70t Cyparian junction field effect transistors (hereinafter abbreviated as GaAs MES FETs) have already been put into practical use as single transistors, for example, for amplification in the microwave band. Furthermore, it is considered to be the mainstream of transistor elements forming compound semiconductor circuit devices intended for information processing devices and the like.

Conventional GaAs MES FETs are roughly divided into two types of structures, the cross-sectional views of which are shown in FIGS. 1(a) and 1(b).

In the structure shown in FIG. 1(a), a semi-insulating GaAs substrate 1
The active layer region 2 is formed by, for example, ion implantation or an epitaxial growth layer of GaAs doped with impurities.
A source electrode 3 and a drain/electrode 4 are formed in ohmic contact with the active layer region 2, and a Schottky barrier junction type gate electrode 5 is formed between the two electrodes.

Furthermore, in the structure shown in FIG. 1(b), in addition to the above-mentioned structure, a source region 6 and a drain region 7 with high impurity concentration are formed under the source electrode 3 and drain electrode 4 to align with the gate electrode 5, respectively. There is.

A method for manufacturing a GaAs MES FET with this structure involves forming a gate electrode 5 on the active layer region 2 using a high melting point metal.
A so-called self-alignment method is generally performed in which a source region 6 and a drain region 7 are formed by implanting impurity ions into the gate using the pole 5 as a mask.

Compared to the former, the characteristics of the MESFET with a high impurity concentration region aligned with the gate electrode are that the source resistance is significantly reduced and the influence of the depletion layer due to surface states is reduced. This structure is used in integrated circuit devices that most strongly require high transconductance, high uniformity of negative voltage, high integration, and high reliability. However, in this structure, the gate metal and Since the highly impurity and low resistance source-drain regions are in contact with each other, problems such as reduction in gate withstand voltage and drain withstand voltage are likely to occur. Furthermore, if impurities are introduced into the high impurity concentration region by ion implantation, as has been commonly done in the past, the maximum n-type activated carrier concentration value remains at about 1×10 [α]. Moreover, even when multistage implantation is performed, the carrier concentration in the surface region is lower than that in the interior, so that the contact resistance value of the source electrode and drain electrode is not sufficiently reduced. An object of the present invention is to provide a method for manufacturing a semiconductor device in which the contact resistance of a source electrode and a drain electrode of a compound semiconductor field effect transistor can be reduced and gate withstand voltage can be ensured.

(e) Structure of the Invention The object of the present invention is to form an active layer in the coating layer portion of a semiconductor substrate having a (100) plane as a main surface, and to place a gate electrode on the active layer so that the gate width direction is aligned with the substrate. The active layer is selectively formed parallel to the <110> direction of the crystal, and using the gate electrode as a mask, all of the active layer in the source/drain formation region is selectively removed to form four parts, and the active layer and the active layer are formed in the recessed parts. A semiconductor buried layer containing a high concentration of impurities of the same conductivity type is selectively formed using a vapor phase growth method, the semiconductor buried layer near the gate electrode is removed, and a source layer is formed on the semiconductor buried layer. This is achieved by a method for manufacturing a semiconductor device that includes a step of forming an electrode and a drain electrode.

(f) Embodiments of the Invention The present invention will be specifically described below by way of embodiments with reference to the drawings.

FIGS. 2(a) to 2(f) show the GaAs MES of the present invention.
Refer to FIG. 2(a), which is a sectional view showing the main steps of an embodiment applied to an FET.A semi-insulating GaAs substrate 11 has a (100) plane as its main surface.For example, silicon (Si) is applied to this substrate 11. is selectively ion-implanted, a protective film (not shown in the figure) with a thickness of, for example, 0.5 [μm] made of silicon dioxide (SiOz), etc. is provided, and the temperature is, for example, 850°C (°C for 2 hours). , an n-type active layer 12 having an impurity concentration of, for example, about 1×lo (cm 2 ) is formed.

Then, for example, titanium tungsten silicide (T
iWS i), Tungsten fist silicide (WS
The gate electrode 13 is formed using a high melting point metal such as i) by a lift-off method or the like. However, the gate electrode 13 is arranged parallel to the <110> direction of the entire substrate 11 in the gate width direction.

FIG. 2(b) A film 14 covering the entire surface of the reference substrate 11 with gold is formed using, for example, 5i02, and the source/drain forming region and gate electrode 1 are covered with gold.
A mask is formed by forming an opening for entering and exiting 3.

Next, the source-drain formation region is etched using a chemical etching method using a sulfuric acid (H2SO4) or potassium hydroxide (KOH) etching solution, or a dry etching method using carbon tetrafluoride (CF'4) plasma gas. The recess 15 is formed by selectively removing the layer 12i to a depth of, for example, 0.2 to 0.3 [μm].

Refer to FIG. 2(c). The cross-sectional shape of the recess 15 is such that the main surface of the substrate 11 is (100
) surface and the gate width direction is arranged parallel to the <110> direction, the lower floor is formed as shown in FIG. 2(c). This shape is the (111) of GaAs crystal.
It is obtained by the difference in etching speed between the A plane (Ga) and the (111)B plane (As plane).

Referring to FIG. 2(d), a GaAs buried layer 16 is formed in the recess 15 using a vapor phase epitaxial growth method. In this example, a metal organic pyrolysis vapor deposition method (MOCVD method) is applied, and for example, trimethyl potassium ((C) is used as a raw material for Ga.
Ha )s Ga ) and arsine (
AaHs) is sent into the growth chamber using hydrogen (H2) or H2 + inert gas as a carrier gas, and the GaAs buried layer 1 is grown at a growth temperature of, for example, about 600 to 680 [°C].
6 growth.

In this example, selenium (Se) was used as an impurity.
and carrier concentration from 5×10 to 9×10 [α
]. Compared to sulfur (S), Se has the advantage that it can be doped at a high concentration and has a small diffusion coefficient and is less affected by impurity diffusion during heat treatment.

In this embodiment, the growth rate of the QaAs buried layer 16 is 0,
01 to 0.03 [tttn/m2], but there are differences depending on the crystal plane, and the (111) A plane that appears on the sidewall of the four parts 15 has less growth, and the p1 buried layer 16 is shown in FIG. As shown in (d), it has a shape with recesses 16' at both ends. This shape is extremely advantageous in securing gate withstand voltage and drain withstand voltage.

For example, 0.01 to 0 for the GaAs buried layer 16, see FIG. 2(e).
．． A slight etching process of about 0.02 (μm) is performed.

As the etching method, a chemical etching method or a dry etching method can be selected according to the formation of the recess 15 described above.

This etching process removes the GaAs layer with a high impurity concentration on the side wall surface of the four portions 15, which had been grown to a small thickness, and the recess 16' between the gate electrode 13 and the buried layer 16 is removed.
The width and depth of the gate electrode are expanded, and sufficient gate and drain withstand voltages can be obtained.

Referring to FIG. 2(f), a source electrode 17 and a drain electrode 18 are then provided on the GaAs buried RF 116, and a protective film 19 is further formed.

These formations can be carried out by conventional techniques.
The table shows measurement examples comparing FET and samples made using the conventional ion implantation method.

As shown in the example shown in the table, the gate withstand voltage and drain withstand voltage are increased by about 1.5 to 2.3 times compared to the conventional structure, and the contact resistance of the source and drain electrodes is also higher than that of the buried layer. The carrier concentration can be uniformly increased to about 9×10″8 (m3)″, which is sufficiently reduced.

Furthermore, the present invention not only has the advantage of self-alignment method similar to the conventional ion implantation method, but also has the advantage of reducing lateral scattering during ion implantation as the gate length is shortened. In contrast, in the present invention, the growth temperature of the buried layer is low, and the gate length is 1 [μm]. ] degree or submicron, the present invention has a great effect on stabilizing the gate threshold voltage.

In the present invention, the gate width direction is <110> of the substrate crystal.
However, if the gate width direction i<no>
If parallel to the direction, as shown in FIG.
The cross-sectional shape of the recess 15 formed by the selective etching in step 2 is slightly downward, and the growth rate of the buried layer 16 on the side wall surface of the recess 15 is high, so that the gate electrode 13
Particularly swells occur in the vicinity. Therefore, placing the gate electrode 13 in this direction must be avoided.

Although the above description has been made using the GaAs MES FET'c as an example, the present invention is not limited to GaAs, but can be similarly applied to compound semiconductors having a crystal structure formed by a face-centered cubic lattice.

(g) As described in detail, according to the present invention, the growth of the buried layer in the vicinity of the gate electrode is suppressed by skillfully utilizing the difference in the etching rate and epitaxial growth rate of the compound semiconductor depending on the crystal plane. By performing a suitable etching process, the buried layer in the vicinity of the gate a is removed, and the buried layer with high carrier concentration reduces the ohmic contact resistance of the source e-drain tm and secures the gate withstand voltage and drain withstand voltage. It is possible to provide a compound conductor field effect transistor that satisfactorily achieves both

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are cross-sectional views showing conventional examples of compound semiconductor MESFETs, and FIGS. 2(a) to (f) are GaA
FIG. 3 is a cross-sectional view showing an embodiment of the present invention related to a s MESFET, and FIG. 3 is a cross-sectional view for comparative explanation with the embodiment. In the figure, 11 is a GaAs substrate, 121-1 is an active layer, 13 is a gate electrode, 14 is a Sin film, 15 is a recessed part,
16 is a GaAs buried layer, 16' is a recess, 17 is a source electrode, 18 is a drain electrode, and 19 is a protection M. 1st junction 27 Fig. 2/3 Fig. 2/3 /6 /4/6;
/2 /6

Claims (1)

[Claims] An active layer is formed on the surface layer of a semiconductor substrate whose main surface is the (100) plane, and a Goo 51 electrode is selectively formed on the active layer so that its gate width direction is parallel to the <110> direction of the base crystal. forming a recess, selectively removing the operation M in the source/drain formation region using the gate electrode as a mask, and filling the recess with a semiconductor containing a high concentration of impurities of the same conductivity type as the operation layer. selectively forming a layer using a vapor phase growth method, removing the semiconductor buried layer near the gate electrode, and forming a source electrode and a drain electrode on the semiconductor buried layer. A method for manufacturing a semiconductor device, characterized in that: