JPS58221535A - Serial data transmitter - Google Patents

Abstract

PURPOSE:To detect an error of an FIFO buffer within a data transmitter, by providing a frame error checking circuit at the following stage of the FIFO buffer which secures the matching between the timing of a received signal and that within the data transmitter. CONSTITUTION:Unlike the conventional constitution, a frame error check circuit 9 is connected to the output side of an FIFO buffer 10. The timing is extracted by a timing extracting circuit 7 for the signal received from a signal line (a). Then the received signal to which a delay is applied through a delay circuit 8 with the extracted timing is written to the buffer 10. The received signal within the buffer 10 is read out with the timing signal of an internal timing generating circuit 11, and a frame error is checked by the circuit 9.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to a frame check method for a system in which a single transmission line is shared by a plurality of data transmission devices and is used as a transmission line for serial data signals.Particularly, F for synchronous alignment
I IF O(F'1rst 工 nFirst 0ut
) This relates to a method for detecting frame errors due to buffer errors.

[Description of prior art]

Conventionally, a data transmission system for linotane has been configured as shown in FIG. That is, the data transmission devices 1 to 4 are connected in a ring through the transmission line 5, and each data transmission device 1 to
40, serial data is sent and received via this transmission line 5.

FIG. 2 is an explanatory diagram of a conventional frame check method in data transmission devices (1 to 4). That is, 7 is a timing extraction circuit that extracts timing from the received data via the reception signal line a, 8 is a delay circuit that provides a delay corresponding to the delay time in the timing extraction circuit 7, and 9 is a 7 frame included in the transmitted data. There is a frame error check circuit for checking frame errors from the test sequence, a 10-digit F FO buffer, and 11 a timing generation circuit using an internal oscillator.

In such a conventional circuit, a signal received through the signal line a enters the timing extraction circuit 7 through the signal line bt-, where the timing is extracted from the received signal, and this is transmitted through the signal line C to the timing extraction circuit 7. It is input to the engineering po buffer 10.

On the other hand, the received signal passes through a delay circuit 8t- having a delay time commensurate with the delay of the timing extraction circuit 7, and is set from the signal #d to the FO buffer 10 by the timing signal of the signal line C. Further, the received signal is checked by a frame error check circuit 9 through a signal line e.

When the received signal is received by this data transmission device, it is taken into the device through the signal IIIf or the signal line g.

F engineer? Reading from the 0 buffer 10 is performed successively by a timing signal from the internal timing generation circuit 11, and sent to the transmission line through the signal line 1tl-. Furthermore, when data is sent from inside this data transmission device to the transmission line, it is sent through signal lines j and 1.

However, in the conventional system, the frame error check circuit 9 was placed before the F-factor FO buffer 1o, which matches the received signal timing and the internal timing of the device. It cannot be detected internally. Therefore, even if an error occurs within that data transmission device, the error is not checked in that data transmission device, and a frame error is detected in the next data transmission device or later. Generally, these data transmission devices are located at a distance from each other, and it is difficult to detect in which data transmission device an error has occurred.

Moreover, in the original F-type FO buffer, write timing and read timing are performed by timing extraction from the received signal and timing by the oscillator inside the device itself, so in long received frames, due to frequency and phase shifts, the F-type FO buffer , it is more prone to errors than completely synchronous parts such as other control circuits.
Particular attention must be paid to error detection.

[Purpose of the invention]

The present invention improves on this point by adding special hardware to correct errors in the F/O buffers used for relay operations in data transmission equipment that transmits serial data by sharing a tree transmission path. The purpose of the present invention is to provide a circuit that can be easily detected inside a device without any interference.

[Summary of the invention]

The present invention is a data transmission device that transmits serial data by sharing one transmission path with each data transmission device. The characteristic is that the 7-frame check sequence is checked on the output side of the FO buffer, which is read at the timing of the oscillator inside the transmission device.

[Explanation based on examples]

An embodiment of the present invention will be described based on the drawings.

FIG. 3 is a block diagram of main parts of an embodiment of the present invention.

When compared with the nine conventional examples shown in FIG. 2, the present invention is characterized in that it is connected to the output side of the frame error check circuit 9tF1FO buffer 1°.

Other points are similar to the conventional example shown in FIG. 1, and the same reference numerals indicate the same parts.

With such a circuit configuration, the timing is extracted from the signal line a by the reception signal company timing extraction circuit 7, and the reception signal delayed by the delay circuit 8 at this timing is sent to the F-factor FO.
Written to buffer 1o. This F engineering FQ buffer lo
The received signal within is read out using a timing signal from an internal timing generation circuit 11, and is checked for frame errors by a frame error check circuit 9. As a result, since the write timing and the feed timing are different, a shift in frequency and phase occurs, causing an error in the FIFO buffer 10, which is immediately detected.

〔Effect of the invention〕

As explained above, according to the present invention, by arranging a frame error check circuit at the edge of the F1FO buffer that matches the timing of the received signal f) and the timing inside the data transmission device, This has the advantage that errors can be detected within the device.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a data transmission system. FIG. 2 is a block diagram of main parts of a conventional example. FIG. 3 is a block diagram of main parts of an embodiment of the present invention. 1-4...Data transmission device, 5...Transmission line, 7...
- Timing extraction circuit, 8...Delay circuit, 9...Frame error check circuit, 10...F engineering FO buffer, 11...Internal timing generation circuit. Patent Applicant NEC Corporation, 2 Agent Patent Attorney Nao Takashi Ide 1 Ugly M 1 Figure

Claims (1)

[Claims] (1) For multiple data transmission devices that share a single transmission line and transmit serial data, an F is provided that extracts each received signal from the received signal and synchronizes the clock timing of the oscillator inside the device. ■FO (First In First Stout)
) A serial data transmission device equipped with a buffer, characterized in that a frame error check circuit for checking frame errors from a frame tick sequence included in received data is connected to the output side of the F1FO buffer. Device.