JPS58186825A - Integrated circuit - Google Patents

Abstract

PURPOSE:To select a logical output in a resetting period optionally by connecting an additional circuit which has high output impedance during the resetting period to the output side of the output port register of a logical output impedance IC. CONSTITUTION:When a reset pulse RS is supplied to a terminal 6 after power-on operation, a data signal DT is supplied from a computer 1 to the input register 3 of a latch IC2 for extension, but it is not transferred to the output register 4. The Q output of an FF circuit 9 is on a level L, so the respective NAND circuits 10 and NAD circuits 11 of logical circuits 8 (i=0-n-1) of the additional circuit 7 are closed and the outputs of the circuits 10 and 11 are on the levels H and L respectively. Therefore, MOSFETs 12 and 13 are both off and high output impedance is obtained at each terminal T3; and terminals connected to a power source B through a resistance 11 or grounded are on the levels H and L respectively and terminals in a floating state sill have the high impedance. Output terminals 10n and 10n+1 are set on the level H or L optionally.

Description

Detailed Description of the Invention In a conventional expansion latch IC, each logic output of its output port register is set to either a high level, a low level, or a high output impedance, either as a whole or in block units during a reset period after power is turned on. It will be completely unified. For this reason, when controlling a control target with such an expansion latch IC, the logic output of the output port register of the expansion latch IC during the reset period may not match the logic of the control target. This leads to a decrease in reliability of the expansion latch IC. Furthermore, in the above case, it is necessary to provide a logic matching circuit between the expansion latch IC and the controlled object.
This leads to an increase in the price of the product.

In view of the above, the present invention provides logic output ICs such as expansion latch ICs, microcomputers, and interface ICs.
The present invention is to propose an integrated circuit that can arbitrarily select the logic output when the output port register of the output port register is reset.

Below, with reference to FIG. 1, the present invention will be described as an expansion latch IC.
An example in which &C is applied will be described in detail. (11 is a microcomputer, and (2) is an expansion latch IC connected to this. Data signal DT, clock signal CK, and strobe pulse 8T from computer m are supplied to the latch IC.

In the latch circuit (2), (3) is an input register, (
4) is an output register (output port register).

(5o), (51) to (5n -1), and (5n)
, (5n+t) are n+2 bit output terminals of the output register (4).

(6) is a reset pulse input terminal, from which a reset pulse R8 is sent to the computer (1) and the latch I C+
21.

An additional circuit (power) is connected to the output side of the output register (4) of the latch IC (2). This additional circuit (7) is connected to each output terminal (5o) of the M output register (4), (51) ~
Logic circuit (8) connected to (sl-x) ((8o)
, (81) to (8n-s)) and a D-type flip-flop circuit (9) forming a control circuit.

Logic circuits (8o), (81) to (8n -1) have input terminals Tl, T2, output terminals T3 . NAND circuit (1G), AND circuit (Ill, P-channel, and N-channel type MO8 field effect transistor (LT)).Input terminal T1 is directly connected to one input end of the NAND circuit via an inverter. Each is connected to one input terminal of the AND circuit (111).The input terminal T2 is a republican NAND circuit α
[and is directly connected to the other input terminal of the AND circuit OD.

Each output terminal of the NAND circuit (11 and AND circuit section is P)
Channel type and N channel type MO8 field effect transistors (connected to the respective gates of 1 and 0; the source of the transistor (121) is connected to the power supply 1B, and the drains of the transistors (12+ and α~ are connected to each other). It is connected to the output terminal T3, and the source of the transistor a3 is grounded.

Then, each output terminal (5o) of the latch IC12), (
51) to (5n-s) are logic circuits (8o) and (8t
) to (8n-i) are connected to each input terminal T1.

The D input terminal of the flip-flop circuit (9) is connected to the power supply
The reset pulse R8 from the input terminal (6) is supplied to the R (reset) input terminal, and the Q output terminal or each input terminal T of the logic circuit (8o), (81) to (8n-1)
2 are commonly connected.

And the logic circuit (8o), (81) to (8n-1)
Each output terminal T3 is an output terminal (Zoo), (101)
~(10n-1). These output terminals (10
o), (101) to αOn -1) are connected to the power supply +B&C through a resistor (high resistance) (Ill) as desired,
or resistor C (high resistance) (grounded through 11 or left as is).

The output terminals (10n) and (10n+1) of the latch IC are directly connected to the output terminals (10n) and (toHH).

Next, the operation of the integrated circuit shown in FIG. 1 will be explained with reference to FIG. 2 as well. After the power is turned on, a reset pulse R8 (see FIG. 2C) is supplied to the input terminal (6). At this time,
In the latch IC+2), a data signal (see FIG. 2C) is supplied to the input register (3), but it is not transferred to the output register (4).

Further, the output of the flip full 2-channel circuit (9) iQ output terminal (see second diagram) is at a low level (L). Therefore, logic circuits (8o), (81L (8g) to (8n-1)
) are closed, the output of each NAND circuit a is always at a high level (H), and the output of each AND circuit 0υ is always at a low level (L).

For this reason, each MO8 field effect transistor (121, (
131 are both off, and the output impedance of each output terminal T3 is high impedance E. Therefore, the output terminals (Zoo), (101), (102) ~ (1
0n-t), the output terminal connected to the power supply 1B via the resistor αυ is at high level (H), and the output terminal connected to the
) 7 and the output terminal is low level (L).
Therefore, the floating output terminal remains at high impedance.

Note that the outputs of the output terminals (10n) and (10n+1) can be arbitrarily selected to be high level (H) or low level (L).

Thereafter, when a strobe pulse ST (see FIG. 2C) is supplied to the clock input terminal of the flip-flop circuit (9), the output of the Q output terminal (see FIG. 2) becomes high level (H). For this reason, each logic circuit (8o), (
81), (82) to (Bl-t) and the AND circuit Qυ are opened. Therefore, when the input to the input terminal T1 is at a high level (H), the NAND circuit section and the AND circuit Qυ are opened. Each output of the circuit αυ is both low level (L
), the field effect transistor (12+ is turned on, the field effect transistor (131) is turned off, and the output of the output terminal T3 becomes a high level (H).

Also, when the input to input terminal T1 is low level (L),
The outputs of the NAND circuit (II and AND circuit 0υ) both become high level (H), field effect transistor α3 is turned off, field effect transistor a3 is turned on, and the output of output terminal T3 becomes low level (L). ).

According to the present invention described above, there is provided an expansion latch IC.

It is possible to obtain an integrated circuit that can arbitrarily select the logic output at the time of resetting the output port register of a logic output IC such as a microcomputer or an interface IC.

Therefore, the reliability of the logic output IC is improved, and since a logic matching circuit is not required, an increase in product prices can be avoided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a waveform diagram. In (2), the latch IC1 (7) as a logic output IC is an additional circuit. 141-

Claims (1)

[Claims] Outputs the logic output of the output port register as it is to the output side of the output port register of the logic output IC during normal operation,
An integrated circuit that is connected to an additional circuit that exhibits high output impedance during the reset period.