[go: up one dir, main page]

JPS55111174A - Nonvolatile semiconductor memory device - Google Patents

Nonvolatile semiconductor memory device

Info

Publication number
JPS55111174A
JPS55111174A JP1935379A JP1935379A JPS55111174A JP S55111174 A JPS55111174 A JP S55111174A JP 1935379 A JP1935379 A JP 1935379A JP 1935379 A JP1935379 A JP 1935379A JP S55111174 A JPS55111174 A JP S55111174A
Authority
JP
Japan
Prior art keywords
igfet
signal line
bistable circuit
transistors
igfets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1935379A
Other languages
Japanese (ja)
Other versions
JPS6410108B2 (en
Inventor
Misao Higuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1935379A priority Critical patent/JPS55111174A/en
Publication of JPS55111174A publication Critical patent/JPS55111174A/en
Publication of JPS6410108B2 publication Critical patent/JPS6410108B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

Landscapes

  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To reduce the number of elements per a memory cell, by connecting two MONOS transistors in series with a single intermediate IGFET between two nodes of a bistable circuit made of IGFETs. CONSTITUTION:The bistable circuit of a conventional static memory cell is made of enhancement-type IGFETs Q11, Q12 and depression-type IGFETs Q13, Q14. MNOS transistors MT11, MT12 are connected in series with an intermediate enhancement- type IFGET Q15 between the connection node N11 of the drain of the IGFET Q11 with the source of the IGFET Q13 and that N12 of the drain of the IGFET Q12 with the source of the IGFET Q14. The gates of the MNOS transistors MT11, MT12 are coupled to a control signal line MG. The gate of the IGFET Q15 is coupled to an inverted signal line MG of inverse phase to the signal line MG. Information to the bistable circuit can be stored in the MNOS transistors or the stored information can be read, by applying a signal voltage. According to this constitution, the number of elements is reduced.
JP1935379A 1979-02-21 1979-02-21 Nonvolatile semiconductor memory device Granted JPS55111174A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1935379A JPS55111174A (en) 1979-02-21 1979-02-21 Nonvolatile semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1935379A JPS55111174A (en) 1979-02-21 1979-02-21 Nonvolatile semiconductor memory device

Publications (2)

Publication Number Publication Date
JPS55111174A true JPS55111174A (en) 1980-08-27
JPS6410108B2 JPS6410108B2 (en) 1989-02-21

Family

ID=11997010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1935379A Granted JPS55111174A (en) 1979-02-21 1979-02-21 Nonvolatile semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS55111174A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57117183A (en) * 1981-01-09 1982-07-21 Plessey Overseas Ram element
JPS58143494A (en) * 1982-02-19 1983-08-26 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Memory array

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5372429A (en) * 1976-12-09 1978-06-27 Toshiba Corp Non-volatile semiconductor memory unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5372429A (en) * 1976-12-09 1978-06-27 Toshiba Corp Non-volatile semiconductor memory unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57117183A (en) * 1981-01-09 1982-07-21 Plessey Overseas Ram element
JPS58143494A (en) * 1982-02-19 1983-08-26 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Memory array

Also Published As

Publication number Publication date
JPS6410108B2 (en) 1989-02-21

Similar Documents

Publication Publication Date Title
US4866307A (en) Integrated programmable bit circuit using single-level poly construction
DE69122481D1 (en) Semiconductor memory with multiplex redundancy
DE69122066D1 (en) Semiconductor memory with pre-loaded redundancy multiplexer
KR890001093A (en) Charge and Equalization Circuit of Semiconductor Memory Device
JPS5833638B2 (en) memory device
EP0381404A3 (en) Non-volatile memory
JPS5619587A (en) Memory circuit
US5058062A (en) Nonvolatile semiconductor memory circuit including a reliable sense amplifier
KR880006698A (en) I / O circuit of SeaMOS semiconductor memory device
US3697775A (en) Three state output logic circuit with bistable inputs
JPS55111174A (en) Nonvolatile semiconductor memory device
KR900002324A (en) Charge Equalization Circuit of Multi-Division Memory Array
JPS6043295A (en) Semiconductor storage device
JPS57143795A (en) Nonvolatile semiconductor storage device
EP0262850B1 (en) Memory cell circuit
US3800297A (en) Non-volatile associative memory
KR950004863B1 (en) Eprom latch circuit
JP2579346B2 (en) Semiconductor nonvolatile storage element
JPS56103536A (en) Mis output circuit
JPS57105890A (en) Semiconductor storage device
FR2300397A1 (en) MOUNTING FOR ADJUSTING THE IN
JPS58141497A (en) Read-only memory circuit
SU834767A1 (en) Storage element
FR2352449A1 (en) Integrated complementary MOS transistor logic circuit - has four pairs of MOS transistors connected to provide three stable states of circuit
JPH0330238B2 (en)