JPH11203882A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an EPROM which can perform exact read-out operation independently of variation of a characteristic. SOLUTION: Stacked gate type memory cells 61, 11e, 11w of same structure corresponding to selected word lines WL are connected to a sense amplifier SA through each column transistor 55a, 55e, 55w. Electrons are extracted from a floating gate of a dummy memory cell 11e and it is in an erasing state, and electrons are injected to a floating gate of a dummy memory cell 11w and it is in a writing state. Therefore, voltage of a node C is made equal to voltage Sine of a node A when a memory cell 61 is in an erasing state independently of variation of temperature and wiring resistance of bit lines BL, BLe, BLw, and voltage of a node D is made equal to voltage Sinw of a node A when a memory cell 61 is in an writing state. Reference voltage Vc (=(Sine + Sinw)/2) is applied to a positive input terminal of a comparator 12, the comparator 12 compares the reference voltage Vc with voltage Sin of the node A and controls a sense transistor 81.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a sense amplifier for an EPROM, an EEPROM, and a flash erase EEPROM.

[0002]

2. Description of the Related Art FIG. 5 shows a block diagram of a main part of a part related to a read operation of a general EPROM. EPRO
In M, the parts related to the read operation include an address bus 51, an address buffer 52, an address predecoder 53, a row address decoder 54, a column address decoder 55, a memory cell array 56, and a sense amplifier group 5.
7, a data bus buffer 58 and a data bus 59, which are formed on a one-chip semiconductor substrate.

An address externally input via an address bus 51 is transferred to an address predecoder 53 via an address buffer 52. The address predecoder 53 divides the input address into a row address and a column address, transfers the row address to the row address decoder 54, and transfers the column address to the column address decoder 55.

FIG. 6 shows a main configuration of a column address decoder 55, a memory cell array 56, and a sense amplifier group 57. The memory cell array 56 includes a plurality of memory cells 61 arranged in a matrix. still,
In the example shown in FIG. 6, 262144 memory cells 61 are arranged in a matrix of 512 in the vertical and horizontal directions to form the memory cell array 56. Therefore, the address predecoder 53 divides the 18-bit address input via the address bus 51 into a 9-bit row address and a 9-bit column address.

FIG. 7 shows a sectional structure of each memory cell 61. Each memory cell 61 is a stacked gate type memory cell including a MOS transistor having a control gate electrode 69 and a floating gate electrode 67. An N-type source region 63 and a drain region 64 are formed on a P-type single crystal semiconductor substrate 62. A channel region 65 is formed between the regions 63 and 64 on the semiconductor substrate 62,
On the channel region 65, a tunnel insulating film 66, a floating gate electrode 67, an interlayer insulating film 68, and a control gate electrode 69 are stacked in this order.

[0006] As shown in FIG.
, The control gate electrode 69 of each memory cell 61 arranged in the column direction has a common word line WL1 to WL51.
2 and the drain regions 64 of the memory cells 61 arranged in the row direction share common bit lines BL1 to BL512.
Is formed. In the read operation shown in FIG. 6, the source regions 63 of all the memory cells 61 are grounded.

The row address decoder 54 selects a word line WL corresponding to a row address. The column address decoder 55 includes a column transistor 55a connected in series with each bit line BL, and selects a column transistor 55a corresponding to a column address to switch the bit line BL connected to the column transistor 55a. select. The data written in the memory cell 61 corresponding to the selected word line WL and bit line BL is transferred to any one of the sense amplifiers SA constituting the sense amplifier group 57 from the bit line BL via the column address decoder 55. Transferred to The sense amplifier SA amplifies the data, and the amplified data is output from the data bus buffer 58 to the outside via the data bus 59.

Incidentally, the sense amplifiers SA are provided in a number corresponding to the data width of the data bus 59. In the example shown in FIG. 6, since the data width of the data bus 59 is 16 bits, the sense amplifier group 57 includes 16 sense amplifiers SA.
1 to SA16. Then, each of the bit lines BL1 to BL512 is grouped by 32 via a column transistor 55a, and connected to each of the sense amplifiers SA1 to SA16. That is, each of the sense amplifiers SA1 to SA16 is provided for each of the 32 bit lines BL.

By the way, the source region 63 of each memory cell 61 is commonly connected to the entire memory cell array 56, or is blocked and commonly connected for each memory cell 61 corresponding to each of the sense amplifiers SA1 to SA16. Have been. Also, the drain region 64 of the memory cell 61
The metal wiring (not shown) is lined with the bit line BL formed by the above-described method, thereby reducing the wiring resistivity.

FIG. 8A shows a configuration of a memory cell 61, a bit line BL, a column transistor 55a, and a sense amplifier SA. The sense amplifier SA includes a sense circuit 71, a load transistor 72, and an output inverter 73. The sense circuit 71 includes a sense transistor 81 and a feedback inverter 82. Load transistor 72 and sense transistor 8
1 is connected in series between the power supply Vdd and the column transistor 55a. The node A between the column transistor 55a and the sense transistor 81 is connected to the input side of the feedback inverter 82, and the output side of the feedback inverter 82 is connected to the gate of the sense transistor 81. A node B between the load transistor 72 and the sense transistor 81 is connected to the gate of the load transistor 72 and is connected to the output inverter 7.
3 is connected to the input side. The output side of the output inverter 73 is connected to the data bus buffer 58. still,
Each of the transistors 81 and 55a is an NMOS transistor, and the load transistor 72 is a PMOS transistor. That is, the sense amplifier SA is a single-ended current detection type, and is basically an inverter using the memory cell 61 as a driver and the load transistor 72 as a load.

The circuit shown in FIG.
Is replaced by a switch SW1 in the equivalent circuit shown in FIG. Next, the operation of the sense amplifier SA will be described. Here, the threshold voltage of the load transistor 72 is Vtp, the threshold voltage of the feedback inverter 82 is Vtis, the threshold voltage of the output inverter 73 is Vtio, the voltage of the node B is So, and the voltage of the node A is S.
in, and the voltage of the power supply Vdd is Vdd.

The write operation of the memory cell 61 is performed by controlling the control gate electrode 69 (word line WL) and the drain region 64.
(Bit line BL) to apply a high voltage to the drain region 64.
This is performed by injecting hot electrons generated near the junction between the gate electrode and the channel region 65 into the floating gate electrode 67 via the tunnel insulating film 66. When electrons are injected into the floating gate electrode 67, the threshold voltage seen from the control gate electrode 69 increases. The state in which electrons are injected into the floating gate electrode 67 of the memory cell 61 is defined as a write state, and is defined as a state in which data “0” is stored.

In the erasing operation of the memory cell 61, a high voltage is applied to the source region 63 and the control gate electrode 69 (word line WL) is grounded, so that the data is accumulated in the floating gate electrode 67 by utilizing a tunnel phenomenon. This is performed by drawing out the collected electrons to the source region 63 through the tunnel insulating film 66. When electrons are extracted from the floating gate electrode 67, the threshold voltage seen from the control gate electrode 69 decreases. The state where electrons are extracted from the floating gate electrode 67 of the memory cell 61 is referred to as an erased state, and is defined as a state where data "1" is stored.

In the read operation of the memory cell 61, a power supply voltage Vdd is applied to the control gate electrode 69 (word line WL), and a low voltage (about 1 V) is applied to the drain region 64 using the sense amplifier SA as described later. This is performed by associating the magnitude of the applied and flowing drain current with data “0” and “1”.

When the memory cell 61 is in the erased state, when the power supply voltage Vdd is applied to the control gate electrode 69 (word line WL), the memory cell 61 is turned on. In the read operation, the power supply voltage Vdd is applied to the gate of the column transistor 55a, so that the column transistor 55a is on. Therefore, the voltage Sin of the node A falls below the threshold voltage Vtis of the feedback inverter 82, and the logic level on the output side of the feedback inverter 82 becomes "1", and the sense transistor 81 is turned on. As a result, the voltage So at the node B falls below the threshold voltage Vtp of the load transistor 72, and the load transistor 72 is turned on.

As described above, when the memory cell 61 is in the erased state, the voltage Sin falls below the threshold voltage Vtis, so that the sense transistor 81 (switch SW1) is turned on, and the voltage So falls below the threshold voltage Vtp. ,
The voltage So is set between the memory cell 61 and each of the transistors 55a and 55a.
It is determined by the resistance division between the on-resistances of the bit lines 1 and 72 and the wiring resistance of the bit line BL.

When the memory cell 61 is in a write state, the memory cell 61 is turned off. Therefore, the voltage Sin of the node A exceeds the threshold voltage Vtis of the feedback inverter 82, the logic level on the output side of the feedback inverter 82 becomes "0", and the sense transistor 81 is turned off. As a result, the voltage So at the node B exceeds the threshold voltage Vtp of the load transistor 72, and the load transistor 72 is turned off.

As described above, when the memory cell 61 is in the write state, the voltage Sin exceeds the threshold voltage Vtis, so that the sense transistor 81 (switch SW1) is turned off, and the voltage So exceeds the threshold voltage Vtp. , The voltage So is changed from the power supply voltage Vdd to the threshold voltage Vtp.
(So = Vdd-Vtp).

Here, the voltages Sin and So when the memory cell 61 is in the erased state are denoted as voltages Sine and Soe, and the voltages Si and So when the memory cell 61 is in the written state.
n and So are described as respective voltages Sinw and Sow. That is, the range of each voltage Sine, Sinw (Sinw-Si
ne) becomes the voltage amplitude of the node A, and the voltages Soe, S
The range of ow (Sow-Soe) is the voltage amplitude of the node B.

The setting range of the threshold voltage Vtis of the feedback inverter 82 is obtained by adding and subtracting a design margin Δ1 to / from a value X of 電 圧 of the voltage amplitude of the node A, as shown in the following equation (1). Is set. The design margin Δ1 is determined by the memory cell 61 and each transistor 55
a, 81, 72 and the bit line B
The setting is made in consideration of the variation of the elements such as the variation of the wiring resistance of L.

X = (Sine + Sinw) / 2 X−Δ1 ≦ Vtis ≦ X + Δ1 (Equation 1) Further, the setting range of the threshold voltage Vtio of the output inverter 73 is, as shown in the equation (2), The value is set by adding / subtracting a design margin Δ2 to / from a value Y of 電 圧 of the voltage amplitude of B. Note that the design margin Δ2 is set in consideration of variations in elements such as variations in the threshold voltage Vtp of the load transistor 72.

Y = (Soe + Sow) / 2 Y−Δ2 ≦ Vtio ≦ Y + Δ2 (Equation 2) Incidentally, the configuration of the sense amplifier SA shown in FIG. 8 is described in IEICE Technical Report SDM90-21 (Seki, Kume et al. : 1Mbit flash erase type EE with on-chip erase control circuit
PROM).

[0023]

FIG. 9 shows each voltage Sin
FIG. 5 conceptually shows temperature changes in the set range of e, Sinw and the threshold voltage Vtis of the feedback inverter 82. Although the actual temperature changes of the voltages Sine and Sinw are not linear as shown in FIG. 9, they are shown in FIG. 9 in a linear manner to make the degree of change easy to understand.

While each of the voltages Sine and Sinw decreases as the temperature rises, the threshold voltage Vtis hardly changes regardless of the temperature. Therefore, by substituting the voltages Sine and Sinw at the general operating temperature T of the EPROM into the equations (1) and (2),
A setting range of the threshold voltage Vtis is required. Further, each of the voltages Sine and Sinw and the threshold voltage Vtis
The operation margin .DELTA.3 is set between the setting ranges.

However, when the temperature is low or high,
Range of each voltage Sine, Sinw (Sinw-Sin
e) falls outside the set range of the threshold voltage Vtis. FIG. 10 shows that when the temperature is low, each voltage Sin
The range of each of the voltages Soe and Sow (voltage amplitude of the node B) in a state where the range of e and Sinw (voltage amplitude of the node A) exceeds the set threshold voltage Vtis. FIG. 11 shows that when the temperature is high, each voltage Sin
e, threshold voltage Vtis with Sinw set
Shows the range of each voltage Soe, Sow in a state where the voltage is lower than.

As shown in FIGS. 10 and 11, when the range of each voltage Sine, Sinw (voltage amplitude of node A) deviates from the set threshold voltage Vtis, sense amplifier SA functions as a current sense amplifier. Therefore, since the voltage amplitude of the node A cannot be amplified, each voltage Soe, So
The range of w (voltage amplitude of the node B) will not expand. Therefore, the ethical level on the output side of the output inverter 73 does not change between the erased state and the written state of the memory cell 61, and the data stored in the memory cell 61 cannot be read accurately.

Even if the range of each of the voltages Sine and Sinw does not deviate from the set range of the threshold voltage Vtis, if it deviates from the general operating temperature T,
Since the operation margin Δ3 on either side of each of the voltages Sine and Sinw is reduced, the possibility of erroneously reading data stored in the memory cell 61 is increased.

As described above, the conventional sense amplifier SA shown in FIG. 8 has a problem that the temperature range in which an accurate read operation can be performed is narrow, and the accuracy of the read operation is reduced due to the influence of a temperature change. In recent years, in the EPROM, it is required to reduce the voltage amplitude of the drain region 64 (bit line BL) of the memory cell 61 in order to increase the operation speed, and the range of each voltage Sine, Sinw (node A Voltage amplitude) must be reduced.
Therefore, the setting range of the threshold voltage Vtis also becomes smaller, and the above problem tends to become more serious.

When the wiring resistivity of the bit line BL is large, the memory cell 61 close to the sense amplifier SA
Since the wiring resistance of the bit line BL greatly differs between the memory cell 61 and the memory cell 61 far from the memory cell 61, it is necessary to set the design margin ± Δ1 large. Therefore, in particular, when the metal wiring is not lined with the bit line BL formed by the drain region 64 of the memory cell 61, the wiring resistivity of the bit line BL increases, so that the above problem becomes more apparent.

The sense amplifier SA having the configuration shown in FIG.
Is used, not only EPROM but also EEPROM
It goes without saying that the same problem occurs in the M and flash erase type EEPROM. The present invention has been made to solve the above problems, and the object is to
An object of the present invention is to provide a semiconductor memory device capable of performing an accurate read operation irrespective of characteristic fluctuation.

[0031]

According to a first aspect of the present invention, there is provided a first dummy memory cell in which data is not written and a first dummy memory cell connected to the first dummy memory cell. A first dummy bit line,
A first potential detecting means for detecting a potential change of the dummy bit line, a second dummy memory cell in which data is written in advance, and a second potential memory connected to the second dummy memory cell.
, A second potential detecting means for detecting a potential change of the second dummy bit line, a bit line connected to a memory cell from which data is to be read, and a potential change of the bit line. And third potential detecting means.
The intermediate potential generating means generates an intermediate potential between the potential of the first dummy bit line detected by the first potential detecting means and the potential of the second dummy bit line detected by the second potential detecting means. I do. The comparing means compares the potential of the bit line detected by the third potential detecting means with the intermediate potential generated by the intermediate potential generating means. Then, the reading means reads the data stored in the memory cell based on the comparison result of the comparing means.

Therefore, in the present invention, the first and second
The dummy memory cell and the memory cell of
If formed on the semiconductor substrate of the chip, the potential of the first dummy bit line becomes equal to the potential of the bit line when no data is written in the memory cell, regardless of the characteristic change such as temperature change. Of the dummy bit line becomes equal to the potential of the bit line when data is written in the memory cell. Therefore, the potential of the bit line and the intermediate potential change at the same rate with respect to the temperature change,
By comparing the potential of the bit line with the intermediate potential, it is possible to determine whether or not data has been written to the memory cell, so that the data stored in the memory cell is independent of a characteristic change such as a temperature change. Data can be read accurately.

Further, in the present invention, if the wiring lengths of the first and second dummy bit lines and the bit lines are made the same and the wiring lengths are made the same, even if the wiring resistance is large, The potential of the first dummy bit line is equal to the potential of the bit line when data is not written in the memory cell, and the potential of the second dummy bit line is the potential of the bit line when data is written in the memory cell. It becomes equal to the potential. Therefore, data stored in the memory cell can be accurately read regardless of the wiring resistance.

In the semiconductor memory device according to the first aspect, a plurality of the first and second dummy memory cells and the memory cells are arranged in a matrix, as in the second aspect of the present invention. The first and second dummy memory cells arranged in a column direction and a plurality of the memory cells are connected to the same word line. Then, the column decoder selects one of the plurality of bit lines connected to the plurality of memory cells, and connects the selected bit line to the third potential detecting means.

In the semiconductor memory device according to the first or second aspect, the first, second, and third potential detecting means may be connected to the dummy memory cell according to the third aspect of the invention. Alternatively, the present invention is a single-ended current detection type sense amplifier including an inverter using the memory cell as a driver and using a MOS transistor connected to a power supply as a load.

Further, in the semiconductor memory device according to the third aspect, the MOS transistor is of a diode connection type as in the invention according to the fourth aspect. In the embodiments of the invention described below, the "first dummy memory cell" described in the claims or the means for solving the problem corresponds to the dummy memory cell 11e, and similarly, the "second dummy memory cell 11e". The memory cell "is a dummy memory cell 11w
Similarly, the "first dummy bit line" corresponds to the dummy bit line BLe, the "second dummy bit line" also corresponds to the dummy bit line BLw, and the "first potential detecting means" is erased. Similarly, the “second potential detecting means” corresponds to the state voltage generating circuit 14.
5, the "third potential detecting means" is composed of the load transistor 72 and the sense transistor 81, and the "intermediate potential generating means" is composed of the voltage followers 13e and 13w and the resistor R. The "comparing means" corresponds to the comparator 12. Similarly, the "reading means" includes a load transistor 72, a sense transistor 81, and an output inverter 73. Similarly, the "MOS transistor" is a dummy load transistor 21.
e, 21w and the load transistor 72.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is embodied in an EPROM will be described below with reference to the drawings. In the present embodiment, the same components as those in the conventional embodiment shown in FIGS. 5 to 8 have the same reference numerals, and a detailed description thereof will be omitted.

The essential block configuration of the portion related to the read operation of the EPROM of this embodiment is the same as that of the conventional embodiment shown in FIG. Further, the structure of the memory cell 61 of the present embodiment is the same as the conventional embodiment shown in FIG. In FIG.
The main configuration of a column address decoder 55, a memory cell array 56, and a sense amplifier group 57 in the present embodiment is shown.

FIG. 2 differs from the conventional embodiment shown in FIG. 6 in the following points. [1] The memory cell array 56 includes dummy memory cells 11e and 11w in addition to the memory cells 61, and the memory cells 61, 11e and 11w are arranged in a matrix. Each dummy memory cell 11e, 11
The structure of w is the same as that of the memory cell 61.

In the reading operation shown in FIG.
Source region 6 of all memory cells 61, 11e, 11w
3 is grounded. Then, each of the memory cells 61, 11
The source region 63 of the memory cell array 56
The memory cells 61 and 11 are connected in common as a whole or correspond to the sense amplifiers SA1 to SA16.
e, 11w, and are commonly connected in blocks.

[2] Electrons have been extracted from the floating gate electrode 67 of the dummy memory cell 11e and are in an erased state. In addition, electrons are injected into the floating gate electrode 67 of the dummy memory cell 11w, and it is in a written state. [3] Each dummy memory cell 11 arranged in the column direction
e, 11w are connected to the common word lines WL1 to WL5 with the memory cells 61 arranged in the same direction.
12 are formed.

[4] The drain region 64 of each dummy memory cell 11e arranged in the row direction forms a common dummy bit line BLe, and the drain region 64 of the dummy memory cell 11w arranged in the row direction is a common dummy bit line. The bit line BLw is formed. Each dummy bit line BLe, BL
One w is provided for each of the sense amplifiers SA1 to SA16.

Each of the dummy bit lines BLe and BLw is lined with a metal wiring (not shown), similarly to the bit line BL, and the bit lines BL, BLe and BLw have the same wiring resistivity. ing. [5] The column address decoder 55 is connected to each bit line BL
And dummy column transistors 55e and 55w connected in series with the dummy bit lines BLe and BLw, respectively, in addition to the column transistors 55a connected in series with the dummy bit lines BLe and BLw. The transistors 55a, 55e, 55
The transistor size of w is the same.

FIG. 1 shows a memory cell 6 according to this embodiment.
1, bit line BL, column transistor 55a, dummy memory cells 11e and 11w, dummy bit lines BLw and B
Le, the configuration of the dummy column transistors 55e and 55w, and the sense amplifier SA are shown. The sense amplifier SA of the present embodiment includes a load transistor 72, an output inverter 73,
It comprises a sense transistor 81, a comparator 12, voltage followers 13e and 13w, a resistor R, an erase state voltage generation circuit 14, and a write state voltage generation circuit 15.

The erase state voltage generation circuit 14 includes a dummy load transistor 21 e and a dummy sense transistor 2.
2e. Dummy load transistor 21
e and the dummy sense transistor 22e are connected to the power supply Vd
d and the dummy column transistor 55e are connected in series. A node E between the dummy load transistor 21e and the dummy sense transistor 22e is connected to the gate of the dummy load transistor 21e. The gate of the dummy sense transistor 22e is connected to the power supply Vdd.

The write state voltage generation circuit 15 includes a dummy load transistor 21w and a dummy sense transistor 22w. The dummy load transistor 21w and the dummy sense transistor 22w are connected in series between the power supply Vdd and the dummy column transistor 55w. A node F between the dummy load transistor 21w and the dummy sense transistor 22w is connected to the gate of the dummy load transistor 21w. The gate of the dummy sense transistor 22w is grounded.

Incidentally, each dummy load transistor 21e, 2
1w is a PMOS transistor which is formed in the same transistor size as the load transistor 72. Further, each of the dummy sense transistors 21e and 22w is NM
This is an OS transistor, and is formed in the same transistor size as the sense transistor 81.

Each of the voltage followers 13e and 13w is constituted by an operational amplifier. The node C between the dummy sense transistor 22e and the dummy column transistor 55e is connected to the input side of the voltage follower 13e, and the node D between the dummy sense transistor 22w and the dummy column transistor 55w is connected to the input side of the voltage follower 13w. It is connected to the. The output side of each of the voltage followers 13e and 13w is connected to the plus input terminal of the comparator 12 via each of the resistors R.

Since each of the voltage followers 13e and 13w has characteristics of high input impedance and low output impedance, it is possible to prevent the resistance R from affecting the voltages of the nodes C and D. The negative input terminal of the comparator 12 is connected to a node A between the column transistor 55a and the sense transistor 81,
Is connected to the gate of the sense transistor 81.

Next, the operation of the sense amplifier SA configured as described above according to the present embodiment will be described. When the row address decoder 54 selects the word line WL corresponding to the row address by applying the power supply voltage Vdd, the word line WL
Are selected and the dummy memory cells 11e and 11w corresponding to. When the column address decoder 55 applies the power supply voltage Vdd to the column transistor 55a corresponding to the column address and selects it, the bit line BL connected to the column transistor 55a is selected, and a plurality of bit lines BL corresponding to the bit line BL are selected. The memory cell 61 is selected. Then, one memory cell 61 corresponding to the selected word line WL and bit line BL is connected to sense amplifier SA via column transistor 55a. In addition, the selected word line WL
, One dummy memory cell 11e, 11w corresponding to each dummy column transistor 55e, 55w.
It is connected to the sense amplifier SA via w.

Here, each bit line BL, BLe, BLw
Have the same wiring resistivity. Then, the length of the bit line BL between the selected memory cell 61 and the column transistor 55a and each of the selected dummy memory cells 11e,
Since the length of each of the dummy bit lines BLe and BLw between 11w and each of the dummy column transistors 55e and 55w is the same, each of the bit lines BL, BLe and BL
The wiring resistance of w is the same.

The load transistor 72, the dummy load transistors 21e and 21w, the sense transistor 8
1 and each dummy sense transistor 22e, 22w, the column transistor 55a and each dummy column transistor 5
5e, 55w, memory cell 61 and each dummy memory cell 1
1e and 11w have the same transistor size.

In the read operation, the column transistor 55a and each of the dummy column transistors 55e, 55
Since the power supply voltage Vdd is applied to the gate of 5w, the transistors 55a, 55e, and 55w are on. Therefore, the voltage of the node C is set such that the dummy sense transistor 22e is in the ON state and the dummy memory cell 11e is in the erased state and is in the ON state. In this case, the voltage is equal to the voltage Sine of the node A. Incidentally, the voltage of the node C is the dummy bit line BL.
It corresponds to the potential of e.

The voltage at the node D is the same as that in the conventional sense amplifier SA shown in FIG. 7 because the dummy sense transistor 22e is in the off state and the dummy memory cell 11w is in the write state and the off state. Is in the write state, the voltage Sin of the node A
w. Note that the voltage of the node D corresponds to the potential of the dummy bit line BLw.

The voltages Sine and Sinw of the nodes C and D are reduced to 1/2 by the resistors R and applied to the plus input terminal of the comparator 12. Therefore, the voltage Vc of the plus input terminal of the comparator 12 is
It is represented by equation (3). Vc = (Sine + Sinw) / 2 (Equation 3) The comparator 12 includes a reference voltage Vs set by adding and subtracting the design margin Δ1 to and from the voltage Vc of the plus input terminal,
The voltage is compared with the voltage of the negative input terminal (the voltage Sin of the node A), and based on the comparison result, the sense transistor 8
1 is controlled. Here, the setting range of the reference voltage Vs is represented by Expression (4).

Incidentally, the design margin Δ1 is determined for each memory cell 6.
1, 11e, 11w and each transistor 55a, 55e,
55w, 72, 21e, 21w, 81, 22e, 22w
Of each bit line BL, BLe,
The setting is made in consideration of the variation of the elements such as the variation of the wiring resistance of BLw.

Vc−Δ1 ≦ Vs ≦ Vc + Δ1 (Expression 4) Since the voltage Vc shown in Expression (3) is the same as the value X shown in Expression (1), the reference voltage Vs shown in Expression (4) is It becomes the same as the threshold voltage Vtis shown in the equation (1). Memory cell 61
Is in the erased state, the memory cell 61 and the column transistor 55a are in the on state, so that the voltage S
In falls below the reference voltage Vs, the logic level on the output side of the comparator 12 becomes “1”, and the sense transistor 81 is turned on. As a result, the voltage So of the node B becomes the threshold voltage Vtp of the load transistor 72.
, And the load transistor 72 is turned on.

As described above, when the memory cell 61 is in the erased state, the voltage Sin falls below the reference voltage Vs, so that the sense transistor 81 is turned on, the voltage So falls below the threshold voltage Vtp, and the voltage Vo falls on the memory cell 61. And the on-resistance of each of the transistors 55a, 81, and 72 and the wiring resistance of the bit line BL.

When the memory cell 61 is in the write state, the memory cell 61 is in the off state, and the voltage S
In exceeds the reference voltage Vs, the logic level on the output side of the comparator 12 becomes “0”, and the sense transistor 81 is turned off. As a result, the voltage So of the node B becomes the threshold voltage Vtp of the load transistor 72.
, And the load transistor 72 is turned off.

As described above, when the memory cell 61 is in the write state, the voltage Sin exceeds the reference voltage Vs, so that the sense transistor 81 is turned off, the voltage So exceeds the threshold voltage Vtp, and the voltage Vo is the power supply voltage Vdd. Minus the threshold voltage Vtp (Vo = V
dd-Vtp).

FIG. 3 conceptually shows a temperature change in a set range of each of the voltages Sine, Sinw and the reference voltage Vs.
Although the actual temperature changes of the voltages Sine, Sinw, and Vs are not linear as shown in FIG. 3, they are shown linearly in FIG. 3 for easy understanding of the degree of change.

Each memory cell 61, 11e, 11w and each transistor 55a, 55e, 55w, 72, 21
Since e, 21w, 81, 22e, and 22w are formed on a one-chip semiconductor substrate, the temperature conditions are the same. The load transistor 72 and each dummy load transistor 21e, 21w, the sense transistor 81 and each dummy sense transistor 22e, 22w, the column transistor 55a and each dummy column transistor 55e, 55
w, memory cell 61 and each dummy memory cell 11e, 11
w has the same temperature characteristic.

Therefore, regardless of the temperature change, the voltage at node C is equal to the voltage Sine at node A when memory cell 61 is in the erased state, and the voltage at node D is the voltage at node A when memory cell 61 is in the written state. Is equal to the voltage Sino. Therefore, each voltage Sine, Sinw, V
s decreases at the same rate as the temperature rises, and each voltage Sin
The range of e and Sinw (Sinw-Sine) does not deviate from the setting range of the reference voltage Vs.

The operating margin Δ is provided between each of the voltages Sine and Sinw and the setting range of the reference voltage Vs.
3 is set. The operation margin Δ3 is always kept at a constant value irrespective of the change in the temperature t. As a result, the sense amplifier SA of the present embodiment functions as a current sense amplifier irrespective of a temperature change, and as shown in FIG.
The range of ine, Sinw (voltage amplitude of node A) can be amplified to expand the range of each voltage Soe, Sow (voltage amplitude of node B). Therefore, the memory cell 6
1 between the erase state and the write state.
, The ethical level on the output side of the memory cell 61 can be reliably changed, and the data stored in the memory cell 61 can be accurately read regardless of the temperature change.

Incidentally, in the EPROM, in order to increase the operation speed, the drain region 6 of the memory cell 61 is required.
4 (bit line BL) must be reduced, and the range of each of the voltages Sine and Sinw (voltage amplitude of the node A) must be reduced.
Is also reduced. However, according to the present embodiment, even when the voltage amplitude of the node A is reduced and the setting range of the reference voltage Vs is reduced, an accurate read operation can be performed regardless of a temperature change. Can be achieved.

Further, regardless of the wiring resistivity of each of the bit lines BL, BLe, BLw, the voltage at the node C is equal to the voltage Sine.
And the voltage at the node D becomes equal to the voltage Sino. Therefore, even when the metal wiring is not backed by the bit line BL formed by the drain region 64 of the memory cell 61 and the wiring resistivity is large, an accurate reading operation can be performed regardless of a temperature change.

The present invention is not limited to the above embodiment, but may be modified as follows. Even in such a case, the same operation and effect as those of the above embodiment can be obtained. (1) Replace each voltage follower 13e, 13w with a source follower. Although the source follower is inferior to the voltage follower but has characteristics of high input impedance and low output impedance, it is possible to prevent the resistance R from affecting the voltages of the nodes C and D.

(2) The gates of the load transistor 72 and the dummy load transistors 21e and 21w are grounded,
The load transistor 72 and each of the dummy load transistors 21e and 21w are of a resistance connection type. In this case, the load transistor 72 and each dummy load transistor 21
Since the voltage amplitude of each of the nodes B, E, and F is larger than that of the above-described embodiment in which e and 21w are diode connection types, the read operation of the sense amplifier SA is delayed, but the same effect as in the above-described embodiment is obtained. Obtainable.

(3) Not only EPROM but also EEPROM
Applies to M or flash erase type EEPROM.
(4) The ratio of each resistor R shown in FIG. 1 does not necessarily have to be the same, but the same value is best.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a main part of an embodiment embodying the present invention.

FIG. 2 is a circuit diagram showing a configuration of a main part of one embodiment.

FIG. 3 is a characteristic diagram for explaining the operation of the embodiment.

FIG. 4 is a characteristic diagram for explaining the operation of the embodiment.

FIG. 5 is a main part block diagram of a conventional mode and one embodiment.

FIG. 6 is a circuit diagram showing a configuration of a main part of a conventional embodiment.

FIG. 7 is a schematic sectional view of a memory cell according to a conventional mode and an embodiment.

FIG. 8 is a circuit diagram showing a configuration of a main part of a conventional embodiment.

FIG. 9 is a characteristic diagram for explaining the operation of the conventional embodiment.

FIG. 10 is a characteristic diagram for explaining the operation of the conventional embodiment.

FIG. 11 is a characteristic diagram for explaining the operation of the conventional embodiment.

[Description of Signs] 11e, 11w: Dummy memory cell 12: Comparator 13e, 13w: Voltage follower 14: Erase state voltage generation circuit 15: Write state voltage generation circuit 21e, 21w: Dummy load transistor 55: Column decoder 61: Memory Cell 72: Load transistor 73
... output inverter 81 ... sense transistors BLe, BLw ... dummy bit lines BL ... bit lines WL ... word lines R ... resistors

Claims (4)

[Claims] A first dummy memory cell to which data is not written; a first dummy bit line connected to the first dummy memory cell; and a potential change of the first dummy bit line. First potential detecting means, a second dummy memory cell in which data is written in advance, a second dummy bit line connected to the second dummy memory cell, and a second dummy bit line. Potential detecting means for detecting a change in the potential of the first dummy bit line, the potential of the first dummy bit line detected by the first potential detecting means, and the second dummy bit line detected by the second potential detecting means. Intermediate potential generating means for generating an intermediate potential with respect to the potential of the bit line, a bit line connected to a memory cell from which data is read, third potential detecting means for detecting a potential change of the bit line, Potential detection means Comparing means for comparing the potential of the bit line with the intermediate potential generated by the intermediate potential generating means, and reading means for reading data stored in the memory cell based on a comparison result of the comparing means. A semiconductor memory device characterized by the above-mentioned. 2. The semiconductor memory device according to claim 1, wherein a plurality of said first and second dummy memory cells and said plurality of memory cells are arranged in a matrix and arranged in a column direction. A semiconductor memory device in which two dummy memory cells and a plurality of said memory cells are connected to the same word line, wherein one of said plurality of bit lines connected to a plurality of said memory cells is selected. And a column decoder for connecting the selected bit line and the third potential detecting means. 3. The semiconductor memory device according to claim 1, wherein said first, second, and third potential detecting means use said dummy memory cell or said memory cell as a driver and connect to a power supply. A single-ended current detection type sense amplifier comprising an inverter having a selected MOS transistor as a load. 4. The semiconductor memory device according to claim 3, wherein said MOS transistor is of a diode connection type.