JPH11120795A - Semiconductor device and inspection method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable reducing an inspection time of a semiconductor device and to enable improving certainty of an inspection. SOLUTION: When a cycle test inspecting durability of writing of a semiconductor memory is performed, a signal is outputted to all selection lines Aall , Ball . This signal is outputted to all word lines and bit lines through OR circuits 21, 22, 23, 24 in a row decoder 6, OR circuits 31, 33, 35, 37 in a column decoder 8, and the signal is given to all word lines and bit lines independently of input of input lines An , An+1 , Bn , Bn+1 . Thereby, all ferroelectric memory cells in a memory cell array 2 are made a selected state. In this state, rewriting is repeated for all ferroelectric memory cells, and a cycle test is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for testing a semiconductor device, and more particularly to a semiconductor device and a semiconductor device capable of reducing the time required for testing a semiconductor device and improving the reliability of the test. Related to inspection method.

[0002]

2. Description of the Related Art A semiconductor memory has a large number of memory cells. These memory cells are arranged in a matrix and are connected by connection lines. Then, data is written to and read from a specific memory cell by applying a selection signal to the row line and the column line. FIG. 5 is a circuit diagram of the row decoder 69. A word line is specified by a combination of signals applied to the input line An and the input line An + 1.

[0003] In a manufacturing process, a semiconductor memory is inspected for proper operation (EDS: Electric).
Die Sort). In this case, a test is performed for each memory cell while a selection signal is applied to the row line and the column line to specify each memory cell.

There is also a method in which an inspection element is formed in advance on a scribe line which is a cutting line of a semiconductor wafer. FIG. 6A shows a semiconductor wafer 60, which is cut along a scribe line 61. FIG. 6B shows the cut portion, and further cuts along the scribe lines 63 to form the chips 62. A large number of memory cells are formed on the chip 62.

FIG. 6C is an enlarged view of the scribe line 63 shown in FIG. 6B. Inspection elements 64, 65 and the like are provided on the scribe line 63. The test element 64 is a resistor, and the test element 65 is a ferroelectric capacitor. The test elements 64 and 65 are formed through the same steps as the memory cells on each chip 62.

[0006] Before cutting along the scribe line 63, the test elements 64 and 65 are tested. Since the test elements 64 and 65 have undergone the same steps as the memory cells on the chip 62, the test elements 64 and 65 are tested to determine indirectly whether or not the memory cells are properly formed. Can be inspected.

[0007]

The above-mentioned conventional inspection of a semiconductor device has the following problems. First, when an inspection is performed for each memory cell, there is a problem that an inspection time is required. In particular, in a cycle test for repeatedly rewriting a memory cell in order to inspect the durability, much time is required and the efficiency of the inspection time is reduced.

On the other hand, according to the method in which the test elements 64 and 65 are formed on the scribe line, it is not necessary to perform the test for each memory cell, and the test time can be reduced. However, these test elements 64 and 65
In order to reliably detect the characteristics, it is formed larger than the memory cell. Further, while the memory cells are densely arranged, the test elements 64 and 65 are provided independently on the scribe line, and the situation around the elements is completely different.

As described above, since the test elements 64 and 65 and the memory cell are different in size and peripheral conditions, it is inaccurate to determine the appropriateness of the memory cell through the test of the test elements 64 and 65. The reliability of memory cell inspection is low.

Further, since each chip obtained by cutting the semiconductor wafer is sealed and packaged with a plastic resin, the characteristics of the memory cell may change at the stage of commercialization due to the effect of the sealing. There is. In particular, in the case of a memory cell using a ferroelectric capacitor, the characteristics are unstable and the deviation due to a change in characteristics is large.

When a memory cell for inspection is used, it must be inspected before the semiconductor wafer is cut, that is, in a step before commercialization, and it is not possible to inspect a commercialized memory cell. For this reason, the reliability of the inspection is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device and a method for inspecting a semiconductor device, which can reduce the time required for the inspection of the semiconductor device and can increase the reliability of the inspection.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor device having a large number of semiconductor elements, wherein a specific semiconductor element is selected and subjected to electrical processing. The semiconductor device is provided with conducting means for forming a test element group with the semiconductor element in a predetermined conductive state, and a test signal is supplied to the test element group.

According to a second aspect of the present invention, there is provided a semiconductor device including a plurality of semiconductor elements connected by a selection line.
In a semiconductor device which performs a specific process by selecting a specific semiconductor element by applying a selection signal to a selection line, the semiconductor device includes switching means provided on the selection line for some or all of the semiconductor elements. Based on the given switching signal, the switching means applies a virtual selection signal to the selection line to form a test element group with some or all of the semiconductor elements in a predetermined conductive state. A test signal is provided.

According to a third aspect of the present invention, there is provided a semiconductor device having a semiconductor element section composed of a large number of semiconductor elements arranged in a matrix, wherein a specific semiconductor element is selected and subjected to electrical processing. A selection circuit that supplies a selection signal to the semiconductor element unit and selects a specific semiconductor element, wherein the selection circuit provides a virtual selection signal to the semiconductor element unit based on the supplied switching signal. And a test element group is formed by setting a part or all of the semiconductor elements in a predetermined conductive state, and a test signal is supplied to the test element group.

According to a fourth aspect of the present invention, there is provided a semiconductor device according to the first aspect.
4. The semiconductor device according to claim 2, wherein the semiconductor element includes a ferroelectric.

According to a fifth aspect of the present invention, there is provided a semiconductor device inspection method comprising:
In a test method for a semiconductor device having a large number of semiconductor elements and selecting a specific semiconductor element and performing electrical processing, a connection element group is formed with a part or all of the semiconductor elements in a predetermined conductive state, The semiconductor device is inspected by supplying an inspection signal to the connection element group.

[0018]

According to the semiconductor device of the first aspect,
The conduction unit sets a part or all of the semiconductor elements in a predetermined conduction state to form an inspection element group. Then, a test signal is given to the test element group.

That is, by supplying a test signal to the test element group that has entered a predetermined conductive state, it is possible to test the entire test element group at once. For this reason, it is not necessary to individually provide an inspection signal to each semiconductor element for inspection, and it is possible to reduce the inspection time of the semiconductor device.

Further, the semiconductor element group can be directly inspected. That is, for example, an element for inspection is formed in the manufacturing process, and the semiconductor element is not indirectly inspected by the element for inspection in the manufacturing process. For this reason, a semiconductor element group included in a semiconductor device as a finished product can be inspected, and the reliability of the inspection can be improved.

In the semiconductor device according to the second aspect, switching means is provided in a selection line for a part or all of the semiconductor elements, and the switching means is configured to switch the selection line based on a given switching signal. A virtual selection signal is applied to the line, and a part or all of the semiconductor elements are brought into a predetermined conduction state to form an inspection element group. Then, a test signal is given to the test element group.

That is, by supplying a test signal to the test element group that has been brought into a predetermined conductive state, it is possible to test the entire test element group at once. For this reason, it is not necessary to individually provide an inspection signal to each semiconductor element for inspection, and it is possible to reduce the inspection time of the semiconductor device.

Further, the semiconductor element group can be directly inspected. That is, for example, an element for inspection is formed in the manufacturing process, and the semiconductor element is not indirectly inspected by the element for inspection in the manufacturing process. For this reason, a semiconductor element group included in a semiconductor device as a finished product can be inspected, and the reliability of the inspection can be improved.

Further, the switching means applies a virtual selection signal to the selection line to bring a part or all of the semiconductor elements into a predetermined conducting state, thereby forming an inspection element group. As described above, since the inspection element group is formed by using the selection line for applying the selection signal and applying the virtual selection signal to this selection line, the inspection element can be easily and reliably formed with a simple configuration. Groups can be formed.

In the semiconductor device according to the third aspect, the selection circuit supplies a virtual selection signal to the semiconductor element portion based on the supplied switching signal, and turns a part or all of the semiconductor elements into a predetermined conduction state. As a test element group. Then, a test signal is given to the test element group.

That is, by supplying a test signal to the test element group that has been brought into a predetermined conducting state, it becomes possible to test the entire test element group at once. For this reason, it is not necessary to individually provide an inspection signal to each semiconductor element for inspection, and it is possible to reduce the inspection time of the semiconductor device.

Further, the semiconductor element group can be directly inspected. That is, for example, an element for inspection is formed in the manufacturing process, and the semiconductor element is not indirectly inspected by the element for inspection in the manufacturing process. For this reason, a semiconductor element group included in a semiconductor device as a finished product can be inspected, and the reliability of the inspection can be improved.

Further, the selection circuit gives a virtual selection signal to the semiconductor element portion, thereby setting a part or all of the semiconductor elements to a predetermined conductive state to form an inspection element group. Therefore, the inspection element group can be easily and reliably formed with a simple configuration.

In the semiconductor device according to the fourth aspect, the semiconductor element has a ferroelectric. Since the characteristics of this ferroelectric are unstable, particularly accurate inspection is required. Therefore, by reducing the inspection time of the semiconductor device, the cycle test for performing the repeated inspection can be efficiently performed, and the semiconductor device having the semiconductor element including the ferroelectric can be accurately inspected. .

In a semiconductor device inspection method according to a fifth aspect of the present invention, a connection element group is formed by setting a part or all of the semiconductor elements in a predetermined conduction state, and an inspection signal is applied to the connection element group. To inspect.

That is, by supplying a test signal to the test element group which has been brought into a predetermined conducting state, it becomes possible to test the entire test element group at once. For this reason, it is not necessary to individually provide an inspection signal to each semiconductor element for inspection, and it is possible to reduce the inspection time of the semiconductor device.

Further, the semiconductor element group can be directly inspected. That is, for example, an element for inspection is formed in the manufacturing process, and the semiconductor element is not indirectly inspected by the element for inspection in the manufacturing process. For this reason, a semiconductor element group included in a semiconductor device as a finished product can be inspected, and the reliability of the inspection can be improved.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION

1. First Embodiment A first embodiment of a semiconductor device and a semiconductor device inspection method according to the present invention will be described with reference to FIGS. 1, 2, and 3. FIG. FIG. 1 is a block diagram of a semiconductor memory according to the present embodiment. FIG. 2 is a diagram showing a circuit configuration of the memory cell array, the row decoder 6, and the column decoder 8, and FIG. 3 is a diagram showing a circuit configuration of the sense amplifier 10 and the I / O controller 12.

[Overall Configuration of Semiconductor Memory] The memory cell array 2 as a semiconductor element portion includes a plurality of ferroelectric memory cells as semiconductor elements connected in a matrix. Data writing or reading is performed by designating a memory cell.

When writing or reading data, a specific address signal is applied to the address decoder 4 from a control unit (not shown). The address decoder 4 outputs a signal to a row decoder 6 as a selection circuit and a column decoder 8 as a selection circuit based on the received address signal, and outputs a word line (selection line) and a bit line (selection line). A specific ferroelectric memory cell in the memory cell array 2 is designated by the combination of (line).

Data writing or reading is performed on the specified ferroelectric memory cell through the I / O controller 12 and the sense amplifier 10. I
The / O controller 12 and the sense amplifier 10 operate in response to a signal from the sequencer 16 and operate.
Is controlled by the control unit.

When writing or reading data, a plate line (to be described later) paired with a word line is made to oscillate in accordance with an input. The plate line controller 14 gives a predetermined signal based on the signal.

[Details of Data Writing or Reading] As shown in FIG. 2, in the present embodiment, the row decoder 6 is provided with OR circuits 21, 22, 23, and 24 as conducting means or switching means. Circuit 3 as a conducting means or a switching means for the column decoder 8
1, 33, 35 and 37 are provided.

When writing or reading data to or from a ferroelectric memory cell in memory array 2, a signal is applied from address decoder 4 (FIG. 1) to row decoder 6 as described above. The address decoder 4
According to the address of the ferroelectric memory cell specified by the control unit, a signal is given to the input line An and the input line An + 1,
AND circuits 41 and 42 according to the combination of the signals,
A signal is output from one of 43 and 44. This signal is output as a selection signal via OR circuits 21, 22, 23, and 24, and any one of the word lines is selected.

A signal is also supplied from the address decoder 4 (FIG. 1) to the column decoder 8. The address decoder 4 supplies a signal to the input line Bn and the input line Bn + 1 according to the address of the ferroelectric memory cell designated by the control unit, and according to a combination of the signals, an AND circuit 51,
A signal is output from any one of 52, 53, and 54.
This signal is output as a selection signal via the OR circuits 31, 33, 35, and 37, and is supplied to the I / O controller 12.

As shown in FIG. 3, a switch 12 in the I / O controller 12
a, 12b, 12c, or 12d is opened, and data is written through a line corresponding to the opened switch;
Reading becomes possible.

When writing and reading are performed, a signal is supplied from the sequencer to the sense amplifier 10. Upon receiving a signal from the sequencer, the switches of the amplifier circuits 10a, 10b, 10c, and 10d in the sense amplifier 10 are opened. For example, regarding the amplifier circuit 10a, the switches 58 and 59 are opened.

Then, the data applied via the I / O controller 12 and the inverted data are output to the bit line pair of the memory cell array 2. As a result, one of the bit line pairs of the memory cell array 2 is selected. The amplifier circuits 10b, 10c, and 10d have the same configuration as the amplifier circuit 10a.

As described above, a specific ferroelectric memory cell is designated by the combination of the selected word line and bit line pair, and the data is transmitted via the I / O controller 12 and the sense amplifier 10 as described above. writing,
Alternatively, reading is performed.

At the time of writing and reading, a predetermined signal is given to the plate line PL from the plate line controller 14 (FIG. 1). This signal is output through AND circuits 45, 46, 47, and 48,
Writing and reading of data are performed with the amplitude of the plate line corresponding to the selected word line.

[Inspection of Semiconductor Memory] Next, the inspection of the semiconductor memory which is a feature of the present invention will be described. In a manufacturing stage, a chip cut out of a semiconductor wafer is sealed with a plastic resin and packaged, and then subjected to a cycle test for inspecting, for example, writing durability of a semiconductor memory. In particular, since the characteristics of ferroelectrics are unstable, more reliable and accurate inspection is required.

When performing a cycle test, address decoder 4 (FIG. 1) operates in accordance with a command from the control unit.
A signal that is a switching signal is output to all the selection lines Aall and Ball.

The signals applied to all the selection lines Aall are output as virtual selection signals to all the word lines through OR circuits 21, 22, 23 and 24 in the row decoder 6. Further, the signal given to all the selection lines Ball is output through OR circuits 31, 33, 35, and 37 in the column decoder 8, and is output to the I / O controller 12, the sense amplifier 10
Are output to all the bit lines as virtual selection signals.

That is, OR circuits 21, 22, 23, 24, OR circuits 31, 3 are placed on word lines and bit lines.
By providing 3, 35, and 37, signals are supplied to all word lines and bit lines regardless of the input of the input lines An, An + 1, Bn, and Bn + 1. Thus, all the ferroelectric memory cells in the memory cell array 2 are in a selected state. In the present embodiment, all the ferroelectric memory cells selected at the time of the inspection and brought into the conductive state are the inspection element group.

In this state, rewriting is repeated for all ferroelectric memory cells, and a cycle test is performed. The rewriting is performed by the sequencer 16 (FIG. 1) repeatedly outputting a signal that is a test signal based on a command from the control unit.

As described above, since the rewriting signal is applied to all the ferroelectric memory cells and the cycle test is performed as a result of conducting the cycle test, all the ferroelectric memory cells are inspected at once. It becomes possible. For this reason,
There is no need to individually apply a signal to each ferroelectric memory for inspection, and the time required for inspection of the semiconductor memory can be reduced.

Also, as in the conventional semiconductor memory inspection shown in FIG.
4 and 65 are formed, and the semiconductor elements are not indirectly inspected by the inspection elements 64 and 65 in a process prior to chip cutting. Therefore, the ferroelectric memory cell included in the semiconductor memory as a finished product can be inspected, and the reliability of the inspection can be increased.

Further, OR circuits 21, 22, 23, 24, OR circuits 31, 3 are arranged on word lines and bit lines.
By providing 3, 35, and 37, signals are given to all word lines and bit lines at the time of inspection. Therefore, all ferroelectric memory cells can be easily and reliably selected with a simple configuration.

2. Second Embodiment Next, a second embodiment of a semiconductor device and a semiconductor device inspection method according to the present invention will be described with reference to FIG. 4A. In the present embodiment, the AND circuits 41, 42, 43, 44 and the AND circuit 5 shown in the first embodiment are used.
Instead of 1, 52, 53 and 54, a NAND circuit as a conduction means or a switching means is provided. Further, the OR circuits 21, 22, 23, 2 shown in the first embodiment are described.
4. Instead of the OR circuits 31, 33, 35 and 37, NAND circuits are provided as conducting means or switching means.

FIG. 4A shows a part of the circuit of the row decoder 6. The same circuit configuration as that of FIG. 4A is employed for the column decoder 8. When reading or writing data, an H signal is given to all the selected lines Aall. This H signal is applied to one input of a NAND circuit 72,... And the NAND circuit 71 applied to the other input.
.. In response to an L signal or an H signal from
The output signals of 2,... Are determined.

That is, the input line An and the input line An + 1
Circuit 7 according to the combination of signals given to
A signal is output from any one of 1,. This signal is output as a selection signal via an OR circuit 72,.
One of the word lines is selected.

According to the same circuit configuration in column decoder 8, any bit line pair is selected. A specific ferroelectric memory cell is designated by the combination of the selected word line and bit line pair, and data reading and writing are performed.

When testing a semiconductor memory, an L signal is applied to all selected lines Aall. Since the L signal is taken into one input of the NAND circuits 72,..., The signal from the NAND circuits 71,. Regardless, signals will be applied to all word lines.

The L signal is also applied to all select lines Ball (see FIG. 2), and signals are applied to all bit line line pairs according to a similar circuit configuration in column decoder 8. Since the signal is applied to all the word line and bit line pairs, all the ferroelectric memory cells in the memory cell array 2 are in a selected state.

In this state, rewriting is repeated for all ferroelectric memory cells, and a cycle test is performed. Other configurations are the same as those described in the first embodiment.

3. Third Embodiment Next, a third embodiment of a semiconductor device and a semiconductor device inspection method according to the present invention will be described with reference to FIG. 4B.
In the present embodiment, the OR circuits 21, 22, 23, 24, OR circuit 31,
Instead of 33, 35, 37, a transfer gate as a conducting means or a switching means is provided. A power supply is connected to the word line and the bit line.

FIG. 4B shows a part of the circuit of the row decoder 6. The same circuit configuration as that of FIG. 4B is employed for the column decoder 8. When reading or writing data, an L signal is given to all the selected lines Aall. This L signal is given to the control input of the transfer gates 73,..., And the transfer gates 73,.
State. Therefore, the transfer gate 73,
The word line signal is determined according to the L signal or the H signal from the AND circuits 41,.

That is, the input line An and the input line An + 1
Circuit 4 according to the combination of signals given to
A signal is output from any one of 1,..., And any word line is selected.

Further, according to a similar circuit configuration in column decoder 8, any bit line pair is selected. A specific ferroelectric memory cell is designated by the combination of the selected word line and bit line pair, and data reading and writing are performed.

When testing a semiconductor memory, an H signal is applied to all selected lines Aall. This H signal is given to the control input of the transfer gates 73,..., And the transfer gates 73,. Therefore,
The H signal is applied to all the word lines irrespective of the voltage supplied from the power supply 74 and the signal from the AND circuits 41,..., That is, the signal applied to the input line An and the input line An + 1.

The H signal is also applied to all select lines Ball (see FIG. 2), and the H signal is applied to all bit line line pairs according to the same circuit configuration in column decoder 8. Since the H signal is supplied to all the word line and bit line pairs in this manner, all the ferroelectric memory cells in the memory cell array 2 are selected.

In this state, rewriting is repeated for all ferroelectric memory cells, and a cycle test is performed. Other configurations are the same as those described in the first embodiment.

4. Fourth Embodiment Next, a fourth embodiment of the semiconductor device and the semiconductor device inspection method according to the present invention will be described with reference to FIG. 4C. In the present embodiment, the OR circuits 21, 22, 23, 24, the OR circuits 31, 3 shown in the first embodiment are described.
Instead of 3, 35, 37, a transistor as a conducting means or a switching means is provided. Also, on the word line,
Connect the power supply to the bit line.

FIG. 4C shows a part of the circuit of the row decoder 6. The same circuit configuration as that of FIG. 4C is employed for the column decoder 8. When reading or writing data, an L signal is given to all the selected lines Aall. This L signal is applied to the gates of the transistors 75,..., And the transistors 75,. Therefore, the word line signal is determined according to the L signal or the H signal from AND circuits 41,.

That is, the input line An and the input line An + 1
Circuit 4 according to the combination of signals given to
A signal is output from any one of 1,..., And any word line is selected.

Further, according to a similar circuit configuration in column decoder 8, any bit line pair is selected. A specific ferroelectric memory cell is designated by the combination of the selected word line and bit line pair, and data reading and writing are performed.

When testing a semiconductor memory, an H signal is applied to all selected lines Aall. This H signal is applied to the gates of the transistors 75,.
Is turned off. Therefore, regardless of the signals supplied from the AND circuits 41,..., That is, the signals supplied to the input lines An and An + 1, the signals are supplied to all the word lines.

The H signal is also applied to all select lines Ball (see FIG. 2), and signals are applied to all bit line line pairs according to a similar circuit configuration in column decoder 8. Since the signal is applied to all the word line and bit line pairs, all the ferroelectric memory cells in the memory cell array 2 are in a selected state.

In this state, rewriting is repeated for all ferroelectric memory cells, and a cycle test is performed. Other configurations are the same as those described in the first embodiment.

5. Other Embodiments The semiconductor device and the method for testing a semiconductor device according to the present invention are not limited to those described in the above embodiments. For example, in the above embodiment, a semiconductor memory is described as an example, but the present invention may be applied to other semiconductor devices.

In the above embodiment, a ferroelectric memory cell including a ferroelectric capacitor is illustrated as a semiconductor element. However, another semiconductor element including a ferroelectric may be used. For example, a ferroelectric memory cell including a ferroelectric transistor can be used. Further, a semiconductor element having no ferroelectric substance can be employed.

In the above embodiment, an OR circuit, a NAND circuit, a transfer gate, and a transistor have been exemplified as the conduction means or the switching means. Other configurations may be adopted as long as the inspection element group is formed in a conductive state. For example, it can be realized using an AND circuit or a NOR circuit.

In the above-described embodiment, the test element group can be freely switched from the non-conductive state to the conductive state by applying switching signals to the OR circuit, the NAND circuit, the transfer gate, and the transistor. The example of forming is shown. However, the inspection element group may be formed by freely switching only a part of the ferroelectric memory cells from the conductive state to the conductive state.

Further, a group of test elements may be formed in a state where a part of the semiconductor elements is fixedly brought into a conductive state, and the part of the group of test elements may be used exclusively for testing the semiconductor device. For example, in the process of manufacturing a semiconductor device, when an aluminum wiring is formed, the aluminum wiring may be provided so that some of the semiconductor elements are in a conductive state.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor memory which is a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a diagram showing a circuit configuration of a memory cell array 2, a row decoder 6, and a column decoder 8 shown in FIG.

FIG. 3 is a diagram showing a circuit configuration of a sense amplifier and an I / O controller shown in FIG. 1;

FIG. 4A is a partial block diagram of a row decoder in a semiconductor device according to a second embodiment of the present invention; FIG. 4B is a partial block diagram of a row decoder in a third embodiment of the semiconductor device according to the present invention; C is a partial block diagram of the row decoder in the fourth embodiment of the semiconductor device according to the present invention.

FIG. 5 is a circuit diagram of a row decoder 69 in a conventional semiconductor memory.

6A is a view showing a semiconductor wafer 60, FIG. 6B is a view showing the semiconductor wafer 60 cut along a scribe line 61, and FIG. 6C is an enlarged view of a scribe line 63.

[Explanation of symbols]

 2 ···· Memory cell array 6 ··· Row decoder 8 ··· Column decoder 21, 22, 23, 24 ··· OR circuit 31, 33, 35, 37 ···・ OR circuit

Claims (5)

[Claims] In a semiconductor device having a large number of semiconductor elements and performing electrical processing by selecting a specific semiconductor element, a part or all of the semiconductor elements are brought into a predetermined conduction state to form an inspection element group. A semiconductor device, comprising: a conducting means for forming; and a test signal is supplied to the test element group. 2. A semiconductor device having a large number of semiconductor elements connected by a selection line, and selecting a specific semiconductor element by applying a selection signal to the selection line and performing electrical processing. Switching means provided on a selection line for all or part of the semiconductor elements, based on the given switching signal, the switching means supplies a virtual selection signal to the selection line, and a part or all of the A semiconductor device, wherein an inspection element group is formed with a semiconductor element in a predetermined conduction state, and an inspection signal is given to the inspection element group. 3. A semiconductor device having a semiconductor element portion composed of a large number of semiconductor elements arranged in a matrix and performing a specific semiconductor element to perform electrical processing. A selection circuit that supplies a selection signal to the semiconductor element unit based on the provided switching signal, and provides a virtual selection signal to the semiconductor element unit, A semiconductor element having a predetermined conduction state to form an inspection element group, and the inspection element group is supplied with an inspection signal. 4. The semiconductor device according to claim 1, wherein the semiconductor element comprises a ferroelectric material. 5. An inspection method for a semiconductor device having a large number of semiconductor elements and performing electrical processing by selecting a specific semiconductor element, wherein a part or all of the semiconductor elements are brought into a predetermined conduction state to form a connection element. Forming a group, and applying a test signal to the connection element group to test the semiconductor device.