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JPH10242387A - Microwave integrated circuit - Google Patents

Microwave integrated circuit

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Publication number
JPH10242387A
JPH10242387A JP4502997A JP4502997A JPH10242387A JP H10242387 A JPH10242387 A JP H10242387A JP 4502997 A JP4502997 A JP 4502997A JP 4502997 A JP4502997 A JP 4502997A JP H10242387 A JPH10242387 A JP H10242387A
Authority
JP
Japan
Prior art keywords
pair
ohmic electrodes
conductive region
integrated circuit
microwave integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4502997A
Other languages
Japanese (ja)
Other versions
JP3499394B2 (en
Inventor
Yasunobu Saito
泰伸 斉藤
Juichi Ozaki
寿一 尾崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP04502997A priority Critical patent/JP3499394B2/en
Publication of JPH10242387A publication Critical patent/JPH10242387A/en
Application granted granted Critical
Publication of JP3499394B2 publication Critical patent/JP3499394B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To attain a low resistance while limiting the area by arranging ohmic electrodes alternately and oppositely on the conductive region of a semiconductor thereby constituting a pair of ohmic electrodes. SOLUTION: A conductive region 102 is formed by implanting ions selectively into a semiinsulating GaAs substrate, for example, and first and second ohmic electrodes 101a, 101b are arranged thereon interdigitally at regular intervals while facing each other thus constituting a pair of ohmic electrodes. Since a pair of ohmic electrodes are arranged interdigitally while facing each other in a resistor, the length B of facing side is equal to the product Axn, i.e., the length A multiplied by the number of pairs n of electrode (4 pairs) facing interdigitally. For example, a resistance of 5Ωcan be attained with an area of 1,000μm<2> for 4 pairs of electrode and the area can be decreased or a lower resistance can be attained for the same area.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、GaAsなどの半
絶縁性半導体基板上に形成されるマイクロ波集積回路に
関する。
[0001] 1. Field of the Invention [0002] The present invention relates to a microwave integrated circuit formed on a semi-insulating semiconductor substrate such as GaAs.

【0002】[0002]

【従来の技術】近年、マイクロ波固体回路では小型化、
低価格化のために整合回路とFET等の半導体をGaA
sなどの半絶縁性半導体基板上に一体化するモノリシッ
クマイクロ波集積回路(以下、MMIC)が広く用いら
れている。
2. Description of the Related Art In recent years, microwave solid-state circuits have become smaller,
GaAs is used for matching circuits and semiconductors such as FETs to reduce costs.
A monolithic microwave integrated circuit (hereinafter, MMIC) integrated on a semi-insulating semiconductor substrate such as s is widely used.

【0003】図4はGaAs FETを用いた増幅器の
一例を示す等価回路である。図において、401はGa
As FET、402〜405は整合回路を構成する伝
送回路、406、407は直流阻止用キャパシタ、41
0は安定化抵抗である。
FIG. 4 is an equivalent circuit showing an example of an amplifier using a GaAs FET. In the figure, 401 is Ga
As FETs, 402 to 405 are transmission circuits forming a matching circuit, 406 and 407 are DC blocking capacitors, 41
0 is a stabilizing resistor.

【0004】図2中の410で示す抵抗体は、FETの
ゲート電極に直列に接続され、MMICに用いるFET
401の特性ばらつきを吸収し、またFETの寄生発振
などの動作をおさえる働きがある。通常、抵抗値として
は接続されるFETのゲート側の入力インピーダンスに
比例し、例えば、ゲート幅に反比例して選択される。
A resistor denoted by reference numeral 410 in FIG. 2 is connected in series to a gate electrode of the FET, and is used for an MMIC.
It has the function of absorbing the characteristic variation of 401 and suppressing the operation such as the parasitic oscillation of the FET. Usually, the resistance value is selected in proportion to the input impedance on the gate side of the connected FET, for example, in inverse proportion to the gate width.

【0005】上記のような抵抗体を実現するには、高抵
抗金属薄膜を用いる方法、半導体の導電性領域と一対の
オーム性電極を用いて構成する方法などがあるが、FE
Tプロセスとの整合性がよいことから導電性領域と一対
のオーム性電極を用いる構成をとる場合が多い。
In order to realize the above resistor, there are a method using a high-resistance metal thin film, a method using a semiconductor conductive region and a pair of ohmic electrodes, and the like.
In many cases, a configuration using a conductive region and a pair of ohmic electrodes is adopted because of good compatibility with the T process.

【0006】図5は導電性領域と一対のオーム性電極を
用いた構成の抵抗体の従来例を図示したものである。図
において、501aと501bは例えばAuGe/Ni
を用いた各々オーム性電極であり、一定の間隔を隔てて
対向し、一対のオーム性電極を構成している。また、図
中の502は半絶縁性の半導体基板上に選択的に形成さ
れた導電性領域である。この導電性領域は例えば半絶縁
性のGaAs基板に対してSiイオンを選択的に注入す
ることにより形成する。
FIG. 5 shows a conventional example of a resistor having a configuration using a conductive region and a pair of ohmic electrodes. In the figure, 501a and 501b are, for example, AuGe / Ni
Are ohmic electrodes, and are opposed to each other at a predetermined interval to form a pair of ohmic electrodes. Reference numeral 502 in the figure denotes a conductive region selectively formed on a semi-insulating semiconductor substrate. This conductive region is formed, for example, by selectively implanting Si ions into a semi-insulating GaAs substrate.

【0007】このような構造の抵抗体により所望の抵抗
値を得るには、半導体の導電性領域の面抵抗率を変える
か、対をなすオーム性電極の間隔(抵抗体の長さ)を変
えるか、オーム性電極の対向する辺で導電性領域に重な
っている長さ(図中でB、抵抗体の幅)を変えることに
より実現できる。
In order to obtain a desired resistance value by the resistor having such a structure, the sheet resistivity of the conductive region of the semiconductor is changed or the interval between the ohmic electrodes forming a pair (the length of the resistor) is changed. Alternatively, it can be realized by changing the length (B in the figure, width of the resistor) overlapping the conductive region on the opposite side of the ohmic electrode.

【0008】[0008]

【発明が解決しようとする課題】近年MMICの高出力
化に伴い、FETのゲート幅が大型化し、結果として、
FETの入力および出力インピーダンスが低くなってい
る。これに対応して、安定化抵抗などの整合回路の抵抗
体に要求される抵抗値も低くなっており、例えばゲート
幅10mmのFETに対しては、一般的には5〜6Ω程
度の値が要求される。
In recent years, as the output of the MMIC has been increased, the gate width of the FET has been increased.
The input and output impedances of the FET are low. Correspondingly, the resistance value required for a resistor of a matching circuit such as a stabilizing resistor is also low. For example, for an FET having a gate width of 10 mm, a value of about 5 to 6Ω is generally used. Required.

【0009】上記の従来例の抵抗体で低い抵抗値を実現
するには、不純物濃度を上げることにより導電性領域の
面抵抗率を下げ、また、オーム性電極の電極間隔を狭
め、また、対向する辺を長くすることで低い抵抗値を実
現できる。ところが、電極間隔をあまり狭めると短絡に
より歩留まり低下を起こしたり、電圧をかけたときに高
電界になり、このことにより破壊してしまうなどの欠点
が出てくる。このため、一般的には数ミクロン程度の間
隔よりは狭くしないことが多い。
In order to realize a low resistance value with the above-described conventional resistor, the surface resistivity of the conductive region is reduced by increasing the impurity concentration, the electrode interval between the ohmic electrodes is reduced, and the resistance is reduced. By making the side to be long, a low resistance value can be realized. However, if the distance between the electrodes is too small, the yield may be reduced due to a short circuit, or a high electric field may be generated when a voltage is applied. For this reason, it is often the case that the interval is not narrower than about several microns.

【0010】また、導電性領域の面抵抗率も、ある量以
上不純物濃度を増しても、抵抗率が下がらなくなる。こ
のため、より低い抵抗値が要求される場合は、オーム性
電極の対向する辺の長さBを長くすることで抵抗値を下
げている。このため、低い抵抗値を要求される高出力M
MICなどでは、高出力のためFETが大きくなるだけ
でなく、整合素子である抵抗体も大きくなり、結果的に
素子面積が非常に大きなMMICとなっている。このた
め、集積度が上がらず歩留まり低下やMMIC単価の上
昇を招く原因となっていた。
Further, the sheet resistivity of the conductive region does not decrease even if the impurity concentration is increased by a certain amount or more. For this reason, when a lower resistance value is required, the resistance value is reduced by increasing the length B of the opposite side of the ohmic electrode. For this reason, high output M which requires a low resistance value
In an MIC or the like, not only the FET becomes large due to the high output, but also the resistor as a matching element becomes large, resulting in an MMIC having a very large element area. For this reason, the degree of integration is not increased, which causes a decrease in yield and an increase in MMIC unit price.

【0011】本発明は、上記欠点を解決し、能動領域と
一対のオーム性電極より構成される抵抗体で、狭い面積
で低い抵抗値を実現できる構造の抵抗体を備えたマイク
ロ波集積回路を提供することを目的とする。
The present invention solves the above-mentioned drawbacks, and provides a microwave integrated circuit provided with a resistor having a structure which can realize a low resistance value in a small area by using a resistor composed of an active region and a pair of ohmic electrodes. The purpose is to provide.

【0012】[0012]

【課題を解決するための手段】上記課題を解決するため
本発明は、半絶縁性半導体基板上の所望の領域に、半導
体の導電性領域と一対のオーム性電極を配置したマイク
ロ波集積回路において、半導体の導電性領域上にオーム
性電極が交互に対向して配置され一対のオーム性電極を
構成したことを特徴とする。
SUMMARY OF THE INVENTION To solve the above problems, the present invention relates to a microwave integrated circuit having a semiconductor conductive region and a pair of ohmic electrodes arranged in a desired region on a semi-insulating semiconductor substrate. The present invention is characterized in that ohmic electrodes are alternately arranged on a conductive region of a semiconductor so as to face each other to form a pair of ohmic electrodes.

【0013】また、半絶縁性半導体基板上の所望の領域
に、半導体の導電性領域と一対のオーム性電極を配置し
たマイクロ波集積回路において、半導体の導電性領域上
に櫛歯型の一対のオーム性電極を構成したことを特徴と
する。
In a microwave integrated circuit in which a semiconductor conductive region and a pair of ohmic electrodes are disposed in a desired region on a semi-insulating semiconductor substrate, a comb-shaped pair of comb-shaped electrodes is provided on the semiconductor conductive region. An ohmic electrode is formed.

【0014】また、半絶縁性半導体基板上の所望の領域
に、半導体の導電性領域と一対のオーム性電極を配置し
たマイクロ波集積回路において、半導体の導電性領域上
に渦巻状の一対のオーム性電極を構成したことを特徴と
する。
In a microwave integrated circuit in which a semiconductor conductive region and a pair of ohmic electrodes are arranged in a desired region on a semi-insulating semiconductor substrate, a pair of spiral ohms is formed on the semiconductor conductive region. And a conductive electrode.

【0015】また、半絶縁性半導体基板上に電界効果ト
ランジスタを配置し、前記半絶縁性半導体基板上の所望
の領域に半導体の導電性領域と一対のオーム性電極を配
置したマイクロ波集積回路において、半導体の導電性領
域上にオーム性電極が交互に対向して配置され一対のオ
ーム性電極を構成したことを特徴とする。
In a microwave integrated circuit having a field effect transistor disposed on a semi-insulating semiconductor substrate and a semiconductor conductive region and a pair of ohmic electrodes disposed in a desired region on the semi-insulating semiconductor substrate. The present invention is characterized in that ohmic electrodes are alternately arranged on a conductive region of a semiconductor so as to face each other to form a pair of ohmic electrodes.

【0016】また、半絶縁性半導体基板上に電界効果ト
ランジスタを配置し、前記半絶縁性半導体基板上の所望
の領域に半導体の導電性領域と一対のオーム性電極を配
置したマイクロ波集積回路において、半導体の導電性領
域上に櫛歯型の一対のオーム性電極を構成したことを特
徴とする。
In a microwave integrated circuit, a field effect transistor is arranged on a semi-insulating semiconductor substrate, and a semiconductor conductive region and a pair of ohmic electrodes are arranged in a desired region on the semi-insulating semiconductor substrate. A pair of comb-shaped ohmic electrodes are formed on a conductive region of a semiconductor.

【0017】また、半絶縁性半導体基板上に電界効果ト
ランジスタを配置し、前記半絶縁性半導体基板上の所望
の領域に半導体の導電性領域と一対のオーム性電極を配
置したマイクロ波集積回路において、半導体の導電性領
域上に渦巻状の一対のオーム性電極を構成したことを特
徴とする。
Further, in a microwave integrated circuit in which a field effect transistor is arranged on a semi-insulating semiconductor substrate, and a semiconductor conductive region and a pair of ohmic electrodes are arranged in a desired region on the semi-insulating semiconductor substrate. A pair of spiral ohmic electrodes is formed on a conductive region of a semiconductor.

【0018】また、前記半絶縁性半導体基板上に選択的
イオン注入により形成した半導体の導電性領域を用いる
ことを特徴とする。
Further, a semiconductor conductive region formed by selective ion implantation on the semi-insulating semiconductor substrate is used.

【0019】また、電界効果トランジスタのソース電極
およびドレイン電極と同一のパターンを前記一対のオー
ム性電極としたことを特徴とする。
Further, the same pattern as the source electrode and the drain electrode of the field effect transistor is used as the pair of ohmic electrodes.

【0020】また、一対のオーム性電極がAuGe/N
iより成ることを特徴とする。
The pair of ohmic electrodes is made of AuGe / N
i.

【0021】また、一対のオーム性電極がAuGe/P
tより成ることを特徴とする。
A pair of ohmic electrodes is made of AuGe / P
t.

【0022】本発明によるマイクロ波集積回路はオーム
性電極が交互に対向して配置された一対の電極を構成
し、例えば櫛歯型又は渦巻状の構造をしている。このた
め従来と同じ面積で対向する電極長を長くできるため、
低い抵抗を狭い面積で実現できる。
The microwave integrated circuit according to the present invention comprises a pair of electrodes in which ohmic electrodes are alternately arranged to face each other, and has, for example, a comb-shaped or spiral structure. For this reason, the opposing electrode length can be increased with the same area as the conventional one,
Low resistance can be achieved in a small area.

【0023】[0023]

【発明の実施の形態】図1は本発明の実施の形態を示す
平面図である。図1において、101aと101bは例
えばAuGe/Niを用いた第一のオーム性電極と第二
のオーム性電極であり、一定の間隔を置いて各々櫛形で
対向し、一対のオーム性電極を構成している。また、図
中の102は半絶縁性半導体基板上に選択的に形成され
た導電性領域である。この導電性領域は、例えば半絶縁
性のGaAs基板に対してSiイオンを選択的に注入す
ることにより形成する。
FIG. 1 is a plan view showing an embodiment of the present invention. In FIG. 1, reference numerals 101a and 101b denote a first ohmic electrode and a second ohmic electrode using, for example, AuGe / Ni, which are opposed to each other in a comb shape at a predetermined interval to form a pair of ohmic electrodes. doing. Reference numeral 102 in the drawing denotes a conductive region selectively formed on the semi-insulating semiconductor substrate. This conductive region is formed, for example, by selectively implanting Si ions into a semi-insulating GaAs substrate.

【0024】一対のオーム性電極 101aと101b
はFETのソース電極およびドレイン電極のパターンを
利用して作成することができる。このため、製造の工程
は増加せずに低い抵抗値の抵抗体を小さい面積で実現で
きる。
A pair of ohmic electrodes 101a and 101b
Can be formed using the pattern of the source electrode and the drain electrode of the FET. Therefore, a resistor having a low resistance value can be realized with a small area without increasing the number of manufacturing steps.

【0025】図に示すように本発明による抵抗体では一
対のオーム性電極が、各々櫛形をして対向している。こ
のため、従来例での対向する辺の長さBに相当する長さ
は、長さAに櫛形で対向している電極対の対向数n(図
中の実施例では4対)を掛けた長さA×nとなる。この
ため、例えば、5Ωの抵抗値を実現するために、従来例
の場合約3500μm2 の面積が必要であったが、本発
明によれば対向数を4対とした場合1000μm2 とな
り、面積で約70%の削減が可能となる。よって、従来
例に比べ、同じ面積で低い抵抗値を実現できる。
As shown in the figure, in the resistor according to the present invention, a pair of ohmic electrodes face each other in a comb shape. For this reason, the length corresponding to the length B of the opposite side in the conventional example is obtained by multiplying the length A by the number n (four pairs in the example in the figure) of the pair of electrodes facing each other in a comb shape. The length is A × n. Thus, for example, in order to achieve a resistance of 5 [Omega, but the area where about 3500 2 in the conventional example was needed, next 1000 .mu.m 2 when the four pairs of opposite number, according to the present invention, in the area About 70% reduction is possible. Therefore, a lower resistance value can be realized in the same area as in the conventional example.

【0026】また、本発明による他の実施の形態を図2
に示す。この場合、櫛歯型のオーム性電極の両端の電極
が図1の例よりも長くなっており、かつ、導電性領域が
櫛歯型の間隙のすべてに形成されている。このため、対
向する長さを図1の場合のA×nよりもさらに長くでき
るため、同一面積でより低い抵抗を実現できる。
FIG. 2 shows another embodiment of the present invention.
Shown in In this case, the electrodes at both ends of the comb-shaped ohmic electrode are longer than those in the example of FIG. 1, and the conductive regions are formed in all of the comb-shaped gaps. Therefore, the opposing length can be made longer than A × n in the case of FIG. 1, and a lower resistance can be realized in the same area.

【0027】また本発明では、同一半絶縁性半導体基板
にFETを形成しているが、説明では省略した。記載し
ていないFETは対向した櫛歯型の電極を構成すること
が多く、一対のオーム性電極101a、101bはFE
Tのソース電極およびドレイン電極のパターンを利用し
て作成することができる。このため、製造工程を増加す
ることなく狭い面積に低抵抗の抵抗体を実現することが
できる。
In the present invention, the FET is formed on the same semi-insulating semiconductor substrate, but is omitted in the description. FETs not described often constitute opposing comb-shaped electrodes, and a pair of ohmic electrodes 101a and 101b are FE-shaped.
It can be formed using the pattern of the source electrode and the drain electrode of T. Therefore, a low-resistance resistor can be realized in a small area without increasing the number of manufacturing steps.

【0028】また、本発明の他の実施の形態を図3に示
した。上記の説明では一対のオーム性電極が櫛歯型の場
合について述べたが、図3に示した渦巻状であっても本
発明は実施できる。
FIG. 3 shows another embodiment of the present invention. In the above description, the case where the pair of ohmic electrodes is comb-shaped has been described.

【0029】このように本発明によれば、同じ面積で、
従来よりも低い抵抗値を実現できるため、より集積度の
高い抵抗体を提供できる。このため、同一の機能を有す
るマイクロ波集積回路を小さな半導体基板上に実現する
ことが可能となり、製造コストを削減できる。
Thus, according to the present invention, with the same area,
Since a resistance value lower than that of the related art can be realized, a resistor with a higher degree of integration can be provided. Therefore, a microwave integrated circuit having the same function can be realized on a small semiconductor substrate, and the manufacturing cost can be reduced.

【0030】なお、上記実施の形態ではオーム性電極と
してAuGe/Niを例示したが、AuGe/Ptでも
よく、また半絶縁性基板もGaAsに限らずInPでも
よいのは上記説明より明らかであり、導電性領域の形成
方法もイオン注入法に限らず本発明は実施できる。
In the above embodiment, AuGe / Ni is exemplified as the ohmic electrode. However, it is clear from the above description that AuGe / Pt may be used, and that the semi-insulating substrate may be InP instead of GaAs. The method for forming the conductive region is not limited to the ion implantation method, and the present invention can be implemented.

【0031】また、分岐した電極の枝の本数、電極の枝
の長さ、導電性領域の形状も図1、図2の形に限らない
のは上記説明から明らかである。また、渦巻の形状も図
3の形に限らない。
It is clear from the above description that the number of branched electrode branches, the length of the electrode branches, and the shape of the conductive region are not limited to those shown in FIGS. Further, the shape of the spiral is not limited to the shape shown in FIG.

【0032】[0032]

【発明の効果】本発明によれば、同じ面積で低い抵抗値
を実現できるため、より集積度の高い抵抗体、より集積
度の高いマイクロ波半導体を提供できる。
According to the present invention, since a low resistance value can be realized in the same area, a resistor with higher integration and a microwave semiconductor with higher integration can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明を説明する平面図である。FIG. 1 is a plan view illustrating the present invention.

【図2】本発明を説明する平面図である。FIG. 2 is a plan view illustrating the present invention.

【図3】本発明を説明する平面図である。FIG. 3 is a plan view illustrating the present invention.

【図4】従来例のFETを用いた増幅器の等価回路図で
ある。
FIG. 4 is an equivalent circuit diagram of a conventional amplifier using an FET.

【図5】従来例を説明する平面図である。FIG. 5 is a plan view illustrating a conventional example.

【符号の説明】[Explanation of symbols]

101a…第一のオーム性電極 101b…第二のオーム性電極 102…導電性領域 A…長さA 201a…第一のオーム性電極 201b…第二のオーム性電極 202…導電性領域 301a…第一のオーム性電極 301b…第二のオーム性電極 302…導電性領域 401…GaAs FET 402〜405…伝送線路 406、407…直流阻止用キャパシタ 408、409…高周波短絡用キャパシタ 410…安定化抵抗 501a…第一のオーム性電極 501b…第二のオーム性電極 502…導電性領域 B…長さB 101a first ohmic electrode 101b second ohmic electrode 102 conductive region A length A 201a first ohmic electrode 201b second ohmic electrode 202 conductive region 301a first One ohmic electrode 301b Second ohmic electrode 302 Conductive region 401 GaAs FETs 402 to 405 Transmission lines 406 and 407 DC blocking capacitors 408 and 409 High frequency short circuit capacitor 410 Stabilizing resistor 501a ... First ohmic electrode 501b ... Second ohmic electrode 502 ... Conductive area B ... Length B

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 半絶縁性半導体基板上の所望の領域に、
半導体の導電性領域と一対のオーム性電極を配置したマ
イクロ波集積回路において、半導体の導電性領域上にオ
ーム性電極が交互に対向して配置され一対のオーム性電
極を構成したことを特徴とするマイクロ波集積回路。
1. A method according to claim 1, wherein a desired region on the semi-insulating semiconductor substrate is
In a microwave integrated circuit in which a conductive region of a semiconductor and a pair of ohmic electrodes are arranged, a pair of ohmic electrodes are formed by alternately opposing ohmic electrodes on the conductive region of the semiconductor. Microwave integrated circuit.
【請求項2】 半絶縁性半導体基板上の所望の領域に、
半導体の導電性領域と一対のオーム性電極を配置したマ
イクロ波集積回路において、半導体の導電性領域上に櫛
歯型の一対のオーム性電極を構成したことを特徴とする
マイクロ波集積回路。
2. In a desired region on a semi-insulating semiconductor substrate,
A microwave integrated circuit in which a semiconductor conductive region and a pair of ohmic electrodes are arranged, wherein a pair of comb-shaped ohmic electrodes are formed on the semiconductor conductive region.
【請求項3】 半絶縁性半導体基板上の所望の領域に、
半導体の導電性領域と一対のオーム性電極を配置したマ
イクロ波集積回路において、半導体の導電性領域上に渦
巻状の一対のオーム性電極を構成したことを特徴とする
マイクロ波集積回路。
3. In a desired region on a semi-insulating semiconductor substrate,
A microwave integrated circuit in which a semiconductor conductive region and a pair of ohmic electrodes are arranged, wherein a pair of spiral ohmic electrodes are formed on the semiconductor conductive region.
【請求項4】 半絶縁性半導体基板上に電界効果トラン
ジスタを配置し、前記半絶縁性半導体基板上の所望の領
域に半導体の導電性領域と一対のオーム性電極を配置し
たマイクロ波集積回路において、半導体の導電性領域上
にオーム性電極が交互に対向して配置され一対のオーム
性電極を構成したことを特徴とするマイクロ波集積回
路。
4. A microwave integrated circuit in which a field effect transistor is disposed on a semi-insulating semiconductor substrate, and a semiconductor conductive region and a pair of ohmic electrodes are disposed in a desired region on the semi-insulating semiconductor substrate. A microwave integrated circuit, wherein ohmic electrodes are alternately arranged on a conductive region of a semiconductor to form a pair of ohmic electrodes.
【請求項5】 半絶縁性半導体基板上に電界効果トラン
ジスタを配置し、前記半絶縁性半導体基板上の所望の領
域に半導体の導電性領域と一対のオーム性電極を配置し
たマイクロ波集積回路において、半導体の導電性領域上
に櫛歯型の一対のオーム性電極を構成したことを特徴と
するマイクロ波集積回路。
5. A microwave integrated circuit in which a field effect transistor is disposed on a semi-insulating semiconductor substrate, and a semiconductor conductive region and a pair of ohmic electrodes are disposed in a desired region on the semi-insulating semiconductor substrate. A microwave integrated circuit comprising a pair of comb-shaped ohmic electrodes formed on a conductive region of a semiconductor.
【請求項6】 半絶縁性半導体基板上に電界効果トラン
ジスタを配置し、前記半絶縁性半導体基板上の所望の領
域に半導体の導電性領域と一対のオーム性電極を配置し
たマイクロ波集積回路において、半導体の導電性領域上
に渦巻状の一対のオーム性電極を構成したことを特徴と
するマイクロ波集積回路。
6. A microwave integrated circuit in which a field effect transistor is disposed on a semi-insulating semiconductor substrate, and a semiconductor conductive region and a pair of ohmic electrodes are disposed in a desired region on the semi-insulating semiconductor substrate. A microwave integrated circuit, comprising a pair of spiral ohmic electrodes formed on a conductive region of a semiconductor.
【請求項7】 前記半絶縁性半導体基板上に選択的イオ
ン注入により形成した半導体の導電性領域を用いること
を特徴とする請求項1乃至請求項6記載のマイクロ波集
積回路。
7. The microwave integrated circuit according to claim 1, wherein a semiconductor conductive region formed on said semi-insulating semiconductor substrate by selective ion implantation is used.
【請求項8】 電界効果トランジスタのソース電極およ
びドレイン電極と同一のパターンを前記一対のオーム性
電極としたことを特徴とする請求項4乃至請求項5記載
のマイクロ波集積回路。
8. The microwave integrated circuit according to claim 4, wherein the same pattern as the source electrode and the drain electrode of the field effect transistor is used as the pair of ohmic electrodes.
【請求項9】 一対のオーム性電極がAuGe/Niよ
り成ることを特徴とする請求項1乃至請求項6記載のマ
イクロ波集積回路。
9. The microwave integrated circuit according to claim 1, wherein the pair of ohmic electrodes is made of AuGe / Ni.
【請求項10】 一対のオーム性電極がAuGe/Pt
より成ることを特徴とする請求項1乃至請求項6記載の
マイクロ波集積回路。
10. A pair of ohmic electrodes are made of AuGe / Pt.
7. The microwave integrated circuit according to claim 1, comprising:
JP04502997A 1997-02-28 1997-02-28 Microwave integrated circuit Expired - Fee Related JP3499394B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP04502997A JP3499394B2 (en) 1997-02-28 1997-02-28 Microwave integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP04502997A JP3499394B2 (en) 1997-02-28 1997-02-28 Microwave integrated circuit

Publications (2)

Publication Number Publication Date
JPH10242387A true JPH10242387A (en) 1998-09-11
JP3499394B2 JP3499394B2 (en) 2004-02-23

Family

ID=12707919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP04502997A Expired - Fee Related JP3499394B2 (en) 1997-02-28 1997-02-28 Microwave integrated circuit

Country Status (1)

Country Link
JP (1) JP3499394B2 (en)

Also Published As

Publication number Publication date
JP3499394B2 (en) 2004-02-23

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