JPH09134380A - Device for estimating virtual wiring length - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute wiring length estimation with high precision by judging whether or not the adjacent arrangement of object macrocells is difficult, changing a calculating system in accordance with it and calculating virtual wiring length. SOLUTION: When an object network is selected by an estimation object net selecting means 3, an arrangement area peripheral length reading means 5 reads information of peripheral length in an arrangement area which it belongs to from an arrangement area storage device 1 and a fan-out number reading means 6 reads fan-out number information of the estimation object net from a connection information storage device 2. A pin number reading and judging means 7 reads information of a pin number in the object macrocells and a net number reading and judging means 8 reads information of the net number connected to the object macrocells so as to respectively judge difficulty in the adjacent arrangement of the object macrocells. A virtual wiring length calculating means 11 changes the calculating system in accordance with the difficulty of adjacent arrangement based on the read information which is stored in a reading information storage device 4 so as to calculate virtual wiring length.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a virtual wiring length estimating device for estimating a virtual wiring length when designing a semiconductor integrated circuit,
In particular, the present invention relates to a virtual wiring length estimation device with improved estimation accuracy.

[0002]

2. Description of the Related Art When a wiring length on a circuit is inappropriately set when designing a semiconductor integrated circuit, the time (delay time) required for a signal to pass through the wiring is extended, and the circuit operation cannot meet the required specifications. Can occur. Therefore, at the stage when the layout design of macro cells and the wiring design between macro cells (hereinafter referred to as placement and routing) are completed, the delay time is checked based on the wiring length, and the wiring having an inappropriately long wiring length is corrected. However, the correction after the placement and wiring is completed requires a large amount of correction and a huge amount of time. Therefore, usually, before executing the placement and routing, the virtual wiring length is estimated for each net to optimize the wiring length, and the correction after placement and routing is minimized.

FIG. 18 shows a conceptual diagram when a virtual wiring length is estimated by using a conventional virtual wiring length estimation device. FIG.
Reference numeral 8 is a model for estimating the virtual wiring length in a state where no cells are arranged. Macro cells I1 and I2 are included in the estimation target net T1, and macro cells I3 and I4 are included in the net T2.
Are connected to each other. Both the nets T1 and T2 to be estimated are arranged in the same arrangement region R, and the peripheral length (length of four sides) of the arrangement region R is L.

In the conventional virtual wiring length estimation device, the virtual wiring length of a net is estimated based on the size (peripheral length) of the arrangement area including the net and the number of fanouts of the net. Specifically, the peripheral length L of the arrangement region R, the number of fan-outs of the estimation target net (the number of gate circuits driven through the target net) F, and the coefficient C1 determined by the design rule when designing the semiconductor integrated circuit And C2 are used. The estimation formula when the estimated value of the virtual wiring length is X is shown in Formula (1).

[0005]

(Equation 1)

Here, the units of X, L, and C2 are lengths, and C1 and F are unitless.

FIG. 18 schematically shows the estimated virtual wiring length value X obtained by the equation (1) as a straight line. The estimated value X of the virtual wiring length is close to the net T1, but is significantly longer than the net T2.

[0008]

As described above,
In the conventional virtual wiring length estimation device, the virtual wiring length is estimated based on the peripheral length of the placement area including the estimation target net and the fanout number of the estimation target net. All nets with fan-out numbers will be estimated for the same virtual wire length.
On an actual semiconductor integrated circuit, even if the nets have the same fan-out number that belong to the same arrangement area, the wiring lengths differ depending on the arrangement positions of the macro cells connected to the respective nets. Therefore, for some nets, the difference between the actual wiring length and the estimated virtual wiring length becomes large,
This is a cause of lowering the estimation accuracy of the virtual wiring length estimation device.

The present invention has been made in order to solve the above-mentioned problems, and in the virtual wiring length estimation, the virtual wiring length estimation is executed in consideration of the connection information of the net to be estimated, and it is highly accurate. An object of the present invention is to provide a virtual wiring length estimation device capable of executing wiring length estimation.

[0010]

According to a first aspect of the present invention, there is provided a virtual wiring length estimating device for virtualizing the wiring length of a net provided between macro cells on the basis of design data required for designing a semiconductor integrated circuit. In the virtual wiring length estimation apparatus for estimating the net length, a net of the nets whose wiring length is to be estimated is a target net, a macro cell connected to the target net among the macro cells is a target macro cell, and the target macro cell has a first And a second target macrocell, which includes a second target macrocell, and determines whether or not the first and second target macrocells are difficult to be adjacently arranged according to a predetermined rule, and the first and second target macrocells. Is difficult to place adjacently, and when the first and second target macro cells are easily placed adjacently, the calculation method is changed to change the virtual wiring length. And a wire length calculation means for output.

According to a second aspect of the virtual wire length estimating apparatus of the present invention, the adjacent placement difficulty determination means uses the design data to obtain data relating to the number of nets connected to the first and second target macrocells. The number of nets for reading the net number is read, and the data regarding the number of nets is compared with a preset reference value to determine the difficulty of the adjacent arrangement of the first and second target macro cells.

According to a third aspect of the present invention, there is provided a virtual wiring length estimating apparatus, wherein the data on the number of nets is the number of first and second nets connected to each of the first and second target macrocells. The possibility that the second target macro cell can be arranged adjacent to the first target macro cell is obtained by comparing the first number of nets with the reference value.
The possibility of arranging the first target macro cell adjacent to the target macro cell is determined by comparing the second number of nets with the reference value, and based on both results, the first and second
The difficulty of the adjacent placement of the target macro cell is determined.

According to a fourth aspect of the virtual wiring length estimating apparatus of the present invention, the data regarding the number of nets is the total number of the nets connected to the first and second target macrocells, and the total number is the total number of the nets. And the reference value are compared to determine the difficulty of the adjacent arrangement of the first and second target macro cells.

In the virtual wiring length estimating device according to a fifth aspect of the present invention, the adjacent placement difficulty determination means reads data regarding the number of pins of the first and second target macrocells from the design data. A pin number reading means is provided, and the data regarding the number of pins is compared with a preset reference value to determine the difficulty of the adjacent arrangement of the first and second target macro cells.

In the virtual wiring length estimating device according to a sixth aspect of the present invention, the data regarding the number of pins is the first and second pin numbers of each of the first and second target macrocells. And adjacent to the first target macro cell to the second
The possibility of arranging the target macro cell of No. 2 is obtained by comparing the first pin count with the reference value, and the possibility of arranging the first target macro cell adjacent to the second target macro cell is The number of pins is compared with the reference value, and the difficulty of the adjacent arrangement of the first and second target macrocells is determined based on both results.

In a virtual wiring length estimating device according to a seventh aspect of the present invention, the data regarding the number of pins is the total number of pins included in the first and second target macrocells, and the total number and the reference. The difficulty of the adjacent arrangement of the first and second target macro cells is determined by comparison with the value.

In the virtual wiring length estimating apparatus according to the present invention, the adjacent placement difficulty determination means uses the design data to obtain data on the number of nets connecting the first and second target macrocells. The number of nets for reading the net number is read, and the data regarding the number of nets is compared with a preset reference value to determine the difficulty of the adjacent arrangement of the first and second target macro cells.

In the virtual wiring length estimating apparatus according to claim 9 of the present invention, the adjacent placement difficulty determining means is a physical device for reading data concerning the physical sizes of the first and second target macrocells from the design data. A physical size reading means, and compares the data relating to the physical size with a preset reference value to determine the difficulty of the adjacent arrangement of the first and second target macro cells.

In the virtual wiring length estimating apparatus according to the present invention, the data regarding the physical size is the first and second physical sizes of each of the first and second target macrocells. Then, the possibility of arranging the second target macrocell adjacent to the first target macrocell is determined by comparing the first physical size with the reference value, and is determined adjacent to the second target macrocell. The possibility of arranging the first target macro cell is obtained by comparing the second physical size with the reference value, and the difficulty of the adjacent arrangement of the first and second target macro cells is determined based on both results. To do.

In the virtual wiring length estimating device according to claim 11 of the present invention, the data regarding the physical size is a total value of the physical sizes of the first and second target macrocells, and the total value. And the reference value are compared to determine the difficulty of the adjacent arrangement of the first and second target macro cells.

A virtual wiring length estimation device according to a twelfth aspect of the present invention estimates a wiring capacitance of the target net from the calculated virtual wiring length and a wiring capacitance per unit length. Means are further provided.

A virtual wiring length estimating device according to a thirteenth aspect of the present invention estimates a delay time of the target net from the calculated virtual wiring length and a delay time per unit length of the virtual wiring. A wiring delay time estimation means is further provided.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION

<Embodiment 1> FIG. 1 shows a virtual wiring length estimation device 10 as a first embodiment of a virtual wiring length estimation device according to the present invention.
The structure of 0 is shown. In FIG. 1, reference numeral 1 denotes an area in which a macro cell and a net are to be placed and wired on a semiconductor integrated circuit, that is, a placement area storage device for storing the position of the placement area and size information of the placement area, and 2 is a connection of each macro cell and net. A connection information storage device 3 for storing information on relations is an estimation target net selecting means for selecting a net for which a virtual wiring length is estimated.

A placement area peripheral length reading means 5 for reading out information about the perimeter of the placement area to which the net to be estimated belongs is connected to the placement area storage device 1, and the connection information storage device 2 has a fanout of the net to be estimated. The fan-out number reading means 6 for reading the information on the number, and the information on the number of pins of the macro cell (hereinafter referred to as the target macro cell) connected to the estimation target net are read.
Pin number read / determination means 7 of the target macro cell for determining the difficulty of adjacent placement of the target macro cell, and information about the number of nets connected to any one of the target macro cells, and the difficulty of adjacent placement of the target macro cell The net number reading / judging means 8 of the target macro cell for judging is connected.

Then, the placement area peripheral length reading means 5, the fan-out number reading means 6, the pin number reading / determining means 7 of the target macro cell, the net number reading of the target macro cell,
The determination means 8 is connected to the read information storage means 4 for storing the read information, and the read information storage means 4 is connected.
Is connected to the virtual wiring length calculation means 11 for estimating the virtual wiring length based on the read information stored in the read information storage means 4. Further, the virtual wiring length calculation means 11 is connected to the output device 12 which outputs the estimated result. Here, a pin of a macro cell is a connectable point of a net provided on the macro cell.

Next, the operation of the virtual wiring length estimation device 100 will be described. The virtual wiring length estimation device 100 is characterized in that the virtual wiring length estimation method is changed based on the information on the number of pins or the number of nets of the target macro cell.

FIG. 2 shows a flowchart for explaining the operation of the virtual wiring length estimation device 100. In FIG. 2, first, the device user selects a net to be estimated (step ST1). Next, information about the peripheral length of the placement area is read from the placement area storage device 1 (step ST
2).

Next, information regarding the fan-out number is read from the connection information storage device 2 (step ST3), and further information regarding the pin number or the net number is read (step ST4).

Next, the possibility of adjacent placement of the target macro cell is calculated based on the information about the number of pins or the information about the number of nets (step ST5).

Here, a method of calculating the possibility of adjacent placement of the target macro cell will be described. The target macrocells are referred to as macrocells A and B, and the probability value P that enables the macrocell B to be arranged in either the left or right direction of the macrocell A.
_A is expressed by the following equations (2) and (3), where MA is the number of macro cells connected to the macro cell A by one net.

[0031]

(Equation 2)

[0032]

(Equation 3)

Similarly, the probability value P _B that enables the macro cell A to be arranged in either the left or right direction of the macro cell _B is
If the number of macro cells connected to the macro cell B by one net is MB, it is expressed by the following equations (4) and (5).

[0034]

(Equation 4)

[0035]

(Equation 5)

In the above equation, "C" represents a combination.

The macrocells A, the possibility of adjacent arrangement of B is determined by the magnitude of the P _A, P _B, P _A, P _B are both 1
In such a case, the macro cells A and B are likely to be arranged adjacent to each other. The values of P _A and P _B are
It is determined by the number MA of macro cells connected to the macro cell A by one net and the number MB of macro cells connected by the macro cell B by one net.

Here, MA and MB have a relationship of monotonically increasing with respect to the number of nets connected to the macro cells A and B and the number of pins of the macro cells A and B, and are connected to the macro cells A and B. It is obtained based on the number of nets or the number of pins of the macro cells A and B. Therefore, it can be said that the possibility that the macro cells A and B are adjacently arranged is determined based on the number of nets connected to the macro cells A and B or the number of pins of the macro cells A and B.

In the above description, the possibility that the target macro cells are adjacently arranged is obtained based on the number of nets connected to the target macro cell or the number of pins of the target macro cell, but based on the number of nets. The difference between the case of performing and the case of using the number of pins will be described with reference to FIG.

In FIG. 3, macro cells A and B are connected to the net N1 to be estimated. Macrocell A has three pins PN and macrocell B has four pins. Therefore, although the number of pins to which the net N2 other than the estimation target net N1 may be connected is 5, the net N2 other than the estimation target net N1 may be connected.
The number of 2 is 4, and there is a difference in the number of pins and the number of nets.

It is more practical to calculate the possibility that the macro cells A and B will be arranged adjacent to each other based on the number of nets. However, as a process, the macro cells A and B can be arranged adjacent to each other based on the number of pins. It is easier to calculate the property, and the execution speed becomes faster by preparing the number of pins for each type of macro cell as a library in advance. Therefore, it is up to the user to decide whether it is based on the number of nets or the number of pins.

Next, in step ST6, step ST5
Numerical value P of the possibility of adjacent placement of the target macro cell calculated in
Based on _A and P _B , it is determined whether the target macro cell is difficult to be adjacently arranged. As an example of the criterion, whether P _A and P _B obtained by the equations (2) to (5) are both 1
An example is based on whether it is smaller than 1. Of course, this reference value can be set arbitrarily according to the configuration of the semiconductor integrated circuit.

When it is determined in step ST6 that the target macro cells are difficult to be arranged adjacent to each other, step ST
In 7, the estimation method for the virtual wiring length of the net between the macro cells in which adjacent placement is difficult is executed.

On the other hand, if it is determined in step ST6 that the target macro cell is not difficult to be adjacently arranged, then in step ST8, an estimation method for the virtual wiring length of the net between macro cells that is easily arranged adjacently is executed. Then, in step ST9, the estimation result is output.

Here, a method for estimating the virtual wiring length of a net between macro cells whose adjacent placement is difficult and a method for estimating the virtual wiring length of a net between macro cells whose adjacent placement is easy will be described.

FIG. 4 shows an example of the configuration of a semiconductor integrated circuit which is a target when the virtual wiring length estimating device 100 is used to estimate the virtual wiring length. In FIG. 4, the nets for which the virtual wiring length is estimated are T1a and T2a, the macro cells I1a and I2a are connected to the net T1a, and the macro cells I3a and I4a are connected to the net T2a.

The macrocell I1a is connected to the macrocell I5a via the net S1a, and the macrocell I2a is connected to the macrocell I6a via the net S2a. Further, the macro cells I3a include nets S3a to S7a.
, And the macrocells I7a to I11a are connected to each other, and the macrocell I4a is connected to the macrocells I12a to I15a via each of the nets S8a to S11a. The nets S1a to S11a are nets other than the virtual wiring length estimation target.

In the semiconductor integrated circuit shown in FIG. 4, the number of nets connected to the target macrocells I1a and I2a is two, and the number of nets connected to the target macrocells I3a and I4a is nine. Is. Therefore, if it is determined that the target macrocells are arranged adjacent to each other based on the number of nets, the net T1a becomes a net between macrocells that can be easily arranged, and the net T2
a is a net between macro cells that are difficult to arrange adjacent to each other.

Assuming that the nets T1a and T2a belong to the same placement area, the peripheral length of the placement area is L, and the fan-out numbers of the nets T1 and T2 are both F, between macro cells that are easily placed adjacent to each other. The virtual wiring length R1 of the net (that is, the net T1a) is estimated by the following formula (6), and the virtual wiring length R2 of the net (that is, the net T2a) between the macro cells in which adjacent placement is difficult is estimated by the following formula (6). It can be calculated in 7).

[0050]

(Equation 6)

[0051]

(Equation 7)

Here, C1 to C4 are coefficients determined by a design rule when designing a semiconductor integrated circuit, and L,
The units of RI, R2 and C2, C4 are length, C
1, C3 and F are unitless. Since the wiring length of the net between the macro cells that are easily arranged adjacent to each other is shorter than the wiring length of the net between the macro cells that are difficult to arrange adjacently,
The values of C1 to C4 are determined so that R1 <R2.

FIG. 5 shows an example of a layout wiring diagram in which the layout and wiring are performed so that the total wiring length in the semiconductor integrated circuit shown in FIG. 4 is minimized. The nets T1b, T2b shown in FIG.
S1b to S11b and macro cells I1b to I15b are the nets T1a, T2a, S1a to S11a,
It has the same configuration as the macro cells I1a to I15a, and is different only in the reference numerals for convenience.

As shown in FIG. 5, the general structure of the semiconductor integrated circuit has a plurality of macrocell stages in which a plurality of macrocells are formed in a row in the left-right direction, and the macrocell stages are arranged in parallel. A wiring step for wiring is provided between them.

In FIG. 5, the macro cells I1b and I2b, which are the target macro cells, are arranged adjacent to each other in the macro cell stage MS1 and the net T which is the target net for estimation.
The wiring length of 1b is the shortest, 2 μm.

The other target macro cells, macro cells I3b and I4b, are respectively in macro cell stage MS2.
Also, the wiring length of the net T2b which is arranged in the MS3 and is the estimation target net is 7 μm.

According to the first embodiment of the virtual wiring length estimating apparatus of the present invention, the difference between the actual wiring length of the net between the macro cells which can be easily arranged adjacently and the actual wiring length of the net between the macro cells which are difficult to be adjacently arranged. In consideration of the above, by changing the virtual wiring length estimation method for the nets between macro cells where adjacent placement is easy and for the nets between macro cells where adjacent placement is difficult, it is possible to estimate the virtual wiring length corresponding to each of them. It is possible to estimate various virtual wiring lengths.

Further, the number of nets connected to the target macro cell or the number of pins of the target macro cell is read out for each individual target macro cell to determine the estimation method. Since it is possible to distinguish not only two types of nets between macro cells that are difficult to place adjacently but also three types of nets that are between macro cells that are easy to place adjacently and macro cells that are difficult to place adjacently, a detailed estimate can be made. .

In the first embodiment, an example in which the estimation method is determined by reading the number of nets connected to the target macro cell or the number of pins of the target macro cell for each target macro cell has been described. The estimation method may be determined based on the total number of nets connected to all target macrocells connected to the estimation target net or the total number of pins of all target macrocells connected to one estimation target net. . By adopting such a method, the time required for estimation can be reduced.

Further, although FIG. 5 shows, as an example, a semiconductor integrated circuit in which a plurality of macro cells are formed in a row in the left-right direction, the macro cells are not only adjacent in the left-right direction but also in the up-down direction. There are also semiconductor integrated circuits. In such a semiconductor integrated circuit,
It is more likely that the target macrocells will be placed next to each other,
The wiring distance between vertically adjacent macro cells is longer than the wiring distance between horizontally adjacent macro cells, reflecting the shape of the macro cells and the like. Therefore, even for a net between macro cells that can be easily arranged adjacent to each other, the method of estimating the virtual wiring length is changed depending on whether the nets are arranged adjacent to each other in the horizontal direction or adjacent to each other in the vertical direction.

<Modification 1 of First Embodiment> In the first embodiment described above, the estimation is performed depending on whether the net is between macro cells in which adjacent placement is easy or a net between macro cells in which adjacent placement is difficult. Although an example of estimating the virtual wiring length corresponding to each by changing the coefficient of the formula has been shown, the same effect can be obtained by using the coefficient table shown in FIG.

For example, when the peripheral length of the allocable area is L, the virtual wiring length R1 of the net between the macro cells that are easily arranged adjacent to each other and the virtual wiring length R2 of the net between the macro cells that are difficult to be arranged adjacent to each other are estimated as follows. It can be calculated by the equation (8).

[0063]

(Equation 8)

Here, when the fan-out number is 1,
The virtual wiring length R1 can be estimated by substituting C1 = 0.01 and C2 = 0.03 into the equation (8), and C1 =
The virtual wiring length R2 can be estimated by substituting 0.05 and C2 = 0.12 into the equation (8).

The coefficient table was obtained by statistical processing from the wiring length data of the semiconductor integrated circuit group designed in the past with the same design rule (the minimum wiring width, the number of aluminum layers for wiring, etc.). The table is different for each design rule.

The advantage of using such a coefficient table is that the estimation formula is simplified and the time required for estimation can be reduced. That is, the estimation formulas (6) and (7) shown in the first embodiment actually have a more complicated structure, and a complicated process is required to determine the coefficients C1 to C4 that match these estimation formulas. Need. On the other hand, if a coefficient table obtained from past data is used, the estimation formula can be simple and the coefficient can be determined only by statistical processing.

<Modification 2 of Embodiment 1> Embodiment 1
, The virtual wiring length corresponding to each is determined by using the estimation formula with only the coefficient changed, depending on whether it is a net between macro cells where adjacent placement is easy or a net between macro cells where adjacent placement is difficult. Although an example of estimation is shown, the virtual wiring length corresponding to each may be estimated by using estimation formulas having completely different configurations. The following formulas (9) and (10) are shown as an example.

[0068]

(Equation 9)

[0069]

(Equation 10)

In equation (10), the effect that the peripheral length L of the placement area has on the virtual wiring length is larger than the effect of other parameters. However, depending on the design rule, the fanout number F is virtual. In some cases, the effect on the wiring length becomes large.

<Modification 3 of Embodiment 1> Embodiment 1
In (1), the fanout number F of the net and the peripheral length L of the arrangement region are reflected in the equation for estimating the virtual wiring length. This is based on the viewpoint that the estimation accuracy can be improved as the number of parameters used for estimation increases, but there is also a problem that the estimation time increases as the number of parameters increases. Therefore, only one of them may be used as a parameter in order to reduce the estimation time.

As an example, equations (11) and (12) using only the fan-out number of the net as a parameter are shown below.

[0073]

[Equation 11]

[0074]

(Equation 12)

<Embodiment 2> FIG. 7 shows the configuration of a virtual wiring length estimation apparatus 200 as Embodiment 2 of the virtual wiring length estimation apparatus according to the present invention. In FIG. 7, the connection information storage device 2 includes a fan-out number reading means 6 for reading information on the fan-out number of the net to be estimated,
The read / determination means 9 for the number of nets connecting the target macrocells is connected, which reads out information about the number of nets connecting the target macrocells and determines the difficulty of the adjacent arrangement of the target macrocells. The fan-out number reading means 6 and the net number reading / determining means 9 for connecting the target macro cells are connected to the read information storage means 4 for storing the read information. In addition, the same components as those of the virtual wiring length estimation device 100 described with reference to FIG. 1 are designated by the same reference numerals, and the duplicate description will be omitted.

Next, the operation of the virtual wiring length estimation device 200 will be described. The virtual wiring length estimation device 200 is characterized in that the virtual wiring length estimation method is changed based on the information on the number of nets connecting the target macro cells.

FIG. 8 shows a flowchart for explaining the operation of the virtual wiring length estimation device 200. In FIG. 8, first, the device user selects a net to be estimated (step ST11). Next, information about the peripheral length of the placement area is read from the placement area storage device 1 (step ST1).
2).

Next, information about the fan-out number is read from the connection information storage device 2 (step ST13), and information about the number of nets connecting the target macro cells is read (step ST14).

Next, it is judged whether or not it is difficult to arrange the target macro cells adjacent to each other based on the information about the number of nets connecting the target macro cells (step S1).
5). As an example of the determination criteria, there is an example based on whether or not there is at least one net that connects target macrocells other than the estimation target net. Needless to say, this reference value can be set arbitrarily according to the configuration of the semiconductor integrated circuit.

The reason why such a criterion is adopted will be described below. In general, at the time of placement and routing, the total area of the placement and routing result is reduced, and the delay time of all the signal lines is kept at a value equal to or less than the value determined by the operating frequency of the semiconductor integrated circuit. However, since the type and number of macro cells are already determined at the time of placement and routing, the above condition can be dealt with by shortening the total wiring length in the semiconductor integrated circuit. That is, by shortening the total wiring length, it is possible to reduce the area occupied by the wirings, reduce the total area of the placement and wiring results, and shorten the delay time of the signal passing through the wirings. Therefore, it is common to execute the placement and routing so as to shorten the total wiring length in the semiconductor integrated circuit.
The macro cells connected by a plurality of nets are preferentially arranged adjacently rather than the macro cells connected by only the nets of the book (that is, only the target net) are arranged adjacently.

Therefore, in step ST15, it is determined that the target macrocells connected by a plurality of nets are easy to be adjacently arranged, and it is determined that the target macrocells connected only by the target net are difficult to be adjacently arranged.

If it is determined in step ST15 that the target macro cells are difficult to be arranged adjacent to each other, step S
At T16, the estimation method for the virtual wiring length of the net between the macro cells in which adjacent placement is difficult is executed.

On the other hand, when it is determined in step ST15 that the target macro cell is not difficult to be adjacently arranged, in step ST17, the estimation method for the virtual wiring length of the net between macro cells that is easily arranged adjacently is executed.
Then, in step ST18, the estimation result is output.

The method of estimating the virtual wiring length of the net between the macro cells whose adjacent placement is difficult and the method of estimating the virtual wiring length of the net between the macro cells whose adjacent placement is easy are performed using the equation (6) described in the first embodiment. ) ~
(12) is used.

FIG. 9 shows an example of the configuration of a semiconductor integrated circuit which is a target when the virtual wiring length estimating device 200 is used to estimate the virtual wiring length. In FIG. 9, nets whose virtual wiring length is to be estimated are T3a and T4a, macro cells I20a and I21a are connected to the net T3a, and macro cells I22a and I2 are connected to the net T4a.
3a is connected.

The macro cells I24a and I25 are connected to the macro cell I20a via the nets S12a and S13a.
a are connected to each other, and the net S1 is connected to the macrocell I21a.
Macro cells I26a and I27a are connected via 4a and S15a, respectively. And macrocell I
20a and I21a are connected to each other by a net S16a.

The macro cell I22a has a net S1.
Macro cells I28a and I29a are connected via 7a and S18a, and net S is connected to macro cell I23a.
19a to S21a through the macro cell I30a to
I32a is connected. The nets S12a to S12
Reference numeral 21a is a net other than the virtual wiring length estimation target.

In the semiconductor integrated circuit shown in FIG. 9, macro cells I20a and I21a which are the target macro cells.
Are connected by the net S16a in addition to the net T3a which is the net to be estimated. On the other hand, the macro cells I22a and I23a, which are the target macro cells,
Only the net T4a, which is the estimated net, is connected. Therefore, when the possibility that the target macro cells are adjacently arranged is determined based on the number of nets that connect the target macro cells, the net T3a is a net between macro cells that are easily arranged adjacent to each other, and the net T4a is a net between macro cells that are difficult to be adjacent arranged. It becomes the net.

Here, the estimation of the virtual wiring length of the net between the macro cells which can be easily arranged adjacent to each other is made in the first embodiment.
The equation (5) described in 1) is applied, and the equation (6) described in the first embodiment is applied to the estimation of the virtual wiring length of the net between the macro cells in which adjacent placement is difficult. When there are a plurality of nets connecting the target macro cells, the estimation accuracy of the virtual wiring length can be improved by modifying the estimation value in the direction in which the virtual wiring length becomes shorter.

FIG. 10 shows an example of a layout and wiring diagram in which the layout and wiring are performed so that the total wiring length in the semiconductor integrated circuit shown in FIG. 9 is minimized. The nets T3b and T4 shown in FIG.
b, S12b to S21b, macro cells I20b to I32
b is the nets T3a, T4a, S12a-shown in FIG.
It has the same configuration as S21a and the macrocells I20a to I32a, and only the symbols are changed for convenience.

As shown in FIG. 10, the general structure of a semiconductor integrated circuit has a plurality of macrocell stages in which a plurality of macrocells are formed in a row in the left-right direction, and the macrocell stages are arranged in parallel. A wiring step for wiring is provided between them.

In FIG. 10, macro cells I20b and I21b, which are the target macro cells, are macro cell stages MS.
The shortest wiring lengths of the net T3b, which is a net to be estimated, and the net S16b, which is a net that is not a virtual wiring length estimation target, are the shortest, 2 μm.

The other target macro cells, macro cells I22b and I23b, are respectively in macro cell stage M.
The wiring length of the net T4b, which is arranged in S2 and MS3 and is a net to be estimated, is 7 μm.

According to the second embodiment of the virtual wiring length estimating device of the present invention, the actual wiring length of the net between macro cells which are easily arranged adjacent to each other and the actual wiring of the net between macro cells which are difficult to be arranged adjacent to each other. Considering the difference from the length, it is possible to estimate the virtual wiring length corresponding to each by changing the virtual wiring length estimation method for the net between macro cells where adjacent placement is easy and for the net between macro cells where adjacent placement is difficult. Therefore, it is possible to estimate the virtual wiring length with high accuracy.

<Third Embodiment> FIG. 11 shows the configuration of a virtual wiring length estimating device 300 as a third embodiment of the virtual wiring length estimating device according to the present invention. 11, the connection information storage device 2 has a fan-out number reading means 6 for reading information about the fan-out number of the net to be estimated.
And the information about the physical size of the target macro cell and determining the difficulty of the adjacent placement of the target macro cell, the physical size reading / determining means 1 of the target macro cell.
0 is connected. The fan-out number reading means 6 and the physical size reading / determining means 10 of the target macro cell are connected to the read information storage means 4 for storing the read information. In addition, the same components as those of the virtual wiring length estimation device 100 described with reference to FIG. 1 are designated by the same reference numerals, and the duplicate description will be omitted.

Next, the operation of the virtual wiring length estimation device 300 will be described. The virtual wiring length estimation apparatus 300 is characterized by changing the virtual wiring length estimation method based on information about the physical size of the target macro cell.

FIG. 12 shows a flowchart for explaining the operation of the virtual wiring length estimation device 300. In FIG.
First, the device user selects a net to be estimated (step ST21). Next, information about the perimeter of the placement area is read from the placement area storage device 1 (step S
T22).

Next, information about the number of fan-outs is read from the connection information storage device 2 (step ST23), and information about the physical size of the target macro cell is read (step ST24).

Next, it is judged whether or not it is difficult to arrange the target macro cells adjacent to each other based on the information on the physical size of the target macro cells (step S25). As an example of the determination criteria, there is an example based on whether the physical size of the target macro cell is larger than the standard cell.
Needless to say, this reference value can be set arbitrarily according to the configuration of the semiconductor integrated circuit.

The reason why such a criterion is adopted will be described below. In order to arrange the target macro cells adjacent to each other in the horizontal direction, it is necessary to secure an area corresponding to the total physical size of the target macro cells in the allocatable area. Since the size of the allocable area is finite, the possibility of securing such an area decreases monotonically with respect to the total physical size of the target macro cell. That is, as the physical size of the target macro cell increases, the possibility that the target macro cells are adjacently arranged decreases.

Therefore, in step ST25, it is determined that the target macro cell having a physical size larger than that of the standard cell is difficult to be adjacently arranged, and that the target macro cell having a physical size equal to or smaller than the standard cell is easily arranged. Become. For comparison between the reference value and the physical size of the target macrocell, the physical size of the target macrocell connected to one estimation target net is determined for each target macrocell, and adjacent placement is possible for each target macrocell. The total size (total area) of the physical sizes of all target macrocells connected to one estimation target net
The possibility of adjacent arrangement may be determined based on the above. By adopting such a method, the time required for estimation can be reduced.

When it is determined in step ST25 that the target macro cells are difficult to be arranged adjacent to each other, step S
At T26, the estimation method for the virtual wiring length of the net between the macro cells in which adjacent placement is difficult is executed.

On the other hand, if it is determined in step ST25 that the target macro cell is not difficult to be placed adjacently, in step ST27, the estimation method for the virtual wiring length of the net between macro cells that is easily placed adjacently is executed.
Then, in step ST28, the estimation result is output.

The method for estimating the virtual wiring length of the net between macro cells whose adjacent placement is difficult and the method for estimating the virtual wiring length of the net between macro cells whose adjacent placement is easy are performed using the equation (6) described in the first embodiment. ) ~
(12) is used.

FIG. 13 shows an example of the configuration of a semiconductor integrated circuit which is a target when the virtual wiring length estimating device 300 is used to estimate the virtual wiring length. In FIG. 13, the nets for which the virtual wiring length is estimated are T5a and T6a,
Macro cells I33a and I34a are connected to the net T5a, and macro cells I35a and I36a are connected to the net T6a.

The macrocells I37a and I38 are connected to the macrocell I33a via the nets S22a and S23a.
a are connected to each other, and the net S2 is connected to the macrocell I34a.
The macro cell I39a is connected via 4a.

The macro cell I35a has a net S2.
The macrocells I40a and I41a are connected via 5a and S26a, respectively, and the macrocell I42a is connected to the macrocell I36a via a net S27a. The nets S22a to S27a are nets other than the virtual wiring length estimation target.

In the semiconductor integrated circuit shown in FIG.
Macro cells I33a and I34 which are target macro cells
The physical size of a is 3 times that of a standard cell. On the other hand, the macro cells I35a and I36a that are the target macro cells
Has the same physical size as the standard cell. Therefore, when the possibility that the target macro cells are adjacently arranged is determined based on the physical size of the target macro cell, the net T5a becomes a net between macro cells that are difficult to be adjacently arranged, and the net T6a.
a is a net between macro cells that can be easily arranged adjacent to each other.

Here, to estimate the virtual wiring length of the net between macro cells which can be easily arranged adjacent to each other, the first embodiment is used.
The equation (5) described in 1) is applied, and the equation (6) described in the first embodiment is applied to the estimation of the virtual wiring length of the net between the macro cells in which adjacent placement is difficult. It is possible to improve the estimation accuracy of the virtual wiring length by correcting the estimation value in the direction in which the virtual wiring length becomes longer as the physical size of the macro cell connected to the estimation target net increases.

FIG. 14 shows an example of a layout and wiring diagram in which the layout and wiring are performed so that the total wiring length in the semiconductor integrated circuit shown in FIG. 13 is minimized. The nets T5b, T shown in FIG.
6b, S22b to S27b, and macro cells I37b to I4.
2b is the net T5a, T6a, S22 shown in FIG.
a to S27a and the macrocells I37a to I42a have the same configuration, and the symbols are simply changed for convenience.

As shown in FIG. 14, the general structure of the semiconductor integrated circuit has a plurality of macrocell stages in which a plurality of macrocells are formed in a row in the left-right direction, and the macrocell stages are arranged in parallel. A wiring step for wiring is provided between them.

In FIG. 14, macro cells I33b and I34b, which are target macro cells, are arranged in macro cell stages MS1 and MS2, respectively, and the net length of net T5b, which is the target net for estimation, is 7 μm.

The other target macro cells, macro cells I35b and I36b, are arranged adjacent to each other in the macro cell stage MS3, and the net T which is the estimation target net.
The wiring length of 6b is the shortest, 2 μm.

According to the third embodiment of the virtual wiring length estimating apparatus of the present invention, the actual wiring length of the net between the macro cells whose adjacent placement is easy and the actual wiring of the net between the macro cells whose adjacent placement is difficult. Considering the difference from the length, it is possible to estimate the virtual wiring length corresponding to each by changing the virtual wiring length estimation method for the net between macro cells where adjacent placement is easy and for the net between macro cells where adjacent placement is difficult. Therefore, it is possible to estimate the virtual wiring length with high accuracy.

<Embodiment 4> FIG. 15 shows a configuration of a virtual wiring length estimating apparatus 400 as Embodiment 4 of the virtual wiring length estimating apparatus according to the present invention. In FIG. 15, the connection information storage device 2 has a fan-out number reading unit 6 for reading information on the fan-out number of the net to be estimated, a pin number reading / determining unit 7 for reading the pin number of the target macro cell, Of the target macrocells, the number-of-nets reading / determining means 8 of the target macrocell that reads information about the number of nets connected to any of the macrocells, and the net that connects the target macrocells to read information about the number of nets that connect the target macrocells The number reading / determining means 9 and the physical size reading / determining means 10 of the target macro cell for reading the information about the physical size of the target macro cell are connected. Then, the fan-out number reading means 6, the pin number reading / judging means 7 of the target macro cell, the net number reading / judging means 8 of the target macro cell, the net number reading / judging means 9 of connecting the target macro cells to each other, and the physical property of the target macro cell The physical size read / determination means 10 is connected to the read information storage means 4 for storing the read information. In addition, the same components as those of the virtual wiring length estimation device 100 described with reference to FIG. 1 are designated by the same reference numerals, and the duplicate description will be omitted.

Virtual wiring length estimating apparatus 400 having such a configuration has all the operations of virtual wiring length estimating apparatuses 100 to 300 described in the first to third embodiments. Therefore, not only is the virtual wiring length estimation method changed based on the number of pins or nets of the target macrocell, but the virtual wiring length estimation method is changed based on the number of nets that connect the target macrocells. It is also possible to estimate the virtual wiring length based on the information about the physical size of the target macro cell, and the number of pins or nets of the target macro cell is different for each estimated net, and Are connected by a plurality of nets, and the virtual wiring length of the semiconductor integrated circuit can be estimated in a composite structure in which the physical size of the target macro cell is different for each estimated net.

<Fifth Preferred Embodiment> FIG. 16 shows a configuration of a virtual wiring length estimating device according to a fifth preferred embodiment of the present invention in which a virtual wiring capacity estimating function for estimating the capacity of a virtual wiring is added.

In FIG. 16, the estimation result output device 12
A virtual wiring capacity estimation means 13 for estimating the charge capacity of the virtual wiring is connected to the output of the. The same components as those of the virtual wiring length estimation device 400 are designated by the same reference numerals, and duplicated description will be omitted.

The virtual wiring capacitance value estimation means 13 multiplies the virtual wiring length estimation value calculated by the virtual wiring length estimation device 400 by the wiring capacitance per unit length to obtain the charge capacity of the virtual wiring length. It is a means of estimating.

With such a structure, the charge capacity of the virtual wiring length can be accurately estimated, and the operating characteristics of the semiconductor integrated circuit can be accurately grasped at the time of designing.

<Sixth Embodiment> FIG. 17 shows, as a sixth embodiment of the virtual wiring length estimating apparatus according to the present invention, a configuration in which a virtual wiring delay time estimating function for estimating a delay time of a virtual wiring is added.

In FIG. 17, the estimation result output device 12
A virtual wiring delay time estimation means 14 for estimating the delay time of the virtual wiring is connected to the output of. The same components as those of the virtual wiring length estimation device 400 are designated by the same reference numerals, and duplicated description will be omitted.

The virtual wiring delay time estimation means 14 multiplies the virtual wiring length estimated value calculated by the virtual wiring length estimation device 400 by the delay time per unit length of the virtual wiring to delay the virtual wiring. It is a means of estimating time.

With such a structure, the delay time in the virtual wiring can be accurately estimated,
It becomes possible to accurately grasp the operating characteristics of the semiconductor integrated circuit at the time of designing.

[0125]

According to the virtual wiring length estimating apparatus of the first aspect of the present invention, it is determined whether or not it is difficult to arrange the first and second target macro cells adjacent to each other. Since the virtual wiring length is calculated by changing the calculation method between the case where the target macro cells are difficult to place adjacent to each other and the case where the first and second target macro cells are easy to place adjacent to each other, the virtual wiring length is calculated. Difference between the virtual wiring length and the actual wiring length of
Also, the difference between the virtual wiring length and the actual wiring length of the net between macro cells, which are difficult to arrange adjacently, is reduced, and the virtual wiring length can be estimated with high accuracy.

According to the virtual wiring length estimating apparatus of the second aspect of the present invention, the data concerning the number of nets connected to the first and second target macro cells is read out and compared with a preset reference value. Then, since the difficulty of the adjacent arrangement of the first and second target macro cells is determined, it is possible to estimate the virtual wiring length according to the actual condition of the semiconductor integrated circuit.

According to the virtual wiring length estimating apparatus of the third aspect of the present invention, there is a possibility that the second target macrocell can be arranged adjacent to the first target macrocell, and the second target macrocell can be arranged adjacent to the second target macrocell. Since the possibility of arranging the first target macro cell is obtained respectively, the net between the first and second target macro cells that is easy to be adjacently arranged, and the first and second target macro cells that are difficult to be adjacently arranged Net, one is easy to place adjacent, the other is difficult to place first,
The nets can be distinguished into three types of nets between the second target macro cells, and the difficulty of adjacent placement can be finely determined, so that the virtual wiring length can be estimated with higher accuracy.

According to the virtual wiring length estimating apparatus of the fourth aspect of the present invention, the first and second targets are compared by comparing the total number of nets connected to the first and second target macrocells with a reference value. Since the difficulty of arranging adjacent macro cells is determined,
It is possible to estimate the execution speed quickly, and it is possible to reduce the time required to estimate the virtual wiring length.

According to the virtual wiring length estimating apparatus of the fifth aspect of the present invention, the data regarding the number of pins of the first and second target macro cells is read out and compared with a preset reference value. Since the difficulty of adjacent placement of the first and second target macrocells is determined, by preparing the number of pins for each type of macrocell as a library in advance, it is possible to estimate the execution speed quickly, and the time required to estimate the virtual wiring length. Can be reduced.

According to the virtual wiring length estimation apparatus of the sixth aspect of the present invention, there is a possibility that the second target macrocell can be arranged adjacent to the first target macrocell, and the second target macrocell can be arranged adjacent to the second target macrocell. Since the possibility of arranging the first target macro cell is obtained respectively, the net between the first and second target macro cells, which is easy to be adjacently arranged, and the first and second target macro cells, which are difficult to be adjacently arranged, Net, one is easy to place adjacent, the other is difficult to place first,
The nets can be distinguished into three types of nets between the second target macro cells, and the difficulty of adjacent placement can be finely determined, so that the virtual wiring length can be estimated with higher accuracy.

According to the virtual wiring length estimation apparatus of the seventh aspect of the present invention, the total number of pins of the first and second target macrocells is compared with the reference value to determine the first and second target macrocells. Since the difficulty of adjacent placement is determined, it is possible to estimate the execution speed at a high speed, and it is possible to reduce the time required to estimate the virtual wiring length.

According to the virtual wiring length estimating apparatus of the eighth aspect of the present invention, the data concerning the number of nets connecting the first and second target macrocells is read out and compared with a preset reference value. Since the difficulty of the adjacent placement of the first and second target macro cells is determined, it is highly likely that the first and second target macro cells will be connected by a net other than the target net and will be placed next to other macro cells with priority. The target macro cell can be identified, and the virtual wiring length can be estimated with high accuracy.

According to the virtual wiring length estimating apparatus of the ninth aspect of the present invention, the data concerning the physical size of the nets connected to the first and second target macro cells is read out and the preset reference value is set. And the difficulty of the adjacent arrangement of the first and second target macro cells is determined by comparing
It is possible to estimate the virtual wiring length according to the actual condition of the semiconductor integrated circuit in which the second target macro cell has many types of physical sizes and the difference in size may be large.

According to the virtual wiring length estimating apparatus of the tenth aspect of the present invention, there is a possibility that the second target macrocell can be arranged adjacent to the first target macrocell, and the second target macrocell can be adjacent to the second target macrocell. Since the possibility of arranging the first target macro cell is obtained respectively, the net between the first and second target macro cells that is easy to be adjacently arranged, and the first and second target macro cells that are difficult to be adjacently arranged Net,
One can easily arrange adjacent nets, and the other can distinguish nets into three types of nets between the first and second target macro cells, which are difficult to be adjacently arranged. Therefore, the difficulty of adjacent arrangement can be determined in detail. It is possible to estimate the virtual wiring length with higher accuracy.

According to the virtual wiring length estimating device of the eleventh aspect of the present invention, the first and second targets are obtained by comparing the total value of the physical sizes of the first and second target macro cells with the reference value. Since the difficulty of arranging adjacent macro cells is determined,
It is possible to estimate the execution speed quickly, and it is possible to reduce the time required to estimate the virtual wiring length.

According to the virtual wiring length estimating device of the twelfth aspect of the present invention, the wiring capacitance of the target net can be estimated with high accuracy by using the virtual wiring length estimation result obtained with high accuracy. Becomes

According to the virtual wiring length estimation device of the thirteenth aspect of the present invention, the delay time of the target net can be estimated with high accuracy by using the virtual wiring length estimation result obtained with high accuracy. Becomes

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a virtual wiring length estimation device according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating the operation of the virtual wiring length estimation apparatus according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a relationship between a target macro cell net and a pin.

FIG. 4 is a diagram showing an example of a configuration of a semiconductor integrated circuit which is a target when a virtual wiring length is estimated.

FIG. 5 is a diagram showing an example of a placement and routing result.

FIG. 6 is a diagram showing a coefficient table when a virtual wiring length is estimated.

FIG. 7 is a block diagram illustrating a configuration of a virtual wiring length estimation device according to a second embodiment of the present invention.

FIG. 8 is a flowchart for explaining the operation of the virtual wiring length estimation device according to the second embodiment of the present invention.

FIG. 9 is a diagram showing an example of a configuration of a semiconductor integrated circuit which is a target when a virtual wiring length is estimated.

FIG. 10 is a diagram showing an example of a placement and routing result.

FIG. 11 is a block diagram illustrating a configuration of a virtual wiring length estimation device according to a third embodiment of the present invention.

FIG. 12 is a flowchart for explaining the operation of the virtual wiring length estimation device according to the third embodiment of the present invention.

FIG. 13 is a diagram showing an example of a configuration of a semiconductor integrated circuit which is a target when a virtual wiring length is estimated.

FIG. 14 is a diagram showing an example of a placement and routing result.

FIG. 15 is a block diagram illustrating a configuration of a virtual wiring length estimation device according to a fourth embodiment of the present invention.

FIG. 16 is a block diagram illustrating a configuration of a virtual wiring length estimation device according to a fifth embodiment of the present invention.

FIG. 17 is a block diagram illustrating a configuration of a sixth embodiment of a virtual wiring length estimation device according to the present invention.

FIG. 18 is a conceptual diagram illustrating a conventional virtual wiring length estimation method.

[Explanation of symbols]

T1a to T6a estimation target net, I1a to I42a
Macro cell, S1a to S27a Net not subject to estimation.

Claims (13)

[Claims] 1. A virtual wiring length estimation device for virtually estimating the wiring length of a net provided between macro cells on the basis of design data required for designing a semiconductor integrated circuit, wherein the virtual wiring length estimation device is a target for estimating the wiring length of the net. A net is a target net, a macro cell connected to the target net among the macro cells is a target macro cell, and the target macro cell includes first and second target macro cells, and the first and second target macro cells are adjacent to each other. Adjacent placement difficulty determination means for determining whether or not placement is difficult according to a predetermined rule, a case where the first and second target macrocells are difficult to place adjacently, and a case where the first and second target macrocells are adjacent to each other A virtual wiring length estimating device, comprising: a virtual wiring length calculating means for calculating a virtual wiring length by changing a calculation method depending on whether the arrangement is easy. 2. The adjacent placement difficulty determination means has net number reading means for reading data related to the number of nets connected to the first and second target macrocells from the design data, and the number of nets is read. 2. The virtual wiring length estimation device according to claim 1, wherein the difficulty of the adjacent arrangement of the first and second target macro cells is determined by comparing the data regarding the above with a preset reference value. 3. The data relating to the number of nets includes first and second data connected to each of the first and second target macrocells.
The possibility of arranging the second target macrocell adjacent to the first target macrocell, which is the second number of nets, is obtained by comparing the first number of nets with the reference value. The possibility of arranging the first target macro cell adjacent to the macro cell is obtained by comparing the second number of nets with the reference value, and based on both results, the first and second target macro cells are arranged adjacent to each other. The virtual wiring length estimation device according to claim 2, wherein the difficulty is determined. 4. The data relating to the number of nets is the total number of the nets connected to the first and second target macrocells, and the first and second nets are obtained by comparing the total number with the reference value. The virtual wiring length estimation device according to claim 2, wherein the difficulty of adjacent placement of the target macro cell is determined. 5. The adjacent placement difficulty determination means has pin number reading means for reading data regarding the number of pins of the first and second target macro cells from the design data, and the data regarding the number of pins. The virtual wiring length estimation device according to claim 1, wherein the difficulty of adjacent placement of the first and second target macrocells is determined by comparing with a preset reference value. 6. The data regarding the number of pins is the first and second pin numbers of each of the first and second target macrocells, and the second data is adjacent to the first target macrocell. The possibility of arranging the target macro cell is obtained by comparing the first number of pins with the reference value, and the possibility of arranging the first target macro cell adjacent to the second target macro cell is determined by the second 6. The virtual wiring length estimation device according to claim 5, wherein the virtual wiring length estimation device is determined by comparing the number of pins and the reference value, and the difficulty of adjacent placement of the first and second target macro cells is determined based on both results. 7. The data regarding the number of pins is the total number of pins of the first and second target macrocells, and the first and second target macrocells are compared by comparing the total number with the reference value. 6. The virtual wiring length estimation device according to claim 5, wherein the difficulty of adjacent placement of the virtual wiring length estimation device is determined. 8. The adjacent placement difficulty determination means has net number reading means for reading data relating to the number of nets connecting the first and second target macrocells from the design data, and the number of nets is read. 2. The virtual wiring length estimation device according to claim 1, wherein the difficulty of the adjacent arrangement of the first and second target macro cells is determined by comparing the data regarding the above with a preset reference value. 9. The adjacent placement difficulty determination means has a physical size reading means for reading data relating to the physical size of the first and second target macro cells from the design data, and the data relating to the physical size. The virtual wiring length estimation device according to claim 1, wherein the difficulty of adjacent placement of the first and second target macrocells is determined by comparing with a preset reference value. 10. The physical size data is:
The first and second target macrocells each have
The possibility of arranging the second target macro cell having the second physical size adjacent to the first target macro cell is obtained by comparing the first physical size with the reference value, The possibility of arranging the first target macro cell adjacent to the target macro cell of (1) is obtained by comparing the second physical size with the reference value, and based on both results, the first and second target macro cells 10. The virtual wiring length estimation device according to claim 9, wherein the difficulty of the adjacent arrangement is determined. 11. The physical size data is:
A total value of physical sizes of the first and second target macrocells, the first and second physical values being obtained by comparing the total value with the reference value.
10. The difficulty of the adjacent arrangement of the target macro cells is determined.
Virtual wiring length estimation device described. 12. The virtual wiring length estimation device according to claim 1, further comprising a virtual wiring capacity estimation means for estimating a wiring capacity of the target net from the calculated virtual wiring length and a wiring capacity per unit length. . 13. The virtual wiring delay time estimating means for estimating the delay time of the target net from the calculated virtual wiring length and the delay time per unit length of the virtual wiring. Wiring length estimation device.