JPH08153799A - Anti-fuse type semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To flatten the surface of a lower layer electrode and to reduce the irregularity of a dielectric breakdown voltage by forming the electrode of a conductive material having an amorphous structure. CONSTITUTION: A lower layer electrode BF is formed of conductive material having amorphous structure. A conductive film for a plurality of lower layer wirings 3 is deposited (a lower layer electrode BF is also deposited) on an interlayer insulating film 2, and patterned. The wirings 3 including the electrode BF is covered together with a substrate 1 with an interlayer insulating film 4, and connecting holes 5 of an anti-fuse element are opened at a plurality of positions. The surface of the electrode BF in the hole 5 is wet treated, a sharp nitride protrusion or a contamination is removed, and an amorphous structure is held. An insulating film AF for the anti-fuse is formed to cover the electrode BF and the insulator 4. An upper layer wiring 6 is deposited to cover the film AF for the anti-fuse, and patterned. A final protective film 9 is deposited to cover the wiring 6 and the film 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an anti-fuse type semiconductor integrated circuit device, and more particularly to an anti-fuse type semiconductor used for a field programmable gate array (hereinafter referred to as FPGA), a programmable read only memory (hereinafter referred to as PROM), and the like. The present invention relates to an integrated circuit device.

[0002]

2. Description of the Related Art Among gate arrays, some semiconductor integrated circuit devices having a user programmable FPGA, PROM or the like in the field have an antifuse element. The antifuse element is, for example, an IEEE Electro
n Device Letter Vol 12 No4 April (1991) pp151-153
(Reference 1), IEEE Electron Device Letter Vol 13 No9
September (1992) pp488-490 (reference 2), IEEE IEDM Te
ch.Dig. (1993) pp31-34 (Reference 3), IEEE Electron Devi
ces Vol 41 No5 May (1994) pp721-725 (Reference 4), a connecting element in which a lower layer electrode, an anti-fuse insulating film and an upper layer electrode are formed in a layered structure in a region of a contact hole. is there. In the present invention, a semiconductor integrated circuit device having a plurality of such antifuse elements is called an antifuse type semiconductor integrated circuit device. In the present invention, unless otherwise specified, the terms lower layer electrode and upper layer electrode respectively form an interface with the antifuse insulating film immediately below and immediately above the constituent element of the antifuse element, that is, above the antifuse insulating film. It means a conductive material. The lower-layer electrode has a lower-layer wiring (also referred to as a first wiring) disposed below the interlayer insulating film, and the upper-layer electrode has an upper-layer wiring (also referred to as a second wiring) disposed above the interlayer insulating film. It is connected. The "electrode" may be provided separately or a part of the "wiring" may be provided for this. Of course, in the antifuse-type semiconductor integrated circuit device, the lower layer wiring and the upper layer wiring are electrically connected to each other directly or through the conductive plug without interposing the insulating film for the antifuse. Some also have multiple).

When programming, a pair of upper layer wiring and lower layer wiring is arbitrarily selected from a plurality of pairs, and a relatively high voltage is applied between the upper and lower electrodes of the anti-fuse element connecting the pair of upper and lower wirings. By doing so, the insulation of the anti-fuse insulating film is destroyed (this programming measure is called "writing"). A conductive path (filament) that electrically connects the lower layer electrode and the upper layer electrode is formed in the destroyed portion.

[0004]

However, the present inventors have found that the conventional anti-fuse type semiconductor integrated circuit device has the following problems. First, TiN having a function as a barrier metal is used for the lower layer electrode of the anti-fuse element described in the above document. However, TiN is formed in a columnar crystal structure having sharp protrusions, and irregularities are formed on the surface of the lower layer electrode according to the shape of the crystal grains formed of TiN. Since the anti-fuse insulating film is formed on this lower layer electrode with an extremely thin film thickness of about several tens of nm, the anti-fuse insulating film formed on the sharply shaped surface of the lower layer electrode is locally formed. A high breakdown voltage is applied. That is, even if an extremely low voltage is applied to a portion having sharp surface irregularities, dielectric breakdown occurs, so that the variation in the dielectric breakdown voltage of the anti-fuse element becomes extremely large. Further, since the variation in the breakdown voltage is large, the variation in the ON resistance is also large. The reason for this will be described below. It is assumed that the same voltage is applied to many anti-fuse elements for 100ms. Due to the effect of surface irregularities, some anti-fuse elements have dielectric breakdown in 0.1 ms, and some anti-fuse elements have 50 ms.
Suppose that the insulation breakdown occurred. In the former case, when the current is applied for 99.9 ms after that, the filament serving as a conduction path grows large and the ON resistance is greatly decreased, but in the latter case, the ON resistance is not sufficiently decreased because the current is applied for about 50 ms. Therefore,
It is considered that the variation in the ON resistance also increases due to the large variation in the dielectric breakdown voltage. This variation is due to the circuit
This affects variations in wiring delay in the wiring that connects the elements. In particular, the FPGA affects the operating frequency. Further, in the PROM, it causes variation in data reading speed.

If TiN is present in the base and silicon nitride, silicon oxide or tantalum oxide is used for the anti-fuse insulating film, a non-uniform reduction reaction occurs with TiN and the anti-fuse insulating film is locally formed. In the case of a lower layer wiring in which a thin film is likely to occur and a barrier metal is laid on the substrate and an Al wiring is formed thereon, the flatness of the lower layer electrode is deteriorated due to the orientation of Al and the antifuse insulating film The film thickness is likely to be uneven. In these cases as well, the dielectric breakdown voltage varies in the same manner as described above, and as a result, the ON resistance varies.

Secondly, among the antifuse elements, those of the group in which the antifuse insulating film is broken are those of the group in which the lower layer electrode and the upper layer electrode are electrically connected securely and conversely are not broken. The insulation must be reliable. However, since a sharp projection is generated on the surface of the lower layer electrode as described above, it is necessary to make the anti-fuse insulating film a thick film with a margin in mind in order to ensure insulation separation. On the other hand, the upper limit of the write voltage depends on the maximum allowable voltage of the MOS transistor used. For example, a MOS transistor having a power supply voltage of 5 V and a gate length of 0.8 μm has a maximum allowable voltage of about 12 V, and a MOS transistor having a power supply voltage of 5 V and a gate length of 0.5 μm has a maximum allowable voltage of about 10 V. Therefore, the write voltage is preferably 12 V or less in the former case and 10 V or less in the latter case. In the case of SiN film, the film thickness required for reliable breakdown below this voltage is about 13 nm or less and about 10 nm or less, respectively. Therefore, it is necessary that the film thickness is at least lower than this upper limit. At the time of writing, there are an anti-fuse element that is written and an anti-fuse element that is not written, but in general, a voltage that is about half the write voltage is applied to the anti-fuse element that is not written. When writing, a voltage of about 5 V is applied to the anti-fuse element which is not written. If a high voltage is locally applied due to unevenness on the surface of the lower electrode, an antifuse that should not be written may be written. That is, the applied voltage required to reach the dielectric breakdown may change greatly due to the unevenness of the surface, and may be distributed from a maximum of 10 V to a minimum of 5 V or less. Then, it becomes difficult to use this element as an anti-fuse element. In particular,
When lowering the operating voltage from 5V to 3.3V, it is necessary to further reduce the write voltage from 10V to 7V or less. In this case, it is necessary to reduce the thickness of the insulating film in order to reduce the maximum breakdown voltage, but if this is done, the effect of surface irregularities will become even greater, and writing will be possible even when an extremely low voltage is applied. Occur. Therefore, the deterioration of the insulating property of the insulating film due to the unevenness of the surface becomes a major obstacle in lowering the voltage of the antifuse-type semiconductor integrated circuit. Therefore, it is indispensable to suppress the unevenness of the surface and reduce the variation of the dielectric breakdown voltage.

Thirdly, in the antifuse element,
A compound is generated by a thermal reaction due to Joule heat generated when the anti-fuse insulating film is destroyed, and this compound forms a conduction path. Lower layer electrode and upper layer electrode are both A
When 1 is the main component, the compound forming the conduction path is also formed with Al as the main component, and the electromigration (EM) resistance deteriorates in the conduction path. Therefore, if an operating voltage is applied to the conductive path for a long time, the probability that the conductive path will be disconnected by EM increases.
Reliability of the antifuse-type semiconductor integrated circuit device for long-term operation is reduced.

The present invention has been made in order to solve the above problems. First, the surface of the lower layer electrode is flattened,
Minimize the variation of dielectric breakdown voltage. This reduces variations in the ON resistance of the conduction path. Further, the ON resistance of the conduction path is reduced as much as possible by combining the upper and lower electrode materials in the anti-fuse element.
This aims to provide an anti-fuse type semiconductor integrated circuit device which improves the reliability of circuit operation and realizes high-speed circuit operation. Secondly, by reducing the variation of the dielectric breakdown voltage, Avoid accidental conduction of antifuse elements to be insulated. Accordingly, it is an object of the present invention to provide an antifuse-type semiconductor integrated circuit device that is highly reliable even when the write voltage is lowered in response to the decrease in the operating voltage of the element. Thirdly, the long-term reliability of the conductive path is increased. Secure. An electrically connected anti-fuse element may be disconnected in the actual operating state of the element. It is an object of the present invention to provide a highly reliable anti-fuse type semiconductor integrated circuit device in which disconnection is unlikely to occur due to a material forming a conduction path or programming polarity.

[0009]

In order to achieve the above object, the present invention comprises the following first to seventh inventions. First, the first invention relates to claims 1 to 5, and
The described one is an anti-fuse type semiconductor integrated circuit device in which the lower layer electrode is made of a conductive material having an amorphous structure.

A second aspect of the present invention is the antifuse-type semiconductor integrated circuit device according to the first aspect, wherein the upper electrode is made of a conductive material having an amorphous structure. According to a third aspect of the present invention, the conductive material having an amorphous structure is an element or compound shown in any of the following (1) to (10). It is a fuse type semiconductor integrated circuit device. (1) First element group (Co, Ni, Cu, Ti, Z
r, Nb, Mo, Hf, Ta, W) A compound composed of two or more elements selected from the group consisting of: (2) an element of the first element group or a compound consisting of two or more kinds selected from these, and a second element group (S
i, B, N, C, Ge, As, P, Sb) and a compound formed with one or more elements. (3) A compound (Y-La) of an element of the third element group (Y, La). (4) A compound formed of Al and an element of the first element group or a compound of two or more kinds selected from these. (5) A compound formed by an element of the third element group or a compound thereof and Al. (6) A compound formed by an element of the first element group or a compound consisting of two or more kinds selected from these, an element of the third element group, and Al. (7) A compound formed by an element of the fourth element group (Au, Pt, Pd, Ag) and an element of the second element group or a compound consisting of two or more kinds selected from these. (8) An element of the first element group or a compound consisting of two or more kinds selected from these elements, and a fourth element group (A
u, Pt, Pd, Ag) and the compound formed. (9) A compound formed by an element of the third element group or a compound thereof and an element of the fourth element group. (10) A compound formed by an element of the first element group or a compound consisting of two or more kinds selected from these, an element of the third element group, and an element of the fourth element group.

According to a fourth aspect of the present invention, among the conductive materials having an amorphous structure, the composition ratio of the metal in the compound formed of the metal element and the non-metal element is higher than the stoichiometric composition. The antifuse-type semiconductor integrated circuit device according to claim 3. According to a fifth aspect of the present invention, the conduction path includes W, Ta, Nb and Mo of the lower layer electrode and the upper layer electrode.
Is formed by applying a breakdown voltage with the one containing at least one of the above as the lower potential side, and contains at least one of W, Ta, Nb and Mo transferred from the electrode on the lower potential side. The antifuse-type semiconductor integrated circuit device according to claim 3.

Next, a second aspect of the present invention relates to claims 6 to 14, wherein the lower electrode is composed of a metal silicide in which the metal composition ratio is larger than the stoichiometric composition. An anti-fuse type semiconductor integrated circuit device characterized by: According to claim 7, the metal silicide is
7. The antifuse-type semiconductor integrated circuit device according to claim 6, wherein the metal film is silicided in a temperature range of 400 to 700 ° C. after formation.

According to the eighth aspect, the metal in the metal silicide is Ti, Ta, Nb, Zr, Y, Hf, A.
The antifuse-type semiconductor integrated circuit device according to claim 6 or 7, wherein the antifuse-type semiconductor integrated circuit device is any one of 1, W, Mo, V, Co, Ni, Pd, and Pt. A ninth aspect of the present invention is the antifuse-type semiconductor integrated circuit device according to the seventh aspect, wherein the crystal grain size of the metal silicide is 20 nm or less.

A tenth aspect of the present invention is the antifuse-type semiconductor integrated circuit device according to the seventh aspect, characterized in that the center line average roughness value Ra of the surface of the metal silicide is 2.0 nm or less. According to claim 11, in the surface of the metal silicide, the solid angle of the protrusion in the crystal grain having a size in the range of 1 nm to 1 μm is 1.8π to 2.
The antifuse-type semiconductor integrated circuit device according to claim 7, wherein the antifuse-type semiconductor integrated circuit device is in the range of 0π.

According to a twelfth aspect of the present invention, the upper electrode is made of Ti.
7. The antifuse-type semiconductor integrated circuit device according to claim 6, wherein the composition ratio of titanium silicide is 40% or more. A thirteenth aspect of the present invention is the antifuse-type semiconductor integrated circuit device according to the sixth aspect, wherein the upper layer electrode is made of titanium nitride having a Ti composition ratio of 55% or more.

According to a fourteenth aspect of the present invention, the conductive path is formed by applying a breakdown voltage with the lower layer electrode on the lower potential side, and contains a metal transferred from the metal silicide of the lower layer electrode. 7. The antifuse-type semiconductor integrated circuit device according to claim 6. And a third invention relates to claims 15 to 34, wherein the lower layer electrode is made of a conductive material containing a refractory metal,
The antifuse-type semiconductor integrated circuit device is characterized in that the upper layer electrode is made of a low melting point metal having a resistance value smaller than that of the high melting point metal.

According to claim 16, the low melting point metal is A
16. The antifuse-type semiconductor integrated circuit device according to claim 15, wherein the antifuse-type semiconductor integrated circuit device is one of Al, Al alloy, Cu, and Ag. According to claim 17, the Al alloy is S
17. The antifuse-type semiconductor integrated circuit device according to claim 16, comprising at least one selected from i, Cu, Sc, Pd, Ti, Ta and Nb.

According to the eighteenth aspect, the conductive material containing the refractory metal is Ti, Zr, Hf, V, Nb, Ta or M.
17. The antifuse-type semiconductor integrated circuit device according to claim 15 or 16, characterized in that one component selected from o and W is a constituent element. According to claim 19, the conductive material containing a refractory metal is Ti, Zr, Hf, V, Nb, T.
19. The anti-fuse type semiconductor integrated circuit device according to claim 18, which is a silicide formed of one kind selected from a, Mo and W and Si.

According to a twentieth aspect of the present invention, the main component of the conduction path is Al, Ti, Zr, Hf, V, Nb, Ta,
17. The antifuse-type semiconductor integrated circuit device according to claim 15 or 16, which is an Al compound of one element selected from Mo and W. According to claim 21,
Al compound is TiAl ₃ , ZrAl ₃ , HfAl ₃ ,
VAl ₃ , NbAl ₃ , TaAl ₃ , MoAl ₁₂ , WA
21. The anti-fuse type semiconductor integrated circuit device according to claim 20, which is one of the L ₁₂ .

A twenty-second aspect of the present invention is the anti-fuse type semiconductor integrated circuit device according to the eighteenth aspect, wherein the lower layer electrode has an amorphous structure or a crystal structure with a crystal grain size of 20 nm or less. The invention according to claim 23 is characterized in that a diffusion prevention film for preventing diffusion of the low melting point metal is interposed between the upper electrode and the wiring formed on the upper electrode. The antifuse-type semiconductor integrated circuit device according to any one of 1.

According to a twenty-fourth aspect, the diffusion preventive film is T
24. The anti-fuse type according to claim 23, which is composed of one element selected from i, Ta, Zr, Hf, V, Nb, Mo, W and Pt, a nitride or silicide of the element, or TiW. It is a semiconductor integrated circuit device. According to claim 25, the film thickness of the upper layer electrode exceeds the film thickness of the anti-fuse insulating film, and is less than the film thickness of the wiring formed on the upper layer electrode and electrically connected to the upper layer electrode, or 25. The anti-fuse type semiconductor integrated circuit device according to claim 15, 16, 23 or 24, characterized in that the diameter is not more than 1/2 of the effective opening diameter of the fuse connecting hole.

According to a twenty-sixth aspect of the present invention, the conduction path is formed by applying a breakdown voltage with the upper layer electrode on the lower potential side, and contains a low melting point metal transferred from the upper layer electrode. 16. The antifuse-type semiconductor integrated circuit device according to claim 15. According to a twenty-seventh aspect of the present invention, in the antifuse-type semiconductor integrated circuit device according to the twenty-sixth aspect, the conductive path also includes a refractory metal transferred from the upper layer electrode.

According to a twenty-eighth aspect of the present invention, the conducting path is formed by applying a breakdown voltage with the lower layer electrode on the lower potential side, and contains a refractory metal transferred from the lower layer electrode. 16. The antifuse-type semiconductor integrated circuit device according to claim 15. According to claim 29, the conduction path is formed by applying a voltage between the upper and lower electrodes to cause a dielectric breakdown of the insulating film for the anti-fuse and immediately after that, a current larger than 5 mA is applied to the breakdown portion. 16. The antifuse-type semiconductor integrated circuit device according to claim 15.

The thirtieth aspect of the present invention is the antifuse-type semiconductor integrated circuit device according to the twenty-ninth aspect, wherein the voltage and the current are applied with the lower layer electrode on the lower potential side. According to a thirty-first aspect of the present invention, the antifuse-type semiconductor integrated circuit device according to the twenty-ninth aspect is characterized in that the application of the electric current is performed a plurality of times.

The thirty-second aspect of the present invention is the anti-fuse type semiconductor integrated circuit device according to the twenty-second aspect, wherein the lower layer electrode is arranged immediately above the conductive layer containing a low melting point metal. According to claim 33, the lower electrode has a film thickness of 50.
33. The antifuse-type semiconductor integrated circuit device according to claim 32, characterized in that

According to a thirty-fourth aspect of the present invention, the conduction path is formed by applying a breakdown voltage with the lower layer electrode on the lower potential side, and the high melting point metal transferred from the lower layer electrode and directly under the lower layer electrode. 34. The anti-fuse type semiconductor integrated circuit device according to claim 32 or 33, further comprising a low melting point metal transferred from the conductive layer of. The fourth invention is
According to Claims 35 and 36, wherein the interface between the antifuse insulating film and the lower electrode is an oxide or a nitride present on the lower electrode surface before the insulating film is formed in the connection hole. This is the lower interface of a new oxide film that is formed uniformly on the front surface of the removal while removing the lower layer electrode in the depth direction. 16. The antifuse-type semiconductor integrated circuit device according to claim 1, 6 or 15, further comprising an insulating film further formed.

According to claim 36, the new oxide film is
36. The antifuse-type semiconductor integrated circuit device according to claim 35, which is formed by a wet treatment using an ammoniacal hydrogen peroxide solution. A fifth invention relates to claims 37 to 39, wherein the lower electrode and the upper electrode are made of a conductive material containing Al, and the antifuse insulating film is a silicon nitride film. The antifuse-type semiconductor integrated circuit device according to claim 1, wherein

According to a thirty-eighth aspect of the present invention, the upper layer wiring related to the antifuse element and the upper layer wiring related to the via are isolated from the region of the via connection hole in which the antifuse element is temporarily arranged and the upper layer electrode and the antifuse insulation. It is formed at the same time in a via forming step of removing the film and then forming a via therethrough, and is characterized by comprising a laminated film of a conductive layer containing a refractory metal and a conductive layer containing Al immediately above the conductive layer. Claim
37 is an anti-fuse type semiconductor integrated circuit device.

According to a thirty-ninth aspect, the conductive layer containing a refractory metal is titanium nitride, TiW, tantalum nitride, TaW.
Of the single layer film, or the single layer film and the Ti layer immediately below
39. The antifuse-type semiconductor integrated circuit according to claim 38, wherein the film thickness of the upper layer electrode formed of a laminated film with the film and filling the space between the conductive layer and the antifuse insulating film is 50 nm or more. It is a device.

The sixth invention relates to claims 40 to 41, and in the claim 40, the lower wiring is composed of an Al alloy film having a titanium nitride film on the uppermost layer, and the lower electrode is An Al alloy film in which the titanium nitride film of the lower wiring uppermost layer is removed in the depth direction at the bottom of the contact hole to expose it, and the anti-fuse insulating film is a silicon oxide film, a silicon nitride film or a tantalum oxide film, Alternatively, an antifuse-type semiconductor integrated circuit device, which is a composite film of these, wherein the upper electrode is a contact portion of an upper wiring having at least the lowermost layer of an Al alloy film to the antifuse insulating film.

The invention according to claim 41 is characterized in that a contact prevention insulating film for preventing contact between these films is provided between the sidewall of the titanium nitride film appearing in the connection hole and the insulating film for the anti-fuse. The antifuse-type semiconductor integrated circuit device according to claim 40. A seventh invention is the invention according to claim 42.
The lower-layer electrode is a contact portion of the lower-layer wiring composed of a single layer film of Al or Al alloy with the anti-fuse insulating film, and the anti-fuse insulating film is a silicon oxide film or a silicon nitride film. Alternatively, it is made of a tantalum oxide film or a composite film thereof, and the upper electrode is made of Al or A.
l alloy and the lower layer wiring is located directly above the insulating film formed to cover the substrate, and a barrier metal composite film formed in contact with the substrate in a connection hole penetrating the insulating film is interposed. The antifuse-type semiconductor integrated circuit device is characterized in that it is electrically connected to a substrate.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first invention is an anti-fuse type semiconductor integrated circuit device in which a lower electrode is made of a conductive material having an amorphous structure. At this time, the upper electrode is also preferably made of a conductive material having an amorphous structure. Further, as the conductive material having the amorphous structure, it is preferable to adopt the element or compound shown in any one of the following (1) to (10) because it is likely to have the amorphous structure. (1) First element group (Co, Ni, Cu, Ti, Z
r, Nb, Mo, Hf, Ta, W) A compound composed of two or more elements selected from the group consisting of: (2) an element of the first element group or a compound consisting of two or more kinds selected from these, and a second element group (S
i, B, N, C, Ge, As, P, Sb) and a compound formed with one or more elements. (3) A compound (Y-La) of an element of the third element group (Y, La). (4) A compound formed of Al and an element of the first element group or a compound of two or more kinds selected from these. (5) A compound formed by an element of the third element group or a compound thereof and Al. (6) A compound formed by an element of the first element group or a compound consisting of two or more kinds selected from these, an element of the third element group, and Al. (7) A compound formed by an element of the fourth element group (Au, Pt, Pd, Ag) and an element of the second element group or a compound consisting of two or more kinds selected from these. (8) An element of the first element group or a compound consisting of two or more kinds selected from these elements, and a fourth element group (A
u, Pt, Pd, Ag) and the compound formed. (9) A compound formed by an element of the third element group or a compound thereof and an element of the fourth element group. (10) A compound formed by an element of the first element group or a compound consisting of two or more kinds selected from these, an element of the third element group, and an element of the fourth element group.

In the antifuse-type semiconductor integrated circuit device having such a structure, since the crystal grain boundaries are eliminated from the surface of the lower layer electrode, the sharp shape resulting from the grain boundary is relaxed and the flattening is promoted. Therefore, the film thickness of the anti-fuse insulating film based on it becomes uniform, and the film quality becomes good with a low defect density. Therefore, the variation in the formation of the conduction path locally (the cross-sectional area of the conduction path). , Variations in conductor component concentration, local breakdown density, etc.), the ON resistance of the anti-fuse element varies less. In addition, the antifuse insulating film is less likely to be locally destroyed, so that the cross-sectional area of the conductive path is increased and the absolute value of the ON resistance is also reduced. At the same time, even if the thickness of the anti-fuse insulating film is reduced, the insulation separation can be surely performed, so that the breakdown voltage can be set low.

Further, in the first invention, the composition ratio of the metal in the compound formed of the metal element and the non-metal element in the amorphous conductive material used for the electrode is more than the stoichiometric composition. Characterized by being large. In the process of forming the conduction path, the metal element diffuses from the lower or upper layer electrode into the anti-fuse insulating film, and the Joule heat at the time of dielectric breakdown forms a crystalline compound there. The metal compound (compound formed by the metal element and the non-metal element) forming the lower or upper electrode, which is the source of the metal element, is metal-rich (the metal composition ratio is larger than the stoichiometric composition). By keeping the composition
This process is accelerated, and the cross-sectional area of the completed conducting path is increased. Therefore, the antifuse element is turned on.
The resistance becomes even smaller.

Further, in the present invention, the conduction path is formed by applying a breakdown voltage in which the lower layer electrode or the upper layer electrode containing at least one of W, Ta, Nb and Mo is set to the lower potential side. It is characterized in that it contains at least one of W, Ta, Nb, and Mo transferred from the electrode on the low potential side. As a result, during programming, a substance having excellent EM resistance of the low-potential side electrode is efficiently transferred into the conductive path due to a large amount of electron flow toward the high-potential side electrode at the same time as dielectric breakdown, and the programming time can be shortened. Then, as a result of including one kind of material (W, Ta, Nb, Mo) having excellent EM resistance in the conductive path, the conductive path itself has EM resistance, and the connection state of the anti-fuse element is maintained for a long time. Note that W, WSix, and WNx, which have a small specific resistance and are hard to be deteriorated, are particularly preferable as the substance which the conductive path should have excellent EM resistance.

Next, a second invention is an anti-fuse type semiconductor integrated circuit device characterized in that the lower layer electrode is made of metal silicide in which the composition ratio of the metal is larger than the stoichiometric composition. This metal silicide is preferably silicided in the temperature range of 400 to 700 ° C. after the formation of the metal film, and the metal in the metal silicide is Ti, Ta, Nb, Zr, Y, Hf, Al. ，
It is preferably any one of W, Mo, V, Co, Ni, Pd, and Pt.

As a result, the metal silicide employed in the lower layer electrode forms a stone wall crystal structure in which the crystal orientation is random, and the smoothing of the lower layer electrode surface is promoted. Therefore, for the same reason as described above, it is possible to reduce the variation in the ON resistance of the antifuse element and the absolute value of the ON resistance, and it is also possible to reduce the breakdown voltage. Further, since the metal silicide of the lower layer electrode, which is a metal supply source to the conduction path, has a metal-rich composition, the conduction path has a metal (Ti,
(W, etc.) will be included in a large amount, and the resistance will decrease.
Moreover, since refractory metals such as Ti and W have a small self-diffusion coefficient, the EM resistance of the conductive path is also improved.

Particularly in the case of titanium silicide, when silicide is formed at 700 ° C. or lower, since the diffusion rate of both Ti and Si is small, the crystal growth rate is suppressed and a silicide having a fine crystal grain structure or an amorphous structure is obtained. . With regard to the microstructure or surface properties, suitable indices for forming a base of the anti-fuse insulating film are that the crystal grain size of the metal silicide is 20 nm or less, and the center line average roughness value Ra of the surface of the metal silicide is 2 or less. 0.0 nm or less, or 1 nm to 1 on the surface of the metal silicide
The solid angle of the protrusions in the crystal grains having a size in the range of μm is in the range of 1.8π to 2.0π.
Further, the titanium silicide silicided at 700 ° C. or lower has a Ti composition ratio in the metastable state higher than the stoichiometric composition ratio (metal rich). That is, in the case of titanium silicide, by only defining the silicidation temperature to be 700 ° C. or lower, which is lower than the crystallization temperature, it is possible to obtain a very remarkable effect that the surface is flattened and the metal is rich. In addition, the basic principle of the second invention is not limited to titanium silicide, but Ta,
Nb, Zr, Y, Hf, Al, W, Mo, V, Co, N
It is common to all metals i, Pd, and Pt.

In the case of titanium silicide, 400 ° C.
If the silicidation is less than less than 3, the composition ratio of Ti will continue to increase, for example, exceeding 3 times the composition ratio of Si, and the columnar crystal structure of Ti will be predominant, so that the surface has a sharp shape. It becomes impossible to secure the flatness. This is also an action common to Ta to Pt described above. Second
In the invention described above, it is more preferable that the upper electrode is formed of titanium silicide having a Ti composition ratio of 40% or more, or titanium nitride having a Ti composition ratio of 55% or more.
By doing so, the proportion of Ti present in the conducting path is further increased.

In the second invention, the conduction path is
It is formed by applying a breakdown voltage with the lower electrode on the lower potential side.
And transferred from the metal silicide of the lower electrode
It is even more preferred to include the metals mentioned. In this case
Also has the same effect as when the lower electrode has an amorphous structure.
As a result, the EM resistance of the conductive path is improved. Next, the third invention
Is a lower electrode made of a conductive material containing a refractory metal,
Low melting point metal whose upper electrode has smaller resistance than high melting point metal
Antifuse type semiconductor integrated device characterized by comprising
It is a circuit device. This low melting point metal is Al, Al alloy,
One of Cu and Ag is preferable, and
Whether the alloy is Si, Cu, Sc, Pd, Ti, Ta, Nb
More preferably, at least one selected from the above is included. Soshi
The refractory metal contained in the conductive material of the lower electrode is Ti, Z
It is preferable to choose from r, Hf, V, Nb, Ta, Mo, W
Furthermore, the substance as the material is
It should be a silicide formed of one of the genus and Si.
Even more preferable. The main component of the conduction path is Al,
Is selected from Ti, Zr, Hf, V, Nb, Ta, Mo, W
It is preferable that it is an Al compound of one kind of element,
This Al compound is TiAl₃, ZrAl₃, HfAl
₃, VAl₃, NbAl ₃, TaAl₃, MoAl₁₂,
WAl₁₂It is even more preferred to be one of the above.

By constructing the antifuse-type semiconductor integrated circuit device in this manner, a conductive material containing a low-resistance low-melting point metal (such as Al) is provided directly above the antifuse insulating film, and excellent EM resistance is provided immediately below. An anti-fuse element having a conductive material containing a high melting point metal can be realized, and the conduction path is a compound containing a low melting point metal taken in from the upper layer electrode side and a high melting point metal taken in simultaneously from the lower layer electrode side. It is formed. Therefore, the resistance of the conductive path itself is reduced and the EM resistance is also improved.

The process of forming the conductive path is as follows: dielectric breakdown of the anti-fuse insulating film → current penetration → migration of the high melting point metal of the lower layer electrode (by EM) / melting of the low melting point metal of the upper layer electrode (by Joule heat) → The contact between the low-melting point metal and the high-melting point metal → the formation of the intermediate melting point compound, and this intermediate melting point compound becomes an element constituting the conduction path. As the low melting point metal for the upper electrode (or the lowermost layer), Al (melting point 660 ° C, resistance 2.83 μΩ · cm) with the smallest resistance value is optimal,
Other than this, the melting point is somewhat high, but Cu (melting point 1080 ° C), Ag
(Melting point 960.5 ° C) can be used, and in addition to Al, Cu, Ag, those with melting points similar to or lower than these (for example, NiSi (melting point about 1000 ° C)), low melting point metal and high melting point can be used. A compound with a metal (for example, Al-Ti) can also be used.

As the refractory metal for the lower layer electrode (or the uppermost layer thereof), Ti, Zr, Hf, V, Nb, Ta and M are used.
o, W (the lowest melting point of Ti is 1680 ° C) is preferable, and among them, Ti, Zr, Nb, Ta, Mo, which have excellent EM resistance,
W is more preferable, and these nitrides or silicides (TiSi having the lowest melting point of about 10
1550 ℃) can also be used. However, in order to maintain the film quality of the antifuse insulating film in a good state, it is desirable to use a conductive material that is easy to smooth the surface as a base immediately below.
Regarding the smoothing of the underlayer, in the third invention as well, as in the first or second invention, it is particularly preferable that the lower electrode has an amorphous structure or a crystal structure with a crystal grain size of 20 nm or less.

Further, in the third invention, a diffusion prevention film for preventing diffusion of the low melting point metal is interposed between the upper layer electrode formed of the low melting point metal and the wiring formed on the upper layer electrode. It is preferable that the diffusion preventive film is made of Ti, T
It is even more preferable to be composed of one element selected from a, Zr, Hf, V, Nb, Mo, W and Pt, a nitride or silicide of the element, or TiW. This is because, especially in writing with the upper layer electrode at a high potential, it not only prevents diffusion of the refractory metal melted by Joule heat to the upper layer wiring side, but also penetrates into the antifuse insulating film side. This is because it produces the effect of promoting

In the third invention, further, the film thickness of the upper layer electrode exceeds the film thickness of the anti-fuse insulating film, and the film thickness of the wiring formed on the upper layer electrode and electrically connected to the upper layer electrode. Or less than 1/2 of the effective opening diameter of the anti-fuse connecting hole. As a result, the undulations of the upper layer wiring connected to the upper portion of the antifuse element can be relaxed (the shape in which the upper layer wiring is depressed inside the connection hole forming the antifuse element can be relaxed), and the step coverage of the step portion of the upper layer wiring can be improved. Therefore, when patterning the upper wiring by lithography and etching,
The film thickness of the etching mask is made uniform, and the processing accuracy of the etching mask itself, and thus the wiring patterning accuracy is improved. At the same time, it is possible to prevent the formation of voids between the upper layer wiring and the upper layer electrode or between the upper layer electrode and the anti-fuse insulating film, so that the defective connection of the conductive path is eliminated, and the reliability is improved.

Further, in the third invention, the conduction path is
It is formed by applying a breakdown voltage with the upper layer electrode at the lower potential side, and is characterized by containing a low melting point metal transferred from the upper layer electrode, and the conduction path has a high melting point transferred from the upper layer electrode. It is also preferable to include a metal. Further, if necessary, the conductive path may be formed by applying a breakdown voltage with the lower layer electrode on the lower potential side, and may include a high melting point metal transferred from the lower layer electrode. As a result, the low-melting-point metal is smoothly introduced to the dielectric breakdown point, becomes a semi-molten state, becomes extremely hard to break, and becomes a low-resistance single-crystal state, and the high-melting-point metal from the lower electrode also coexists there. The subsequent conductive path itself can have low resistance and excellent EM resistance. The basic idea of the process of forming the conductive path is as described in the second invention or the third invention.

Further, in the third invention, the conduction path is
It is characterized in that it is formed by applying a voltage between the upper layer electrode and the lower layer electrode to cause a dielectric breakdown of the anti-fuse insulating film, and then applying a current larger than 5 mA to the dielectric breakdown portion. This current is called a write current, and is usually applied as a pulse, so it is also called a write pulse. This voltage and current application is preferably performed with the lower layer electrode on the low potential side. Further, it is preferable that the current is applied by applying the write pulse a plurality of times.

The reason for this will be described below. In a conventional antifuse element (for example, a structure whose structure is TiW / α-Si / TiW from the lower layer) that uses an amorphous silicon (abbreviated as α-Si) film as an insulating film for antifuses, When a current larger than the write current flows, a phenomenon (referred to as a switch-off phenomenon) in which a conductive path (filament) once formed is disconnected may occur. Since such an excessive current during the operation of the anti-fuse type semiconductor integrated circuit device cannot be completely prevented, an anti-fuse element which does not cause a switch-off phenomenon even if such an unexpected situation is encountered must be mounted. Therefore, the antifuse-type semiconductor integrated circuit device cannot be said to have sufficient reliability.
In the past, a sacrifice was made to reduce the design margin in order to prevent this.

On the other hand, in the antifuse-type semiconductor integrated circuit device according to the fifteenth aspect, the intermediate melting point compound forming the conduction path has a write current if the current value is appropriately set at the time of writing. Even if a larger current flows through it again, there is no disconnection, that is, the switch-off phenomenon does not occur. This is because the high melting point metal forming the lower layer electrode is moved by EM at the same time as the disconnection voltage is applied, and the upper and lower layer electrodes are connected (dielectric breakdown step completed), and immediately after that, the low melting point forming the upper layer electrode is applied by applying a current of 5 mA or more. A sufficient amount of Joule heat is supplied to sufficiently promote the reaction between the metal and the refractory metal forming the lower electrode, and as a result of such reaction, even if a current larger than the write current flows thereafter, the wire will not be broken and is strong. This is because an intermediate melting point compound is produced. This intermediate melting point compound formation reaction is promoted by promoting the melting of the low melting point metal and its diffusion to the high melting point metal side. The Joule heat generated by the application of a current of more than 5 mA exceeds the heat of fusion of the low melting point metal, so that the above reaction is preferably promoted and the diameter of the conducting path is increased.

On the other hand, the write current when forming the conduction path is
It is preferable to apply the write pulse a plurality of times. This can further enhance the disconnection resistance of the anti-fuse element. The reason for this is that when the antifuse element according to the present invention has a current value that is lower than a write current value when a current flows through the antifuse element again, the ON resistance value suddenly increases from several tens Ω to several Ω. This is because it has the property of implementing a switch-on phenomenon that is reduced to some extent. In other words, a conduction path made of an intermediate melting point compound, which has been formed by writing once, can be made more resistant to disconnection by passing a current of the same or higher level again. In the second and subsequent writing, the switch-on phenomenon will occur even if a pulse with a shorter pulse time / pulse height or a lower pulse is added than in the first writing, but the pulse scale will be increased (pulse height or Larger pulse widths) or reversing the polarity gives better results.

In the third aspect of the invention, a lower layer electrode having an amorphous structure or a crystal structure having a crystal grain size of 20 nm or less and having flatness at the interface of the anti-fuse insulating film is provided.
It is also one of the features that it is arranged directly above a conductive layer containing a low melting point metal (such as Al) (often formed integrally with the lower layer wiring at the same time). Here, the film thickness of the lower layer electrode is 50-250 nm
It is preferred that By applying a breakdown voltage with the lower electrode at the lower potential side in this way, both the high melting point metal of the lower layer electrode and the low melting point metal of the conductive layer immediately below can be efficiently taken into the conduction path. The reason why the preferable range of the film thickness of the lower layer electrode is 50 to 250 nm is that this is 50
If it is less than nm, the roughness of the surface increases and the insulation breakdown voltage of the insulating film becomes low, and if it exceeds 250 nm, the resistivity of the laminated wiring of WSix and Al increases. Increase delay. The WSix film thickness is reduced by etching during via processing, pretreatment before deposition of the anti-fuse insulating film, etc., as compared with the film thickness during deposition. Therefore, the preferred range here is 50-250n
m is the film thickness of the completed antifuse element. Therefore, in order to simultaneously realize the reliability of the insulating film and the suppression of the increase of the wiring resistance, the film thickness of WSix should be 50
It is desirable to set in the range of ~ 250nm.

Next, the fourth invention can be applied in combination with the above-mentioned first to third inventions, in which the interface between the anti-fuse insulating film and the lower layer electrode is in the connection hole before the insulating film is formed. This is the lower interface of a new oxide film formed by removing oxides or nitrides existing on the surface of the lower layer electrode and further removing the lower layer electrode in the depth direction to form a uniform oxide film on the front surface of the lower electrode. The antifuse-type semiconductor integrated circuit device is characterized by comprising the new oxide film and an insulating film further formed thereon. And it is most preferable that this new oxide film is formed by a wet process using ammoniacal hydrogen peroxide solution. According to the fourth aspect of the present invention, it is possible to preferably remove the oxide having poor film quality or the nitride having a sharp protrusion shape, which is inevitably formed on the surface of the lower electrode of the base before forming the insulating film for the anti-fuse, and at the same time, the lower electrode itself. While removing in the depth direction, an oxide film having good film quality can be formed on the surface being removed. Since this oxide film has excellent adhesion to the base lower electrode and has a uniformly smooth surface,
An antifuse insulating film having excellent film quality and flatness can be formed by supplementing the oxide film with a required film thickness on the oxide film to form the antifuse insulating film as a whole.

In common with the first to fourth inventions, a silicon oxide film, a silicon nitride film, a tantalum oxide film, or a composite film thereof can be used as the antifuse insulating film. Then, the lower layer electrode may be arranged on the first wiring layer and the upper layer electrode may be arranged on the second wiring layer, respectively, or the lower layer electrode may be arranged on an insulating separator (LOCOS) for insulating and separating the semiconductor elements. Good.

In the second and third inventions, the metal silicide used as the material of the lower layer electrode may be either a single layer film or a composite film.
It may be on the semiconductor element region before the interlayer insulating film is formed, a silicon film may be formed on an insulating separator (LOCOS) for insulating and separating the semiconductor elements, and a metal film may be deposited on the silicon film for silicidation. After forming the interlayer insulating film and forming the connection hole, silicidation may be performed in the region of the connection hole.

Next, a fifth invention is characterized in that, in the first invention, the lower layer electrode and the upper layer electrode are made of a conductive material containing Al, and the insulating film for antifuse is a silicon nitride film. Here, as the conductive material having an amorphous structure and containing Al, among the materials listed in the first invention, Co, Ni, Cu, Ti, Zr, Nb, Mo, Hf, and T are listed.
of at least one element of a, W, Y, and La (these are likely to be amorphous and have a high reflow property of the compound with Al) and any one of Al, Al-Si, and Al-Cu-Si A compound is preferably used, whereby the conducting path is mainly composed of Al and Co, Ni, Cu, Ti, Z.
1 of r, Nb, Mo, Hf, Ta, W, Y, La
It will include more than one species. It has been described in the first aspect that the antifuse insulating film can be planarized by making the lower layer electrode amorphous. It can be said that the present invention further includes Al in the lower layer electrode in the third aspect of the invention, whereby the ON resistance of the anti-fuse element can be lowered to the limit. In this case, the antifuse insulating film has particularly low reactivity with Al (4
By adopting a silicon nitride film (which does not react with Al at 00 ° C. or lower), the conduction path is extremely stabilized. Since the silicon nitride film is extremely hard, even if the flatness of the base is poor, the stress generated during the formation of the silicon nitride causes
This also has the effect that the Al compound having a high reflow property forming the interface with the base material flows and the interface is naturally flattened.

According to a fifth aspect of the present invention, the upper layer wiring related to the anti-fuse element and the upper layer wiring related to the via are arranged from the region of the via connecting hole in which the anti-fuse element is temporarily arranged to the upper layer electrode and the anti-fuse insulating film. Is formed at the same time in a via formation step of removing the above and forming a via therethrough, and is characterized by comprising a laminated film of a conductive layer containing a refractory metal and a conductive layer containing Al immediately above. In this case, the conductive layer containing the refractory metal is titanium nitride, TiW,
A film of an upper layer electrode which is composed of a single-layer film of either tantalum nitride or TaW, or a laminated film of the single-layer film and a Ti film immediately below the single-layer film, and which fills the space between the conductive layer and the anti-fuse insulating film. The thickness is preferably 50 nm or more. As a result, the via and the anti-fuse element can be formed in the same layer by adding one mask. Also, the upper layer electrode that fills the gap between the conductive layer (titanium nitride, TiW, tantalum nitride, TaW) containing a refractory metal useful as a barrier metal and the anti-fuse insulating film has a thickness of 50 nm or more. This is because if the thickness is less than 50 nm, the leak current tends to increase. It is preferable that this film thickness does not exceed 250 nm from the viewpoint of step coverage.

Next, in a sixth aspect of the present invention, the lower layer wiring is made of an Al alloy film having a titanium nitride film as the uppermost layer, and the lower layer electrode is formed of the titanium nitride film as the uppermost layer of the lower layer wiring at the bottom of the connection hole. An Al alloy film exposed and removed in the depth direction, the insulating film for antifuses is a silicon oxide film, a silicon nitride film or a tantalum oxide film, or a composite film thereof, and the upper electrode is at least the lowermost layer. The antifuse-type semiconductor integrated circuit device is characterized in that it is a contact portion of the upper wiring made of an Al alloy film with the insulating film for antifuse. This eliminates the layer interface (horizontal direction) between the titanium nitride for the antireflection film and the insulating film for the anti-fuse, so that the anti-reaction due to the non-uniform reduction reaction between Ti and the silicon oxide film, the silicon nitride film or the tantalum oxide film is eliminated. It is possible to prevent the film thickness of the fuse insulating film from decreasing. In this case, the anti-fuse insulating film contacts the Al alloy film at the upper and lower interfaces, but since Al has a much lower reactivity with the silicon oxide film, the silicon nitride film, and the tantalum oxide film than Ti, the anti-fuse insulating film There is no concern about thinning the fuse insulating film. Therefore, the insulation separation between the upper and lower wirings can be reliably performed. At the same time, as described in the fifth aspect, Al of the upper and lower electrodes is introduced into the conduction path, so that the ON resistance of the anti-fuse element becomes extremely low.

Further, in the sixth invention, it is more preferable to provide a contact prevention insulating film between the side wall of the titanium nitride film appearing in the connection hole and the insulating film for the anti-fuse so as to prevent contact between these films. Even more preferable. As a result, the contact between Ti and the anti-fuse insulating film can be completely prevented,
The above effect can be obtained more reliably. The lower layer wiring may be a single layer of an Al alloy film, but a composite film in which one or more metal films are provided under the Al alloy film is advantageous in terms of wiring reliability and low resistance. Are more preferable, and as the Al alloy film for the lower and upper wirings, Co, Ni, T
The use of a compound of at least one element selected from i, Zr, Nb, Mo, Hf, Ta and W and any of Al, Al-Si and Al-Cu-Si is an antifuse due to surface smoothing. It is preferable from the viewpoint of improving the reliability of the device.

Next, in the seventh invention, the lower electrode is made of Al.
Alternatively, it is a contact portion of the lower layer wiring composed of a single layer film of Al alloy to the insulating film for antifuses, and the insulating film for antifuses is a silicon oxide film, a silicon nitride film or a tantalum oxide film, or a composite film of these. And the upper layer electrode is made of Al or an Al alloy, and the lower layer wiring is located directly above the insulating film formed to cover the substrate and formed in contact with the substrate in a connection hole penetrating the insulating film. The antifuse-type semiconductor integrated circuit device is characterized in that it is electrically connected to a substrate through a barrier metal composite film. As the Al alloy, those listed in the third, fifth or sixth invention can be applied. In addition to the composite film of Ti and titanium nitride, tungsten or titanium tungsten can be used as the barrier metal. As a result, the lower layer wiring can be formed directly on the insulating film covering the substrate, not directly on the barrier metal, so that there is no adverse effect of deterioration of flatness due to the orientation of Al, which is conventionally formed on the barrier metal. Therefore, the flattening of the base of the anti-fuse insulating film is promoted, so that an anti-fuse insulating film having a uniform film thickness including the upper and lower electrodes as an Al-containing conductive film can be obtained.
The object of the present application can be achieved.

[0060]

【Example】

(Embodiment 1) This embodiment mainly relates to the first and fourth inventions. FIG. 1 is a cross-sectional view of a main part of an anti-fuse type semiconductor integrated circuit device according to the first embodiment. In the figure, 1 is a semiconductor substrate (substrate), 2 is an interlayer insulating film, 3
Is a lower layer wiring (first layer wiring), BF is a lower layer electrode, 4 is an interlayer insulating film, 5 is a connection hole, 6 is an upper layer wiring (second layer wiring), 6
A is the upper wiring first layer (lowermost layer), 6B is the upper wiring second layer
Layer, TF is an upper layer electrode, AF is an anti-fuse insulating film,
CW is a conducting path, and 9 is a final protective film.

As shown in FIG. 1A, in the anti-fuse type semiconductor integrated circuit device, a wiring layer is formed on the substrate 1. As the substrate 1, for example, a single crystal silicon substrate is used. Although not shown, the main surface of the substrate 1 has a MISFET (Metal Insulator Se) which constitutes an FPGA or a PROM.
miconductor Field Effect Transistor) etc. are arranged.

The wiring layer generally has a two-layer wiring structure including a first wiring layer (lower wiring layer) on the interlayer insulating film 2 and a second wiring layer on the interlayer insulating film 4, and the wiring layer is formed in the first wiring layer. In this case, a plurality of lower layer wirings 3 are provided in parallel (the extension direction is parallel to the paper surface in FIG. 1), and a plurality of upper layer wirings 6 are provided in parallel in the second wiring layer (the extension direction is vertical to the paper surface in FIG. 1). . The lower layer wiring 3 and the upper layer wiring 6 are electrically connected to each other through a connection hole 5 formed in the interlayer insulating film 4. These upper and lower wirings 6 and 3 are used as signal lines connecting circuits, for example, logic circuits.

The anti-fuse element is incorporated in this signal line and is used as an element for selecting whether or not to connect the circuits. This anti-fuse element has a lower electrode B
F, an anti-fuse insulating film AF, and an upper layer electrode TF. In the example of FIG. 1, the lower-layer electrode BF corresponds to a part of the lower-layer wiring 3 that forms an interface with the anti-fuse insulating film AF, and the upper-layer electrode TF is one of the upper-layer wiring first layers 6A. The part corresponding to the interface with the anti-fuse insulating film AF corresponds to this.

The anti-fuse insulating film AF is formed between the lower layer electrode BF and the upper layer electrode TF, and is formed in the connection hole 5 for the anti-fuse which is opened at the same time in the process of forming the via connection hole (not shown). It is formed. In FIG. 1A, the anti-fuse insulating film AF is interposed between the lower layer electrode BF and the upper layer electrode TF and is in a non-conducting state.
In (b), the anti-fuse insulating film AF of an arbitrary (right side in the figure) anti-fuse element is destroyed and the lower layer electrode B
The conductive path CW is formed between F and the upper layer electrode TF. The upper wiring 6 is covered with a final protective film 9.

Now, in the first invention, the lower layer electrode B
F is composed of an electrically conductive material having an amorphous structure, and the element or compound listed in claim 3 is suitable as the material. Among them, a metal element having a small self-diffusion coefficient and a large mass (specifically, W, Ta, Nb, Mo) or a compound thereof is particularly preferable because it has excellent EM resistance, and the compound is a silicide (eg WSix) or a nitride. (Eg WNx) is preferred.

In this embodiment, a titanium silicide film and a tungsten silicide film are used as the lower electrode BF.
The tungsten silicide film is particularly preferred in the semiconductor manufacturing process because it has excellent EM resistance, low specific resistance, and is unlikely to deteriorate. Further, a titanium nitride film is used for the upper layer electrode TF (upper layer wiring first layer 6A), and an upper layer wiring second layer 6B.
An Al-Cu alloy film was used for each.

FIG. 2 is a sectional view showing the principal part of each manufacturing step of the anti-fuse type semiconductor integrated circuit device according to the first embodiment (hereinafter also appropriately referred to as the “device of the present invention”). It should be noted that the same members as those in the above-mentioned drawings are designated by the same reference numerals and the description thereof will be omitted. The manufacturing process of the device of the present invention will be described below with reference to FIG. First step: formation of lower layer electrode (see FIG. 2A) A conductive film for a plurality of lower layer wirings 3 is deposited on the interlayer insulating film 2 (at the same time, a lower layer electrode BF is also deposited), and a conventional photolithography technique and etching are performed. Pattern by technology. [Titanium silicide film] Using a target material in which the composition ratio of Ti is larger than the stoichiometric composition ratio (Ti / Si = 1 / 1.8),
By a sputtering method with a substrate temperature of 100 ° C., a titanium silicide film having an amorphous structure with a thickness of 200 nm was obtained. Ti in the film
The composition ratio of was adjusted by changing the Ti composition ratio of the target material.

After the completion of the film formation, unlike the conventional method, the amorphous structure of the lower layer electrode BF was maintained by controlling the manufacturing process temperature below 700 ° C., which is below the crystallization temperature. In addition to the sputtering method, the titanium silicide film is formed by CVD.
Methods or solid phase reaction methods can be used. [Tungsten silicide film] Substrate temperature 250 ℃, pressure 0.
By the plasma CVD method under the conditions of 5 torr, WF ₆ : SiH ₄ = 1: 4 and a flow rate of 300 sccm, the W composition ratio is larger than the stoichiometric composition ratio (W / Si = 2/1) and the film thickness is 200 nm. A tungsten silicide film having a crystalline structure was obtained. As a comparative example, a tungsten silicide film having a W composition ratio smaller than the stoichiometric composition ratio as the lower electrode was also prepared.

After the completion of the film formation, unlike the conventional method, the amorphous structure of the lower layer electrode BF was maintained by controlling the manufacturing process temperature below 700 ° C., which is below the crystallization temperature. Note that a CVD method (for example, a thermochemical vapor deposition method) or a sputtering method other than the plasma CVD method can be used for forming the tungsten silicide film. Second step: formation of a connection hole for an anti-fuse element (Fig. 2
(See (b)) The lower wiring 3 including the lower electrode BF and the substrate 1 have a film thickness of 1.
A 0 μm interlayer insulating film 4 (for example, a silicon oxide film) is coated, and a via hole (not shown) having a hole diameter of 1.0 μm and a connection hole 5 for an anti-fuse element are formed by a conventional photolithography technique and etching technique. A plurality of openings are provided at predetermined locations.

Third step: underlying flattening according to the fourth invention (see FIG. 2 (b)) The lower electrode B in the connection hole 5 for the anti-fuse element
The surface of F is subjected to a wet treatment to remove oxides with poor film quality or nitrides with sharp protrusions or contamination formed on the surface of the electrode during film formation or during exposure to the atmosphere. While removing a part in the depth direction, a new ultra-thin (film thickness 1-2
An oxide film with a good film quality (mainly silicon oxide)
Were uniformly formed. This wet treatment was performed for 5 minutes using ammoniacal hydrogen peroxide solution (NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: 1: 5, 70 ° C.) (using APM cleaning). The removal depth by this wet treatment is 5 for titanium silicide.
.About.10 nm, 5 to 20 nm in the case of tungsten silicide, and at least the lower layer electrode BF having a thickness of 40 nm or more could be secured. As a comparative example, a non-wet treatment was also prepared.

In this example, it was confirmed that even if the isotropic chemical dry etching treatment (dry treatment) under the following treatment conditions was adopted instead of the wet treatment, almost the same lower electrode surface was obtained. ing. Dry processing has a non-plasma processing method and a plasma processing method,
The following conditions are preferable respectively. The temperature means the substrate temperature.

Non-plasma treatment method: ClF ₃ : Ar = 1: 9, 500 to 2000 sccm, 100torr, 30 ° C., 1 minute or F ₂ : He = 3: 97, 1000 sccm, 1.0torr, 200 ° C., 3
For plasma treatment method: BCl ₃ : Ar = 4: 1, 100 sccm, 0.1torr, 200 ℃, 3 minutes (13.56
MHz) or CF ₄ : O ₂ = 8: 2, 100 sccm, 0.1torr, 30 ℃, 2
Min (13.56MHz) As the fluorine-based gas used for this dry processing,
Besides the above example, NF ₃ , C ₂ F ₆ , CH ₂ F ₂ , CH ₃ F, SF ₆ etc. can also be used.

The above-mentioned wet treatment and dry treatment were all performed at a temperature of 200 ° C. or lower, and the amorphous structure of the lower layer electrode BF was maintained to maintain the surface flatness. Fourth step: formation of insulating film for antifuse (see FIG. 2C) An insulating film AF for antifuse is formed to cover the lower layer electrode BF and the interlayer insulating film 4. This anti-fuse insulating film AF forms a layer on an oxide film (not shown) newly formed on the lower layer electrode BF in the third step, and the anti-fuse insulating film AF is formed including the oxide film. Will be done.

In this embodiment, SiH ₄ , NH ₃ and N ₂ are vapor-phase-reacted by a plasma CVD method to deposit a silicon nitride film, which is then used as an anti-fuse insulating film AF (deposition conditions: SiH 4 1700 sccm, NH 3 500sccm, N2 300sccm, pressure
0.35torr, substrate temperature 350 ℃, high frequency 50kHz, high frequency output
0.98kW). The preferred range of silicon nitride film thickness is 5 to 20n
m, which is 10 nm in this embodiment. In addition to the silicon nitride film, a silicon oxide film or a tantalum oxide film can be used as the anti-fuse insulating film AF.
A composite membrane in which any two or more of the two are laminated can also be used.

Fifth step: upper electrode formation (see FIG. 2 (d))
See) Depositing the upper wiring 6 covering the anti-fuse insulating film AF
Common photolithography and etching techniques
These films are patterned together by a technique. This embodiment
In forming the upper layer wiring 6, first, the upper layer wiring first layer
6A (on the anti-fuse insulating film AF, the upper electrode TF
Becomes ) Is used for the reactive sputtering method.
Deposited to a film thickness of 100 nm, and then the upper layer wiring second layer
The Al alloy film that composes 6B has a thickness of 800 nm and is sputtered.
It was deposited in a film thickness. The deposition conditions for the titanium nitride film are as follows:
The substrate material is Ti, the substrate temperature is 100 ℃, and the mixed gas ratio is Ar / N.₂=
7, pressure 4torr, high frequency 13.65MHz, high frequency output 400W
As a result, a titanium nitride film having a Ti composition ratio of 65% was obtained. This T
Experimentally determined titanium nitride for adjusting the composition ratio of i
The relationship between the composition ratio of N in the film and the mixed gas ratio is shown in FIG.
Change the metal composition ratio not only in the lower electrode but also in the upper electrode.
If it is larger than the stoichiometric composition ratio, antifuse element
I will touch on before that the ON resistance of the child can be further reduced.
However, when the upper electrode is a titanium nitride film, the realization (T
i / composition ratio 55% or more) ₂ If ≧ 5
Yes. As a comparative example, the Ti composition ratio is a stoichiometric composition ratio.
Smaller titanium nitride as the upper layer electrode is also prepared
Was.

The upper layer wiring 6 may be deposited by the CVD method instead of the reactive sputtering method or the sputtering method. The upper wiring first layer 6A (upper layer electrode TF)
Alternatively, a titanium silicide film formed by sputtering may be used instead of the titanium nitride film formed by reactive sputtering. In that case, in order to obtain a titanium silicide film containing Ti at a stoichiometric composition ratio of 40% or more, The composition of the target material may be adjusted as in the case of forming the lower electrode in the process.

Sixth step: Finishing (see FIG. 1A) Finally, a final protective film 9 is deposited so as to cover the upper wiring 6 and the interlayer insulating film 2. In the present embodiment, a laminated film of a phosphorus-doped silicon dioxide film and a SiN film formed by plasma CVD is used as the final protective film 9. The antifuse-type semiconductor integrated circuit device that has undergone such a manufacturing process was used as a device under test to write data into them, and the dielectric breakdown voltage, ON resistance, etc. were tested.

FIG. 4 shows the relationship between the ON resistance and the composition ratio of Ti in the titanium nitride film forming the upper electrode in the test device in which the lower electrode is titanium silicide. FIG.
In (a), the ON resistance distributions are compared for the Ti composition ratios of 50% and 65%, and it can be seen that the Ti resistance ratio of 65% has smaller absolute values and variations in the ON resistance. FIG.
(B) shows the relationship between the average value of the ON resistance and the Ti composition ratio, and the ON resistance decreases as the Ti composition ratio increases,
It can be seen that the decrease becomes more rapid at around 55%, which exceeds the stoichiometric composition ratio. This tendency was the same in the test device in which the lower layer electrode was tungsten silicide.

FIG. 5 shows the lower layer electrode BF of the device under test for the device under test using tungsten silicide as the lower layer electrode.
It is the graph which represented the surface shape of (lower layer wiring 3) as a cross-sectional curve, (a) shows what was wet-processed, (b) shows what is not wet-processed, respectively. From the figure, it is understood that the wet treatment according to the fourth invention alleviates the sharp shape of the surface of the lower layer electrode and promotes the flattening.

FIG. 6 shows the relationship between the presence or absence of the wet treatment and the distribution of the dielectric breakdown voltage in the above test equipment. From this figure, the breakdown voltage of the test equipment with the wet treatment is the wet treatment. It can be seen that the variability is significantly reduced compared to that without. This means that in the wet-processed device of the present invention, the probability of an accidental short circuit between the upper and lower electrodes under a long-term operating voltage application is significantly reduced, that is, the dielectric breakdown characteristics are significantly improved. It means that long-term operation reliability is improved. The tendency shown in FIGS. 5 and 6 was the same in the test device in which the lower electrode was made of titanium silicide.

FIG. 7 shows a device under test (A: W about 80%) in which the lower electrode BF is formed of tungsten silicide having a W composition ratio higher than the stoichiometric composition ratio (about 33% in WSi ₂ ).
%, B: W about 48%) is a graph showing the relationship between the W content of the lower layer electrode BF and the W content of the conductive path CW. Writing was performed with the lower layer electrode BF on the low potential side. From the figure,
The W content in the conduction path CW gradually decreases from the lower layer electrode BF to the upper layer electrode TF, but maintains a value higher than the stoichiometric composition ratio, and W of the lower layer electrode BF.
The higher the composition ratio, the higher (A is always higher than B)
You can see that.

As described above, the lower layer electrode is made of tungsten silicide having a large W composition ratio, and writing is performed with the lower silicide layer on the lower potential side, so that W can be suitably incorporated into the conduction path. FIG. 8 is a graph showing the relationship between the W content of the conducting path CW and the EM resistance according to the test devices A and B. In the figure, the horizontal axis shows the operating time, and the vertical axis shows the cumulative defective rate such as disconnection. In the same figure, the data relating to the device under test in which the lower electrode is W and titanium silicide (TiSix) are also shown. From FIG. 8, it can be seen that in the conductive path made of tungsten silicide, the EM resistance improves as the W content increases, that tungsten silicide is basically superior in EM resistance to titanium silicide, and the conductive path is formed of W alone ( It can be seen that the W plug) has the best EM resistance.

FIG. 9 shows the W composition ratio of the lower layer electrode made of tungsten silicide and the ON resistance ((a) distribution, (b) of the lower layer lower potential writing element (the antifuse element in which writing is performed with the lower layer electrode on the lower potential side)). ) Is a graph showing a relationship with (average value). Fig. 9 (a) shows the ON resistance distribution with a W composition ratio of 35%,
The 50% W composition ratios are compared, and it can be seen that the W composition ratio of 50% has smaller absolute values and variations in ON resistance.
FIG. 9B shows the relationship between the average value of the ON resistance and the W composition ratio. The ON resistance decreases as the W composition ratio increases,
It can be seen that the decrease becomes more rapid at around 40%, which exceeds the stoichiometric composition ratio.

As described above, the lower electrode has an amorphous structure and the bottom of the contact hole is subjected to wet treatment to flatten the base of the anti-fuse insulating film, and the lower electrode is made of tungsten silicide having a large W composition ratio. Is set to the low potential side and writing is performed to capture W in the conduction path,
It is possible to obtain an anti-fuse type semiconductor integrated circuit device having a small resistance and its variation, stable dielectric breakdown characteristics, and excellent EM resistance. (Embodiment 2) This embodiment relates to the first and third inventions,
Even when the lower layer electrode has a crystalline structure instead of the amorphous structure in Example 1, the microstructure or shape of the surface of the lower layer electrode, which is the base of the anti-fuse insulating film, is defined in claims 9 to 11. It is shown that the dielectric breakdown characteristics of the anti-fuse element are improved if it falls within the specified numerical range. In the device under test of this example, the lower layer electrode was a tungsten silicide film, and 700 ° C. to 900 ° C. above the crystallization temperature after completion of film formation in the first step described in Example 1.
The microstructure or the surface shape was variously adjusted by maintaining the temperature within the range of ° C, and thereafter, those manufactured through the same steps as in Example 1 were used.

FIG. 10 shows the crystal grain size of the lower electrode and the life of the insulating film for the anti-fuse until dielectric breakdown ((a) distribution,
It is a graph which shows the relationship with (b) variation. According to the figure (a), the crystal grain size of the lower layer electrode is large (100 n
In the case of m), the life leading to dielectric breakdown is short and the width of the distribution is wide, but as the grain size is reduced to 20 nm and 10 nm, this life is extended and the width of the distribution is narrowed. Further, according to FIG. 6B, the variation in life rapidly increases when the particle size exceeds 20 nm, and deviates from the practical level.

FIG. 11 shows the center line average roughness Ra of the lower layer electrode and the life of the antifuse insulating film up to the dielectric breakdown ((a)).
3 is a graph showing a relationship between distribution and (b) variation).
According to FIG. 5A, the center line average roughness R of the lower electrode surface
When a is large (3.0 nm), the life to dielectric breakdown is short and the distribution is wide, but the center line average roughness Ra is 2.0 nm.
As it becomes as small as 0 nm, this life span extends and the width of the distribution narrows. Further, according to FIG. 6B, the variation in life rapidly increases when the centerline average roughness Ra exceeds 2.0 nm, and deviates from the practical level.

FIG. 12 shows a specific size (1n
(m) to 1 μm) is a graph showing the relationship between the solid angle of the crystal grains and the life ((a) distribution, (b) variation) until dielectric breakdown of the anti-fuse insulating film. According to FIG. 6A, when the solid angle of the lower electrode surface is small (1.6 π), the life until dielectric breakdown is short and the distribution is wide, but the solid angle is small.
As the size is reduced to 1.7 π and 1.8 π, this lifetime extends and the width of the distribution narrows. Further, according to FIG. 9B, the variation in the life rapidly increases when the solid angle falls below 1.8 π, and deviates from the practical level.

The tendency shown in FIGS. 10 to 12 is not limited to the case where tungsten silicide is used as the lower layer electrode.
It has been confirmed that the metal silicide formed of the metal and Si mentioned above can also be obtained when the lower layer electrode is used. Therefore, the microstructure or shape of the surface of the lower electrode made of metal silicide is limited to the numerical range described in claims 9 to 11. (Embodiment 3) This embodiment relates to the first to third inventions, and is an element isolation body (LOCOS: which isolates between complementary MISFETs).
For example, an input terminal for a gate electrode made of a polycide film (lower layer: silicon film, upper layer: composite film of metal silicide film) is provided on the LOCal Oxidation Of Silicon), and an antifuse is formed by using the metal silicide film above the polycide film as a lower layer electrode. A manufacturing process of an anti-fuse type semiconductor integrated circuit device in which elements are arranged is disclosed.

FIG. 13 is a sectional view of an essential part of each manufacturing process of the anti-fuse type semiconductor integrated circuit device according to the third embodiment.
In FIG. 13, 5A is a connection hole for an anti-fuse element, 10
Is a p-type well, 11 is an n-type well, 12 is an element isolation body, 13 is a channel stopper region, 14 is a gate insulating film, 15 is a gate electrode, 15A is a gate electrode first layer (lowermost layer), and 15B is a gate electrode. The second layer, 16 is a sidewall spacer, 17 is an n-type semiconductor region, and 18 is a p-type semiconductor region. It should be noted that the same members as those in the above-mentioned drawings are designated by the same reference numerals and the description thereof will be omitted.

First step: Simultaneous formation of a gate electrode and a lower layer electrode (see FIG. 13A) (1) A gate insulating film 14, an element isolation body 12 and a channel stopper region 13 are formed on a substrate 1 to form an element isolation body. Impurities are introduced into the region of the substrate 1 divided by 12 to form the p-type well 1
A 0, n-type well 11 (generally referred to as a semiconductor element region) is formed, and a film for the gate electrode 15 is deposited so as to cover these. For the gate electrode first layer 15A, an amorphous or polycrystalline silicon film (about 150 nm thick), the gate electrode second layer 15B
Tungsten silicide film (film thickness of about 200 nm) is used for each. The silicon film is deposited by the CVD method or the sputtering method. When using the CVD method, the substrate temperature
At 600 ℃, pressure 0.3 torr, P
Is introduced to reduce the resistance value (P introduction condition: ion implantation method with a dose amount of 7.0 × 10 ¹⁵ atoms / cm ² and energy of 30 keV). In this embodiment, the substrate 1 is the p-type well 10, n.
Although a twin well structure having the type well 11 is formed, the present invention is not limited to this structure, for example, a single well structure in which the substrate 1 is p-type and does not have the p-type well 10. May be. (2) A tungsten silicide film for the gate electrode second layer 15B made of amorphous or fine crystal grains is deposited on this silicon film under the conditions adopted in the first or second embodiment. Similar to Examples 1 and 2, the subsequent steps are performed at 700 ° C. or lower, which is a temperature range where no crystal growth occurs, or at 700 to 850 ° C., which is a temperature range in which fine crystals are formed. (3) Pattern the film for the gate electrode 15. At this time, a part of the gate electrode 15 is left on the element isolation body 12 to serve as a gate input terminal. (4) Source / drain regions (n-type semiconductor region 17 in p-type well 10 and p-type semiconductor region 18 in n-type well 11) are provided in the semiconductor element region to form a complementary MISFET. Although not particularly limited, in the MISFET of this embodiment, according to a conventional method, impurities are first introduced by using the gate electrode 15 as a mask, then the gate electrode 15 is covered with the sidewall spacers 16, and the impurities are again introduced by using it as a mask. As a result, the LDD (Lightl
y Doped Drain) structure.

Second step: formation of connection hole for antifuse element (see FIG. 13B) Interlayer insulating film 2 is formed on the entire surface of substrate 1 including gate electrode 15, and antifuse element of interlayer insulating film 2 is formed. A connection hole 5A for antifuse element is opened in the region. Here, the gate electrode second layer 15B (made of tungsten silicide) exposed at the bottom of the antifuse element connection hole 5A forms the lower layer electrode BF.

Third step: flattening of underlying layer according to the fourth invention (see FIG. 13B) The surface of the lower layer electrode BF is wet-processed or dry-processed by the method described in the first embodiment. Fourth Step: Formation of Anti-Fuse Insulating Film (see FIG. 13C) By the method described in the first embodiment, the anti-fuse insulating film AF is deposited on the entire surface of the substrate including the anti-fuse element connection hole 5A.

Fifth Step: Formation of Upper Layer Electrode (See FIG. 13D) A conductive film for the first layer wiring 3 is deposited and patterned on the first wiring layer so as to cover the antifuse insulating film AF.
In this embodiment, as the conductive film, a titanium nitride film (a film thickness of about 100 nm by the sputtering method), an Al alloy film (a film thickness of about 800 nm by the sputtering method), a titanium nitride film (a film thickness of 30 nm by the sputtering method) are formed from the bottom. A layered film having a three-layer structure is adopted. After patterning the first-layer wiring 3, the anti-fuse insulating film AF is patterned using the first-layer wiring as a mask, and formation of the anti-fuse element is completed at the time of completion of the patterning. At this time, the lowermost titanium nitride film of the lower layer wiring 3 forms the upper layer electrode TF.

Sixth step: Finishing (see FIG. 13E) The interlayer insulating film 4 and the connection hole 5 are sequentially formed, and the second layer wiring 6 is further formed on the second wiring layer. Finally, a final protective film (not shown) is formed. (Embodiment 4) This embodiment relates to the first to third inventions, in which a multipurpose connection wiring made of a silicide single layer film is provided on an element isolator for separating complementary MISFETs, and the silicide single layer film is formed. Disclosed is a manufacturing process of an antifuse-type semiconductor integrated circuit device in which an antifuse element is arranged as a lower layer electrode.

FIG. 14 is a cross-sectional view of an essential part of each manufacturing process of the anti-fuse type semiconductor integrated circuit device according to the fourth embodiment.
In FIG. 14, 25 is a wiring and 26 is an interlayer insulating film. It should be noted that the same members as those in the above-mentioned drawings are designated by the same reference numerals and the description thereof will be omitted. First step: formation of lower layer electrode (see FIG. 14 (a)) After forming a complementary MISFET by the method according to the third embodiment, the interlayer insulating film 26 of 100 to 200 is formed by the low temperature low pressure CVD method.
The element isolation body is deposited with a thickness of nm and the interlayer insulating film 26 is interposed.
A wiring 25 is formed (deposited and patterned) on the surface 12.
In this embodiment, the film for the wiring 25 is made of Ti-Si-N.
The single layer film of is used. The single-layer film uses a TiSi ₂ target material and has a pressure of 1.0 × 10 ^-3 torr in an Ar-N ₂ mixed gas atmosphere.
By the reactive sputtering method under the condition that the power is 0.5 kW,
Amorphous structure with composition ratio Ti: Si: N = 1: 2: 3 (film thickness 400 nm
Degree) is obtained. This Ti-Si-N single layer film is 800
It remains amorphous even after annealing for 30 minutes at or below ℃. As described in Example 2, the single layer film may have a fine grain crystal structure of 20 nm or less instead of the amorphous structure.

Second step: formation of anti-fuse element connection hole (see FIG. 14 (b)) The interlayer insulating film 2 is formed on the entire surface of the substrate 1 including the wiring 25, and the anti-fuse element forming region of the interlayer insulating film 2 is formed. The anti-fuse element connection hole 5A is opened. Here, the wiring 25 (Ti
-Si-N) forms the lower layer electrode BF.

In the present embodiment, the following third to sixth steps are carried out in the same manner as in the third embodiment, and the explanation thereof will be omitted. Third step: flattening the underlying layer according to the fourth invention (see FIG. 14 (b)) Fourth step: forming an anti-fuse insulating film (see FIG. 14 (c)) Fifth step: forming an upper layer electrode (see FIG. 14 ( d)) 6th step: finishing (see FIG. 14 (e)) (Example 5) This example relates to the first to third inventions, and
Disclosed is a manufacturing process of an anti-fuse type semiconductor integrated circuit device in which a lower layer wiring made of a laminated film whose uppermost layer is a tungsten silicide film is provided in a wiring layer, and an anti-fuse element is arranged using the tungsten silicide film as a lower layer electrode.

FIG. 15 is a cross-sectional view of essential parts in each manufacturing step of the antifuse-type semiconductor integrated circuit device according to the fifth embodiment.
In FIG. 15, 3A is the lower wiring first layer (lowermost layer), 3B
Is a lower layer wiring second layer, 3C is a lower layer wiring third layer, and 3D is a lower layer wiring fourth layer (uppermost layer). It should be noted that the same members as those in the above-mentioned drawings are designated by the same reference numerals and the description thereof will be omitted. First step: formation of lower layer electrode (see FIG. 15A) A laminated film for the lower layer wiring 3 is sequentially deposited on the first wiring layer on the interlayer insulating film 2, and the deposited laminated film is simultaneously patterned. In the present embodiment, the lower wiring first layer 3A to the lower wiring fourth layer 3D are each made of titanium nitride (Ti) for barrier metal.
N) film (film thickness of about 100 nm), Al-C as wiring matrix
The u alloy film (thickness is about 800 nm), titanium nitride film for preventing alloy spike (thickness of about 300 nm), and tungsten silicide (WSix) film for preventing reflection (thickness of about 100 nm). The WSix film has a substrate temperature of 100 ° C. and a composition ratio W: Si.
An amorphous structure is obtained by depositing a target material of 1: 1.8 by a sputtering method. In the subsequent steps, the amorphous structure is maintained by controlling in the temperature range where crystal growth does not occur, as described in the first embodiment.

The following second to sixth steps are carried out in the same manner as in Example 1 except for the matters noted, and the description thereof will be omitted. Second step: formation of connection hole for anti-fuse element (Fig. 15
(Refer to (b)) 3rd process: Base leveling based on 4th invention (refer FIG. 15 (b)) 4th process: Insulating film formation for antifuses (refer FIG. 15c) 5th process: Upper layer electrode Formation (see FIG. 15D) Note: The titanium nitride film of the upper-layer electrode TF (upper-layer wiring lowermost layer 6A) is used as a barrier metal by sputtering to a film thickness of 50.
Deposit to a thickness of about nm.

Sixth Step: Finishing (Refer to FIG. 15E) (Embodiment 6) This embodiment mainly relates to the second invention. In the second invention, the lower-layer electrode BF is made of metal silicide having a metal composition ratio higher than the stoichiometric composition ratio (also referred to as metal rich), and a suitable metal element forming the metal silicide is set forth in claim 7. It was In this embodiment, a metal-rich titanium silicide film is used as the lower electrode BF. Ti, which forms titanium silicide, is a refractory metal, has a small specific resistance and is unlikely to deteriorate, and is therefore widely used in the semiconductor manufacturing process together with W.

Since the cross-sectional structure of the essential part of the device of the present invention according to this embodiment is the same as that shown in FIGS. 1 and 2 in the first embodiment, the manufacturing process will be described below with reference to these drawings. explain. First Step: Formation of Lower Layer Electrode (See FIG. 2A) A titanium silicide film is formed on the interlayer insulating film 2 by the following procedure. (1) Deposition of Si film and Ti film: Other crystalline Si film (film thickness 200 nm
) And a Ti film (film thickness of about 400 nm) are sequentially deposited. The deposition of these films was performed by the sputtering method, but may be performed by the CVD method. (2) Silicide treatment: A rapid thermal annealing method (lamp heating: Rapid Thermal Annealing) is adopted, and heating is performed for 10 to 100 seconds in a silicidable temperature range in a nitrogen atmosphere at normal pressure.

FIG. 16 shows the relationship between the titanium silicide composition ratio and the silicidation temperature, which were obtained by an experiment for searching a suitable range of the silicidation temperature. As shown in the figure, Ti / Si
Has a stoichiometric composition ratio of 0.5 when the processing temperature exceeds 700 ° C.
It stabilizes at and below 700 ° C, it increases with decreasing temperature (the degree of metal richness increases). Titanium silicide at this stage has a stone wall crystal structure, which is advantageous for flattening the surface of the lower electrode. However, at the stage where the processing temperature is lower than 400 ° C. and Ti / Si exceeds 3, the columnar crystal structure of Ti (having a sharp projection shape) becomes dominant,
It is disadvantageous for flattening the surface of the lower electrode. This tendency is common to the metals recited in claim 8, and therefore, in claim 7, the silicidation temperature is specified to be 400 to 700 ° C.

In place of the so-called silicidation method performed in steps (1) and (2), a sputtering method (condition example: substrate temperature 200
C., target material = titanium silicide (Ti / Si = 1) with metal-rich composition can also be used. Alternatively, a tungsten silicide single layer film may be used as the lower wiring instead of the titanium silicide single layer film. In addition to the sputtering method, the CVD method can be used for the film formation. For example, substrate temperature 250 ℃, pressure 0.5 torr, WF ₆ : SiH ₄ = 1: 4, flow rate 300 sccm
By a plasma CVD method under the following conditions, a tungsten silicide film (film thickness 200n with a metal-rich composition (W / Si = 2/1))
m) is obtained.

The film for lower layer wiring 3 after film formation is patterned to form lower layer wiring 3 (a part of which is lower layer electrode BF). In addition, maintaining the amorphous or fine grain structure of the lower layer electrode BF by controlling the subsequent steps below 700 ° C. below the crystallization temperature is the same as in the first embodiment.

Since the following second to sixth steps are carried out in the same manner as in the third embodiment in this embodiment, the description thereof will be omitted. Second step: formation of a connection hole for an anti-fuse element (Fig. 2
(See (b)) Third step: Base planarization according to the fourth invention (see FIG. 2 (b)) Fourth step: Formation of insulating film for antifuse (see FIG. 2 (c)) Fifth step: Upper layer electrode Forming (see FIG. 2 (d)) Sixth step: Finishing (see FIG. 1 (a)) The antifuse-type semiconductor integrated circuit device that has undergone such a manufacturing process is used as a device under test to perform writing, and dielectric breakdown The voltage, ON resistance, etc. were tested.

FIG. 17 shows the relationship between the titanium silicide composition ratio (Ti / Si) of the lower layer electrode BF and the ON resistance. As shown in the figure, it can be seen that the ON resistance of the conductive path CW decreases as the Ti / Si value increases (the degree of metal rich increases). FIG. 18 is a graph showing the flatness of the surface of the lower layer electrode BF which has been subjected to the wet treatment according to the fourth invention. As shown in the figure, in the lower layer electrode BF subjected to the wet treatment, inflection points P ₁ and P ₂ that are arbitrarily adjacent to each other on the cross-section (surface) curve and an intersection point P _{0 of} two tangent lines passing therethrough are provided.
It can be seen that the angle θ (= ∠P ₁ P ₀ P ₂ ) formed by and can be set within 150 ° to 180 °, and the flatness of the lower layer electrode BF is remarkably improved.

FIG. 19 shows the relationship between the presence / absence of wet treatment and the distribution of the dielectric breakdown voltage. Similar to the tungsten silicide lower layer electrode shown in FIG. However, it can be seen that the variation in the dielectric breakdown voltage of the EUT with wet treatment is significantly reduced compared to that without wet treatment. (Embodiment 7) This embodiment relates to the second invention and discloses another method for obtaining a titanium silicide film having a preferable surface shape as a base of the insulating film AF for antifuses. It is T
After i is deposited, the degree of vacuum is 10 ⁻⁵ to 10 ⁻¹⁰ torr and the temperature is 600.
It is the silicidation at ~ 800 ℃. On the surface of titanium silicide formed under these conditions, hemispherical projections are uniformly distributed instead of sharp projections. A cross-sectional view of a titanium silicide film having hemispherical protrusions on the surface
Shown in 20. Such silicidation treatment is the same as the first embodiment.
It may be performed in a step, or may be performed between the second step and the third step. As a result, a smooth surface with ridges is obtained, but the defect density of the anti-fuse insulating film AF, which is based on it, is reduced and the film quality is improved. (Embodiment 8) This embodiment relates to the second invention and discloses a manufacturing process of an anti-fuse type semiconductor integrated circuit device in which a diffusion layer formed on a main surface of a substrate is used as a base of a lower layer electrode BF.

FIG. 21 is a sectional view showing the principal part of each manufacturing step of the anti-fuse type semiconductor integrated circuit device according to the eighth embodiment.
In the figure, 22 is a Ti film and 23 is a titanium silicide film. It should be noted that the same members as those in the above-mentioned drawings are designated by the same reference numerals and the description thereof will be omitted. First step: formation of base material (diffusion layer region) of lower layer electrode (FIG. 21)
(See (a)) In the same manner as in Example 3, a semiconductor element region having an LDD structure is formed on the substrate 1. This example is different from Example 3 in that the MISFET region and the diffusion layer region are arranged adjacent to each other, but this structure can be manufactured by a conventional method.

Second step: Opening of connection hole for anti-fuse element / Formation of lower layer electrode in connection hole (1) Formation of connection hole (see FIG. 21 (b)): Entire surface of substrate 1 including MISFET region and diffusion layer region An inter-layer insulating film 2 is formed on the inter-layer insulating film 2, and an anti-fuse element connection hole 5A is formed in the anti-fuse element forming region of the inter-layer insulating film 2. Here, the n-type semiconductor region 17 exposed at the bottom of the antifuse element connection hole 5A serves as a base of the lower layer electrode BF. (2) Ti film deposition (see FIG. 21C): A Ti film 22 (having a film thickness of 40) is sputtered on the entire surface of the interlayer insulating film 2 including the n-type semiconductor region 17 exposed at the bottom of the antifuse element connection hole 5A.
nm) is deposited. (3) Silicide treatment (see FIG. 21 (d)): Silicide treatment is performed in the same manner as in Example 6 (lamp heating: 650 ° C. for 30 seconds). At this time, the Ti film 22 reacts with the Si in the n-type semiconductor region 17 thereunder at the bottom of the anti-fuse element connection hole 5A to form a titanium silicide film 23 (lower layer electrode BF). (4) Removal of unreacted Ti film (see Fig. 21 (d)): 100 ° C x 10
The unreacted Ti film is removed by selective etching for a minute. As the etching solution, sulfuric acid hydrogen peroxide solution (mixed aqueous solution of H ₂ SO ₄ and H ₂ O ₂ ) can be used. However, sulfuric acid hydrogen peroxide has no effect exerted by the ammoniacal hydrogen peroxide solution used in the wet treatment according to the fourth invention.

Since the third step and subsequent steps of this embodiment can be carried out in the same manner as in the third embodiment except for the notes, the description thereof will be omitted. Third step: planarization of the base according to the fourth invention (see FIG. 21 (d)) Fourth step: formation of an anti-fuse insulating film (see FIG. 21 (e)) Fifth step: formation of an upper layer electrode (see FIG. 21 ( e)) Note: As a conductive film for the first layer wiring 3, a titanium nitride film (film thickness of about 20 nm by sputtering method = upper layer electrode TF), Al from the bottom
Adopted a laminated film with a three-layer structure of an alloy film (a film thickness of about 800 nm by the sputtering method) and a titanium nitride film (a film thickness of about 50 nm by the sputtering method).

Sixth Step: Finishing (Refer to FIG. 21F) (Embodiment 9) This embodiment relates to the second invention and is a complementary MI.
An anti-fuse type semiconductor in which a multi-purpose connection wiring made of a laminated film of a Si film and a titanium silicide film is provided on an element separator for separating SFETs, and an anti-fuse element is arranged with the titanium silicide film under the wiring as a lower layer electrode. A manufacturing process of an integrated circuit device is disclosed.

FIG. 22 is a sectional view showing the main part of each manufacturing step of the anti-fuse type semiconductor integrated circuit device according to the ninth embodiment.
In FIG. 22, 25A is a Si film, 25B is a Ti film, and 25C is a titanium silicide film. It should be noted that the same members as those in the above-mentioned drawings are designated by the same reference numerals and the description thereof will be omitted. First Step: Formation of Lower Layer Electrode (1) Formation of Lower Layer Electrode Base (See FIG. 22A): Example 4
After forming the complementary MISFET and depositing the interlayer insulating film 26 in the same manner as described above, Si is formed on the element isolation body 12 through the interlayer insulating film 26.
Film 25A (by CVD method or sputtering method. Film thickness 200 nm
It may be amorphous or crystalline. ), Ti film 25B
(By sputtering, film thickness of about 40 nm) is sequentially deposited and patterned. (2) Silicidation treatment (see FIG. 22B): Silicidation is performed in the same manner as in Example 6 (lamp heating: 650 ° C. for 30 seconds). At this time, in the laminated film (wiring 25), the Ti film 25B and a part of the Si film 25A react with each other to react with the titanium silicide film 25C.
(Lower layer electrode BF) is generated.

In the present embodiment, the following second to sixth steps are carried out in the same manner as in the fourth embodiment, and the explanation thereof will be omitted. Second step: formation of connection hole for antifuse element (not shown) Third step: planarization of underlying layer according to fourth invention (not shown) Fourth step: formation of insulating film for antifuse (FIG. 22 (c)) Fifth step: formation of upper layer electrode (see FIG. 22 (d)) Sixth step: finishing (see FIG. 22 (e)) (Example 10) This example relates to the second invention, and MISFE
Disclosed is a manufacturing process of an anti-fuse type semiconductor integrated circuit device in which an anti-fuse element is arranged with a source / drain wiring connected to a source / drain region of T in a self-aligned manner as a lower layer electrode.

FIG. 23 is a sectional view of an essential part in each manufacturing step of the anti-fuse type semiconductor integrated circuit device according to the tenth embodiment.
In the figure, 27 is a source / drain wiring (titanium silicide film), 27A is a Si film, and 27B is a Ti film. It should be noted that the same members as those in the above-mentioned drawings are designated by the same reference numerals and the description thereof will be omitted. First step: formation of lower layer electrode (1) Deposition of laminated film (see FIG. 23 (a)): Complementary MISFE
LDD structure semiconductor device region (gate electrode 15, sidewall spacer 16, n
-Type semiconductor region 17, p-type semiconductor region 18) and element isolation body
A laminated film for the source / drain wiring 27 is deposited on the entire surface of the substrate 1 including 12. The laminated film is composed of a Si film 27A (film thickness of about 80 nm) and a Ti film 27B (film thickness of about 40 nm) thereon. The Si film 27A can be formed by a CVD method or a sputtering method, and may have an amorphous or crystalline structure. See also T
The i film 27B can be formed by a sputtering method. (2) Patterning (see FIG. 23 (b)): The laminated film is patterned by a conventional method. (3) Silicide treatment (see FIG. 23 (c)): Silicide treatment is performed in the same manner as in Example 6 (lamp heating: 650 ° C. for 30 seconds). At this time, in the laminated film, the Ti film 27B and the Si film 27A
React with each other to generate a titanium silicide film 27 (lower layer electrode BF).

In the present embodiment, the following second to sixth steps are carried out in the same manner as in the fourth embodiment except for matters noted, so that the description thereof will be omitted. Second step: formation of connection holes for anti-fuse elements (Fig. 23
(See (d)) Note: The anti-fuse element connection hole 5A is an element isolation body.
Open every other 12 on.

Third step: planarization of the base according to the fourth invention (see FIG. 23 (d)) Fourth step: formation of an anti-fuse insulating film (see FIG. 23 (e)) Fifth step: formation of upper layer electrode ( 23 (f)) 6th step: finishing (see FIG. 23 (g)) (Embodiment 11) This embodiment relates to the third invention. FIG. 24 is a sectional view showing an essential part of an anti-fuse semiconductor integrated circuit device according to the eleventh embodiment. It should be noted that the same members as those in the above-mentioned drawings are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 24 (a), the anti-between the lower layer electrode BF (lower layer wiring second layer 3B (uppermost layer)) and the upper layer electrode TF (not used as the upper layer wiring first layer 6A in this embodiment). The fuse insulating film AF is interposed and the fuse is in a non-conducting state.
In (b), the anti-fuse insulating film AF of an arbitrary (right side in the figure) anti-fuse element is destroyed and the lower layer electrode B
The conductive path CW is formed between F and the upper layer electrode TF.

Now, in the third invention, the lower layer electrode B
F is made of a conductive material of refractory metal, and the upper electrode T
It is specified that F is made of a conductive material of a low melting point metal. As the refractory metal for the lower layer electrode BF, Ti, Zr, Hf, V,
Nb, Ta, Mo or W is preferable, and silicide of these elements is more preferable from the viewpoint of stable film quality.

A low melting point metal for the upper layer electrode TF is A
1, Al alloy, Cu or Ag is preferable from the viewpoint of reducing the ON resistance, and among them, Al is Si, Cu, S.
A material containing c, Pd, Ti, Ta or Nb as an additive is preferable from the viewpoint of improving the reliability of the antifuse element by surface smoothing. A suitable Al alloy is Al
-1.0 wt% Si alloy, Al- 0.5 wt% Cu alloy, Al-
0.15wt% Sc alloy, Al-1.0wt% Si-0.5〜4.0wt
% Cu alloy, Al-1.0 wt% Si-0.3 wt% Pd alloy,
Al-0.1 wt% Cu-0.15 wt% Ti alloy can be mentioned.
Note that Ta and Nb as additives can be expected to have the same effect as Ti as an additive. It is preferable that the amount of the additive added to the Al alloy is within a range that does not increase the wiring resistance, for example, within 5 wt%. However, by using the laminated wiring of Al-Cu wiring and Al-Ta, the wiring of the laminated wiring can be obtained. If increase in resistance is not a problem, for example, Ti, Ta, Nb, etc. may be added up to 50 wt% at the maximum.

By constructing the antifuse element in this way in the third invention, the low melting point metal is used as the upper electrode T.
It can be suitably incorporated from F to the conductive path CW. The low melting point metal is
Since the resistance value is smaller by several orders of magnitude than that of Si used as a so-called gate material, the resistance value of the conduction path CW itself can be reduced. The basic idea according to the third invention has been described in detail in the section "Embodiment of the Invention" and will not be described here.

FIG. 25 is a sectional view showing an essential part of each step of manufacturing the device of the present invention according to the eleventh embodiment. It should be noted that the same members as those in the above-mentioned drawings are designated by the same reference numerals and the description thereof will be omitted. The manufacturing process of the device of the present invention will be described below with reference to FIG. First step: formation of lower layer electrode (see FIG. 25A) A film for lower layer wiring first layer 3A and a film for lower layer wiring second layer 3B (= lower layer electrode BF) are sequentially deposited on the interlayer insulating film 2,
Patterning is performed by a conventional method. The film for the lower wiring first layer 3A includes A containing at least one of Cu and Si as an additive.
l Alloy film 800-
Deposit with a film thickness of 1000 nm. As the lower wiring second layer 3B film, a tungsten silicide (WSix) film is used.
The film is deposited with a film thickness of 50 to 200 nm under the following conditions, which are different from the conventional method. At this time, the WSix film has an amorphous structure or a fine crystal structure (grain size of 20 nm or less) and has excellent flatness as described in the first embodiment. [WSix film formation conditions] The substrate temperature is set to 450 ° C or lower, which is lower than the crystallization temperature, in an Ar gas atmosphere of 5 mtorr, and a film is formed by a sputtering method using WSix (x = 1.0 to 2.5) as a target material. No heat treatment. Then, in the subsequent steps, the processing temperature is controlled below the crystallization temperature. Further, it is preferable that the composition of WSix is W-rich (x≤2) as described in Embodiment 1 from the viewpoint of improving the EM resistance of the conductive path CW.

Since the following second to fourth steps may be carried out in the same manner as described in Example 1, the description thereof will be omitted, and the fifth step according to the third invention will be described in detail. Second step: formation of connection holes for anti-fuse elements (Fig. 25
(Refer to (b)) Third step: Base planarization according to the fourth invention (Refer to FIG. 25 (b)) Fourth step: Formation of insulating film for antifuse (Refer to FIG. 25 (c)) Fifth step: Upper layer electrode Formation (1) Upper-layer electrode formation (see FIG. 25 (d)): A film for the upper-layer electrode TF made of a suitable material such as Al described above is deposited to cover the anti-fuse insulating film AF (film thickness of about 20 nm), These anti-fuse insulating film AF, upper wiring first layer 6A
Are patterned together by a conventional method. At this point, formation of the antifuse element is completed. The upper layer electrode TF is made of Al alloy because the conductive path C is formed by incorporating the additive.
It is preferable from the viewpoint of improving the EM resistance of W, and the film formation in that case may be performed by a sputtering method using a target material that has been alloyed in advance. (2) Upper layer wiring formation (see FIG. 25 (e)): upper layer electrode TF,
On the entire surface of the substrate 1 where the interlayer insulating film 4 is exposed, films for the upper wiring first layer 6A and the second wiring 6B are sequentially deposited, and they are cut into layers by a conventional method. The upper wiring first layer 6A film is preferably a titanium nitride film (film thickness of about 100 nm), and the second layer 6B film is preferably an Al alloy film (film thickness of about 800 nm). Both of these films can be formed by the reactive sputtering method or the CVD method.

By forming the upper layer wiring in such a layer structure, the following effects (a) and (b) can be obtained. (A) By interposing the upper wiring first layer (made of titanium nitride) 6A, Al of the upper wiring second layer 6B can be prevented from diffusing to the anti-fuse insulating film AF side, and the upper wiring, which is the main line of the signal current, can be prevented. The two layers 6B can be protected.

(B) Upper wiring first layer (made of titanium nitride) 6
A serves as a reaction force wall when Al of the upper electrode TF melts and expands during writing, and promotes diffusion and penetration of the molten Al into the conductive path CW, thus lowering the resistance of the conductive path CW. Can be realized more effectively. In this embodiment, further, a preferable dimensional relationship in the cross-sectional layer structure of the antifuse element is defined. FIG. 26 is a fragmentary cross-sectional view of the anti-fuse element according to Example 11. In the figure, numeral 7 is a nest. It should be noted that the same members as those in the above-mentioned drawings are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 26, the film thickness t ₁ of the anti-fuse insulating film AF, the film thickness t _{2 of} the upper layer electrode TF, the film thickness t ₃ of the upper layer wiring 6, the opening diameter d of the connection hole 5 and the effective opening diameter are shown. Td (=
d-2t ₁ ) is entered. The preferable dimensional relationship means (c) t ₁ <t ₂ , (d) t ₂ <t ₃ , (e) t ₂
<Td / 2. The following effects can be obtained by these regulations.

According to the definition of (c), the upper layer electrode T at the time of writing
The supply of the low melting point metal (for example, Al) from F to the conductive path CW becomes more stable. According to the definition of (d), the step coverage of the upper wiring 6 is improved. For example, t ₁ = 10 to ₂₀ nm, t ₂ =
In the case of 20 nm and t ₃ = 800 to 1000 nm, the level difference generated on the surface of the upper wiring 6 is t ₁ + t ₂ = 30 to 40 nm, which is 1 / t ₃ at most.
Fifty. Therefore, the processing accuracy of the etching mask (patterning accuracy of the upper layer wiring) formed by the lithography technique during patterning is improved.

According to the definition of (e), the void 7 as shown in FIG. 26 (b) is less likely to occur, and the conduction failure of the conduction path CW due to the void 7 can be prevented in advance. The property is improved. Sixth step: finishing (see FIG. 24B) The entire surface of the substrate 1 is covered with the final protective film 9.

The device of the present invention according to the third aspect of the invention, which has undergone such a manufacturing process, is written into them as a device under test.
N resistance and EM resistance were tested. Writing was performed by a constant current writing method and a constant voltage writing method. In the constant current writing method, a target current value is set and the applied voltage between the upper and lower electrodes is increased until the current reaches the target value.
The target current value is the programming current, and the resistance of the conduction path CW when it reaches the programming current is the ON resistance. The anti-fuse insulating film is initially in an insulating film state and almost no current flows, but as the voltage increases, it reaches the dielectric breakdown voltage and causes dielectric breakdown, and then the current flows rapidly, but at this time only for a preset time. The ON resistance is reduced by passing a constant current. On the other hand, writing was also performed by the constant voltage writing method. In this case, a constant voltage is applied. Initially, the anti-fuse insulating film is in an insulating state and almost no current flows, but at the same time as the dielectric breakdown, a current starts to flow. This current value varies depending on the resistance of the anti-fuse insulating film itself, other wiring resistance, the parasitic resistance of the transistor, and the like. In the case of the constant current writing described above, it is necessary to control the current value to be constant, but in the case of the constant voltage writing, no particular control mechanism is required, and the writing method is simple. There are merits. In the constant current writing method, it is possible to make an adjustment so that the writing conditions are the same for all antifuse elements. Therefore, the obtained ON resistance distribution has an advantage that a uniform ON resistance distribution can be obtained as compared with the constant voltage writing method. Regarding the value of the ON resistance itself, there was almost no difference between both writing methods. In this embodiment,
The results obtained mainly by the constant current writing method will be described below.

FIG. 27 is a graph showing the relationship between the ON resistance and the programming current. (A) shows the lower electrode and (b) shows
Is a voltage applied with the upper layer electrodes on the low potential side. In the figure, the upper layer electrode TF is shown as a low melting point metal (A
3) the third invention example described above and refractory metals (Ti, Ti
The comparative example of N) is entered. Here, the writing time is 10 ms, and the value of the flowing current is plotted on the horizontal axis by the constant voltage writing method. From the figures (a) and (b), in comparison with the ON resistance of the comparative example, when Al is used as the upper layer electrode, the same writing condition is used as compared with when Ti and TiN are used as the upper layer electrode. It is possible to obtain a low ON resistance at. Particularly, at a write current of 10 to 20 mA, the ON resistance has a good value of about 10 to 30 Ω. Similar ON resistance T
In order to obtain the i, TiN upper electrode structure, it is necessary to pass a large current of 20 mA or more. When the upper layer electrode is Al, a relatively low ON resistance can be obtained even when the upper layer electrode is on the high potential side. This is a temperature where the conduction path is formed, the temperature rises as the current flows, and the temperature exceeds the melting point of Al. Therefore, it is considered that Al melts and melts into the conduction path.

Further, when the lower potential side is the upper layer electrode as shown in FIG. 27 (b), a lower ON resistance can be obtained. This is because Al used as the upper layer electrode diffuses in the electron flow direction (direction opposite to the current) by so-called electromigration, and the Al composition in the conduction path increases. In the constant current writing method, the variation in ON resistance is significantly improved as compared with the constant voltage writing method. However, the absolute value of the ON resistance almost depends only on the magnitude of the flowing current, and there is no difference depending on the writing method.

FIG. 28 is a graph showing the influence of the write voltage polarity on the EM resistance. In the figure, the vertical axis represents the ON resistance, and the horizontal axis represents the operating time (unit: AU: Arbitrary Unit) until the conduction path CW disappears by EM. The data in the figure shows a book in which the upper electrode TF is an Al-Cu alloy. The present invention relates to an apparatus. As shown in FIG. 28, the ON resistance of the data written with the lower layer electrode on the lower potential side (data of polarity +) is slightly higher than that of the opposite polarity (data of polarity −), although it is about 5Ω. It can be seen that the EM resistance is about three times better while maintaining the value.

As described above, according to the third invention, it is possible to supply an anti-fuse type semiconductor integrated circuit device which can smoothly obtain a low-level ON resistance in writing and is excellent in long-term EM resistance. (Example 12) This example relates to claims 29 to 31,
The conditions for applying the write current will be disclosed.

The antifuse-type semiconductor integrated circuit device according to this embodiment has the antifuse element structure shown in FIG. 26, for example. The essential points of a suitable manufacturing process for obtaining the element structure shown in the figure are as follows. After forming an Al-Cu (0.5%) film (film thickness 400 to 1000 nm) as a lower layer wiring first layer 3A by a sputtering method, amorphous WSi is formed as a lower layer wiring second layer 3B (lower layer electrode BF).
An x film (film thickness 50 to 250 nm) is formed by a sputtering method at a substrate temperature of 450 ° C. or less, and patterned by a conventional method.

Next, the inter-layer insulating film 4 is formed, and the
A connection hole 5 having a diameter of 0.2 to 2.0 μm is opened, and the bottom of the hole is wet-treated with ammoniacal hydrogen peroxide solution. Next, plasma C is used as the anti-fuse insulating film AF.
After forming a silicon nitride film (film thickness: 5 to 20 nm) by the VD method, an Al-Cu (0.5%) film (film thickness:
10-200nm) is deposited.

This antifuse element is used as a lower layer electrode BF.
Immediately after dielectric breakdown with the low potential side, write current 5mA,
Writing was performed at 10 mA, 15 mA, and 20 mA, and after the writing was completed, the voltage was gradually applied to investigate the switch-off phenomenon and the switch-on phenomenon described in the section of the “Embodiment of the Invention”. Figure
29 is an explanatory view showing a part of the investigation result and showing the influence of the write current on the switch-off phenomenon and the switch-on phenomenon. As shown in the figure, when the write current is 5 mA, the switch-off phenomenon occurs with an applied voltage of 1 V or more after writing, but the switch-on phenomenon is not observed. 2.5
The ON resistance sharply decreases near V, but this is a phenomenon called self-healing in which a wire that has been disconnected once becomes conductive again. It is a phenomenon different from the switch-on phenomenon in which the ON resistance drops sharply after the wire breaks. Is. On the other hand, when the write current exceeds 5 mA, the switch-off phenomenon is not observed, and only the switch-on phenomenon appears.

FIG. 30 shows an integrated arrangement of the results shown in FIG.
5 is a graph showing a switch-off phenomenon and a switch-on phenomenon occurring area on a plane with a write current and a current (abbreviated as post-write current) flowing in a conduction path after writing on a coordinate axis. In the figure, a region above the broken line is a switch-off phenomenon occurrence region of a conventional example using an α-Si film as an anti-fuse insulating film, a hatched region is a switch-off phenomenon occurrence region of the present invention, and a solid line curve. The upper area is the area where the switch-on phenomenon occurs in the example of the present invention. As is clear from FIG. 30, in the conventional example, the switch-off phenomenon occurs when the current after writing exceeds the write current value, but in the example of the present invention, the occurrence occurs only when the write current is 5 mA or less,
In addition, when the write current exceeds 5 mA, only the switch-on phenomenon occurs even at the post-write current smaller than the write current, which is a very convenient effect.

As described above, the write current is 5 mA immediately after the dielectric breakdown.
In the antifuse-type semiconductor integrated circuit device of the present invention in which writing is performed as exceeding, the conduction path CW which is not broken even if a current larger than the write current flows thereafter is provided between the upper and lower electrodes in the antifuse element. Can be formed. Furthermore, if writing to the anti-fuse type semiconductor integrated circuit device of the present invention that implements the switch-on phenomenon as shown in FIG. 29 or FIG. It turns out that a significantly low ON resistance is obtained.

That is, the antifuse element mounted on the antifuse type semiconductor integrated circuit device of the third invention is
It is possible to avoid the switch-off phenomenon that often occurs in conventional anti-fuse elements that use an α-Si film as an anti-fuse insulating film, thus improving reliability during device operation and widening the design margin. Since the lower ON resistance value can be realized by dividing the charging into a plurality of times, it has an excellent effect that the performance and reliability of the device can be further improved.

When performing writing a plurality of times, a pulse having a height (maximum current value) or a width (connection time) smaller than that of the first writing pulse may be used from the second time onward.
The effect of reducing the ON resistance is greater when a pulse having a larger width is used. Here, the application of the pulse may be continuously performed without changing the polarity, or may be performed while alternately changing the polarity. (Example 13) This example relates to claim 32 to claim 34, and in the eleventh example, the film thickness of the lower layer electrode BF is set to 50 to 250 nm.
It is disclosed that when the lower layer low potential writing is performed, Al of the lower layer wiring first layer 3A is taken into the conduction path CW and contributes to the reduction of the ON resistance.

FIG. 31 is a graph showing the distribution of the ON resistance of the antifuse element when the film thickness of the lower layer electrode BF (WSix film) is 50 to 250 nm. The writing condition was a constant current writing of 20 mA × 200 ms with a voltage pulse of 10 V applied. In order to secure a loss amount due to etching during the formation of the connection hole and during the above-mentioned wet treatment as a margin, for example, when the film thickness after completion of formation of the lower layer electrode BF is 50 nm, WS
The film thickness of the ix film is 100 nm. From Figure 31,
It can be seen that the ON resistance is distributed in the low range of 5 to 10Ω. If the film thickness of the lower layer electrode BF is less than 50 nm, the surface roughness increases as described above, which is not preferable.

FIG. 32 is a graph showing the distribution of the ON resistance of the antifuse element when the film thickness of the lower layer electrode BF (WSix film) exceeds 250 nm. The writing conditions and the WSix film thickness margin are the same as in the case of FIG. As shown in FIG. 32, the distribution of the ON resistance was reduced to about 10% in the case of 5 to 10Ω, and was distributed in the high resistance range of 20 to 50Ω in the remaining 80%.

In this way, WSix forming the lower electrode BF
By setting the film thickness to 50-250 nm,
Al of the layer 3A was taken into the conduction path CW, and an anti-fuse element having an ON resistance distributed in a low range was obtained. (Embodiment 14) This embodiment relates to the fifth invention. FIG. 33 is a sectional view showing an essential part of an anti-fuse semiconductor integrated circuit device according to the fourteenth embodiment. It should be noted that the same members as those in the above-mentioned drawings are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 33, in the fifth invention,
The lower-layer electrode BF (= lower-layer wiring uppermost layer (fourth layer) 3D) is an Al-containing conductive material having an amorphous structure (Al-T in this embodiment).
a, film thickness 50 nm), the upper electrode TF is an Al-containing conductive material (Al-Cu in this embodiment, film thickness 100 nm), the anti-fuse insulating film AF is a silicon nitride film (in this embodiment a plasma SiNx film, The film thickness is 10 nm).

In this embodiment, in addition to the above characteristics, the lower layer wiring 3 is on the inter-layer insulating film 2 and the first layer 3A to the third layer 3C are Ti film (20 nm) and TiN film (100 nm, respectively).
), An Al-Cu film (film thickness 700 nm), the upper wiring 6 is on the interlayer insulating film (SiO ₂ film, film thickness about 1 μm) 4, and the first layer 6A and the second layer 6B are TiN films, respectively. (Thickness 30 nm), Al-Cu film (thickness 700 nm),
The opening diameter of the anti-fuse element connection hole 5A is about 1 μm.

FIG. 34 shows a histogram of the distribution of ON resistance of the device of the present invention according to Example 14. As can be seen from this, the ON resistance of the device of the present invention shows an extremely low value of 0.9 to 1.4 Ω. The data in the figure shows a breakdown voltage of 13V,
This is obtained by Kelvin contact measurement for the device of the present invention in which writing was performed with a programming current of 10 mA.
FIG. 35 is a histogram of the breakdown voltage distribution of the device of the present invention according to Example 14. As shown in the figure, the dielectric breakdown characteristics of the device of the present invention are extremely uniform.

FIG. 36 is a graph showing the relationship between the dielectric breakdown life and the stress voltage of the device of the present invention according to Example 14.
From the stress voltage of 3.3 V in the normal operation, it can be seen that the device of the present invention has sufficient insulation reliability (reliability for maintaining the OFF state). FIG. 37 is a cross-sectional view of a main part of each manufacturing process of the anti-fuse semiconductor integrated circuit device according to the fourteenth embodiment. It should be noted that the same members as those in the above-mentioned drawings are designated by the same reference numerals and the description thereof will be omitted.

FIG. 37 (a) shows a state in which the film for the lower layer wiring 3 of the above-mentioned material and film thickness is deposited (patterned) on the interlayer insulating film 2 deposited on the substrate 1 (not shown). .
The Al-Ta film for the lower electrode BF is formed by a sputtering method (target material: AlTax (x = 0.05), atmosphere: Ar (5 mto
rr), power: 1 kW). Al-Ta after formation
It was confirmed by X-ray diffraction that the film was amorphous. The amorphous structure has a Ta composition ratio x = 0.01 of the target material.
Obtained from 5 to 0.25.

FIG. 37 (b) shows a state in which the interlayer insulating film 2 including the processed lower layer wiring 3 is covered with the interlayer insulating film 4 and the anti-fuse element connection hole 5A is opened. Figure 37 (c) shows
On the inter-layer insulating film 4 having the anti-fuse element connection hole 5A opened, the anti-fuse insulating film AF having the above-mentioned material and film thickness is formed.
And a state in which a film for the upper layer electrode TF is sequentially deposited and then processed. At this point, formation of the antifuse element is completed.

FIG. 37D shows the upper layer wiring first layer 6 of the above-mentioned material and film thickness on the interlayer insulating film 4 including the anti-fuse element.
2A shows a state in which the second layer 6B is deposited and processed to cover the antifuse element. Thereafter, the final protective film 9 (see FIG. 33) is deposited by a conventional method to form a pad (not shown).

In this embodiment, the antifuse element is provided between the first and second wiring layers, but it may be provided between the second and third wiring layers or on the MISFET. The present invention can be applied to the case where the semiconductor element region is arranged below the interlayer insulating film 2. (Embodiment 15) This embodiment discloses a preferable manufacturing method of the device of the present invention in which the via and the antifuse element coexist in the same layer in the fifth invention.

FIG. 38 is a sectional view showing the main part of each manufacturing process of the antifuse-type semiconductor integrated circuit device according to the fifteenth embodiment.
In the figure, 5A is a connection hole for an anti-fuse element, 5B
Is a via connection hole. It should be noted that the same members as those in the above-mentioned drawings are designated by the same reference numerals and the description thereof will be omitted. The manufacturing process will be described below with reference to FIG. (1) _{On the} interlayer insulating film 2 made of SiO ₂ , the lower layer wiring
An Al-Cu film for the layer 3A is deposited to a thickness of 800 nm, and then an Al-Ta film for the lower wiring second layer 3B (the lower electrode BF) is deposited to a thickness of 50 nm in the same manner as in Example 14 and processed (see FIG. )reference). (2) The interlayer insulating film 4 is deposited in the same manner as in Example 14 to form the anti-fuse element connection hole 5A and the via connection hole 5B (see FIG. 38 (b)). (3) Plasma Si as insulating film AF for anti-fuse
Nx film is deposited to 10 nm, and Al-C for upper layer electrode TF
After the u film is deposited to a thickness of 100 nm to form a laminated film, processing is performed so that the laminated film remains only in the region of the antifuse element (region of the connection hole 5A). At this point, the formation of the anti-fuse element and the pre-via treatment of the via hole 5B are completed (see FIG. 38 (c)). (4) On the entire surface of the interlayer insulating film 4 including the anti-fuse element and the via hole 5B, Ti (20) for the upper wiring first layer 6A is formed.
nm) / TiN (100 nm) laminated film is deposited, and then an Al-Cu film for the upper wiring second layer 6B is deposited to 800 nm to form a laminated film for the upper wiring 6 (see FIG. 38 (d)). (5) The laminated film for the upper wiring 6 is patterned so as to surround the antifuse element (see FIG. 38 (e)).

According to the manufacturing method of this embodiment, the antifuse type semiconductor integrated circuit device having the antifuse element and the via in the same layer can be manufactured by adding only one mask.
FIG. 39 shows the relationship between the film thickness of the Al—Cu film for the upper electrode TF of the antifuse-type semiconductor integrated circuit device and the leakage current density according to the fifteenth embodiment. From the figure, the thickness of the Al-Cu film is
It can be seen that the leakage current density increases when the thickness is less than 50 nm.
At a film thickness of 100 nm, the leakage current density becomes a low value without problems, but a film thickness exceeding 100 nm deteriorates the step coverage. Therefore, the film thickness of the Al-Cu film for the upper layer electrode TF is 50
It is preferably -100 nm.

Data showing the advantage of using an Al-containing conductive film as the upper electrode when the anti-fuse insulating film AF is made of SiNx are shown below. FIG. 40 shows a histogram of the withstand voltage distribution of the SiNx anti-fuse insulating film, where (a) is a TiN film and (b) is an Al film.
Each film was used as a material for the upper layer electrode. From the figure, it can be seen that the withstand voltage is 12 to 13 MV / cm when the conventionally used TiN film is used for the upper layer electrode, and 14 to 15 MV / cm for the Al-containing conductive film upper layer electrode according to the fifth invention. It is lower than cm. This is because in the former case, the capacitance value of the anti-fuse element is about 10% smaller than that in the latter case.
This is because the N film reacts with the SiNx film directly below. Therefore, in the case of a SiNx anti-fuse insulating film, it is preferable in terms of reliability to dispose an Al-containing conductive film as the upper electrode in place of the conventional TiN film. (Embodiment 16) This embodiment relates to the sixth invention. 41 is a cross-sectional view of an essential part of the anti-fuse semiconductor integrated circuit device according to the sixteenth embodiment, FIG.
FIG. 44 shows a cross-sectional view of an essential part of an anti-fuse type semiconductor integrated circuit device after (b) programming) and as a comparative example of the sixteenth embodiment. It should be noted that the same members as those in the above-mentioned drawings are designated by the same reference numerals and the description thereof will be omitted.

In the comparative example shown in FIG. 44, the anti-fuse insulating film AF is formed so as to bite into the wet-processed lower-layer wiring second layer 3B according to the fourth aspect of the present invention. Consists of part of the lower wiring second layer 3B. In the antifuse-type semiconductor integrated circuit device having such a structure, for example, a titanium nitride film for an antireflection film is arranged as the lower layer electrode BF, and a silicon oxide film, a silicon nitride film, a tantalum oxide film as the antifuse insulating film AF. When any one of the films is arranged, Ti in titanium nitride reduces Si and Ta in the film forming the anti-fuse insulating film AF to non-uniformly thin the anti-fuse insulating film AF. The present inventors have found that an unfavorable situation (the reason why such a situation is not desirable is explained in the section “Problems to be solved by the invention”). The sixth invention solves this problem.

As shown in FIG. 41, the sixth aspect of the present invention is an antifuse for which the lower wiring second layer 3B is penetrated to open the connection hole 5 and the lower wiring first layer 3A is used as a base (lower electrode BF). It is different from the comparative example in that the insulating film AF is provided. As is apparent from the figure, the contact area between the anti-fuse insulating film AF and the titanium nitride film (lower wiring second layer 3B) as a reducing factor thereof is greatly reduced by the sixth invention, so the above problem is solved. To do.

FIG. 42 is a sectional view showing the main part of each manufacturing process of the antifuse-type semiconductor integrated circuit device according to the sixteenth embodiment. Figure
The manufacturing process of this device will be described below with reference to FIG. It should be noted that the same members as those in the above-mentioned drawings are designated by the same reference numerals and the description thereof will be omitted. First step: formation of lower electrode (see FIG. 42 (a)) On the inter-layer insulation film 2 is formed by sputtering or CVD.
An Al alloy film (including a simple substance of Al) for the lower layer wiring first layer 3A (a film thickness of about 600 nm) and a titanium nitride film for the lower layer wiring second layer 3B (a film thickness of about 30 nm) are sequentially deposited, followed by a conventional method (photolithography). Technology and etching technology). In this embodiment, the Al alloy film forming the lower wiring first layer 3A serves as the lower electrode BF.

Second Step: Formation of Connection Hole for Anti-Fuse Element (See FIG. 42B) After the interlayer insulating film 4 is deposited on the entire surface of the interlayer insulating film 2 including the lower layer wiring 3 in the same manner as in Example 1, it is necessary. The connection hole 5 is opened at the location. At this time, unlike the first to fifth inventions, the connection hole 5
Opens through the lower wiring second layer 3B (titanium nitride film) to expose the lower wiring first layer 3A (Al alloy film). The preferred etching conditions for opening the connection hole 5 are: CF ₄ / O ₂ (8%) 50 sccm for the interlayer insulating film 4;
0.05 torr, 300 W, BCl ₃ : Ar = for titanium nitride film
It can be removed by 4: 1 100sccm, 0.1torr, 200 ° C. Thereby, the Al alloy film can be exposed on the bottom surface of the opening.

Third step: underlying flattening according to the fourth invention (see FIG. 42 (b)) In this embodiment, this step need not be performed. Fourth step: formation of insulating film for antifuse (see FIG. 42 (c)) The same procedure as in Example 1 is carried out. Fifth step: formation of upper layer electrode (see FIG. 42 (d)) On the anti-fuse insulating film AF, sputtering method or C
By the VD method, an Al alloy film (film thickness for the upper wiring first layer 6A)
600 nm) and a titanium nitride film for the upper wiring second layer 6B (film thickness of about 30 nm) are successively deposited, and they are cut into layers by a conventional method.
In this embodiment, the Al alloy film forming the upper wiring first layer 6A serves as the upper electrode TF. Note that a different metal film (for example, a titanium film) is interposed between the Al alloy film for the upper wiring first layer 6A and the titanium nitride film for the upper wiring second layer 6B for the purpose of wiring reliability and low resistance. Is preferred.

The Al alloy films forming the lower and upper wirings are Co, Ni, Ti, Zr, Nb and M from the viewpoint of improving the reliability of the anti-fuse element by smoothing the surface.
o, Hf, Ta, W, at least one element and Al, Al
It is preferably a compound with any one of —Si and Al—Cu—Si. Sixth step: finishing (see FIG. 41 (a)) A final protective film 9 is deposited so as to cover the interlayer insulating film 4 including the upper wiring 6. (Embodiment 17) This embodiment discloses a more preferable form of the sixth invention. 43 is a sectional view showing the principal part of each manufacturing process of the anti-fuse semiconductor integrated circuit device according to the seventeenth embodiment. In the figure, 30 is a contact prevention insulating film. It should be noted that the same members as those in the above-mentioned drawings are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 43 (c), in this embodiment, the contact prevention insulating film 30 is interposed between the side wall of the titanium nitride film for the lower wiring second layer 3B and the anti-fuse insulating film AF. It differs from Example 16 in the point. By adopting such a configuration, the contact between the titanium nitride film for the lower layer second layer 3B and the insulating film AF for the antifuse is completely cut off.
The effect of the sixth invention is more complete.

In the manufacturing process of the anti-fuse type semiconductor integrated circuit device according to this embodiment, the following steps (1) and (2) are sequentially performed between the third step and the fourth step according to the sixteenth embodiment. Otherwise, it is the same as Example 16. (1) Contact prevention insulating film formation: (see FIG. 43 (a)) The contact prevention insulating film is formed on the entire surface of the interlayer insulating film 4 including the connection holes 5.
Deposit 30. As the contact prevention insulating film 30, ozone T
It is preferable to deposit a silicon oxide film having a good step coverage by the EOS-CVD method with a film thickness of 10 nm, for example. (2) Substrate treatment: (see FIG. 43 (b)) The contact prevention insulating film 30 at the bottom of the connection hole 5 is removed by conventional anisotropic etching, and at least the titanium nitride on the inner surface of the connection hole 5 is covered. The contact prevention insulating film 30 is left. (Embodiment 18) This embodiment discloses a method for manufacturing an antifuse-type semiconductor integrated circuit device according to the seventh invention. Seventh
The object of the invention is to provide a barrier metal film (lower layer wiring first and second layers 3 on the semiconductor substrate 1 as shown in FIG. 37 (d), for example.
In the lower layer wiring 3 in which an Al alloy film (lower layer wiring third layer 3C) is arranged on (A, 3B), the anti-fuse insulating film AF underlying layer due to the orientation of Al (the property that easily follows the surface shape of the underlying layer) This is to solve the problem of flatness deterioration (the barrier metal film has sharp projections on its surface as described above, so Al as the lower layer electrode BF arranged thereon also follows that shape).

45 (a) and 45 (b) are sectional views of the essential portion of the device of the present invention according to the eighteenth embodiment, where (a) shows the state before programming and (b) shows the state after programming. In the figure, 40
Is a plug, 41 is a first barrier metal, 42 is a second barrier metal, and 43 is a third barrier metal. It should be noted that the same members as those in the above-mentioned drawings are designated by the same reference numerals and the description thereof will be omitted. As shown in the figure, the problem is to lay an interlayer insulating film 2 having no sharp protrusions on the surface, instead of laying a barrier metal film directly under the lower layer wiring 3 made of an Al alloy film, Electrical connection between the upper and lower conductive layers (the substrate 1 and the Al alloy film lower layer electrode 3) of the interlayer insulating film 2 can be achieved by providing a plug 40 made of barrier metal (41, 42, 43). In addition,
Since the conduction path CW is formed of a metal film formed by mutual diffusion of Al and the refractory metal element in the upper and lower electrodes (TF, BF) and the component element in the anti-fuse insulating film AF,
Low ON resistance and excellent EM resistance.

FIG. 46 is a sectional view showing the principal part of each step of manufacturing the device of the present invention according to the eighteenth embodiment. It should be noted that the same members as those in the above-mentioned drawings are designated by the same reference numerals and the description thereof will be omitted. The manufacturing process will be described below with reference to FIG. (1) The substrate 1 is covered with an interlayer insulating film 2 (for example, a silicon oxide film) to a film thickness of about 1.0 μm (see FIG. 46 (a)). (2) The connection hole 5 is opened, and the first to third barrier metals 41 to 43 are sequentially deposited on the interlayer insulating film 2 including the connection hole 5. Connection hole 5
Is opened to a diameter of 1.0 μm by using photolithography technology and etching technology. First and second barrier metal 4
The Ti film (thickness: about 20 nm) and the TiN film (thickness: about 100 nm) formed by the sputtering method are used for 1, 42, and the W film (thickness: about 800 nm) formed by the metal CVD method is used for the third barrier metal. Good (see FIG. 46 (b)). (3) The third to first barrier metals 43 are formed by RIE (Reactive Ion Etching) until the surface of the interlayer insulating film 2 is exposed.
Etch back ~ 41. Then, an Al film or an Al alloy film for the lower layer wiring 3 is further deposited thereon by a sputtering method and patterned (see FIG. 46 (c)). At this stage, formation of the plug 40 that electrically connects the substrate 1 and the lower layer wiring 3 is completed. In this embodiment, part of the lower layer wiring 3 becomes the lower layer electrode BF. (4) The interlayer insulating film 4 is deposited on the entire surface of the interlayer insulating film 2 including the lower layer wiring 3 in the same manner as in (1) and (2) above, and the anti-fuse element connection hole 5A is opened (see FIG. See d)). (5) The anti-fuse insulating film AF is formed in the same manner as in the fourth step of Example 1 (see FIG. 46 (e)). Since the base of the anti-fuse insulating film AF is an Al film or an Al alloy film whose surface is also flattened because it is arranged not on the barrier metal having poor flatness but on the interlayer insulating film 2 having good flatness. The insulating film AF for antifuses has a good film quality and a low defect density. (6) An Al alloy film for the upper wiring 6 is deposited on the entire surface of the anti-fuse insulating film AF covering the interlayer insulating film 4 by the sputtering method or the CVD method, and is cut along with the anti-fuse insulating film AF. At this stage, formation of the anti-fuse element is completed. And the interlayer insulating film 4 including the upper wiring 6
A final protective film 9 is deposited on the entire surface of the. (See FIG. 45 (a)).

[0164]

As described above, according to the present invention, the absolute value and variation of the ON resistance of the conductive path are extremely small, and both the electrical connection and the insulation separation between the upper and lower electrodes can be surely achieved. Since the anti-fuse element with improved EM resistance in the conduction path can be arranged in the area of a plurality of connection holes with uniform quality, reliability in circuit operation, high speed operation, low breakdown voltage, low operation voltage The anti-fuse type semiconductor integrated circuit device having excellent adaptability to long-term use and long-term reliability can be provided.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a main part of an anti-fuse type semiconductor integrated circuit device according to a first embodiment, (a) showing before programming and (b) showing after programming.

FIG. 2 is a cross-sectional view of a main part of each manufacturing process of the anti-fuse semiconductor integrated circuit device according to the first embodiment.

FIG. 3 is a graph showing a relationship between a composition ratio of N in a titanium nitride film and a mixed gas ratio.

FIG. 4 is a graph showing the relationship between the composition ratio of Ti in the titanium nitride film and the ON resistance ((a) distribution, (b) average value).

5A and 5B are graphs showing a surface shape of a lower layer electrode as a cross-sectional curve, in which FIG. 5A shows a wet treatment and FIG. 5B shows a non-wet treatment.

FIG. 6 is a graph showing the relationship between the presence or absence of wet treatment and the distribution of dielectric breakdown voltage.

FIG. 7 is a graph showing the relationship between the W content of the lower layer electrode and the W content of the conducting path.

FIG. 8 is a graph showing the relationship between the W content of the conductive path and the EM resistance.

FIG. 9 is a W composition ratio of a lower layer electrode made of tungsten silicide and an ON resistance ((a) distribution, (b) of a lower layer low potential writing element).
It is a graph which shows the relationship with an average value.

FIG. 10 is the crystal grain size of the lower electrode and the life of the insulating film for the anti-fuse that leads to dielectric breakdown ((a) distribution, (b) variation)
It is a graph which shows the relationship with.

FIG. 11 is a center line average roughness Ra of a lower layer electrode and a life ((a) distribution, (b) until dielectric breakdown of an insulating film for an anti-fuse)
(Variation) is a graph showing the relationship.

FIG. 12 is a solid angle of a crystal grain of a specific size on the surface of the lower electrode and a life until dielectric breakdown of the anti-fuse insulating film ((a)).
3 is a graph showing a relationship between distribution and (b) variation).

FIG. 13 is a cross-sectional view of a main part of each manufacturing process of the anti-fuse semiconductor integrated circuit device according to the third embodiment.

FIG. 14 is a cross-sectional view of a main part of each manufacturing process of the anti-fuse semiconductor integrated circuit device according to the fourth embodiment.

FIG. 15 is a cross-sectional view of a main part of each manufacturing process of the anti-fuse semiconductor integrated circuit device according to the fifth embodiment.

FIG. 16 is a graph showing a relationship between a titanium silicide composition ratio and a silicidation temperature.

FIG. 17 is a graph showing the relationship between titanium silicide composition ratio and ON resistance.

FIG. 18 is a graph showing the flatness of the surface of the lower layer electrode which has been subjected to the wet treatment.

FIG. 19 is a graph showing the relationship between the presence or absence of wet treatment and the distribution of dielectric breakdown voltage.

FIG. 20 is a cross-sectional view of a titanium silicide film having hemispherical protrusions on its surface.

FIG. 21 is a cross-sectional view of a main part of each manufacturing process of the anti-fuse semiconductor integrated circuit device according to the eighth embodiment.

22A and 22B are cross-sectional views of a main part of each manufacturing process of the anti-fuse semiconductor integrated circuit device according to the ninth embodiment.

FIG. 23 is a cross-sectional view of a main part of each manufacturing process of the anti-fuse semiconductor integrated circuit device according to the tenth embodiment.

FIG. 24 is a main-portion cross-sectional view of the anti-fuse semiconductor integrated circuit device according to the eleventh embodiment.

FIG. 25 is a cross-sectional view of a main part of each manufacturing process of the anti-fuse semiconductor integrated circuit device according to the eleventh embodiment.

FIG. 26 is a cross-sectional view of essential parts of the anti-fuse element according to Example 11.

FIG. 27 is a graph showing the relationship between ON resistance and programming current, in which (a) is a lower layer electrode and (b) is an upper layer electrode on the low potential side, and a voltage is applied.

FIG. 28 is a graph showing the influence of write voltage polarity on EM resistance.

FIG. 29 is an explanatory diagram showing the influence of the write current on the switch-off phenomenon and the switch-on phenomenon.

FIG. 30 is a graph showing a region where a switch-off phenomenon and a switch-on phenomenon occur.

FIG. 31 is a graph showing the distribution of ON resistance of the anti-fuse element when the film thickness of the lower layer electrode is 50 to 250 nm.

FIG. 32 is a graph showing the distribution of ON resistance of the anti-fuse element when the film thickness of the lower layer electrode exceeds 250 nm.

FIG. 33 is a cross-sectional view of essential parts of the anti-fuse semiconductor integrated circuit device according to the fourteenth embodiment.

34 is a histogram of the distribution of ON resistance of the device of the present invention according to Example 14. FIG.

FIG. 35 is a histogram of distribution of dielectric breakdown voltage of the device of the present invention according to Example 14.

FIG. 36 is a graph showing the relationship between the dielectric breakdown life and the stress voltage of the device of the present invention according to Example 14.

FIG. 37 is a cross-sectional view of a main part of each manufacturing process of the anti-fuse semiconductor integrated circuit device according to the fourteenth embodiment.

FIG. 38 is a cross-sectional view of a main part of each manufacturing process of the anti-fuse semiconductor integrated circuit device according to the fifteenth embodiment.

FIG. 39 is a graph showing the relationship between the film thickness of the Al—Cu film for the upper-layer electrode TF and the leakage current density according to the fifteenth embodiment.

[Fig. 40] Fig. 40 is a histogram of the distribution of the withstand voltage of the SiNx anti-fuse insulating film, in which (a) shows Ti.
The N film and (b) are Al films used as the materials of the upper layer electrodes.

41A and 41B are cross-sectional views of an essential part of the anti-fuse semiconductor integrated circuit device according to the sixteenth embodiment, where FIG. 41A shows before programming and FIG.

FIG. 42 is a cross-sectional view of a main part of each manufacturing process of the anti-fuse semiconductor integrated circuit device according to the sixteenth embodiment.

43A and 43B are cross-sectional views of a main part of each manufacturing process of the anti-fuse semiconductor integrated circuit device according to the seventeenth embodiment.

FIG. 44 is a main-portion cross-sectional view of an anti-fuse semiconductor integrated circuit device as a comparative example of Example 16;

45A and 45B are cross-sectional views of the essential parts of the device of the present invention according to Example 18, (a) showing the state before programming and (b) showing the state after programming.

FIG. 46 is a sectional view of a key portion for each manufacturing step of the device of the present invention according to Embodiment 18.

[Explanation of symbols]

 BF Lower layer electrode AF Anti-fuse insulating film TF Upper layer electrode CW Conducting path 1 Semiconductor substrate (substrate) 2,4,26 Interlayer insulating film 3 Lower layer wiring (first layer wiring) 3A Lower layer wiring First layer (bottom layer) 3B Lower layer Wiring 2nd layer 3C Lower wiring 3rd layer 3D Lower wiring 4th layer (uppermost layer) 5 Connection hole 5A Antifuse element connection hole 5B Via connection hole 6 Upper layer wiring (2nd layer wiring) 6A Upper layer wiring 1st layer (Bottom layer) 6B Upper layer second layer 6C Upper layer third layer 7 Nest (void) 9 Final protective film 10 P-type well 11 N-type well 12 Element separator 13 Channel stopper region 14 Gate insulating film 15 Gate electrode 15A Gate Electrode 1st layer (bottom layer) 15B Gate electrode 2nd layer 16 Sidewall spacer 17 n-type semiconductor region 18 p-type semiconductor region 22 Ti film 23 Titanium silicide film 25 Wiring 25A Si film 25B Ti film 25 Titanium silicide film 27 source and drain lines (titanium silicide film) 27A Si film 27B Ti film 30 contact preventing insulating film 40 plugs 41 first barrier metal 42 and the second barrier metal 43 third barrier metal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication H01L 27/04 21/822 27/10 431 H01L 21/90 B 27/04 P (31) Priority Claim No. Japanese Patent Application No. 6-195690 (32) Priority Date No. 6 (1994) August 19 (33) Country of priority claim Japan (JP) (31) Priority claim number Japanese Patent Application No. 6-235057 (32) Priority Hihei 6 (1994) September 29 (33) Priority claiming country Japan (JP) (31) Priority claim number Japanese Patent Application No. 6-235058 (32) Priority Day Hei 6 (1994) September 29 (33) ) Priority claiming country Japan (JP) (31) Priority claiming number Japanese Patent Application No. 6-235059 (32) Priority date Hei 6 (1994) September 29 (33) Priority claiming country Japan (JP) (72) Inventor Yoshitaka Kimura 2-3-2 Uchisaiwaicho, Chiyoda-ku, Tokyo Within Kawasaki Steel Works (72) Inventor Chie Tsutsui Chiyoda-ku, Tokyo 2-3-2 Saiwaicho Kawasaki Steel Co., Ltd. (72) Inventor Yoyo Ota 2-3-3 Uchimachi Kawasaki, Tokyo (72) Inventor Takayuki Komiya Chiyoda-ku, Tokyo 2-3 2-3 Uchisaiwaicho Kawasaki Steel Works Ltd.

Claims (42)

[Claims] 1. An anti-fuse type semiconductor integrated circuit device, wherein the lower layer electrode is made of a conductive material having an amorphous structure. 2. The anti-fuse type semiconductor integrated circuit device according to claim 1, wherein the upper electrode is made of a conductive material having an amorphous structure. 3. The antifuse-type semiconductor according to claim 1, wherein the conductive material having an amorphous structure is an element or compound shown in any one of the following (1) to (10). Integrated circuit device. (1) First element group (Co, Ni, Cu, Ti, Z
r, Nb, Mo, Hf, Ta, W) A compound composed of two or more elements selected from the group consisting of: (2) an element of the first element group or a compound consisting of two or more kinds selected from these, and a second element group (S
i, B, N, C, Ge, As, P, Sb) and a compound formed with one or more elements. (3) A compound (Y-La) of an element of the third element group (Y, La). (4) A compound formed of Al and an element of the first element group or a compound of two or more kinds selected from these. (5) A compound formed by an element of the third element group or a compound thereof and Al. (6) A compound formed by an element of the first element group or a compound consisting of two or more kinds selected from these, an element of the third element group, and Al. (7) A compound formed by an element of the fourth element group (Au, Pt, Pd, Ag) and an element of the second element group or a compound consisting of two or more kinds selected from these. (8) An element of the first element group or a compound consisting of two or more kinds selected from these elements, and a fourth element group (A
u, Pt, Pd, Ag) and the compound formed. (9) A compound formed by an element of the third element group or a compound thereof and an element of the fourth element group. (10) A compound formed by an element of the first element group or a compound consisting of two or more kinds selected from these, an element of the third element group, and an element of the fourth element group. 4. The composition ratio of the metal in the compound formed of the metal element and the non-metal element of the conductive material having the amorphous structure is higher than the stoichiometric composition. Antifuse type semiconductor integrated circuit device. 5. The conduction path has one of a lower layer electrode and an upper layer electrode,
W, Ta, Nb, Mo formed by applying a breakdown voltage with one containing at least one of W, Ta, Nb, and Mo as the lower potential side, and transferred from the electrode on the lower potential side. 4. The anti-fuse type semiconductor integrated circuit device according to claim 3, comprising at least one of the above. 6. The anti-fuse type semiconductor integrated circuit device, wherein the lower layer electrode is made of metal silicide in which the composition ratio of metal is higher than the stoichiometric composition. 7. The metal silicide is formed after the metal film is formed.
7. The anti-fuse type semiconductor integrated circuit device according to claim 6, wherein the anti-fuse type semiconductor integrated circuit device is silicided in a temperature range of 00 to 700.degree. 8. The metal in the metal silicide is Ti,
Ta, Nb, Zr, Y, Hf, Al, W, Mo, V, C
8. The antifuse-type semiconductor integrated circuit device according to claim 6, which is any one of o, Ni, Pd, and Pt. 9. The antifuse-type semiconductor integrated circuit device according to claim 7, wherein the crystal grain size of the metal silicide is 20 nm or less. 10. The anti-fuse type semiconductor integrated circuit device according to claim 7, wherein the center line average roughness value Ra of the surface of the metal silicide is 2.0 nm or less. 11. The surface of the metal silicide is 1 nm to
8. The anti-fuse type semiconductor integrated circuit device according to claim 7, wherein the solid angle of the protrusion in the crystal grain having a size in the range of 1 μm is in the range of 1.8π to 2.0π. 12. The upper layer electrode is made of titanium silicide having a Ti composition ratio of 40% or more.
An antifuse-type semiconductor integrated circuit device according to claim 1. 13. The antifuse-type semiconductor integrated circuit device according to claim 6, wherein the upper layer electrode is made of titanium nitride having a Ti composition ratio of 55% or more. 14. The conductive path is formed by applying a breakdown voltage with the lower layer electrode on the lower potential side, and contains a metal transferred from a metal silicide of the lower layer electrode. 7. An anti-fuse type semiconductor integrated circuit device according to item 6. 15. The antifuse-type semiconductor integrated circuit device, wherein the lower layer electrode is made of a conductive material containing a high melting point metal, and the upper layer electrode is made of a low melting point metal having a resistance value lower than that of the high melting point metal. 16. The low melting point metal is Al, Al alloy, Cu,
16. The anti-fuse type semiconductor integrated circuit device according to claim 15, which is one of Ag. 17. The Al alloy is Si, Cu, Sc, Pd,
17. The anti-fuse type semiconductor integrated circuit device according to claim 16, comprising at least one selected from Ti, Ta and Nb. 18. The conductive material containing a refractory metal is Ti,
1 selected from Zr, Hf, V, Nb, Ta, Mo, W
Claim 15 or 16 characterized in that the seed is a component
An antifuse-type semiconductor integrated circuit device according to claim 1. 19. The conductive material containing a refractory metal is Ti,
1 selected from Zr, Hf, V, Nb, Ta, Mo, W
19. The antifuse-type semiconductor integrated circuit device according to claim 18, wherein the antifuse-type semiconductor integrated circuit device is a silicide formed of a seed and Si. 20. The main component of the conducting path is Al or Ti,
1 selected from Zr, Hf, V, Nb, Ta, Mo, W
16. An Al compound of a seed element.
Alternatively, the antifuse-type semiconductor integrated circuit device according to item 16. 21. The Al compound is TiAl ₃ , ZrA
l ₃ , HfAl ₃ , VAl ₃ , NbAl ₃ , TaA
21. The antifuse-type semiconductor integrated circuit device according to claim 20, which is one of l ₃ , MoAl ₁₂ , and WAl ₁₂ . 22. The anti-fuse type semiconductor integrated circuit device according to claim 18, wherein the lower layer electrode has an amorphous structure or a crystal structure having a crystal grain size of 20 nm or less. 23. The diffusion prevention film for preventing diffusion of a low melting point metal is interposed between the upper layer electrode and the wiring formed on the upper layer electrode. 7. An anti-fuse type semiconductor integrated circuit device according to. 24. The diffusion prevention film comprises Ti, Ta, Zr, Hf,
24. The anti-fuse type semiconductor integrated circuit device according to claim 23, which is made of one element selected from V, Nb, Mo, W and Pt, a nitride or a silicide of the element, or TiW. 25. The film thickness of the upper layer electrode is thicker than the film thickness of the anti-fuse insulating film, and is less than the film thickness of the wiring formed on the upper layer electrode and electrically connected to the upper layer electrode, or the anti-fuse connection. 25. The anti-fuse type semiconductor integrated circuit device according to claim 15, 16, 23 or 24, characterized in that the diameter is 1/2 or less of the effective opening diameter of the hole. 26. The conductive path is formed by applying a breakdown voltage with the upper layer electrode on the lower potential side, and contains a low melting point metal transferred from the upper layer electrode. An antifuse-type semiconductor integrated circuit device according to claim 1. 27. The anti-fuse type semiconductor integrated circuit device according to claim 26, wherein the conductive path also includes a refractory metal transferred from the upper layer electrode. 28. The conductive path is formed by applying a breakdown voltage with the lower layer electrode on the lower potential side, and contains a refractory metal transferred from the lower layer electrode. An antifuse-type semiconductor integrated circuit device according to claim 1. 29. The conductive path is formed by applying a voltage between the upper and lower layer electrodes to cause a dielectric breakdown of the anti-fuse insulating film, and immediately after that, a current larger than 5 mA is applied to the dielectric breakdown portion. 16. The antifuse-type semiconductor integrated circuit device according to claim 15. 30. The antifuse-type semiconductor integrated circuit device according to claim 29, wherein the voltage and current are applied with the lower layer electrode on the lower potential side. 31. The antifuse-type semiconductor integrated circuit device according to claim 29, wherein the application of the current is performed in a plurality of times. 32. The anti-fuse type semiconductor integrated circuit device according to claim 22, wherein the lower layer electrode is arranged immediately above the conductive layer containing a low melting point metal. 33. The antifuse-type semiconductor integrated circuit device according to claim 32, wherein the film thickness of the lower layer electrode is 50 to 250 nm. 34. The conduction path is formed by applying a breakdown voltage with the lower electrode on the lower potential side, and is transferred from the refractory metal transferred from the lower electrode and the conductive layer directly below the lower electrode. 34. The anti-fuse type semiconductor integrated circuit device according to claim 32 or 33, further comprising a low melting point metal. 35. The interface between the anti-fuse insulating film and the lower electrode removes oxide or nitride existing on the surface of the lower electrode before forming the insulating film in the connection hole, and further removes the lower electrode in the depth direction. It is the lower interface of the new oxide film that was uniformly formed on the front surface while removing, and the insulating film for the anti-fuse is
16. The antifuse-type semiconductor integrated circuit device according to claim 1, 6 or 15, comprising the new oxide film and an insulating film further formed thereon. 36. The anti-fuse type semiconductor integrated circuit device according to claim 35, wherein the new oxide film is formed by a wet process using an ammoniacal hydrogen peroxide solution. 37. The antifuse-type semiconductor integrated circuit device according to claim 1, wherein the lower layer electrode and the upper layer electrode are made of a conductive material containing Al, and the insulating film for antifuse is a silicon nitride film. 38. After removing the upper layer electrode and the anti-fuse insulating film from the region of the via connection hole in which the anti-fuse element is temporarily arranged, the upper-layer wiring related to the anti-fuse element and the upper-layer wiring related to the via exist there. 38. The anti-reflective film according to claim 37, which is formed at the same time in a via forming step of forming a via, and is formed of a laminated film of a conductive layer containing a refractory metal and a conductive layer containing Al immediately above the conductive layer. Fuse type semiconductor integrated circuit device. 39. The conductive layer containing a refractory metal is formed of a single-layer film of any one of titanium nitride, TiW, tantalum nitride, and TaW, or a laminated film of the single-layer film and a Ti film immediately below the single-layer film, 39. The antifuse-type semiconductor integrated circuit device according to claim 38, wherein the film thickness of the upper layer electrode filling the space between the conductive layer and the antifuse insulating film is 50 nm or more. 40. The lower layer wiring is composed of an Al alloy film having a titanium nitride film on the uppermost layer, and the lower layer electrode removes the titanium nitride film on the uppermost layer of the lower layer wiring in the depth direction at the bottom of the connection hole. The exposed Al alloy film, the anti-fuse insulating film is a silicon oxide film, a silicon nitride film or a tantalum oxide film, or a composite film of these, and the upper electrode is
An antifuse-type semiconductor integrated circuit device, wherein at least the lowermost layer is an Al alloy film and is a contact portion of an upper layer wiring to an insulating film for antifuse. 41. A contact prevention insulating film is provided between a side wall of the titanium nitride film appearing in the connection hole and the insulating film for antifuses so as to prevent contact between these films. Antifuse type semiconductor integrated circuit device. 42. The lower-layer electrode is a contact portion of the lower-layer wiring composed of a single-layer film of Al or Al alloy with the anti-fuse insulating film, and the anti-fuse insulating film is a silicon oxide film or a silicon nitride film. Alternatively, it is made of a tantalum oxide film or a composite film thereof, and the upper electrode is made of Al or A.
l alloy and the lower layer wiring is located immediately above an insulating film formed to cover the substrate, and a barrier metal composite film formed in contact with the substrate in a connection hole penetrating the insulating film is interposed. An antifuse-type semiconductor integrated circuit device characterized by being electrically connected to a substrate.