JPH0748796B2 - Image signal correction method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention is intended to correct an image by sharpening or smoothing a recorded image in an image scanning recording apparatus such as a scanner for printing plate making or a facsimile machine. The present invention relates to an image signal correction method.

(Prior Art) First, an example of a conventional image scanning recording apparatus to which the present invention can be applied will be briefly described with reference to FIG.

FIG. 6 shows the configuration of an original image reading system and a recording system of this image scanning recording apparatus.

In this figure, 31 is an Ar laser light source for both recording and reading, which emits a randomly polarized light beam. After the once separated into a read beam B ₂ of the s-polarized light of the recording beams B ₁ and p-polarized light light beam at beam splitter 32 from the laser light source 31, through the recording beams B ₁ to the optical modulator 33, the reading beam
It is combined by B ₂ and the half mirror 34 and sent to a galvano mirror 35 which is a scanning optical system, converted into one-dimensional scanning light by this galvano mirror 35 and made incident on a next light beam splitting system 36. Here, it is again divided into a recording beam B ₁ and a reading beam B _2, and the recording beam B ₁ is sent to the recording device 37 to record on the recording material.

On the other hand, the reading beam B ₂ is directed toward the document 38 and acts as a scanning beam to scan the surface of the document 38. This scanning direction is the main scanning direction.

The document 38 is conveyed by a suitable feeding means in the direction shown by the arrow orthogonal to the main scanning direction. The transport direction of this document is the sub-scanning direction.

Therefore, the scanning beam two-dimensionally scans the original image of the document 38 in the main and sub-scanning directions. By this scanning, an image signal is obtained by a light receiving system including an optical fiber 39 and a photoelectric conversion block 40 which are arranged to receive the reflected light or the transmitted light of the scanning beam, and the image signal is amplified by an amplifier 41 to control the circuit.
Supply 50.

On the other hand, in the light beam splitting system 36, a part of the reading beam B ₂ is taken out and sent to the grating 42, the light that has passed through the grating 42 is converted into an electric signal by the photoelectric converter 43, and further amplified by the amplifier 44. The grid signal synchronized with the scanning of the original is taken out and the grid signal is supplied to the I / O interface 51 in the control circuit 50.

The I / O interface 51 generates a clock signal with the lattice signal as a reference, supplies the clock signal to the drive circuit 45 of the galvanometer mirror 35, the first signal processing circuit 52 in the control circuit 50, and the line memory device. 53, the second signal processing circuit 54 and the halftone image forming apparatus 55. The interface 51 and each of these circuits 51 to 55 are connected to a central processing unit 57 via a bus line 56, and various controls are performed according to commands from the central processing unit 57. There is.

The image signal supplied to the control circuit 50 is the first signal processing circuit.
After performing A / D conversion, gradation modulation, and shading correction at 52, the line memory device 53 stores the data. The image signal read from the line memory device 53 is subjected to image sharpness correction by the second signal processing circuit 54 using a method described later, and then the image signal is guided to the halftone dot image forming device 55 to generate the halftone dot image signal. Then, the halftone dot image signal is formed and supplied to the light modulator driver 46. In response to this halftone image signal, the optical modulator driver 46
From the optical modulator 33, a modulation signal is applied to modulate the recording beam B ₁ from the laser light source 31, so that the image information whose sharpness is corrected can be recorded on the recording material in the recording device 37.

By the way, the sharpness correction method performed in such an image scanning recording apparatus is performed by the line memory device 53 and the second signal processing circuit 54, and the image signals arranged two-dimensionally are processed. A pixel matrix area (hereinafter referred to as “window”) of a predetermined n rows and n columns centering on the pixel to be corrected is set, and the correction amount S for the pixel information at the center position in this window is, for example, S = n ² amm- (a11 + a12 ... + a1n + a21 + ... + ann) (1) However, m = (n + 1) / 2 amm: image information of the central pixel a11 to ann: pixel information of each pixel in the window .

In the calculation, all the image information a11 to ann of n × n pixels in the window are temporarily stored in the line memory in the line memory device 53, and then these image information are sequentially read out, and first, (A11 + a12 + ... a1n + a21 + ...) of equation (1)
+ Ann) is calculated, then the correction amount S is obtained by computer processing based on the equation (1), and the center pixel signal of the original image is corrected by this correction amount S.

(Problems to be Solved by the Invention) However, as is well known, image signals obtained by two-dimensionally scanning an original are arranged in time series. It is impossible to calculate (a11 + a12 + ... a1n + a21 + ... + ann) until all the lines of the above are sequentially written in the corresponding line memories. Moreover, it is not possible to write to the line memory and read from the line memory at the same time, which is why after writing the image information of all the pixels in the window to the line memory as in the conventional method described above. The method of performing the arithmetic processing of the equation (1) has a drawback in that the arithmetic processing takes a long time and high-speed image processing cannot be achieved.

(Means for Solving Problems) The present invention relates to an image signal obtained by scanning an original image,
A window of n × n pixel matrix (where n is an odd number) is set, and a correction amount S for the image information amm at the center position of the window is calculated by a predetermined calculation formula S = n ² based on all pixel information in the window. a _mm −Σa _ij (where Σa _ij is an added value of the image information of all pixels in the window), and the image information amm of the center pixel of the window is corrected according to the correction amount S. In the signal correction method, the image information of the pixels of each line arranged on the same column in the window is counted from the latest addition value of the sequential addition values obtained by adding for each column. The added value obtained by adding (n + 1) times before is subtracted, the subtracted value is led to the latch circuit through the adder and latched, and the latched value is fed back to the adder to sequentially output the subtracted value. By adding, the added value Σa _ij is obtained, while After selectively branching the center image information a _mm of the window, n of the image information a _mm that can be placed at the center position of the window
^Double value, simultaneously with the image information? A _ij, obtained from the n ² a _mm value and the image information? A _ij the said correction amount S by using the _{^{S = (n 2 a mm -Σa}} ij) Characterized by seeking.

(Description of Embodiments) Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 (A) is a block diagram for explaining the embodiment of the present invention and corresponds to the line memory device 53 and the second signal processing circuit 54 in the image scanning recording apparatus of FIG.

Now, a case will be described in which a window including a pixel matrix of n rows and n columns centering on a pixel to be corrected is set for a two-dimensionally arranged image signal. In this case, n is an odd number, the column direction corresponds to the main scanning direction and the line direction, the row direction corresponds to the sub-scanning direction and the line direction, and the row direction corresponds to the sub-scanning direction. Corresponds to the number of lines.

Reference numeral 1 denotes a data signal input terminal, which is an A / D converter for an image signal obtained by two-dimensionally scanning an image of a document 37 or the like.
A signal obtained by performing conversion, gradation conversion, and shading correction is supplied. 2a to 2p are line memories 3 respectively
And the multiplexer 4, the number of P line memory devices is set to be one more than the maximum number N of lines in the maximum window size to be set.

Reference numeral 5 denotes a control unit which is controlled by a clock signal generated with reference to the lattice signal, and controls various line memory devices 2a to 2p such as a write / read selection signal, a write signal, and a read signal from the control unit 5. Control signal.

With this control signal, P (Pn, n is an odd number) line memory devices required to obtain a desired maximum window size.
One of 2a to 2p is cyclically used for sequential writing and the rest is used for reading. Then, the line memory device including the line memory device in which the writing is finished immediately before the line memory device in the process of writing is counted in the reverse order of the writing order and the number n of line memory devices corresponding to the number n of lines in the window size to be set. If the read pixel information of (1) is sequentially and simultaneously guided to the adder, the writing and reading processes of the line memory device can be simultaneously performed in parallel, so that these processes can be performed in real time.

Reference numerals 6a to 6p are used to selectively output the read pixel information of the line memory devices 2a to 2p to the adder 7 by selectively outputting the output of n line memory devices corresponding to the number n of lines in a desired window size. There are P gate circuits. That is,
In each of these gate circuits 6a to 6p, the line memory device that has just been written immediately before the line memory device that is being written is counted in the reverse order from the write order, corresponding to the number n of window-sized lines to be set. In order to selectively conduct the read pixel information of n line memory devices up to the line memory device written n times before, to n gate circuits leading to the adder 7 all at once. The circuit is controlled by the control signal from the control unit 5.

In this way, the pixel information from the selected n line memory devices is arranged in the column direction of the pixel matrix of the n × n pixel information in the window of the size set by the selection of the gate circuits 6a to 6p as described above. The pixel information arranged in the (sub-scanning direction) is added by the adder 4, and this addition is
The pixel rows in the row direction (main scanning direction) are sequentially performed a total of n times.

FIG. 1B shows a write line selection signal for selecting a write line memory, a gate signal for selectively turning on the gate circuits 6a to 6p all at once, and a line memory output corresponding to the central row of the window. A center row select signal for controlling the multiplexer 14 to selectively fetch, and each multiplexer in each line memory device 2a to 2p
7 is a block diagram showing a configuration example of a main part in a control unit 5 for obtaining each of a write address signal and a read address signal for controlling 14. FIG.

In the figure, 24 is P for counting the line block pulses.
A line memory device with a line counter, for example
A count value incremented by +1 or -1 is generated every time an image signal for one line is cyclically written into 2a to 2p. By adding this count value to the first decoder 25, one of the sequential line memory devices 2a to 2p corresponding to the count value is sequentially and cyclically written into a memory as shown in Table 1 below. A write line selection signal to be selected as is obtained.

At the same time, by adding the count value of the line counter 24 to the second decoder 26 together with the window size designation signal, as shown in Tables 2 to 5 below, a window of designated n × n pixels is displayed. A gate signal for selectively simultaneously turning on n gate circuits corresponding to the size according to the count value, and an output of each line memory device led to the gate circuit turned on by these gate signals, A center row selection signal for extracting the pixel information of the center row in the specified window size is obtained.

Reference numeral 27 is a read address counter, and 28 is a write address counter, which increments or decrements the output address by +1 or -1 each time the data read of one pixel is completed or the data write of one pixel is completed by the read clock signal and the write clock signal. , A read address and a write address are output, and are reset to the initial values each time one line is read and each write is completed.

Read address counter 27 and write address counter
The read address signal and the write address signal from 28 are commonly supplied to each of the memory devices 2a to 2p, and only the line memory device selected by the write line selection signal is input using the write address signal. Image signals are stored, and the remaining line memory devices that have not been selected have their stored values read by the read address signal.

Further, in FIG. 1A, dividers 8a to 8p are inserted between the input side of the adder 7 and the output sides of the line memory devices 2a to 2p as shown in FIG. By dividing the digitalized image information to be input by an appropriate divisor, the lower bits of the digitized signal representing the image information are removed, and the fluctuation of the lower bits due to the influence of noise is added to the added value. I try not to affect it.

The added value V for each column of the image information of the n pixels arranged in one line in the sub-scanning direction in the window added by the adder 7 is provided corresponding to the number of pixels in the main scanning direction of the window. A register of stages, that is, in this embodiment, the number N of pixels in the main scanning direction in the maximum window is set to 11, and P = 11 + 1
The output of the adder 7 is guided to the first shift register 9 having 12 stages V1 to V12 and sequentially stored.

Reference numerals 10a to 10d denote multiplexers for selecting the (n + 1) th stage register determined by the size of the n × n pixel matrix of the window to be set and extracting the output. In this embodiment, by selectively operating these multiplexers 10a to 10d from the outside, 5 × 5, 7 × 7,
6th corresponding to each window setting of 9x9, 11x11,
The memory values vi of the eighth, tenth and twelfth registers V6, V8, V10 and V12 are selected and read. In this example, four multiplexers are provided, but more multiplexers may be provided depending on the size of the window. The stored value vi retrieved via any of those multiplexers 10a-10d in relation to the setting of the window is supplied to the subtractor 11.

On the other hand, the latest storage value v ₁ stored in the register V 1 of the first stage of the first register 9 is supplied to the subtractor 11, and from this storage value v ₁ to the storage value vi of the (n + 1) th stage. Is subtracted to calculate a subtraction value v.

By inputting and adding the subtraction value v to the adder, it is possible to obtain a cumulative addition value obtained by adding all pixel information in the window set to an arbitrary desired size in real time. That is, the output v of the subtractor 11 is led to the adder 12, and the latch value Σ corresponding to the previous cumulative addition value latched by the latch circuit 13 is returned to the adder 12 of the previous stage and supplied. By adding the subtraction value v and the latch value Σ in the adder 12, the addition value of all the pixel information within the window can be obtained. Then, the added value is latched by the latch circuit 13 as a new Σ.

On the other hand, the multiplexer 14 is controlled by the control signal from the control unit 5, and outputs the image information amm of the pixel at the center position of the center line in the window in the read signals of the line memory devices 2a to 2p to the window line. It moves out in the same direction, and it is extracted at least (P / 2 + M) steps (M
Is the number of latch stages inserted in the circuit for adding the correction value obtained by using the extracted pixel information to the adder / subtractor as the correction value of the pixel information), for example, in this embodiment, it comprises nine stages of registers M1 to M9. Supply to the shift register 15.

16a to 16d are multiplexers that can be selectively operated according to a command from an external processor according to the size of a window to be set. The multiplexers of the (n + 1) / 2th stage of the shift register 15, in this example, the third and subsequent stages 5x the output of the register of each stage
Corresponding to the window settings of 5, 7 × 7, 9 × 9, and 11 × 11, the registers M3 to M6 are selected and extracted.
The image information amm thus fetched is the information of the center pixel of the window, and when calculating the correction amount S of the above-mentioned formula (1) using the image information amm of this center pixel,
Considering that the number of pixels in the window is n × n, the n ² is multiplied by the image information amm in multiplier 17, the n ²
Send xamm to the latch circuit 18.

Next, the signal Σa _ij from the above-mentioned latch circuit 13 (however,
Σa _ij is the sum of the image information of all the pixels in the window) and the signal n ² × amm from this latch circuit 18 are added by the adder 19 (actually n ² × amm−Σ is calculated. ) Correction amount S
To get

This correction amount S is supplied via a latch circuit 20 to a table random access memory (hereinafter referred to as "RAM") 21 that can be preset. As is well known, the table RAM 21 converts an input signal into an address signal, converts the input signal into a value corresponding to the address, and outputs the value.
With respect to the input value, that is, the correction amount S obtained as described above, the stored value of the address for the correction amount S corresponds to the value of the correction amount S and is linear or non-linear, and the influence of the above-mentioned division The correction coefficient k in consideration of the compensation is converted into a correction value Sk obtained by multiplying the correction amount S and preset so as to be output. Therefore, the correction coefficient k set corresponding to each of the input correction amounts S can be preset in advance by a processor (not shown). Therefore, when the correction amount S is input to the table RAM 21, it is possible to output in real time a correction value Sk that changes in desired characteristics corresponding to the correction amount S and that can compensate the influence of division. The correction value Sk can be calculated at high speed.

The correction value Sk from the table RAM 21 is supplied to the adder / subtractor 23 for sharpening or smoothing the edge portion of the image through the latch circuit 22.

On the other hand, the adder / subtractor 23 includes the sixth to ninth parts of the shift register 15.
The central image information amm is selected and supplied from the stage in which the adder / subtractor 23 in the stages M6 to M9 coincides with the correction value Sk obtained as described above. In this embodiment, the pixel information amm of the window center position obtained from the multiplier 17 is used by the calculation of the correction value and latched by the three latch circuits 18, 20, and 22 before reaching the adder / subtractor 23. Therefore, it is necessary to delay the pixel information amm to be corrected guided to the adder / subtractor by the number of latch circuit stages. Therefore, the second shift register 15 has (P / 2 + 3) stages, for example, 9 stages as shown in the figure, so that the center pixel information amm of the window can be selectively taken out at the timing as described above in accordance with the window size. Constitute. And, n of the arbitrarily set window size
Corresponding to the × n pixel matrix, another multiplexers 20a to 20d are connected to (n + 1) / 2 + 3rd and subsequent registers M6 to M9, and the image information of the central pixel in the window of these registers M6 to M9 is stored. The output of the desired register stage is selectively taken out by a command from a processor (not shown).

The central image information amm extracted in this way is added to the adder / subtractor 2
It is supplied to 3 and addition and subtraction with the above-mentioned correction value Sk are performed to obtain an image signal in which the contour of the image is arbitrarily corrected. In this case, sharpening or smoothing can be switched by a command from an external processor, and sharpening can be performed by adding and smoothing can be performed by subtracting.

Next, the operation of image signal correction in the above embodiment will be described in detail with reference to FIGS.

FIG. 2 is an explanatory diagram for explaining a specific example in which the window is fixedly set to the 5 × 5 pixel matrix. The pixel arrangement in the window in this case is shown in FIG.

In this embodiment, for convenience of description, the lines from the line memory device during writing are omitted, and the first and second shift registers 9 and 9 are provided corresponding to the set size of the pixel matrix of the window. The number of stages of 15 is 6 and the window switching multiplexer is omitted. Since the other structure is the same as that of the case of FIG. 1, its detailed description is omitted.

In this example, signals of five lines are indicated by a, b, c, d, and e, the central image information is c in the third stage, and this is connected so as to be input to the second shift register 15.

FIG. 3 shows stored values in each stage of the first shift register 9.
vi is a holding state of the central image information c in each stage of the shift register 15, the stored value vi and the latch value .SIGMA. Is.

As shown in FIG. 3, the first added value from the adder 7 is stored in the first register V1 of the first shift register 9 as a stored value.
When stored as v ₁ , the first register M 1 of the second shift register 15 receives the image information c ₁ of the third line. Next, on the added value of the second time is recorded in the register V1 as stored value v _2, first round of stored value v ₁ is shifted to the next register V2. Similarly, the second shift register
The stored value c ₁ of the first register M1 of 15 is also shifted to the next register M2, the next center image information c ₂ of the third line is newly stored in the register of M1, and the latch value Σ is v ₁ Becomes
Similarly, when sequentially stored and when the sixth addition value is obtained as the storage value v ₆ , all the registers of both shift registers 9 and 15 store the storage value, and the latch value Σ also It can be seen that the correct value is shown, the steady state is reached, and the correction amount S is obtained in only five calculation times.

Further, the correction amount S is determined by the table RA as described above.
Since it is immediately converted into a linear or non-linear correction value Sk by M21, a conventional image signal correction apparatus of this kind has a calculation speed for enhancing or smoothing an edge portion of an image so as to obtain a desired sharpness. Can be significantly faster than

For example, when the image information of the pixels in the window for the original image is arranged as shown in FIG. 4, the image information of the pixel at the center position is a33. In the adder 7, the added value (a11 + a21 + a31 + a41) for each image information lined up in the vertical direction
+ A51) or (a12 + a22 + a32 + a42 + a52), the addition value v is sequentially sent to the first shift register 9.

Therefore, the correction value Sk in this case becomes Sk = k (25a33- (a11 + a12 + ... + a15 + a21 + ... + a55) (2), and the corrected image information X becomes X = a33 + Sk (3). Is corrected so that

FIGS. 5A to 5E are waveform charts for explaining the progress of the above-described correction.

FIG. 5 (A) shows an image signal amm having an edge portion to be corrected, and FIG. 5 (B) shows a correction coefficient k for the correction amount S for the image signal amm (in this case, k is less than 1). The correction value Sk is obtained by multiplying by a number). This correction value Sk
Is added to amm shown in FIG. 5 (A) with a positive polarity, a waveform with a sharp edge portion is obtained as shown in FIG. 5 (D). Further, when the correction value Sk shown in FIG. 5 (C) is added to the image signal amm of FIG. 5 (A) in the negative polarity, the waveform in which the edge portion is smoothed as shown in FIG. 5 (E). Becomes

Therefore, the digitalized image signal thus corrected is added to the halftone image forming apparatus 55 including the D / A converter of the image scanning recording apparatus described with reference to FIG. 6, and converted into the halftone image signal there. The signal thus obtained is used as an optical modulation driver 46.
By modulating the s-polarized light from the recording laser 31 supplied to the recording medium, an image corrected to a desired sharpness can be recorded by the recording device.

Incidentally, when the correction value Sk to be preset in the table RAM 21 is calculated, the correction coefficient k multiplied by the correction amount S can be easily and quickly changed by an external processor. Further, in this case, the correction coefficient k having a value can be selectively used linearly or non-linearly depending on the property of the original image.

Obviously, the present invention is not limited to the above-mentioned embodiments.

It is also clear that the image device to which the present invention can be applied is not limited to the device of the type shown in FIG.

(Effects of the Invention) As is apparent from the above description, according to the method of the present invention, a line memory corresponding to the maximum number of window lines capable of coping with correction of various original images is prepared, and a desired window is prepared. The (n + 1) line memories are cyclically used in relation to the number n of pixel columns, and the image information of the original image is stored in one of them, and the output of the n line memories excluding the line memory in the write mode is stored. Is added at the same time, the addition process is sequentially performed in the line direction, these addition values are sequentially stored in the shift register once, and the number of line memories read out to obtain the addition value is changed. Therefore, the desired window size is set, and if necessary, the switching is selected by interlocking with the read register stage of the shift register to correct various images. A window having a corresponding size can be set, and correction calculation of image information with respect to the center pixel of the window can be performed in real time. Therefore, image signal correction can be made faster than before. .

Further, in the present invention, the difference between the average value of the image data in the window and the center pixel value is used as the correction value to obtain a correction value corresponding to the value of a _mm , whereby the center portion of the image as well as the edge portion is corrected. The correction can be optimized.

Further, such high-speed processing can be easily carried out by a device having almost the same scale as the conventional device.

[Brief description of drawings]

FIG. 1 (A) is a block diagram for explaining an embodiment of the image signal correction method of the present invention, and FIG. 1 (B) shows various signals used in the embodiment of FIG. 1 (A). 2 is a block diagram showing the outline of the configuration of the control unit for the above, FIG. 2 is an explanatory view for explaining the image signal correction method when the window is set to be a 5 × 5 pixel matrix, and FIG. 3 is an explanation of the present invention. FIG. 4 is a diagram showing a pixel array in a window of a 5 × 5 pixel matrix, FIG. 5 is a waveform diagram for explaining a process of correcting central image information by the method of the present invention, FIG. 6 is a block diagram showing an example of an image scanning recording apparatus to which the present invention can be applied. 1 ... Data signal input terminal 2a-2p ... Line memory device 3 ... Line memory 4,10a-10d, 14,16a-16d ... Multiplexer 5 ... Control section, 6a-6p ... Gate circuit 7,12 , 19 …… Adder, 8a ～ 8p …… Divider 9 …… First shift register 10a ～ 10d, 14 …… Multiplexer 11 …… Subtractor 13,18,20,22 …… Latch circuit 15 …… Second Shift register 17 …… Multiplier, 21 …… Table RAM 23 …… Adder / subtractor, 24 …… Line counter 25 …… First decoder, 26 …… Second decoder 27 …… Read address counter 28 …… Write address counter.

Claims (1)

[Claims] 1. An image signal obtained by scanning an original image,
A window of n × n pixel matrix (where n is an odd number) is set, and a correction amount S for the image information a _{mm at} the center position of the window is calculated by a predetermined calculation formula S = n based on all pixel information in the window. ² a _mm −Σa _ij (where Σa _ij is the added value of the image information of all pixels in the window), and the image information a _mm of the center pixel of the window is corrected according to the correction amount S. In the correction method of the image signal, the image information of the pixels of each line arranged on the same column in the window, from the latest addition value of the sequential addition values obtained by adding for each column, from the addition value The added value obtained by adding (n + 1) times before counting is subtracted, the subtracted value is led to a latch circuit via an adder and latched, and the latched value is fed back to the adder to perform the subtraction. give an added value? a _ij by sequentially adding to the value one , After selectively branching a central image information a _mm of the window, n of the image information a _mm at the center position of the window
^Double value, simultaneously with the image information? A _ij, obtained from the n ² a _mm value and the image information? A _ij the said correction amount S by using the _{^{S = (n 2 a mm -Σa}} ij) An image signal correction method characterized by obtaining.